1*f2105c61SSimon Glass /* 2*f2105c61SSimon Glass * Copyright (C) 2011 Freescale Semiconductor, Inc. 3*f2105c61SSimon Glass * Author: Tang Yuantian <b29983@freescale.com> 4*f2105c61SSimon Glass * 5*f2105c61SSimon Glass * SPDX-License-Identifier: GPL-2.0+ 6*f2105c61SSimon Glass */ 7*f2105c61SSimon Glass 8*f2105c61SSimon Glass #ifndef SATA_SIL3132_H 9*f2105c61SSimon Glass #define SATA_SIL3132_H 10*f2105c61SSimon Glass 11*f2105c61SSimon Glass #define READ_CMD 0 12*f2105c61SSimon Glass #define WRITE_CMD 1 13*f2105c61SSimon Glass 14*f2105c61SSimon Glass /* 15*f2105c61SSimon Glass * SATA device driver struct for each dev 16*f2105c61SSimon Glass */ 17*f2105c61SSimon Glass struct sil_sata { 18*f2105c61SSimon Glass char name[12]; 19*f2105c61SSimon Glass void *port; /* the port base address */ 20*f2105c61SSimon Glass int lba48; 21*f2105c61SSimon Glass u16 pio; 22*f2105c61SSimon Glass u16 mwdma; 23*f2105c61SSimon Glass u16 udma; 24*f2105c61SSimon Glass pci_dev_t devno; 25*f2105c61SSimon Glass int wcache; 26*f2105c61SSimon Glass int flush; 27*f2105c61SSimon Glass int flush_ext; 28*f2105c61SSimon Glass }; 29*f2105c61SSimon Glass 30*f2105c61SSimon Glass /* sata info for each controller */ 31*f2105c61SSimon Glass struct sata_info { 32*f2105c61SSimon Glass ulong iobase[3]; 33*f2105c61SSimon Glass pci_dev_t devno; 34*f2105c61SSimon Glass int portbase; 35*f2105c61SSimon Glass int maxport; 36*f2105c61SSimon Glass }; 37*f2105c61SSimon Glass 38*f2105c61SSimon Glass /* 39*f2105c61SSimon Glass * Scatter gather entry (SGE),MUST 8 bytes aligned 40*f2105c61SSimon Glass */ 41*f2105c61SSimon Glass struct sil_sge { 42*f2105c61SSimon Glass __le64 addr; 43*f2105c61SSimon Glass __le32 cnt; 44*f2105c61SSimon Glass __le32 flags; 45*f2105c61SSimon Glass } __attribute__ ((aligned(8), packed)); 46*f2105c61SSimon Glass 47*f2105c61SSimon Glass /* 48*f2105c61SSimon Glass * Port request block, MUST 8 bytes aligned 49*f2105c61SSimon Glass */ 50*f2105c61SSimon Glass struct sil_prb { 51*f2105c61SSimon Glass __le16 ctrl; 52*f2105c61SSimon Glass __le16 prot; 53*f2105c61SSimon Glass __le32 rx_cnt; 54*f2105c61SSimon Glass struct sata_fis_h2d fis; 55*f2105c61SSimon Glass } __attribute__ ((aligned(8), packed)); 56*f2105c61SSimon Glass 57*f2105c61SSimon Glass struct sil_cmd_block { 58*f2105c61SSimon Glass struct sil_prb prb; 59*f2105c61SSimon Glass struct sil_sge sge; 60*f2105c61SSimon Glass }; 61*f2105c61SSimon Glass 62*f2105c61SSimon Glass enum { 63*f2105c61SSimon Glass HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ 64*f2105c61SSimon Glass HOST_CTRL = 0x40, 65*f2105c61SSimon Glass HOST_IRQ_STAT = 0x44, 66*f2105c61SSimon Glass HOST_PHY_CFG = 0x48, 67*f2105c61SSimon Glass HOST_BIST_CTRL = 0x50, 68*f2105c61SSimon Glass HOST_BIST_PTRN = 0x54, 69*f2105c61SSimon Glass HOST_BIST_STAT = 0x58, 70*f2105c61SSimon Glass HOST_MEM_BIST_STAT = 0x5c, 71*f2105c61SSimon Glass HOST_FLASH_CMD = 0x70, 72*f2105c61SSimon Glass /* 8 bit regs */ 73*f2105c61SSimon Glass HOST_FLASH_DATA = 0x74, 74*f2105c61SSimon Glass HOST_TRANSITION_DETECT = 0x75, 75*f2105c61SSimon Glass HOST_GPIO_CTRL = 0x76, 76*f2105c61SSimon Glass HOST_I2C_ADDR = 0x78, /* 32 bit */ 77*f2105c61SSimon Glass HOST_I2C_DATA = 0x7c, 78*f2105c61SSimon Glass HOST_I2C_XFER_CNT = 0x7e, 79*f2105c61SSimon Glass HOST_I2C_CTRL = 0x7f, 80*f2105c61SSimon Glass 81*f2105c61SSimon Glass /* HOST_SLOT_STAT bits */ 82*f2105c61SSimon Glass HOST_SSTAT_ATTN = (1 << 31), 83*f2105c61SSimon Glass 84*f2105c61SSimon Glass /* HOST_CTRL bits */ 85*f2105c61SSimon Glass HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ 86*f2105c61SSimon Glass HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ 87*f2105c61SSimon Glass HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ 88*f2105c61SSimon Glass HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ 89*f2105c61SSimon Glass HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ 90*f2105c61SSimon Glass HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ 91*f2105c61SSimon Glass 92*f2105c61SSimon Glass /* 93*f2105c61SSimon Glass * Port registers 94*f2105c61SSimon Glass * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) 95*f2105c61SSimon Glass */ 96*f2105c61SSimon Glass PORT_REGS_SIZE = 0x2000, 97*f2105c61SSimon Glass 98*f2105c61SSimon Glass PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ 99*f2105c61SSimon Glass PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 100*f2105c61SSimon Glass 101*f2105c61SSimon Glass PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ 102*f2105c61SSimon Glass PORT_PMP_STATUS = 0x0000, /* port device status offset */ 103*f2105c61SSimon Glass PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ 104*f2105c61SSimon Glass PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ 105*f2105c61SSimon Glass 106*f2105c61SSimon Glass /* 32 bit regs */ 107*f2105c61SSimon Glass PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 108*f2105c61SSimon Glass PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 109*f2105c61SSimon Glass PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ 110*f2105c61SSimon Glass PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ 111*f2105c61SSimon Glass PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ 112*f2105c61SSimon Glass PORT_ACTIVATE_UPPER_ADDR = 0x101c, 113*f2105c61SSimon Glass PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ 114*f2105c61SSimon Glass PORT_CMD_ERR = 0x1024, /* command error number */ 115*f2105c61SSimon Glass PORT_FIS_CFG = 0x1028, 116*f2105c61SSimon Glass PORT_FIFO_THRES = 0x102c, 117*f2105c61SSimon Glass 118*f2105c61SSimon Glass /* 16 bit regs */ 119*f2105c61SSimon Glass PORT_DECODE_ERR_CNT = 0x1040, 120*f2105c61SSimon Glass PORT_DECODE_ERR_THRESH = 0x1042, 121*f2105c61SSimon Glass PORT_CRC_ERR_CNT = 0x1044, 122*f2105c61SSimon Glass PORT_CRC_ERR_THRESH = 0x1046, 123*f2105c61SSimon Glass PORT_HSHK_ERR_CNT = 0x1048, 124*f2105c61SSimon Glass PORT_HSHK_ERR_THRESH = 0x104a, 125*f2105c61SSimon Glass 126*f2105c61SSimon Glass /* 32 bit regs */ 127*f2105c61SSimon Glass PORT_PHY_CFG = 0x1050, 128*f2105c61SSimon Glass PORT_SLOT_STAT = 0x1800, 129*f2105c61SSimon Glass PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 */ 130*f2105c61SSimon Glass PORT_CONTEXT = 0x1e04, 131*f2105c61SSimon Glass PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 */ 132*f2105c61SSimon Glass PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 */ 133*f2105c61SSimon Glass PORT_SCONTROL = 0x1f00, 134*f2105c61SSimon Glass PORT_SSTATUS = 0x1f04, 135*f2105c61SSimon Glass PORT_SERROR = 0x1f08, 136*f2105c61SSimon Glass PORT_SACTIVE = 0x1f0c, 137*f2105c61SSimon Glass 138*f2105c61SSimon Glass /* PORT_CTRL_STAT bits */ 139*f2105c61SSimon Glass PORT_CS_PORT_RST = (1 << 0), /* port reset */ 140*f2105c61SSimon Glass PORT_CS_DEV_RST = (1 << 1), /* device reset */ 141*f2105c61SSimon Glass PORT_CS_INIT = (1 << 2), /* port initialize */ 142*f2105c61SSimon Glass PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 143*f2105c61SSimon Glass PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 144*f2105c61SSimon Glass PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ 145*f2105c61SSimon Glass PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 146*f2105c61SSimon Glass PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ 147*f2105c61SSimon Glass PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 148*f2105c61SSimon Glass 149*f2105c61SSimon Glass /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 150*f2105c61SSimon Glass /* bits[11:0] are masked */ 151*f2105c61SSimon Glass PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ 152*f2105c61SSimon Glass PORT_IRQ_ERROR = (1 << 1), /* command execution error */ 153*f2105c61SSimon Glass PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ 154*f2105c61SSimon Glass PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ 155*f2105c61SSimon Glass PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ 156*f2105c61SSimon Glass PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ 157*f2105c61SSimon Glass PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ 158*f2105c61SSimon Glass PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ 159*f2105c61SSimon Glass PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ 160*f2105c61SSimon Glass PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ 161*f2105c61SSimon Glass PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ 162*f2105c61SSimon Glass PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ 163*f2105c61SSimon Glass 164*f2105c61SSimon Glass DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | 165*f2105c61SSimon Glass PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | 166*f2105c61SSimon Glass PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, 167*f2105c61SSimon Glass 168*f2105c61SSimon Glass /* bits[27:16] are unmasked (raw) */ 169*f2105c61SSimon Glass PORT_IRQ_RAW_SHIFT = 16, 170*f2105c61SSimon Glass PORT_IRQ_MASKED_MASK = 0x7ff, 171*f2105c61SSimon Glass PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), 172*f2105c61SSimon Glass 173*f2105c61SSimon Glass /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ 174*f2105c61SSimon Glass PORT_IRQ_STEER_SHIFT = 30, 175*f2105c61SSimon Glass PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), 176*f2105c61SSimon Glass 177*f2105c61SSimon Glass /* PORT_CMD_ERR constants */ 178*f2105c61SSimon Glass PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ 179*f2105c61SSimon Glass PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ 180*f2105c61SSimon Glass PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ 181*f2105c61SSimon Glass PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ 182*f2105c61SSimon Glass PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ 183*f2105c61SSimon Glass PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ 184*f2105c61SSimon Glass PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ 185*f2105c61SSimon Glass PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ 186*f2105c61SSimon Glass 187*f2105c61SSimon Glass /* bits of PRB control field */ 188*f2105c61SSimon Glass PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ 189*f2105c61SSimon Glass PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ 190*f2105c61SSimon Glass PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ 191*f2105c61SSimon Glass PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ 192*f2105c61SSimon Glass PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ 193*f2105c61SSimon Glass 194*f2105c61SSimon Glass /* PRB protocol field */ 195*f2105c61SSimon Glass PRB_PROT_PACKET = (1 << 0), 196*f2105c61SSimon Glass PRB_PROT_TCQ = (1 << 1), 197*f2105c61SSimon Glass PRB_PROT_NCQ = (1 << 2), 198*f2105c61SSimon Glass PRB_PROT_READ = (1 << 3), 199*f2105c61SSimon Glass PRB_PROT_WRITE = (1 << 4), 200*f2105c61SSimon Glass PRB_PROT_TRANSPARENT = (1 << 5), 201*f2105c61SSimon Glass 202*f2105c61SSimon Glass /* 203*f2105c61SSimon Glass * Other constants 204*f2105c61SSimon Glass */ 205*f2105c61SSimon Glass SGE_TRM = (1 << 31), /* Last SGE in chain */ 206*f2105c61SSimon Glass SGE_LNK = (1 << 30), /* linked list 207*f2105c61SSimon Glass Points to SGT, not SGE */ 208*f2105c61SSimon Glass SGE_DRD = (1 << 29), /* discard data read (/dev/null) 209*f2105c61SSimon Glass data address ignored */ 210*f2105c61SSimon Glass 211*f2105c61SSimon Glass CMD_ERR = 0x21, 212*f2105c61SSimon Glass }; 213*f2105c61SSimon Glass 214*f2105c61SSimon Glass #endif 215