1 /* 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 3 * Terry Lv <r65388@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <ahci.h> 10 #include <fis.h> 11 #include <libata.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <sata.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/sys_proto.h> 18 #include <linux/bitops.h> 19 #include <linux/ctype.h> 20 #include <linux/errno.h> 21 #include "dwc_ahsata_priv.h" 22 23 struct sata_port_regs { 24 u32 clb; 25 u32 clbu; 26 u32 fb; 27 u32 fbu; 28 u32 is; 29 u32 ie; 30 u32 cmd; 31 u32 res1[1]; 32 u32 tfd; 33 u32 sig; 34 u32 ssts; 35 u32 sctl; 36 u32 serr; 37 u32 sact; 38 u32 ci; 39 u32 sntf; 40 u32 res2[1]; 41 u32 dmacr; 42 u32 res3[1]; 43 u32 phycr; 44 u32 physr; 45 }; 46 47 struct sata_host_regs { 48 u32 cap; 49 u32 ghc; 50 u32 is; 51 u32 pi; 52 u32 vs; 53 u32 ccc_ctl; 54 u32 ccc_ports; 55 u32 res1[2]; 56 u32 cap2; 57 u32 res2[30]; 58 u32 bistafr; 59 u32 bistcr; 60 u32 bistfctr; 61 u32 bistsr; 62 u32 bistdecr; 63 u32 res3[2]; 64 u32 oobr; 65 u32 res4[8]; 66 u32 timer1ms; 67 u32 res5[1]; 68 u32 gparam1r; 69 u32 gparam2r; 70 u32 pparamr; 71 u32 testr; 72 u32 versionr; 73 u32 idr; 74 }; 75 76 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) 77 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) 78 79 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) 80 81 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) 82 { 83 return base + 0x100 + (port * 0x80); 84 } 85 86 static int waiting_for_cmd_completed(u8 *offset, 87 int timeout_msec, 88 u32 sign) 89 { 90 int i; 91 u32 status; 92 93 for (i = 0; 94 ((status = readl(offset)) & sign) && i < timeout_msec; 95 ++i) 96 mdelay(1); 97 98 return (i < timeout_msec) ? 0 : -1; 99 } 100 101 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) 102 { 103 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 104 105 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); 106 writel(0x02060b14, &host_mmio->oobr); 107 108 return 0; 109 } 110 111 static int ahci_host_init(struct ahci_uc_priv *uc_priv) 112 { 113 u32 tmp, cap_save, num_ports; 114 int i, j, timeout = 1000; 115 struct sata_port_regs *port_mmio = NULL; 116 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 117 int clk = mxc_get_clock(MXC_SATA_CLK); 118 119 cap_save = readl(&host_mmio->cap); 120 cap_save |= SATA_HOST_CAP_SSS; 121 122 /* global controller reset */ 123 tmp = readl(&host_mmio->ghc); 124 if ((tmp & SATA_HOST_GHC_HR) == 0) 125 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc); 126 127 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout) 128 ; 129 130 if (timeout <= 0) { 131 debug("controller reset failed (0x%x)\n", tmp); 132 return -1; 133 } 134 135 /* Set timer 1ms */ 136 writel(clk / 1000, &host_mmio->timer1ms); 137 138 ahci_setup_oobr(uc_priv, 0); 139 140 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc); 141 writel(cap_save, &host_mmio->cap); 142 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; 143 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi); 144 145 /* 146 * Determine which Ports are implemented by the DWC_ahsata, 147 * by reading the PI register. This bit map value aids the 148 * software to determine how many Ports are available and 149 * which Port registers need to be initialized. 150 */ 151 uc_priv->cap = readl(&host_mmio->cap); 152 uc_priv->port_map = readl(&host_mmio->pi); 153 154 /* Determine how many command slots the HBA supports */ 155 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1; 156 157 debug("cap 0x%x port_map 0x%x n_ports %d\n", 158 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); 159 160 for (i = 0; i < uc_priv->n_ports; i++) { 161 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); 162 port_mmio = uc_priv->port[i].port_mmio; 163 164 /* Ensure that the DWC_ahsata is in idle state */ 165 tmp = readl(&port_mmio->cmd); 166 167 /* 168 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR 169 * are all cleared, the Port is in an idle state. 170 */ 171 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | 172 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { 173 174 /* 175 * System software places a Port into the idle state by 176 * clearing P#CMD.ST and waiting for P#CMD.CR to return 177 * 0 when read. 178 */ 179 tmp &= ~SATA_PORT_CMD_ST; 180 writel_with_flush(tmp, &port_mmio->cmd); 181 182 /* 183 * spec says 500 msecs for each bit, so 184 * this is slightly incorrect. 185 */ 186 mdelay(500); 187 188 timeout = 1000; 189 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) 190 && --timeout) 191 ; 192 193 if (timeout <= 0) { 194 debug("port reset failed (0x%x)\n", tmp); 195 return -1; 196 } 197 } 198 199 /* Spin-up device */ 200 tmp = readl(&port_mmio->cmd); 201 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd); 202 203 /* Wait for spin-up to finish */ 204 timeout = 1000; 205 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) 206 && --timeout) 207 ; 208 if (timeout <= 0) { 209 debug("Spin-Up can't finish!\n"); 210 return -1; 211 } 212 213 for (j = 0; j < 100; ++j) { 214 mdelay(10); 215 tmp = readl(&port_mmio->ssts); 216 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || 217 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) 218 break; 219 } 220 221 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ 222 timeout = 1000; 223 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) 224 && --timeout) 225 ; 226 if (timeout <= 0) { 227 debug("Can't find DIAG_X set!\n"); 228 return -1; 229 } 230 231 /* 232 * For each implemented Port, clear the P#SERR 233 * register, by writing ones to each implemented\ 234 * bit location. 235 */ 236 tmp = readl(&port_mmio->serr); 237 debug("P#SERR 0x%x\n", 238 tmp); 239 writel(tmp, &port_mmio->serr); 240 241 /* Ack any pending irq events for this port */ 242 tmp = readl(&host_mmio->is); 243 debug("IS 0x%x\n", tmp); 244 if (tmp) 245 writel(tmp, &host_mmio->is); 246 247 writel(1 << i, &host_mmio->is); 248 249 /* set irq mask (enables interrupts) */ 250 writel(DEF_PORT_IRQ, &port_mmio->ie); 251 252 /* register linkup ports */ 253 tmp = readl(&port_mmio->ssts); 254 debug("Port %d status: 0x%x\n", i, tmp); 255 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) 256 uc_priv->link_port_map |= (0x01 << i); 257 } 258 259 tmp = readl(&host_mmio->ghc); 260 debug("GHC 0x%x\n", tmp); 261 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc); 262 tmp = readl(&host_mmio->ghc); 263 debug("GHC 0x%x\n", tmp); 264 265 return 0; 266 } 267 268 static void ahci_print_info(struct ahci_uc_priv *uc_priv) 269 { 270 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 271 u32 vers, cap, impl, speed; 272 const char *speed_s; 273 const char *scc_s; 274 275 vers = readl(&host_mmio->vs); 276 cap = uc_priv->cap; 277 impl = uc_priv->port_map; 278 279 speed = (cap & SATA_HOST_CAP_ISS_MASK) 280 >> SATA_HOST_CAP_ISS_OFFSET; 281 if (speed == 1) 282 speed_s = "1.5"; 283 else if (speed == 2) 284 speed_s = "3"; 285 else 286 speed_s = "?"; 287 288 scc_s = "SATA"; 289 290 printf("AHCI %02x%02x.%02x%02x " 291 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 292 (vers >> 24) & 0xff, 293 (vers >> 16) & 0xff, 294 (vers >> 8) & 0xff, 295 vers & 0xff, 296 ((cap >> 8) & 0x1f) + 1, 297 (cap & 0x1f) + 1, 298 speed_s, 299 impl, 300 scc_s); 301 302 printf("flags: " 303 "%s%s%s%s%s%s" 304 "%s%s%s%s%s%s%s\n", 305 cap & (1 << 31) ? "64bit " : "", 306 cap & (1 << 30) ? "ncq " : "", 307 cap & (1 << 28) ? "ilck " : "", 308 cap & (1 << 27) ? "stag " : "", 309 cap & (1 << 26) ? "pm " : "", 310 cap & (1 << 25) ? "led " : "", 311 cap & (1 << 24) ? "clo " : "", 312 cap & (1 << 19) ? "nz " : "", 313 cap & (1 << 18) ? "only " : "", 314 cap & (1 << 17) ? "pmp " : "", 315 cap & (1 << 15) ? "pio " : "", 316 cap & (1 << 14) ? "slum " : "", 317 cap & (1 << 13) ? "part " : ""); 318 } 319 320 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, 321 unsigned char *buf, int buf_len) 322 { 323 struct ahci_ioports *pp = &uc_priv->port[port]; 324 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 325 u32 sg_count, max_bytes; 326 int i; 327 328 max_bytes = MAX_DATA_BYTES_PER_SG; 329 sg_count = ((buf_len - 1) / max_bytes) + 1; 330 if (sg_count > AHCI_MAX_SG) { 331 printf("Error:Too much sg!\n"); 332 return -1; 333 } 334 335 for (i = 0; i < sg_count; i++) { 336 ahci_sg->addr = 337 cpu_to_le32((u32)buf + i * max_bytes); 338 ahci_sg->addr_hi = 0; 339 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 340 (buf_len < max_bytes 341 ? (buf_len - 1) 342 : (max_bytes - 1))); 343 ahci_sg++; 344 buf_len -= max_bytes; 345 } 346 347 return sg_count; 348 } 349 350 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) 351 { 352 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + 353 AHCI_CMD_SLOT_SZ * cmd_slot); 354 355 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); 356 cmd_hdr->opts = cpu_to_le32(opts); 357 cmd_hdr->status = 0; 358 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 359 #ifdef CONFIG_PHYS_64BIT 360 pp->cmd_slot->tbl_addr_hi = 361 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 362 #endif 363 } 364 365 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) 366 367 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, 368 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len, 369 s32 is_write) 370 { 371 struct ahci_ioports *pp = &uc_priv->port[port]; 372 struct sata_port_regs *port_mmio = pp->port_mmio; 373 u32 opts; 374 int sg_count = 0, cmd_slot = 0; 375 376 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci)); 377 if (32 == cmd_slot) { 378 printf("Can't find empty command slot!\n"); 379 return 0; 380 } 381 382 /* Check xfer length */ 383 if (buf_len > MAX_BYTES_PER_TRANS) { 384 printf("Max transfer length is %dB\n\r", 385 MAX_BYTES_PER_TRANS); 386 return 0; 387 } 388 389 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); 390 if (buf && buf_len) 391 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); 392 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); 393 if (is_write) { 394 opts |= 0x40; 395 flush_cache((ulong)buf, buf_len); 396 } 397 ahci_fill_cmd_slot(pp, cmd_slot, opts); 398 399 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); 400 writel_with_flush(1 << cmd_slot, &port_mmio->ci); 401 402 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, 403 0x1 << cmd_slot)) { 404 printf("timeout exit!\n"); 405 return -1; 406 } 407 invalidate_dcache_range((int)(pp->cmd_slot), 408 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); 409 debug("ahci_exec_ata_cmd: %d byte transferred.\n", 410 pp->cmd_slot->status); 411 if (!is_write) 412 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len); 413 414 return buf_len; 415 } 416 417 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port) 418 { 419 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 420 struct sata_fis_h2d *cfis = &h2d; 421 422 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 423 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 424 cfis->pm_port_c = 1 << 7; 425 cfis->command = ATA_CMD_SET_FEATURES; 426 cfis->features = SETFEATURES_XFER; 427 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e; 428 429 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD); 430 } 431 432 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) 433 { 434 struct ahci_ioports *pp = &uc_priv->port[port]; 435 struct sata_port_regs *port_mmio = pp->port_mmio; 436 u32 port_status; 437 u32 mem; 438 int timeout = 10000000; 439 440 debug("Enter start port: %d\n", port); 441 port_status = readl(&port_mmio->ssts); 442 debug("Port %d status: %x\n", port, port_status); 443 if ((port_status & 0xf) != 0x03) { 444 printf("No Link on this port!\n"); 445 return -1; 446 } 447 448 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); 449 if (!mem) { 450 free(pp); 451 printf("No mem for table!\n"); 452 return -ENOMEM; 453 } 454 455 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ 456 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); 457 458 /* 459 * First item in chunk of DMA memory: 32-slot command table, 460 * 32 bytes each in size 461 */ 462 pp->cmd_slot = (struct ahci_cmd_hdr *)mem; 463 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); 464 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); 465 466 /* 467 * Second item: Received-FIS area, 256-Byte aligned 468 */ 469 pp->rx_fis = mem; 470 mem += AHCI_RX_FIS_SZ; 471 472 /* 473 * Third item: data area for storing a single command 474 * and its scatter-gather table 475 */ 476 pp->cmd_tbl = mem; 477 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); 478 479 mem += AHCI_CMD_TBL_HDR; 480 481 writel_with_flush(0x00004444, &port_mmio->dmacr); 482 pp->cmd_tbl_sg = (struct ahci_sg *)mem; 483 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); 484 writel_with_flush(pp->rx_fis, &port_mmio->fb); 485 486 /* Enable FRE */ 487 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), 488 &port_mmio->cmd); 489 490 /* Wait device ready */ 491 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR | 492 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) 493 && --timeout) 494 ; 495 if (timeout <= 0) { 496 debug("Device not ready for BSY, DRQ and" 497 "ERR in TFD!\n"); 498 return -1; 499 } 500 501 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 502 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 503 PORT_CMD_START, &port_mmio->cmd); 504 505 debug("Exit start port %d\n", port); 506 507 return 0; 508 } 509 510 static void dwc_ahsata_print_info(struct blk_desc *pdev) 511 { 512 printf("SATA Device Info:\n\r"); 513 #ifdef CONFIG_SYS_64BIT_LBA 514 printf("S/N: %s\n\rProduct model number: %s\n\r" 515 "Firmware version: %s\n\rCapacity: %lld sectors\n\r", 516 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 517 #else 518 printf("S/N: %s\n\rProduct model number: %s\n\r" 519 "Firmware version: %s\n\rCapacity: %ld sectors\n\r", 520 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 521 #endif 522 } 523 524 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id) 525 { 526 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 527 struct sata_fis_h2d *cfis = &h2d; 528 u8 port = uc_priv->hard_port_no; 529 530 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 531 532 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 533 cfis->pm_port_c = 0x80; /* is command */ 534 cfis->command = ATA_CMD_ID_ATA; 535 536 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2, 537 READ_CMD); 538 ata_swap_buf_le16(id, ATA_ID_WORDS); 539 } 540 541 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id) 542 { 543 uc_priv->pio_mask = id[ATA_ID_PIO_MODES]; 544 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES]; 545 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask); 546 } 547 548 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start, 549 u32 blkcnt, u8 *buffer, int is_write) 550 { 551 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 552 struct sata_fis_h2d *cfis = &h2d; 553 u8 port = uc_priv->hard_port_no; 554 u32 block; 555 556 block = start; 557 558 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 559 560 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 561 cfis->pm_port_c = 0x80; /* is command */ 562 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; 563 cfis->device = ATA_LBA; 564 565 cfis->device |= (block >> 24) & 0xf; 566 cfis->lba_high = (block >> 16) & 0xff; 567 cfis->lba_mid = (block >> 8) & 0xff; 568 cfis->lba_low = block & 0xff; 569 cfis->sector_count = (u8)(blkcnt & 0xff); 570 571 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 572 ATA_SECT_SIZE * blkcnt, is_write) > 0) 573 return blkcnt; 574 else 575 return 0; 576 } 577 578 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv) 579 { 580 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 581 struct sata_fis_h2d *cfis = &h2d; 582 u8 port = uc_priv->hard_port_no; 583 584 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 585 586 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 587 cfis->pm_port_c = 0x80; /* is command */ 588 cfis->command = ATA_CMD_FLUSH; 589 590 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 591 } 592 593 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start, 594 lbaint_t blkcnt, u8 *buffer, int is_write) 595 { 596 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 597 struct sata_fis_h2d *cfis = &h2d; 598 u8 port = uc_priv->hard_port_no; 599 u64 block; 600 601 block = (u64)start; 602 603 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 604 605 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 606 cfis->pm_port_c = 0x80; /* is command */ 607 608 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT 609 : ATA_CMD_READ_EXT; 610 611 cfis->lba_high_exp = (block >> 40) & 0xff; 612 cfis->lba_mid_exp = (block >> 32) & 0xff; 613 cfis->lba_low_exp = (block >> 24) & 0xff; 614 cfis->lba_high = (block >> 16) & 0xff; 615 cfis->lba_mid = (block >> 8) & 0xff; 616 cfis->lba_low = block & 0xff; 617 cfis->device = ATA_LBA; 618 cfis->sector_count_exp = (blkcnt >> 8) & 0xff; 619 cfis->sector_count = blkcnt & 0xff; 620 621 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 622 ATA_SECT_SIZE * blkcnt, is_write) > 0) 623 return blkcnt; 624 else 625 return 0; 626 } 627 628 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv) 629 { 630 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 631 struct sata_fis_h2d *cfis = &h2d; 632 u8 port = uc_priv->hard_port_no; 633 634 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 635 636 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 637 cfis->pm_port_c = 0x80; /* is command */ 638 cfis->command = ATA_CMD_FLUSH_EXT; 639 640 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 641 } 642 643 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id) 644 { 645 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) 646 uc_priv->flags |= SATA_FLAG_WCACHE; 647 if (ata_id_has_flush(id)) 648 uc_priv->flags |= SATA_FLAG_FLUSH; 649 if (ata_id_has_flush_ext(id)) 650 uc_priv->flags |= SATA_FLAG_FLUSH_EXT; 651 } 652 653 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr, 654 lbaint_t blkcnt, const void *buffer, 655 int is_write) 656 { 657 u32 start, blks; 658 u8 *addr; 659 int max_blks; 660 661 start = blknr; 662 blks = blkcnt; 663 addr = (u8 *)buffer; 664 665 max_blks = ATA_MAX_SECTORS_LBA48; 666 667 do { 668 if (blks > max_blks) { 669 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, 670 max_blks, addr, 671 is_write)) 672 return 0; 673 start += max_blks; 674 blks -= max_blks; 675 addr += ATA_SECT_SIZE * max_blks; 676 } else { 677 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks, 678 addr, is_write)) 679 return 0; 680 start += blks; 681 blks = 0; 682 addr += ATA_SECT_SIZE * blks; 683 } 684 } while (blks != 0); 685 686 return blkcnt; 687 } 688 689 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr, 690 lbaint_t blkcnt, const void *buffer, 691 int is_write) 692 { 693 u32 start, blks; 694 u8 *addr; 695 int max_blks; 696 697 start = blknr; 698 blks = blkcnt; 699 addr = (u8 *)buffer; 700 701 max_blks = ATA_MAX_SECTORS; 702 do { 703 if (blks > max_blks) { 704 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start, 705 max_blks, addr, 706 is_write)) 707 return 0; 708 start += max_blks; 709 blks -= max_blks; 710 addr += ATA_SECT_SIZE * max_blks; 711 } else { 712 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks, 713 addr, is_write)) 714 return 0; 715 start += blks; 716 blks = 0; 717 addr += ATA_SECT_SIZE * blks; 718 } 719 } while (blks != 0); 720 721 return blkcnt; 722 } 723 724 static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv) 725 { 726 u32 linkmap; 727 int i; 728 729 linkmap = uc_priv->link_port_map; 730 731 if (0 == linkmap) { 732 printf("No port device detected!\n"); 733 return -ENXIO; 734 } 735 736 for (i = 0; i < uc_priv->n_ports; i++) { 737 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { 738 if (ahci_port_start(uc_priv, (u8)i)) { 739 printf("Can not start port %d\n", i); 740 return 1; 741 } 742 uc_priv->hard_port_no = i; 743 break; 744 } 745 } 746 747 return 0; 748 } 749 750 static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv, 751 struct blk_desc *pdev) 752 { 753 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; 754 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; 755 u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; 756 u64 n_sectors; 757 u8 port = uc_priv->hard_port_no; 758 ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS); 759 760 /* Identify device to get information */ 761 dwc_ahsata_identify(uc_priv, id); 762 763 /* Serial number */ 764 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); 765 memcpy(pdev->product, serial, sizeof(serial)); 766 767 /* Firmware version */ 768 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); 769 memcpy(pdev->revision, firmware, sizeof(firmware)); 770 771 /* Product model */ 772 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); 773 memcpy(pdev->vendor, product, sizeof(product)); 774 775 /* Totoal sectors */ 776 n_sectors = ata_id_n_sectors(id); 777 pdev->lba = (u32)n_sectors; 778 779 pdev->type = DEV_TYPE_HARDDISK; 780 pdev->blksz = ATA_SECT_SIZE; 781 pdev->lun = 0; 782 783 /* Check if support LBA48 */ 784 if (ata_id_has_lba48(id)) { 785 pdev->lba48 = 1; 786 debug("Device support LBA48\n\r"); 787 } 788 789 /* Get the NCQ queue depth from device */ 790 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK); 791 uc_priv->flags |= ata_id_queue_depth(id); 792 793 /* Get the xfer mode from device */ 794 dwc_ahsata_xfer_mode(uc_priv, id); 795 796 /* Get the write cache status from device */ 797 dwc_ahsata_init_wcache(uc_priv, id); 798 799 /* Set the xfer mode to highest speed */ 800 ahci_set_feature(uc_priv, port); 801 802 dwc_ahsata_print_info(pdev); 803 804 return 0; 805 } 806 807 /* 808 * SATA interface between low level driver and command layer 809 */ 810 static ulong sata_read_common(struct ahci_uc_priv *uc_priv, 811 struct blk_desc *desc, ulong blknr, 812 lbaint_t blkcnt, void *buffer) 813 { 814 u32 rc; 815 816 if (desc->lba48) 817 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, 818 READ_CMD); 819 else 820 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, 821 READ_CMD); 822 823 return rc; 824 } 825 826 static ulong sata_write_common(struct ahci_uc_priv *uc_priv, 827 struct blk_desc *desc, ulong blknr, 828 lbaint_t blkcnt, const void *buffer) 829 { 830 u32 rc; 831 u32 flags = uc_priv->flags; 832 833 if (desc->lba48) { 834 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, 835 WRITE_CMD); 836 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT)) 837 dwc_ahsata_flush_cache_ext(uc_priv); 838 } else { 839 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, 840 WRITE_CMD); 841 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH)) 842 dwc_ahsata_flush_cache(uc_priv); 843 } 844 845 return rc; 846 } 847 848 static int ahci_init_one(int pdev) 849 { 850 int rc; 851 struct ahci_uc_priv *uc_priv = NULL; 852 853 uc_priv = malloc(sizeof(struct ahci_uc_priv)); 854 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 855 uc_priv->dev = pdev; 856 857 uc_priv->host_flags = ATA_FLAG_SATA 858 | ATA_FLAG_NO_LEGACY 859 | ATA_FLAG_MMIO 860 | ATA_FLAG_PIO_DMA 861 | ATA_FLAG_NO_ATAPI; 862 863 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; 864 865 /* initialize adapter */ 866 rc = ahci_host_init(uc_priv); 867 if (rc) 868 goto err_out; 869 870 ahci_print_info(uc_priv); 871 872 /* Save the uc_private struct to block device struct */ 873 sata_dev_desc[pdev].priv = uc_priv; 874 875 return 0; 876 877 err_out: 878 return rc; 879 } 880 881 int init_sata(int dev) 882 { 883 struct ahci_uc_priv *uc_priv = NULL; 884 885 #if defined(CONFIG_MX6) 886 if (!is_mx6dq() && !is_mx6dqp()) 887 return 1; 888 #endif 889 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 890 printf("The sata index %d is out of ranges\n\r", dev); 891 return -1; 892 } 893 894 ahci_init_one(dev); 895 896 uc_priv = sata_dev_desc[dev].priv; 897 898 return dwc_ahci_start_ports(uc_priv) ? 1 : 0; 899 } 900 901 int reset_sata(int dev) 902 { 903 struct ahci_uc_priv *uc_priv; 904 struct sata_host_regs *host_mmio; 905 906 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 907 printf("The sata index %d is out of ranges\n\r", dev); 908 return -1; 909 } 910 911 uc_priv = sata_dev_desc[dev].priv; 912 if (NULL == uc_priv) 913 /* not initialized, so nothing to reset */ 914 return 0; 915 916 host_mmio = uc_priv->mmio_base; 917 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); 918 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) 919 udelay(100); 920 921 return 0; 922 } 923 924 int sata_port_status(int dev, int port) 925 { 926 struct sata_port_regs *port_mmio; 927 struct ahci_uc_priv *uc_priv = NULL; 928 929 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) 930 return -EINVAL; 931 932 if (sata_dev_desc[dev].priv == NULL) 933 return -ENODEV; 934 935 uc_priv = sata_dev_desc[dev].priv; 936 port_mmio = uc_priv->port[port].port_mmio; 937 938 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; 939 } 940 941 /* 942 * SATA interface between low level driver and command layer 943 */ 944 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) 945 { 946 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 947 948 return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, 949 buffer); 950 } 951 952 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) 953 { 954 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 955 956 return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, 957 buffer); 958 } 959 960 int scan_sata(int dev) 961 { 962 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 963 struct blk_desc *pdev = &sata_dev_desc[dev]; 964 965 return dwc_ahsata_scan_common(uc_priv, pdev); 966 } 967