1 /* 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 3 * Terry Lv <r65388@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <ahci.h> 10 #include <fis.h> 11 #include <libata.h> 12 #include <malloc.h> 13 #include <sata.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/sys_proto.h> 17 #include <linux/bitops.h> 18 #include <linux/ctype.h> 19 #include <linux/errno.h> 20 #include "dwc_ahsata_priv.h" 21 22 struct sata_port_regs { 23 u32 clb; 24 u32 clbu; 25 u32 fb; 26 u32 fbu; 27 u32 is; 28 u32 ie; 29 u32 cmd; 30 u32 res1[1]; 31 u32 tfd; 32 u32 sig; 33 u32 ssts; 34 u32 sctl; 35 u32 serr; 36 u32 sact; 37 u32 ci; 38 u32 sntf; 39 u32 res2[1]; 40 u32 dmacr; 41 u32 res3[1]; 42 u32 phycr; 43 u32 physr; 44 }; 45 46 struct sata_host_regs { 47 u32 cap; 48 u32 ghc; 49 u32 is; 50 u32 pi; 51 u32 vs; 52 u32 ccc_ctl; 53 u32 ccc_ports; 54 u32 res1[2]; 55 u32 cap2; 56 u32 res2[30]; 57 u32 bistafr; 58 u32 bistcr; 59 u32 bistfctr; 60 u32 bistsr; 61 u32 bistdecr; 62 u32 res3[2]; 63 u32 oobr; 64 u32 res4[8]; 65 u32 timer1ms; 66 u32 res5[1]; 67 u32 gparam1r; 68 u32 gparam2r; 69 u32 pparamr; 70 u32 testr; 71 u32 versionr; 72 u32 idr; 73 }; 74 75 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) 76 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) 77 78 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) 79 80 static int is_ready; 81 82 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) 83 { 84 return base + 0x100 + (port * 0x80); 85 } 86 87 static int waiting_for_cmd_completed(u8 *offset, 88 int timeout_msec, 89 u32 sign) 90 { 91 int i; 92 u32 status; 93 94 for (i = 0; 95 ((status = readl(offset)) & sign) && i < timeout_msec; 96 ++i) 97 mdelay(1); 98 99 return (i < timeout_msec) ? 0 : -1; 100 } 101 102 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) 103 { 104 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 105 106 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); 107 writel(0x02060b14, &host_mmio->oobr); 108 109 return 0; 110 } 111 112 static int ahci_host_init(struct ahci_uc_priv *uc_priv) 113 { 114 u32 tmp, cap_save, num_ports; 115 int i, j, timeout = 1000; 116 struct sata_port_regs *port_mmio = NULL; 117 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 118 int clk = mxc_get_clock(MXC_SATA_CLK); 119 120 cap_save = readl(&host_mmio->cap); 121 cap_save |= SATA_HOST_CAP_SSS; 122 123 /* global controller reset */ 124 tmp = readl(&host_mmio->ghc); 125 if ((tmp & SATA_HOST_GHC_HR) == 0) 126 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc); 127 128 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout) 129 ; 130 131 if (timeout <= 0) { 132 debug("controller reset failed (0x%x)\n", tmp); 133 return -1; 134 } 135 136 /* Set timer 1ms */ 137 writel(clk / 1000, &host_mmio->timer1ms); 138 139 ahci_setup_oobr(uc_priv, 0); 140 141 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc); 142 writel(cap_save, &host_mmio->cap); 143 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; 144 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi); 145 146 /* 147 * Determine which Ports are implemented by the DWC_ahsata, 148 * by reading the PI register. This bit map value aids the 149 * software to determine how many Ports are available and 150 * which Port registers need to be initialized. 151 */ 152 uc_priv->cap = readl(&host_mmio->cap); 153 uc_priv->port_map = readl(&host_mmio->pi); 154 155 /* Determine how many command slots the HBA supports */ 156 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1; 157 158 debug("cap 0x%x port_map 0x%x n_ports %d\n", 159 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); 160 161 for (i = 0; i < uc_priv->n_ports; i++) { 162 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); 163 port_mmio = uc_priv->port[i].port_mmio; 164 165 /* Ensure that the DWC_ahsata is in idle state */ 166 tmp = readl(&port_mmio->cmd); 167 168 /* 169 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR 170 * are all cleared, the Port is in an idle state. 171 */ 172 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | 173 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { 174 175 /* 176 * System software places a Port into the idle state by 177 * clearing P#CMD.ST and waiting for P#CMD.CR to return 178 * 0 when read. 179 */ 180 tmp &= ~SATA_PORT_CMD_ST; 181 writel_with_flush(tmp, &port_mmio->cmd); 182 183 /* 184 * spec says 500 msecs for each bit, so 185 * this is slightly incorrect. 186 */ 187 mdelay(500); 188 189 timeout = 1000; 190 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) 191 && --timeout) 192 ; 193 194 if (timeout <= 0) { 195 debug("port reset failed (0x%x)\n", tmp); 196 return -1; 197 } 198 } 199 200 /* Spin-up device */ 201 tmp = readl(&port_mmio->cmd); 202 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd); 203 204 /* Wait for spin-up to finish */ 205 timeout = 1000; 206 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) 207 && --timeout) 208 ; 209 if (timeout <= 0) { 210 debug("Spin-Up can't finish!\n"); 211 return -1; 212 } 213 214 for (j = 0; j < 100; ++j) { 215 mdelay(10); 216 tmp = readl(&port_mmio->ssts); 217 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || 218 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) 219 break; 220 } 221 222 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ 223 timeout = 1000; 224 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) 225 && --timeout) 226 ; 227 if (timeout <= 0) { 228 debug("Can't find DIAG_X set!\n"); 229 return -1; 230 } 231 232 /* 233 * For each implemented Port, clear the P#SERR 234 * register, by writing ones to each implemented\ 235 * bit location. 236 */ 237 tmp = readl(&port_mmio->serr); 238 debug("P#SERR 0x%x\n", 239 tmp); 240 writel(tmp, &port_mmio->serr); 241 242 /* Ack any pending irq events for this port */ 243 tmp = readl(&host_mmio->is); 244 debug("IS 0x%x\n", tmp); 245 if (tmp) 246 writel(tmp, &host_mmio->is); 247 248 writel(1 << i, &host_mmio->is); 249 250 /* set irq mask (enables interrupts) */ 251 writel(DEF_PORT_IRQ, &port_mmio->ie); 252 253 /* register linkup ports */ 254 tmp = readl(&port_mmio->ssts); 255 debug("Port %d status: 0x%x\n", i, tmp); 256 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) 257 uc_priv->link_port_map |= (0x01 << i); 258 } 259 260 tmp = readl(&host_mmio->ghc); 261 debug("GHC 0x%x\n", tmp); 262 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc); 263 tmp = readl(&host_mmio->ghc); 264 debug("GHC 0x%x\n", tmp); 265 266 return 0; 267 } 268 269 static void ahci_print_info(struct ahci_uc_priv *uc_priv) 270 { 271 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 272 u32 vers, cap, impl, speed; 273 const char *speed_s; 274 const char *scc_s; 275 276 vers = readl(&host_mmio->vs); 277 cap = uc_priv->cap; 278 impl = uc_priv->port_map; 279 280 speed = (cap & SATA_HOST_CAP_ISS_MASK) 281 >> SATA_HOST_CAP_ISS_OFFSET; 282 if (speed == 1) 283 speed_s = "1.5"; 284 else if (speed == 2) 285 speed_s = "3"; 286 else 287 speed_s = "?"; 288 289 scc_s = "SATA"; 290 291 printf("AHCI %02x%02x.%02x%02x " 292 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 293 (vers >> 24) & 0xff, 294 (vers >> 16) & 0xff, 295 (vers >> 8) & 0xff, 296 vers & 0xff, 297 ((cap >> 8) & 0x1f) + 1, 298 (cap & 0x1f) + 1, 299 speed_s, 300 impl, 301 scc_s); 302 303 printf("flags: " 304 "%s%s%s%s%s%s" 305 "%s%s%s%s%s%s%s\n", 306 cap & (1 << 31) ? "64bit " : "", 307 cap & (1 << 30) ? "ncq " : "", 308 cap & (1 << 28) ? "ilck " : "", 309 cap & (1 << 27) ? "stag " : "", 310 cap & (1 << 26) ? "pm " : "", 311 cap & (1 << 25) ? "led " : "", 312 cap & (1 << 24) ? "clo " : "", 313 cap & (1 << 19) ? "nz " : "", 314 cap & (1 << 18) ? "only " : "", 315 cap & (1 << 17) ? "pmp " : "", 316 cap & (1 << 15) ? "pio " : "", 317 cap & (1 << 14) ? "slum " : "", 318 cap & (1 << 13) ? "part " : ""); 319 } 320 321 static int ahci_init_one(int pdev) 322 { 323 int rc; 324 struct ahci_uc_priv *uc_priv = NULL; 325 326 uc_priv = malloc(sizeof(struct ahci_uc_priv)); 327 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 328 uc_priv->dev = pdev; 329 330 uc_priv->host_flags = ATA_FLAG_SATA 331 | ATA_FLAG_NO_LEGACY 332 | ATA_FLAG_MMIO 333 | ATA_FLAG_PIO_DMA 334 | ATA_FLAG_NO_ATAPI; 335 336 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; 337 338 /* initialize adapter */ 339 rc = ahci_host_init(uc_priv); 340 if (rc) 341 goto err_out; 342 343 ahci_print_info(uc_priv); 344 345 /* Save the uc_private struct to block device struct */ 346 sata_dev_desc[pdev].priv = uc_priv; 347 348 return 0; 349 350 err_out: 351 return rc; 352 } 353 354 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, 355 unsigned char *buf, int buf_len) 356 { 357 struct ahci_ioports *pp = &uc_priv->port[port]; 358 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 359 u32 sg_count, max_bytes; 360 int i; 361 362 max_bytes = MAX_DATA_BYTES_PER_SG; 363 sg_count = ((buf_len - 1) / max_bytes) + 1; 364 if (sg_count > AHCI_MAX_SG) { 365 printf("Error:Too much sg!\n"); 366 return -1; 367 } 368 369 for (i = 0; i < sg_count; i++) { 370 ahci_sg->addr = 371 cpu_to_le32((u32)buf + i * max_bytes); 372 ahci_sg->addr_hi = 0; 373 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 374 (buf_len < max_bytes 375 ? (buf_len - 1) 376 : (max_bytes - 1))); 377 ahci_sg++; 378 buf_len -= max_bytes; 379 } 380 381 return sg_count; 382 } 383 384 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) 385 { 386 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + 387 AHCI_CMD_SLOT_SZ * cmd_slot); 388 389 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); 390 cmd_hdr->opts = cpu_to_le32(opts); 391 cmd_hdr->status = 0; 392 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 393 #ifdef CONFIG_PHYS_64BIT 394 pp->cmd_slot->tbl_addr_hi = 395 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 396 #endif 397 } 398 399 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) 400 401 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, 402 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len, 403 s32 is_write) 404 { 405 struct ahci_ioports *pp = &uc_priv->port[port]; 406 struct sata_port_regs *port_mmio = pp->port_mmio; 407 u32 opts; 408 int sg_count = 0, cmd_slot = 0; 409 410 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci)); 411 if (32 == cmd_slot) { 412 printf("Can't find empty command slot!\n"); 413 return 0; 414 } 415 416 /* Check xfer length */ 417 if (buf_len > MAX_BYTES_PER_TRANS) { 418 printf("Max transfer length is %dB\n\r", 419 MAX_BYTES_PER_TRANS); 420 return 0; 421 } 422 423 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); 424 if (buf && buf_len) 425 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); 426 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); 427 if (is_write) { 428 opts |= 0x40; 429 flush_cache((ulong)buf, buf_len); 430 } 431 ahci_fill_cmd_slot(pp, cmd_slot, opts); 432 433 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); 434 writel_with_flush(1 << cmd_slot, &port_mmio->ci); 435 436 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, 437 0x1 << cmd_slot)) { 438 printf("timeout exit!\n"); 439 return -1; 440 } 441 invalidate_dcache_range((int)(pp->cmd_slot), 442 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); 443 debug("ahci_exec_ata_cmd: %d byte transferred.\n", 444 pp->cmd_slot->status); 445 if (!is_write) 446 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len); 447 448 return buf_len; 449 } 450 451 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port) 452 { 453 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 454 struct sata_fis_h2d *cfis = &h2d; 455 456 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 457 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 458 cfis->pm_port_c = 1 << 7; 459 cfis->command = ATA_CMD_SET_FEATURES; 460 cfis->features = SETFEATURES_XFER; 461 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e; 462 463 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD); 464 } 465 466 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) 467 { 468 struct ahci_ioports *pp = &uc_priv->port[port]; 469 struct sata_port_regs *port_mmio = pp->port_mmio; 470 u32 port_status; 471 u32 mem; 472 int timeout = 10000000; 473 474 debug("Enter start port: %d\n", port); 475 port_status = readl(&port_mmio->ssts); 476 debug("Port %d status: %x\n", port, port_status); 477 if ((port_status & 0xf) != 0x03) { 478 printf("No Link on this port!\n"); 479 return -1; 480 } 481 482 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); 483 if (!mem) { 484 free(pp); 485 printf("No mem for table!\n"); 486 return -ENOMEM; 487 } 488 489 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ 490 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); 491 492 /* 493 * First item in chunk of DMA memory: 32-slot command table, 494 * 32 bytes each in size 495 */ 496 pp->cmd_slot = (struct ahci_cmd_hdr *)mem; 497 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); 498 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); 499 500 /* 501 * Second item: Received-FIS area, 256-Byte aligned 502 */ 503 pp->rx_fis = mem; 504 mem += AHCI_RX_FIS_SZ; 505 506 /* 507 * Third item: data area for storing a single command 508 * and its scatter-gather table 509 */ 510 pp->cmd_tbl = mem; 511 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); 512 513 mem += AHCI_CMD_TBL_HDR; 514 515 writel_with_flush(0x00004444, &port_mmio->dmacr); 516 pp->cmd_tbl_sg = (struct ahci_sg *)mem; 517 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); 518 writel_with_flush(pp->rx_fis, &port_mmio->fb); 519 520 /* Enable FRE */ 521 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), 522 &port_mmio->cmd); 523 524 /* Wait device ready */ 525 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR | 526 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) 527 && --timeout) 528 ; 529 if (timeout <= 0) { 530 debug("Device not ready for BSY, DRQ and" 531 "ERR in TFD!\n"); 532 return -1; 533 } 534 535 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 536 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 537 PORT_CMD_START, &port_mmio->cmd); 538 539 debug("Exit start port %d\n", port); 540 541 return 0; 542 } 543 544 static void dwc_ahsata_print_info(struct blk_desc *pdev) 545 { 546 printf("SATA Device Info:\n\r"); 547 #ifdef CONFIG_SYS_64BIT_LBA 548 printf("S/N: %s\n\rProduct model number: %s\n\r" 549 "Firmware version: %s\n\rCapacity: %lld sectors\n\r", 550 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 551 #else 552 printf("S/N: %s\n\rProduct model number: %s\n\r" 553 "Firmware version: %s\n\rCapacity: %ld sectors\n\r", 554 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 555 #endif 556 } 557 558 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id) 559 { 560 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 561 struct sata_fis_h2d *cfis = &h2d; 562 u8 port = uc_priv->hard_port_no; 563 564 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 565 566 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 567 cfis->pm_port_c = 0x80; /* is command */ 568 cfis->command = ATA_CMD_ID_ATA; 569 570 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2, 571 READ_CMD); 572 ata_swap_buf_le16(id, ATA_ID_WORDS); 573 } 574 575 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id) 576 { 577 uc_priv->pio_mask = id[ATA_ID_PIO_MODES]; 578 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES]; 579 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask); 580 } 581 582 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start, 583 u32 blkcnt, u8 *buffer, int is_write) 584 { 585 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 586 struct sata_fis_h2d *cfis = &h2d; 587 u8 port = uc_priv->hard_port_no; 588 u32 block; 589 590 block = start; 591 592 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 593 594 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 595 cfis->pm_port_c = 0x80; /* is command */ 596 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; 597 cfis->device = ATA_LBA; 598 599 cfis->device |= (block >> 24) & 0xf; 600 cfis->lba_high = (block >> 16) & 0xff; 601 cfis->lba_mid = (block >> 8) & 0xff; 602 cfis->lba_low = block & 0xff; 603 cfis->sector_count = (u8)(blkcnt & 0xff); 604 605 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 606 ATA_SECT_SIZE * blkcnt, is_write) > 0) 607 return blkcnt; 608 else 609 return 0; 610 } 611 612 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv) 613 { 614 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 615 struct sata_fis_h2d *cfis = &h2d; 616 u8 port = uc_priv->hard_port_no; 617 618 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 619 620 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 621 cfis->pm_port_c = 0x80; /* is command */ 622 cfis->command = ATA_CMD_FLUSH; 623 624 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 625 } 626 627 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start, 628 lbaint_t blkcnt, u8 *buffer, int is_write) 629 { 630 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 631 struct sata_fis_h2d *cfis = &h2d; 632 u8 port = uc_priv->hard_port_no; 633 u64 block; 634 635 block = (u64)start; 636 637 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 638 639 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 640 cfis->pm_port_c = 0x80; /* is command */ 641 642 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT 643 : ATA_CMD_READ_EXT; 644 645 cfis->lba_high_exp = (block >> 40) & 0xff; 646 cfis->lba_mid_exp = (block >> 32) & 0xff; 647 cfis->lba_low_exp = (block >> 24) & 0xff; 648 cfis->lba_high = (block >> 16) & 0xff; 649 cfis->lba_mid = (block >> 8) & 0xff; 650 cfis->lba_low = block & 0xff; 651 cfis->device = ATA_LBA; 652 cfis->sector_count_exp = (blkcnt >> 8) & 0xff; 653 cfis->sector_count = blkcnt & 0xff; 654 655 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 656 ATA_SECT_SIZE * blkcnt, is_write) > 0) 657 return blkcnt; 658 else 659 return 0; 660 } 661 662 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv) 663 { 664 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 665 struct sata_fis_h2d *cfis = &h2d; 666 u8 port = uc_priv->hard_port_no; 667 668 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 669 670 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 671 cfis->pm_port_c = 0x80; /* is command */ 672 cfis->command = ATA_CMD_FLUSH_EXT; 673 674 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 675 } 676 677 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id) 678 { 679 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) 680 uc_priv->flags |= SATA_FLAG_WCACHE; 681 if (ata_id_has_flush(id)) 682 uc_priv->flags |= SATA_FLAG_FLUSH; 683 if (ata_id_has_flush_ext(id)) 684 uc_priv->flags |= SATA_FLAG_FLUSH_EXT; 685 } 686 687 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr, 688 lbaint_t blkcnt, const void *buffer, 689 int is_write) 690 { 691 u32 start, blks; 692 u8 *addr; 693 int max_blks; 694 695 start = blknr; 696 blks = blkcnt; 697 addr = (u8 *)buffer; 698 699 max_blks = ATA_MAX_SECTORS_LBA48; 700 701 do { 702 if (blks > max_blks) { 703 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, 704 max_blks, addr, 705 is_write)) 706 return 0; 707 start += max_blks; 708 blks -= max_blks; 709 addr += ATA_SECT_SIZE * max_blks; 710 } else { 711 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks, 712 addr, is_write)) 713 return 0; 714 start += blks; 715 blks = 0; 716 addr += ATA_SECT_SIZE * blks; 717 } 718 } while (blks != 0); 719 720 return blkcnt; 721 } 722 723 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr, 724 lbaint_t blkcnt, const void *buffer, 725 int is_write) 726 { 727 u32 start, blks; 728 u8 *addr; 729 int max_blks; 730 731 start = blknr; 732 blks = blkcnt; 733 addr = (u8 *)buffer; 734 735 max_blks = ATA_MAX_SECTORS; 736 do { 737 if (blks > max_blks) { 738 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start, 739 max_blks, addr, 740 is_write)) 741 return 0; 742 start += max_blks; 743 blks -= max_blks; 744 addr += ATA_SECT_SIZE * max_blks; 745 } else { 746 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks, 747 addr, is_write)) 748 return 0; 749 start += blks; 750 blks = 0; 751 addr += ATA_SECT_SIZE * blks; 752 } 753 } while (blks != 0); 754 755 return blkcnt; 756 } 757 758 int init_sata(int dev) 759 { 760 int i; 761 u32 linkmap; 762 struct ahci_uc_priv *uc_priv = NULL; 763 764 #if defined(CONFIG_MX6) 765 if (!is_mx6dq() && !is_mx6dqp()) 766 return 1; 767 #endif 768 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 769 printf("The sata index %d is out of ranges\n\r", dev); 770 return -1; 771 } 772 773 ahci_init_one(dev); 774 775 uc_priv = sata_dev_desc[dev].priv; 776 linkmap = uc_priv->link_port_map; 777 778 if (0 == linkmap) { 779 printf("No port device detected!\n"); 780 return 1; 781 } 782 783 for (i = 0; i < uc_priv->n_ports; i++) { 784 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { 785 if (ahci_port_start(uc_priv, (u8)i)) { 786 printf("Can not start port %d\n", i); 787 return 1; 788 } 789 uc_priv->hard_port_no = i; 790 break; 791 } 792 } 793 794 return 0; 795 } 796 797 int reset_sata(int dev) 798 { 799 struct ahci_uc_priv *uc_priv; 800 struct sata_host_regs *host_mmio; 801 802 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 803 printf("The sata index %d is out of ranges\n\r", dev); 804 return -1; 805 } 806 807 uc_priv = sata_dev_desc[dev].priv; 808 if (NULL == uc_priv) 809 /* not initialized, so nothing to reset */ 810 return 0; 811 812 host_mmio = uc_priv->mmio_base; 813 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); 814 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) 815 udelay(100); 816 817 return 0; 818 } 819 820 int sata_port_status(int dev, int port) 821 { 822 struct sata_port_regs *port_mmio; 823 struct ahci_uc_priv *uc_priv = NULL; 824 825 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) 826 return -EINVAL; 827 828 if (sata_dev_desc[dev].priv == NULL) 829 return -ENODEV; 830 831 uc_priv = sata_dev_desc[dev].priv; 832 port_mmio = uc_priv->port[port].port_mmio; 833 834 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; 835 } 836 837 /* 838 * SATA interface between low level driver and command layer 839 */ 840 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) 841 { 842 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 843 u32 rc; 844 845 if (sata_dev_desc[dev].lba48) 846 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, 847 buffer, READ_CMD); 848 else 849 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, 850 buffer, READ_CMD); 851 return rc; 852 } 853 854 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) 855 { 856 u32 rc; 857 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 858 u32 flags = uc_priv->flags; 859 860 if (sata_dev_desc[dev].lba48) { 861 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, 862 WRITE_CMD); 863 if ((flags & SATA_FLAG_WCACHE) && 864 (flags & SATA_FLAG_FLUSH_EXT)) 865 dwc_ahsata_flush_cache_ext(uc_priv); 866 } else { 867 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, 868 WRITE_CMD); 869 if ((flags & SATA_FLAG_WCACHE) && 870 (flags & SATA_FLAG_FLUSH)) 871 dwc_ahsata_flush_cache(uc_priv); 872 } 873 return rc; 874 } 875 876 int scan_sata(int dev) 877 { 878 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; 879 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; 880 u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; 881 u16 *id; 882 u64 n_sectors; 883 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 884 u8 port = uc_priv->hard_port_no; 885 struct blk_desc *pdev = &sata_dev_desc[dev]; 886 887 id = (u16 *)memalign(ARCH_DMA_MINALIGN, 888 roundup(ARCH_DMA_MINALIGN, 889 (ATA_ID_WORDS * 2))); 890 if (!id) { 891 printf("id malloc failed\n\r"); 892 return -1; 893 } 894 895 /* Identify device to get information */ 896 dwc_ahsata_identify(uc_priv, id); 897 898 /* Serial number */ 899 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); 900 memcpy(pdev->product, serial, sizeof(serial)); 901 902 /* Firmware version */ 903 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); 904 memcpy(pdev->revision, firmware, sizeof(firmware)); 905 906 /* Product model */ 907 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); 908 memcpy(pdev->vendor, product, sizeof(product)); 909 910 /* Totoal sectors */ 911 n_sectors = ata_id_n_sectors(id); 912 pdev->lba = (u32)n_sectors; 913 914 pdev->type = DEV_TYPE_HARDDISK; 915 pdev->blksz = ATA_SECT_SIZE; 916 pdev->lun = 0 ; 917 918 /* Check if support LBA48 */ 919 if (ata_id_has_lba48(id)) { 920 pdev->lba48 = 1; 921 debug("Device support LBA48\n\r"); 922 } 923 924 /* Get the NCQ queue depth from device */ 925 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK); 926 uc_priv->flags |= ata_id_queue_depth(id); 927 928 /* Get the xfer mode from device */ 929 dwc_ahsata_xfer_mode(uc_priv, id); 930 931 /* Get the write cache status from device */ 932 dwc_ahsata_init_wcache(uc_priv, id); 933 934 /* Set the xfer mode to highest speed */ 935 ahci_set_feature(uc_priv, port); 936 937 free((void *)id); 938 939 dwc_ahsata_print_info(&sata_dev_desc[dev]); 940 941 is_ready = 1; 942 943 return 0; 944 } 945