1 /* 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 3 * Terry Lv <r65388@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <ahci.h> 10 #include <fis.h> 11 #include <libata.h> 12 #include <malloc.h> 13 #include <sata.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/sys_proto.h> 17 #include <linux/bitops.h> 18 #include <linux/ctype.h> 19 #include <linux/errno.h> 20 #include "dwc_ahsata_priv.h" 21 22 struct sata_port_regs { 23 u32 clb; 24 u32 clbu; 25 u32 fb; 26 u32 fbu; 27 u32 is; 28 u32 ie; 29 u32 cmd; 30 u32 res1[1]; 31 u32 tfd; 32 u32 sig; 33 u32 ssts; 34 u32 sctl; 35 u32 serr; 36 u32 sact; 37 u32 ci; 38 u32 sntf; 39 u32 res2[1]; 40 u32 dmacr; 41 u32 res3[1]; 42 u32 phycr; 43 u32 physr; 44 }; 45 46 struct sata_host_regs { 47 u32 cap; 48 u32 ghc; 49 u32 is; 50 u32 pi; 51 u32 vs; 52 u32 ccc_ctl; 53 u32 ccc_ports; 54 u32 res1[2]; 55 u32 cap2; 56 u32 res2[30]; 57 u32 bistafr; 58 u32 bistcr; 59 u32 bistfctr; 60 u32 bistsr; 61 u32 bistdecr; 62 u32 res3[2]; 63 u32 oobr; 64 u32 res4[8]; 65 u32 timer1ms; 66 u32 res5[1]; 67 u32 gparam1r; 68 u32 gparam2r; 69 u32 pparamr; 70 u32 testr; 71 u32 versionr; 72 u32 idr; 73 }; 74 75 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) 76 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) 77 78 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) 79 80 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) 81 { 82 return base + 0x100 + (port * 0x80); 83 } 84 85 static int waiting_for_cmd_completed(u8 *offset, 86 int timeout_msec, 87 u32 sign) 88 { 89 int i; 90 u32 status; 91 92 for (i = 0; 93 ((status = readl(offset)) & sign) && i < timeout_msec; 94 ++i) 95 mdelay(1); 96 97 return (i < timeout_msec) ? 0 : -1; 98 } 99 100 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) 101 { 102 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 103 104 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); 105 writel(0x02060b14, &host_mmio->oobr); 106 107 return 0; 108 } 109 110 static int ahci_host_init(struct ahci_uc_priv *uc_priv) 111 { 112 u32 tmp, cap_save, num_ports; 113 int i, j, timeout = 1000; 114 struct sata_port_regs *port_mmio = NULL; 115 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 116 int clk = mxc_get_clock(MXC_SATA_CLK); 117 118 cap_save = readl(&host_mmio->cap); 119 cap_save |= SATA_HOST_CAP_SSS; 120 121 /* global controller reset */ 122 tmp = readl(&host_mmio->ghc); 123 if ((tmp & SATA_HOST_GHC_HR) == 0) 124 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc); 125 126 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout) 127 ; 128 129 if (timeout <= 0) { 130 debug("controller reset failed (0x%x)\n", tmp); 131 return -1; 132 } 133 134 /* Set timer 1ms */ 135 writel(clk / 1000, &host_mmio->timer1ms); 136 137 ahci_setup_oobr(uc_priv, 0); 138 139 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc); 140 writel(cap_save, &host_mmio->cap); 141 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; 142 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi); 143 144 /* 145 * Determine which Ports are implemented by the DWC_ahsata, 146 * by reading the PI register. This bit map value aids the 147 * software to determine how many Ports are available and 148 * which Port registers need to be initialized. 149 */ 150 uc_priv->cap = readl(&host_mmio->cap); 151 uc_priv->port_map = readl(&host_mmio->pi); 152 153 /* Determine how many command slots the HBA supports */ 154 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1; 155 156 debug("cap 0x%x port_map 0x%x n_ports %d\n", 157 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); 158 159 for (i = 0; i < uc_priv->n_ports; i++) { 160 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); 161 port_mmio = uc_priv->port[i].port_mmio; 162 163 /* Ensure that the DWC_ahsata is in idle state */ 164 tmp = readl(&port_mmio->cmd); 165 166 /* 167 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR 168 * are all cleared, the Port is in an idle state. 169 */ 170 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | 171 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { 172 173 /* 174 * System software places a Port into the idle state by 175 * clearing P#CMD.ST and waiting for P#CMD.CR to return 176 * 0 when read. 177 */ 178 tmp &= ~SATA_PORT_CMD_ST; 179 writel_with_flush(tmp, &port_mmio->cmd); 180 181 /* 182 * spec says 500 msecs for each bit, so 183 * this is slightly incorrect. 184 */ 185 mdelay(500); 186 187 timeout = 1000; 188 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) 189 && --timeout) 190 ; 191 192 if (timeout <= 0) { 193 debug("port reset failed (0x%x)\n", tmp); 194 return -1; 195 } 196 } 197 198 /* Spin-up device */ 199 tmp = readl(&port_mmio->cmd); 200 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd); 201 202 /* Wait for spin-up to finish */ 203 timeout = 1000; 204 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) 205 && --timeout) 206 ; 207 if (timeout <= 0) { 208 debug("Spin-Up can't finish!\n"); 209 return -1; 210 } 211 212 for (j = 0; j < 100; ++j) { 213 mdelay(10); 214 tmp = readl(&port_mmio->ssts); 215 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || 216 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) 217 break; 218 } 219 220 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ 221 timeout = 1000; 222 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) 223 && --timeout) 224 ; 225 if (timeout <= 0) { 226 debug("Can't find DIAG_X set!\n"); 227 return -1; 228 } 229 230 /* 231 * For each implemented Port, clear the P#SERR 232 * register, by writing ones to each implemented\ 233 * bit location. 234 */ 235 tmp = readl(&port_mmio->serr); 236 debug("P#SERR 0x%x\n", 237 tmp); 238 writel(tmp, &port_mmio->serr); 239 240 /* Ack any pending irq events for this port */ 241 tmp = readl(&host_mmio->is); 242 debug("IS 0x%x\n", tmp); 243 if (tmp) 244 writel(tmp, &host_mmio->is); 245 246 writel(1 << i, &host_mmio->is); 247 248 /* set irq mask (enables interrupts) */ 249 writel(DEF_PORT_IRQ, &port_mmio->ie); 250 251 /* register linkup ports */ 252 tmp = readl(&port_mmio->ssts); 253 debug("Port %d status: 0x%x\n", i, tmp); 254 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) 255 uc_priv->link_port_map |= (0x01 << i); 256 } 257 258 tmp = readl(&host_mmio->ghc); 259 debug("GHC 0x%x\n", tmp); 260 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc); 261 tmp = readl(&host_mmio->ghc); 262 debug("GHC 0x%x\n", tmp); 263 264 return 0; 265 } 266 267 static void ahci_print_info(struct ahci_uc_priv *uc_priv) 268 { 269 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 270 u32 vers, cap, impl, speed; 271 const char *speed_s; 272 const char *scc_s; 273 274 vers = readl(&host_mmio->vs); 275 cap = uc_priv->cap; 276 impl = uc_priv->port_map; 277 278 speed = (cap & SATA_HOST_CAP_ISS_MASK) 279 >> SATA_HOST_CAP_ISS_OFFSET; 280 if (speed == 1) 281 speed_s = "1.5"; 282 else if (speed == 2) 283 speed_s = "3"; 284 else 285 speed_s = "?"; 286 287 scc_s = "SATA"; 288 289 printf("AHCI %02x%02x.%02x%02x " 290 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 291 (vers >> 24) & 0xff, 292 (vers >> 16) & 0xff, 293 (vers >> 8) & 0xff, 294 vers & 0xff, 295 ((cap >> 8) & 0x1f) + 1, 296 (cap & 0x1f) + 1, 297 speed_s, 298 impl, 299 scc_s); 300 301 printf("flags: " 302 "%s%s%s%s%s%s" 303 "%s%s%s%s%s%s%s\n", 304 cap & (1 << 31) ? "64bit " : "", 305 cap & (1 << 30) ? "ncq " : "", 306 cap & (1 << 28) ? "ilck " : "", 307 cap & (1 << 27) ? "stag " : "", 308 cap & (1 << 26) ? "pm " : "", 309 cap & (1 << 25) ? "led " : "", 310 cap & (1 << 24) ? "clo " : "", 311 cap & (1 << 19) ? "nz " : "", 312 cap & (1 << 18) ? "only " : "", 313 cap & (1 << 17) ? "pmp " : "", 314 cap & (1 << 15) ? "pio " : "", 315 cap & (1 << 14) ? "slum " : "", 316 cap & (1 << 13) ? "part " : ""); 317 } 318 319 static int ahci_init_one(int pdev) 320 { 321 int rc; 322 struct ahci_uc_priv *uc_priv = NULL; 323 324 uc_priv = malloc(sizeof(struct ahci_uc_priv)); 325 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 326 uc_priv->dev = pdev; 327 328 uc_priv->host_flags = ATA_FLAG_SATA 329 | ATA_FLAG_NO_LEGACY 330 | ATA_FLAG_MMIO 331 | ATA_FLAG_PIO_DMA 332 | ATA_FLAG_NO_ATAPI; 333 334 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; 335 336 /* initialize adapter */ 337 rc = ahci_host_init(uc_priv); 338 if (rc) 339 goto err_out; 340 341 ahci_print_info(uc_priv); 342 343 /* Save the uc_private struct to block device struct */ 344 sata_dev_desc[pdev].priv = uc_priv; 345 346 return 0; 347 348 err_out: 349 return rc; 350 } 351 352 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, 353 unsigned char *buf, int buf_len) 354 { 355 struct ahci_ioports *pp = &uc_priv->port[port]; 356 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 357 u32 sg_count, max_bytes; 358 int i; 359 360 max_bytes = MAX_DATA_BYTES_PER_SG; 361 sg_count = ((buf_len - 1) / max_bytes) + 1; 362 if (sg_count > AHCI_MAX_SG) { 363 printf("Error:Too much sg!\n"); 364 return -1; 365 } 366 367 for (i = 0; i < sg_count; i++) { 368 ahci_sg->addr = 369 cpu_to_le32((u32)buf + i * max_bytes); 370 ahci_sg->addr_hi = 0; 371 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 372 (buf_len < max_bytes 373 ? (buf_len - 1) 374 : (max_bytes - 1))); 375 ahci_sg++; 376 buf_len -= max_bytes; 377 } 378 379 return sg_count; 380 } 381 382 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) 383 { 384 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + 385 AHCI_CMD_SLOT_SZ * cmd_slot); 386 387 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); 388 cmd_hdr->opts = cpu_to_le32(opts); 389 cmd_hdr->status = 0; 390 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 391 #ifdef CONFIG_PHYS_64BIT 392 pp->cmd_slot->tbl_addr_hi = 393 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 394 #endif 395 } 396 397 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) 398 399 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, 400 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len, 401 s32 is_write) 402 { 403 struct ahci_ioports *pp = &uc_priv->port[port]; 404 struct sata_port_regs *port_mmio = pp->port_mmio; 405 u32 opts; 406 int sg_count = 0, cmd_slot = 0; 407 408 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci)); 409 if (32 == cmd_slot) { 410 printf("Can't find empty command slot!\n"); 411 return 0; 412 } 413 414 /* Check xfer length */ 415 if (buf_len > MAX_BYTES_PER_TRANS) { 416 printf("Max transfer length is %dB\n\r", 417 MAX_BYTES_PER_TRANS); 418 return 0; 419 } 420 421 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); 422 if (buf && buf_len) 423 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); 424 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); 425 if (is_write) { 426 opts |= 0x40; 427 flush_cache((ulong)buf, buf_len); 428 } 429 ahci_fill_cmd_slot(pp, cmd_slot, opts); 430 431 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); 432 writel_with_flush(1 << cmd_slot, &port_mmio->ci); 433 434 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, 435 0x1 << cmd_slot)) { 436 printf("timeout exit!\n"); 437 return -1; 438 } 439 invalidate_dcache_range((int)(pp->cmd_slot), 440 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); 441 debug("ahci_exec_ata_cmd: %d byte transferred.\n", 442 pp->cmd_slot->status); 443 if (!is_write) 444 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len); 445 446 return buf_len; 447 } 448 449 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port) 450 { 451 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 452 struct sata_fis_h2d *cfis = &h2d; 453 454 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 455 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 456 cfis->pm_port_c = 1 << 7; 457 cfis->command = ATA_CMD_SET_FEATURES; 458 cfis->features = SETFEATURES_XFER; 459 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e; 460 461 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD); 462 } 463 464 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) 465 { 466 struct ahci_ioports *pp = &uc_priv->port[port]; 467 struct sata_port_regs *port_mmio = pp->port_mmio; 468 u32 port_status; 469 u32 mem; 470 int timeout = 10000000; 471 472 debug("Enter start port: %d\n", port); 473 port_status = readl(&port_mmio->ssts); 474 debug("Port %d status: %x\n", port, port_status); 475 if ((port_status & 0xf) != 0x03) { 476 printf("No Link on this port!\n"); 477 return -1; 478 } 479 480 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); 481 if (!mem) { 482 free(pp); 483 printf("No mem for table!\n"); 484 return -ENOMEM; 485 } 486 487 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ 488 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); 489 490 /* 491 * First item in chunk of DMA memory: 32-slot command table, 492 * 32 bytes each in size 493 */ 494 pp->cmd_slot = (struct ahci_cmd_hdr *)mem; 495 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); 496 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); 497 498 /* 499 * Second item: Received-FIS area, 256-Byte aligned 500 */ 501 pp->rx_fis = mem; 502 mem += AHCI_RX_FIS_SZ; 503 504 /* 505 * Third item: data area for storing a single command 506 * and its scatter-gather table 507 */ 508 pp->cmd_tbl = mem; 509 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); 510 511 mem += AHCI_CMD_TBL_HDR; 512 513 writel_with_flush(0x00004444, &port_mmio->dmacr); 514 pp->cmd_tbl_sg = (struct ahci_sg *)mem; 515 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); 516 writel_with_flush(pp->rx_fis, &port_mmio->fb); 517 518 /* Enable FRE */ 519 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), 520 &port_mmio->cmd); 521 522 /* Wait device ready */ 523 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR | 524 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) 525 && --timeout) 526 ; 527 if (timeout <= 0) { 528 debug("Device not ready for BSY, DRQ and" 529 "ERR in TFD!\n"); 530 return -1; 531 } 532 533 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 534 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 535 PORT_CMD_START, &port_mmio->cmd); 536 537 debug("Exit start port %d\n", port); 538 539 return 0; 540 } 541 542 static void dwc_ahsata_print_info(struct blk_desc *pdev) 543 { 544 printf("SATA Device Info:\n\r"); 545 #ifdef CONFIG_SYS_64BIT_LBA 546 printf("S/N: %s\n\rProduct model number: %s\n\r" 547 "Firmware version: %s\n\rCapacity: %lld sectors\n\r", 548 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 549 #else 550 printf("S/N: %s\n\rProduct model number: %s\n\r" 551 "Firmware version: %s\n\rCapacity: %ld sectors\n\r", 552 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 553 #endif 554 } 555 556 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id) 557 { 558 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 559 struct sata_fis_h2d *cfis = &h2d; 560 u8 port = uc_priv->hard_port_no; 561 562 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 563 564 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 565 cfis->pm_port_c = 0x80; /* is command */ 566 cfis->command = ATA_CMD_ID_ATA; 567 568 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2, 569 READ_CMD); 570 ata_swap_buf_le16(id, ATA_ID_WORDS); 571 } 572 573 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id) 574 { 575 uc_priv->pio_mask = id[ATA_ID_PIO_MODES]; 576 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES]; 577 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask); 578 } 579 580 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start, 581 u32 blkcnt, u8 *buffer, int is_write) 582 { 583 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 584 struct sata_fis_h2d *cfis = &h2d; 585 u8 port = uc_priv->hard_port_no; 586 u32 block; 587 588 block = start; 589 590 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 591 592 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 593 cfis->pm_port_c = 0x80; /* is command */ 594 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; 595 cfis->device = ATA_LBA; 596 597 cfis->device |= (block >> 24) & 0xf; 598 cfis->lba_high = (block >> 16) & 0xff; 599 cfis->lba_mid = (block >> 8) & 0xff; 600 cfis->lba_low = block & 0xff; 601 cfis->sector_count = (u8)(blkcnt & 0xff); 602 603 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 604 ATA_SECT_SIZE * blkcnt, is_write) > 0) 605 return blkcnt; 606 else 607 return 0; 608 } 609 610 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv) 611 { 612 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 613 struct sata_fis_h2d *cfis = &h2d; 614 u8 port = uc_priv->hard_port_no; 615 616 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 617 618 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 619 cfis->pm_port_c = 0x80; /* is command */ 620 cfis->command = ATA_CMD_FLUSH; 621 622 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 623 } 624 625 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start, 626 lbaint_t blkcnt, u8 *buffer, int is_write) 627 { 628 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 629 struct sata_fis_h2d *cfis = &h2d; 630 u8 port = uc_priv->hard_port_no; 631 u64 block; 632 633 block = (u64)start; 634 635 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 636 637 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 638 cfis->pm_port_c = 0x80; /* is command */ 639 640 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT 641 : ATA_CMD_READ_EXT; 642 643 cfis->lba_high_exp = (block >> 40) & 0xff; 644 cfis->lba_mid_exp = (block >> 32) & 0xff; 645 cfis->lba_low_exp = (block >> 24) & 0xff; 646 cfis->lba_high = (block >> 16) & 0xff; 647 cfis->lba_mid = (block >> 8) & 0xff; 648 cfis->lba_low = block & 0xff; 649 cfis->device = ATA_LBA; 650 cfis->sector_count_exp = (blkcnt >> 8) & 0xff; 651 cfis->sector_count = blkcnt & 0xff; 652 653 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 654 ATA_SECT_SIZE * blkcnt, is_write) > 0) 655 return blkcnt; 656 else 657 return 0; 658 } 659 660 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv) 661 { 662 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 663 struct sata_fis_h2d *cfis = &h2d; 664 u8 port = uc_priv->hard_port_no; 665 666 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 667 668 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 669 cfis->pm_port_c = 0x80; /* is command */ 670 cfis->command = ATA_CMD_FLUSH_EXT; 671 672 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 673 } 674 675 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id) 676 { 677 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) 678 uc_priv->flags |= SATA_FLAG_WCACHE; 679 if (ata_id_has_flush(id)) 680 uc_priv->flags |= SATA_FLAG_FLUSH; 681 if (ata_id_has_flush_ext(id)) 682 uc_priv->flags |= SATA_FLAG_FLUSH_EXT; 683 } 684 685 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr, 686 lbaint_t blkcnt, const void *buffer, 687 int is_write) 688 { 689 u32 start, blks; 690 u8 *addr; 691 int max_blks; 692 693 start = blknr; 694 blks = blkcnt; 695 addr = (u8 *)buffer; 696 697 max_blks = ATA_MAX_SECTORS_LBA48; 698 699 do { 700 if (blks > max_blks) { 701 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, 702 max_blks, addr, 703 is_write)) 704 return 0; 705 start += max_blks; 706 blks -= max_blks; 707 addr += ATA_SECT_SIZE * max_blks; 708 } else { 709 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks, 710 addr, is_write)) 711 return 0; 712 start += blks; 713 blks = 0; 714 addr += ATA_SECT_SIZE * blks; 715 } 716 } while (blks != 0); 717 718 return blkcnt; 719 } 720 721 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr, 722 lbaint_t blkcnt, const void *buffer, 723 int is_write) 724 { 725 u32 start, blks; 726 u8 *addr; 727 int max_blks; 728 729 start = blknr; 730 blks = blkcnt; 731 addr = (u8 *)buffer; 732 733 max_blks = ATA_MAX_SECTORS; 734 do { 735 if (blks > max_blks) { 736 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start, 737 max_blks, addr, 738 is_write)) 739 return 0; 740 start += max_blks; 741 blks -= max_blks; 742 addr += ATA_SECT_SIZE * max_blks; 743 } else { 744 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks, 745 addr, is_write)) 746 return 0; 747 start += blks; 748 blks = 0; 749 addr += ATA_SECT_SIZE * blks; 750 } 751 } while (blks != 0); 752 753 return blkcnt; 754 } 755 756 int init_sata(int dev) 757 { 758 int i; 759 u32 linkmap; 760 struct ahci_uc_priv *uc_priv = NULL; 761 762 #if defined(CONFIG_MX6) 763 if (!is_mx6dq() && !is_mx6dqp()) 764 return 1; 765 #endif 766 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 767 printf("The sata index %d is out of ranges\n\r", dev); 768 return -1; 769 } 770 771 ahci_init_one(dev); 772 773 uc_priv = sata_dev_desc[dev].priv; 774 linkmap = uc_priv->link_port_map; 775 776 if (0 == linkmap) { 777 printf("No port device detected!\n"); 778 return 1; 779 } 780 781 for (i = 0; i < uc_priv->n_ports; i++) { 782 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { 783 if (ahci_port_start(uc_priv, (u8)i)) { 784 printf("Can not start port %d\n", i); 785 return 1; 786 } 787 uc_priv->hard_port_no = i; 788 break; 789 } 790 } 791 792 return 0; 793 } 794 795 int reset_sata(int dev) 796 { 797 struct ahci_uc_priv *uc_priv; 798 struct sata_host_regs *host_mmio; 799 800 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 801 printf("The sata index %d is out of ranges\n\r", dev); 802 return -1; 803 } 804 805 uc_priv = sata_dev_desc[dev].priv; 806 if (NULL == uc_priv) 807 /* not initialized, so nothing to reset */ 808 return 0; 809 810 host_mmio = uc_priv->mmio_base; 811 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); 812 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) 813 udelay(100); 814 815 return 0; 816 } 817 818 int sata_port_status(int dev, int port) 819 { 820 struct sata_port_regs *port_mmio; 821 struct ahci_uc_priv *uc_priv = NULL; 822 823 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) 824 return -EINVAL; 825 826 if (sata_dev_desc[dev].priv == NULL) 827 return -ENODEV; 828 829 uc_priv = sata_dev_desc[dev].priv; 830 port_mmio = uc_priv->port[port].port_mmio; 831 832 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; 833 } 834 835 /* 836 * SATA interface between low level driver and command layer 837 */ 838 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) 839 { 840 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 841 u32 rc; 842 843 if (sata_dev_desc[dev].lba48) 844 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, 845 buffer, READ_CMD); 846 else 847 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, 848 buffer, READ_CMD); 849 return rc; 850 } 851 852 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) 853 { 854 u32 rc; 855 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 856 u32 flags = uc_priv->flags; 857 858 if (sata_dev_desc[dev].lba48) { 859 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, 860 WRITE_CMD); 861 if ((flags & SATA_FLAG_WCACHE) && 862 (flags & SATA_FLAG_FLUSH_EXT)) 863 dwc_ahsata_flush_cache_ext(uc_priv); 864 } else { 865 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, 866 WRITE_CMD); 867 if ((flags & SATA_FLAG_WCACHE) && 868 (flags & SATA_FLAG_FLUSH)) 869 dwc_ahsata_flush_cache(uc_priv); 870 } 871 return rc; 872 } 873 874 int scan_sata(int dev) 875 { 876 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; 877 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; 878 u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; 879 u16 *id; 880 u64 n_sectors; 881 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 882 u8 port = uc_priv->hard_port_no; 883 struct blk_desc *pdev = &sata_dev_desc[dev]; 884 885 id = (u16 *)memalign(ARCH_DMA_MINALIGN, 886 roundup(ARCH_DMA_MINALIGN, 887 (ATA_ID_WORDS * 2))); 888 if (!id) { 889 printf("id malloc failed\n\r"); 890 return -1; 891 } 892 893 /* Identify device to get information */ 894 dwc_ahsata_identify(uc_priv, id); 895 896 /* Serial number */ 897 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); 898 memcpy(pdev->product, serial, sizeof(serial)); 899 900 /* Firmware version */ 901 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); 902 memcpy(pdev->revision, firmware, sizeof(firmware)); 903 904 /* Product model */ 905 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); 906 memcpy(pdev->vendor, product, sizeof(product)); 907 908 /* Totoal sectors */ 909 n_sectors = ata_id_n_sectors(id); 910 pdev->lba = (u32)n_sectors; 911 912 pdev->type = DEV_TYPE_HARDDISK; 913 pdev->blksz = ATA_SECT_SIZE; 914 pdev->lun = 0 ; 915 916 /* Check if support LBA48 */ 917 if (ata_id_has_lba48(id)) { 918 pdev->lba48 = 1; 919 debug("Device support LBA48\n\r"); 920 } 921 922 /* Get the NCQ queue depth from device */ 923 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK); 924 uc_priv->flags |= ata_id_queue_depth(id); 925 926 /* Get the xfer mode from device */ 927 dwc_ahsata_xfer_mode(uc_priv, id); 928 929 /* Get the write cache status from device */ 930 dwc_ahsata_init_wcache(uc_priv, id); 931 932 /* Set the xfer mode to highest speed */ 933 ahci_set_feature(uc_priv, port); 934 935 free((void *)id); 936 937 dwc_ahsata_print_info(&sata_dev_desc[dev]); 938 939 return 0; 940 } 941