1 /* 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 3 * Terry Lv <r65388@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <libata.h> 9 #include <ahci.h> 10 #include <fis.h> 11 #include <sata.h> 12 13 #include <common.h> 14 #include <malloc.h> 15 #include <linux/ctype.h> 16 #include <linux/errno.h> 17 #include <asm/io.h> 18 #include <linux/bitops.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/sys_proto.h> 21 #include "dwc_ahsata.h" 22 23 struct sata_port_regs { 24 u32 clb; 25 u32 clbu; 26 u32 fb; 27 u32 fbu; 28 u32 is; 29 u32 ie; 30 u32 cmd; 31 u32 res1[1]; 32 u32 tfd; 33 u32 sig; 34 u32 ssts; 35 u32 sctl; 36 u32 serr; 37 u32 sact; 38 u32 ci; 39 u32 sntf; 40 u32 res2[1]; 41 u32 dmacr; 42 u32 res3[1]; 43 u32 phycr; 44 u32 physr; 45 }; 46 47 struct sata_host_regs { 48 u32 cap; 49 u32 ghc; 50 u32 is; 51 u32 pi; 52 u32 vs; 53 u32 ccc_ctl; 54 u32 ccc_ports; 55 u32 res1[2]; 56 u32 cap2; 57 u32 res2[30]; 58 u32 bistafr; 59 u32 bistcr; 60 u32 bistfctr; 61 u32 bistsr; 62 u32 bistdecr; 63 u32 res3[2]; 64 u32 oobr; 65 u32 res4[8]; 66 u32 timer1ms; 67 u32 res5[1]; 68 u32 gparam1r; 69 u32 gparam2r; 70 u32 pparamr; 71 u32 testr; 72 u32 versionr; 73 u32 idr; 74 }; 75 76 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) 77 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) 78 79 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) 80 81 static int is_ready; 82 83 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) 84 { 85 return base + 0x100 + (port * 0x80); 86 } 87 88 static int waiting_for_cmd_completed(u8 *offset, 89 int timeout_msec, 90 u32 sign) 91 { 92 int i; 93 u32 status; 94 95 for (i = 0; 96 ((status = readl(offset)) & sign) && i < timeout_msec; 97 ++i) 98 mdelay(1); 99 100 return (i < timeout_msec) ? 0 : -1; 101 } 102 103 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) 104 { 105 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 106 107 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); 108 writel(0x02060b14, &host_mmio->oobr); 109 110 return 0; 111 } 112 113 static int ahci_host_init(struct ahci_uc_priv *uc_priv) 114 { 115 u32 tmp, cap_save, num_ports; 116 int i, j, timeout = 1000; 117 struct sata_port_regs *port_mmio = NULL; 118 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 119 int clk = mxc_get_clock(MXC_SATA_CLK); 120 121 cap_save = readl(&host_mmio->cap); 122 cap_save |= SATA_HOST_CAP_SSS; 123 124 /* global controller reset */ 125 tmp = readl(&host_mmio->ghc); 126 if ((tmp & SATA_HOST_GHC_HR) == 0) 127 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc); 128 129 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout) 130 ; 131 132 if (timeout <= 0) { 133 debug("controller reset failed (0x%x)\n", tmp); 134 return -1; 135 } 136 137 /* Set timer 1ms */ 138 writel(clk / 1000, &host_mmio->timer1ms); 139 140 ahci_setup_oobr(uc_priv, 0); 141 142 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc); 143 writel(cap_save, &host_mmio->cap); 144 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; 145 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi); 146 147 /* 148 * Determine which Ports are implemented by the DWC_ahsata, 149 * by reading the PI register. This bit map value aids the 150 * software to determine how many Ports are available and 151 * which Port registers need to be initialized. 152 */ 153 uc_priv->cap = readl(&host_mmio->cap); 154 uc_priv->port_map = readl(&host_mmio->pi); 155 156 /* Determine how many command slots the HBA supports */ 157 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1; 158 159 debug("cap 0x%x port_map 0x%x n_ports %d\n", 160 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); 161 162 for (i = 0; i < uc_priv->n_ports; i++) { 163 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); 164 port_mmio = uc_priv->port[i].port_mmio; 165 166 /* Ensure that the DWC_ahsata is in idle state */ 167 tmp = readl(&port_mmio->cmd); 168 169 /* 170 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR 171 * are all cleared, the Port is in an idle state. 172 */ 173 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | 174 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { 175 176 /* 177 * System software places a Port into the idle state by 178 * clearing P#CMD.ST and waiting for P#CMD.CR to return 179 * 0 when read. 180 */ 181 tmp &= ~SATA_PORT_CMD_ST; 182 writel_with_flush(tmp, &port_mmio->cmd); 183 184 /* 185 * spec says 500 msecs for each bit, so 186 * this is slightly incorrect. 187 */ 188 mdelay(500); 189 190 timeout = 1000; 191 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) 192 && --timeout) 193 ; 194 195 if (timeout <= 0) { 196 debug("port reset failed (0x%x)\n", tmp); 197 return -1; 198 } 199 } 200 201 /* Spin-up device */ 202 tmp = readl(&port_mmio->cmd); 203 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd); 204 205 /* Wait for spin-up to finish */ 206 timeout = 1000; 207 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) 208 && --timeout) 209 ; 210 if (timeout <= 0) { 211 debug("Spin-Up can't finish!\n"); 212 return -1; 213 } 214 215 for (j = 0; j < 100; ++j) { 216 mdelay(10); 217 tmp = readl(&port_mmio->ssts); 218 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || 219 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) 220 break; 221 } 222 223 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ 224 timeout = 1000; 225 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) 226 && --timeout) 227 ; 228 if (timeout <= 0) { 229 debug("Can't find DIAG_X set!\n"); 230 return -1; 231 } 232 233 /* 234 * For each implemented Port, clear the P#SERR 235 * register, by writing ones to each implemented\ 236 * bit location. 237 */ 238 tmp = readl(&port_mmio->serr); 239 debug("P#SERR 0x%x\n", 240 tmp); 241 writel(tmp, &port_mmio->serr); 242 243 /* Ack any pending irq events for this port */ 244 tmp = readl(&host_mmio->is); 245 debug("IS 0x%x\n", tmp); 246 if (tmp) 247 writel(tmp, &host_mmio->is); 248 249 writel(1 << i, &host_mmio->is); 250 251 /* set irq mask (enables interrupts) */ 252 writel(DEF_PORT_IRQ, &port_mmio->ie); 253 254 /* register linkup ports */ 255 tmp = readl(&port_mmio->ssts); 256 debug("Port %d status: 0x%x\n", i, tmp); 257 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) 258 uc_priv->link_port_map |= (0x01 << i); 259 } 260 261 tmp = readl(&host_mmio->ghc); 262 debug("GHC 0x%x\n", tmp); 263 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc); 264 tmp = readl(&host_mmio->ghc); 265 debug("GHC 0x%x\n", tmp); 266 267 return 0; 268 } 269 270 static void ahci_print_info(struct ahci_uc_priv *uc_priv) 271 { 272 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 273 u32 vers, cap, impl, speed; 274 const char *speed_s; 275 const char *scc_s; 276 277 vers = readl(&host_mmio->vs); 278 cap = uc_priv->cap; 279 impl = uc_priv->port_map; 280 281 speed = (cap & SATA_HOST_CAP_ISS_MASK) 282 >> SATA_HOST_CAP_ISS_OFFSET; 283 if (speed == 1) 284 speed_s = "1.5"; 285 else if (speed == 2) 286 speed_s = "3"; 287 else 288 speed_s = "?"; 289 290 scc_s = "SATA"; 291 292 printf("AHCI %02x%02x.%02x%02x " 293 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 294 (vers >> 24) & 0xff, 295 (vers >> 16) & 0xff, 296 (vers >> 8) & 0xff, 297 vers & 0xff, 298 ((cap >> 8) & 0x1f) + 1, 299 (cap & 0x1f) + 1, 300 speed_s, 301 impl, 302 scc_s); 303 304 printf("flags: " 305 "%s%s%s%s%s%s" 306 "%s%s%s%s%s%s%s\n", 307 cap & (1 << 31) ? "64bit " : "", 308 cap & (1 << 30) ? "ncq " : "", 309 cap & (1 << 28) ? "ilck " : "", 310 cap & (1 << 27) ? "stag " : "", 311 cap & (1 << 26) ? "pm " : "", 312 cap & (1 << 25) ? "led " : "", 313 cap & (1 << 24) ? "clo " : "", 314 cap & (1 << 19) ? "nz " : "", 315 cap & (1 << 18) ? "only " : "", 316 cap & (1 << 17) ? "pmp " : "", 317 cap & (1 << 15) ? "pio " : "", 318 cap & (1 << 14) ? "slum " : "", 319 cap & (1 << 13) ? "part " : ""); 320 } 321 322 static int ahci_init_one(int pdev) 323 { 324 int rc; 325 struct ahci_uc_priv *uc_priv = NULL; 326 327 uc_priv = malloc(sizeof(struct ahci_uc_priv)); 328 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 329 uc_priv->dev = pdev; 330 331 uc_priv->host_flags = ATA_FLAG_SATA 332 | ATA_FLAG_NO_LEGACY 333 | ATA_FLAG_MMIO 334 | ATA_FLAG_PIO_DMA 335 | ATA_FLAG_NO_ATAPI; 336 337 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; 338 339 /* initialize adapter */ 340 rc = ahci_host_init(uc_priv); 341 if (rc) 342 goto err_out; 343 344 ahci_print_info(uc_priv); 345 346 /* Save the uc_private struct to block device struct */ 347 sata_dev_desc[pdev].priv = uc_priv; 348 349 return 0; 350 351 err_out: 352 return rc; 353 } 354 355 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, 356 unsigned char *buf, int buf_len) 357 { 358 struct ahci_ioports *pp = &uc_priv->port[port]; 359 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 360 u32 sg_count, max_bytes; 361 int i; 362 363 max_bytes = MAX_DATA_BYTES_PER_SG; 364 sg_count = ((buf_len - 1) / max_bytes) + 1; 365 if (sg_count > AHCI_MAX_SG) { 366 printf("Error:Too much sg!\n"); 367 return -1; 368 } 369 370 for (i = 0; i < sg_count; i++) { 371 ahci_sg->addr = 372 cpu_to_le32((u32)buf + i * max_bytes); 373 ahci_sg->addr_hi = 0; 374 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 375 (buf_len < max_bytes 376 ? (buf_len - 1) 377 : (max_bytes - 1))); 378 ahci_sg++; 379 buf_len -= max_bytes; 380 } 381 382 return sg_count; 383 } 384 385 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) 386 { 387 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + 388 AHCI_CMD_SLOT_SZ * cmd_slot); 389 390 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); 391 cmd_hdr->opts = cpu_to_le32(opts); 392 cmd_hdr->status = 0; 393 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 394 #ifdef CONFIG_PHYS_64BIT 395 pp->cmd_slot->tbl_addr_hi = 396 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 397 #endif 398 } 399 400 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) 401 402 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, 403 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len, 404 s32 is_write) 405 { 406 struct ahci_ioports *pp = &uc_priv->port[port]; 407 struct sata_port_regs *port_mmio = pp->port_mmio; 408 u32 opts; 409 int sg_count = 0, cmd_slot = 0; 410 411 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci)); 412 if (32 == cmd_slot) { 413 printf("Can't find empty command slot!\n"); 414 return 0; 415 } 416 417 /* Check xfer length */ 418 if (buf_len > MAX_BYTES_PER_TRANS) { 419 printf("Max transfer length is %dB\n\r", 420 MAX_BYTES_PER_TRANS); 421 return 0; 422 } 423 424 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); 425 if (buf && buf_len) 426 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); 427 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); 428 if (is_write) { 429 opts |= 0x40; 430 flush_cache((ulong)buf, buf_len); 431 } 432 ahci_fill_cmd_slot(pp, cmd_slot, opts); 433 434 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); 435 writel_with_flush(1 << cmd_slot, &port_mmio->ci); 436 437 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, 438 0x1 << cmd_slot)) { 439 printf("timeout exit!\n"); 440 return -1; 441 } 442 invalidate_dcache_range((int)(pp->cmd_slot), 443 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); 444 debug("ahci_exec_ata_cmd: %d byte transferred.\n", 445 pp->cmd_slot->status); 446 if (!is_write) 447 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len); 448 449 return buf_len; 450 } 451 452 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port) 453 { 454 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 455 struct sata_fis_h2d *cfis = &h2d; 456 457 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 458 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 459 cfis->pm_port_c = 1 << 7; 460 cfis->command = ATA_CMD_SET_FEATURES; 461 cfis->features = SETFEATURES_XFER; 462 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e; 463 464 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD); 465 } 466 467 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) 468 { 469 struct ahci_ioports *pp = &uc_priv->port[port]; 470 struct sata_port_regs *port_mmio = pp->port_mmio; 471 u32 port_status; 472 u32 mem; 473 int timeout = 10000000; 474 475 debug("Enter start port: %d\n", port); 476 port_status = readl(&port_mmio->ssts); 477 debug("Port %d status: %x\n", port, port_status); 478 if ((port_status & 0xf) != 0x03) { 479 printf("No Link on this port!\n"); 480 return -1; 481 } 482 483 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); 484 if (!mem) { 485 free(pp); 486 printf("No mem for table!\n"); 487 return -ENOMEM; 488 } 489 490 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ 491 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); 492 493 /* 494 * First item in chunk of DMA memory: 32-slot command table, 495 * 32 bytes each in size 496 */ 497 pp->cmd_slot = (struct ahci_cmd_hdr *)mem; 498 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); 499 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); 500 501 /* 502 * Second item: Received-FIS area, 256-Byte aligned 503 */ 504 pp->rx_fis = mem; 505 mem += AHCI_RX_FIS_SZ; 506 507 /* 508 * Third item: data area for storing a single command 509 * and its scatter-gather table 510 */ 511 pp->cmd_tbl = mem; 512 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); 513 514 mem += AHCI_CMD_TBL_HDR; 515 516 writel_with_flush(0x00004444, &port_mmio->dmacr); 517 pp->cmd_tbl_sg = (struct ahci_sg *)mem; 518 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); 519 writel_with_flush(pp->rx_fis, &port_mmio->fb); 520 521 /* Enable FRE */ 522 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), 523 &port_mmio->cmd); 524 525 /* Wait device ready */ 526 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR | 527 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) 528 && --timeout) 529 ; 530 if (timeout <= 0) { 531 debug("Device not ready for BSY, DRQ and" 532 "ERR in TFD!\n"); 533 return -1; 534 } 535 536 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 537 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 538 PORT_CMD_START, &port_mmio->cmd); 539 540 debug("Exit start port %d\n", port); 541 542 return 0; 543 } 544 545 static void dwc_ahsata_print_info(struct blk_desc *pdev) 546 { 547 printf("SATA Device Info:\n\r"); 548 #ifdef CONFIG_SYS_64BIT_LBA 549 printf("S/N: %s\n\rProduct model number: %s\n\r" 550 "Firmware version: %s\n\rCapacity: %lld sectors\n\r", 551 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 552 #else 553 printf("S/N: %s\n\rProduct model number: %s\n\r" 554 "Firmware version: %s\n\rCapacity: %ld sectors\n\r", 555 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 556 #endif 557 } 558 559 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id) 560 { 561 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 562 struct sata_fis_h2d *cfis = &h2d; 563 u8 port = uc_priv->hard_port_no; 564 565 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 566 567 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 568 cfis->pm_port_c = 0x80; /* is command */ 569 cfis->command = ATA_CMD_ID_ATA; 570 571 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2, 572 READ_CMD); 573 ata_swap_buf_le16(id, ATA_ID_WORDS); 574 } 575 576 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id) 577 { 578 uc_priv->pio_mask = id[ATA_ID_PIO_MODES]; 579 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES]; 580 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask); 581 } 582 583 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start, 584 u32 blkcnt, u8 *buffer, int is_write) 585 { 586 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 587 struct sata_fis_h2d *cfis = &h2d; 588 u8 port = uc_priv->hard_port_no; 589 u32 block; 590 591 block = start; 592 593 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 594 595 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 596 cfis->pm_port_c = 0x80; /* is command */ 597 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; 598 cfis->device = ATA_LBA; 599 600 cfis->device |= (block >> 24) & 0xf; 601 cfis->lba_high = (block >> 16) & 0xff; 602 cfis->lba_mid = (block >> 8) & 0xff; 603 cfis->lba_low = block & 0xff; 604 cfis->sector_count = (u8)(blkcnt & 0xff); 605 606 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 607 ATA_SECT_SIZE * blkcnt, is_write) > 0) 608 return blkcnt; 609 else 610 return 0; 611 } 612 613 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv) 614 { 615 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 616 struct sata_fis_h2d *cfis = &h2d; 617 u8 port = uc_priv->hard_port_no; 618 619 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 620 621 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 622 cfis->pm_port_c = 0x80; /* is command */ 623 cfis->command = ATA_CMD_FLUSH; 624 625 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 626 } 627 628 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start, 629 lbaint_t blkcnt, u8 *buffer, int is_write) 630 { 631 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 632 struct sata_fis_h2d *cfis = &h2d; 633 u8 port = uc_priv->hard_port_no; 634 u64 block; 635 636 block = (u64)start; 637 638 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 639 640 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 641 cfis->pm_port_c = 0x80; /* is command */ 642 643 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT 644 : ATA_CMD_READ_EXT; 645 646 cfis->lba_high_exp = (block >> 40) & 0xff; 647 cfis->lba_mid_exp = (block >> 32) & 0xff; 648 cfis->lba_low_exp = (block >> 24) & 0xff; 649 cfis->lba_high = (block >> 16) & 0xff; 650 cfis->lba_mid = (block >> 8) & 0xff; 651 cfis->lba_low = block & 0xff; 652 cfis->device = ATA_LBA; 653 cfis->sector_count_exp = (blkcnt >> 8) & 0xff; 654 cfis->sector_count = blkcnt & 0xff; 655 656 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 657 ATA_SECT_SIZE * blkcnt, is_write) > 0) 658 return blkcnt; 659 else 660 return 0; 661 } 662 663 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv) 664 { 665 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 666 struct sata_fis_h2d *cfis = &h2d; 667 u8 port = uc_priv->hard_port_no; 668 669 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 670 671 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 672 cfis->pm_port_c = 0x80; /* is command */ 673 cfis->command = ATA_CMD_FLUSH_EXT; 674 675 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 676 } 677 678 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id) 679 { 680 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) 681 uc_priv->flags |= SATA_FLAG_WCACHE; 682 if (ata_id_has_flush(id)) 683 uc_priv->flags |= SATA_FLAG_FLUSH; 684 if (ata_id_has_flush_ext(id)) 685 uc_priv->flags |= SATA_FLAG_FLUSH_EXT; 686 } 687 688 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr, 689 lbaint_t blkcnt, const void *buffer, 690 int is_write) 691 { 692 u32 start, blks; 693 u8 *addr; 694 int max_blks; 695 696 start = blknr; 697 blks = blkcnt; 698 addr = (u8 *)buffer; 699 700 max_blks = ATA_MAX_SECTORS_LBA48; 701 702 do { 703 if (blks > max_blks) { 704 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, 705 max_blks, addr, 706 is_write)) 707 return 0; 708 start += max_blks; 709 blks -= max_blks; 710 addr += ATA_SECT_SIZE * max_blks; 711 } else { 712 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks, 713 addr, is_write)) 714 return 0; 715 start += blks; 716 blks = 0; 717 addr += ATA_SECT_SIZE * blks; 718 } 719 } while (blks != 0); 720 721 return blkcnt; 722 } 723 724 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr, 725 lbaint_t blkcnt, const void *buffer, 726 int is_write) 727 { 728 u32 start, blks; 729 u8 *addr; 730 int max_blks; 731 732 start = blknr; 733 blks = blkcnt; 734 addr = (u8 *)buffer; 735 736 max_blks = ATA_MAX_SECTORS; 737 do { 738 if (blks > max_blks) { 739 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start, 740 max_blks, addr, 741 is_write)) 742 return 0; 743 start += max_blks; 744 blks -= max_blks; 745 addr += ATA_SECT_SIZE * max_blks; 746 } else { 747 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks, 748 addr, is_write)) 749 return 0; 750 start += blks; 751 blks = 0; 752 addr += ATA_SECT_SIZE * blks; 753 } 754 } while (blks != 0); 755 756 return blkcnt; 757 } 758 759 int init_sata(int dev) 760 { 761 int i; 762 u32 linkmap; 763 struct ahci_uc_priv *uc_priv = NULL; 764 765 #if defined(CONFIG_MX6) 766 if (!is_mx6dq() && !is_mx6dqp()) 767 return 1; 768 #endif 769 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 770 printf("The sata index %d is out of ranges\n\r", dev); 771 return -1; 772 } 773 774 ahci_init_one(dev); 775 776 uc_priv = sata_dev_desc[dev].priv; 777 linkmap = uc_priv->link_port_map; 778 779 if (0 == linkmap) { 780 printf("No port device detected!\n"); 781 return 1; 782 } 783 784 for (i = 0; i < uc_priv->n_ports; i++) { 785 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { 786 if (ahci_port_start(uc_priv, (u8)i)) { 787 printf("Can not start port %d\n", i); 788 return 1; 789 } 790 uc_priv->hard_port_no = i; 791 break; 792 } 793 } 794 795 return 0; 796 } 797 798 int reset_sata(int dev) 799 { 800 struct ahci_uc_priv *uc_priv; 801 struct sata_host_regs *host_mmio; 802 803 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 804 printf("The sata index %d is out of ranges\n\r", dev); 805 return -1; 806 } 807 808 uc_priv = sata_dev_desc[dev].priv; 809 if (NULL == uc_priv) 810 /* not initialized, so nothing to reset */ 811 return 0; 812 813 host_mmio = uc_priv->mmio_base; 814 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); 815 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) 816 udelay(100); 817 818 return 0; 819 } 820 821 int sata_port_status(int dev, int port) 822 { 823 struct sata_port_regs *port_mmio; 824 struct ahci_uc_priv *uc_priv = NULL; 825 826 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) 827 return -EINVAL; 828 829 if (sata_dev_desc[dev].priv == NULL) 830 return -ENODEV; 831 832 uc_priv = sata_dev_desc[dev].priv; 833 port_mmio = uc_priv->port[port].port_mmio; 834 835 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; 836 } 837 838 /* 839 * SATA interface between low level driver and command layer 840 */ 841 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) 842 { 843 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 844 u32 rc; 845 846 if (sata_dev_desc[dev].lba48) 847 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, 848 buffer, READ_CMD); 849 else 850 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, 851 buffer, READ_CMD); 852 return rc; 853 } 854 855 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) 856 { 857 u32 rc; 858 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 859 u32 flags = uc_priv->flags; 860 861 if (sata_dev_desc[dev].lba48) { 862 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, 863 WRITE_CMD); 864 if ((flags & SATA_FLAG_WCACHE) && 865 (flags & SATA_FLAG_FLUSH_EXT)) 866 dwc_ahsata_flush_cache_ext(uc_priv); 867 } else { 868 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, 869 WRITE_CMD); 870 if ((flags & SATA_FLAG_WCACHE) && 871 (flags & SATA_FLAG_FLUSH)) 872 dwc_ahsata_flush_cache(uc_priv); 873 } 874 return rc; 875 } 876 877 int scan_sata(int dev) 878 { 879 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; 880 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; 881 u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; 882 u16 *id; 883 u64 n_sectors; 884 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 885 u8 port = uc_priv->hard_port_no; 886 struct blk_desc *pdev = &sata_dev_desc[dev]; 887 888 id = (u16 *)memalign(ARCH_DMA_MINALIGN, 889 roundup(ARCH_DMA_MINALIGN, 890 (ATA_ID_WORDS * 2))); 891 if (!id) { 892 printf("id malloc failed\n\r"); 893 return -1; 894 } 895 896 /* Identify device to get information */ 897 dwc_ahsata_identify(uc_priv, id); 898 899 /* Serial number */ 900 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); 901 memcpy(pdev->product, serial, sizeof(serial)); 902 903 /* Firmware version */ 904 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); 905 memcpy(pdev->revision, firmware, sizeof(firmware)); 906 907 /* Product model */ 908 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); 909 memcpy(pdev->vendor, product, sizeof(product)); 910 911 /* Totoal sectors */ 912 n_sectors = ata_id_n_sectors(id); 913 pdev->lba = (u32)n_sectors; 914 915 pdev->type = DEV_TYPE_HARDDISK; 916 pdev->blksz = ATA_SECT_SIZE; 917 pdev->lun = 0 ; 918 919 /* Check if support LBA48 */ 920 if (ata_id_has_lba48(id)) { 921 pdev->lba48 = 1; 922 debug("Device support LBA48\n\r"); 923 } 924 925 /* Get the NCQ queue depth from device */ 926 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK); 927 uc_priv->flags |= ata_id_queue_depth(id); 928 929 /* Get the xfer mode from device */ 930 dwc_ahsata_xfer_mode(uc_priv, id); 931 932 /* Get the write cache status from device */ 933 dwc_ahsata_init_wcache(uc_priv, id); 934 935 /* Set the xfer mode to highest speed */ 936 ahci_set_feature(uc_priv, port); 937 938 free((void *)id); 939 940 dwc_ahsata_print_info(&sata_dev_desc[dev]); 941 942 is_ready = 1; 943 944 return 0; 945 } 946