1 /* 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 3 * Terry Lv <r65388@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <libata.h> 9 #include <ahci.h> 10 #include <fis.h> 11 #include <sata.h> 12 13 #include <common.h> 14 #include <malloc.h> 15 #include <linux/ctype.h> 16 #include <linux/errno.h> 17 #include <asm/io.h> 18 #include <linux/bitops.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/sys_proto.h> 21 #include "dwc_ahsata.h" 22 23 struct sata_port_regs { 24 u32 clb; 25 u32 clbu; 26 u32 fb; 27 u32 fbu; 28 u32 is; 29 u32 ie; 30 u32 cmd; 31 u32 res1[1]; 32 u32 tfd; 33 u32 sig; 34 u32 ssts; 35 u32 sctl; 36 u32 serr; 37 u32 sact; 38 u32 ci; 39 u32 sntf; 40 u32 res2[1]; 41 u32 dmacr; 42 u32 res3[1]; 43 u32 phycr; 44 u32 physr; 45 }; 46 47 struct sata_host_regs { 48 u32 cap; 49 u32 ghc; 50 u32 is; 51 u32 pi; 52 u32 vs; 53 u32 ccc_ctl; 54 u32 ccc_ports; 55 u32 res1[2]; 56 u32 cap2; 57 u32 res2[30]; 58 u32 bistafr; 59 u32 bistcr; 60 u32 bistfctr; 61 u32 bistsr; 62 u32 bistdecr; 63 u32 res3[2]; 64 u32 oobr; 65 u32 res4[8]; 66 u32 timer1ms; 67 u32 res5[1]; 68 u32 gparam1r; 69 u32 gparam2r; 70 u32 pparamr; 71 u32 testr; 72 u32 versionr; 73 u32 idr; 74 }; 75 76 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) 77 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) 78 79 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) 80 81 static int is_ready; 82 83 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) 84 { 85 return base + 0x100 + (port * 0x80); 86 } 87 88 static int waiting_for_cmd_completed(u8 *offset, 89 int timeout_msec, 90 u32 sign) 91 { 92 int i; 93 u32 status; 94 95 for (i = 0; 96 ((status = readl(offset)) & sign) && i < timeout_msec; 97 ++i) 98 mdelay(1); 99 100 return (i < timeout_msec) ? 0 : -1; 101 } 102 103 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) 104 { 105 struct sata_host_regs *host_mmio = 106 (struct sata_host_regs *)uc_priv->mmio_base; 107 108 writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr)); 109 writel(0x02060b14, &(host_mmio->oobr)); 110 111 return 0; 112 } 113 114 static int ahci_host_init(struct ahci_uc_priv *uc_priv) 115 { 116 u32 tmp, cap_save, num_ports; 117 int i, j, timeout = 1000; 118 struct sata_port_regs *port_mmio = NULL; 119 struct sata_host_regs *host_mmio = 120 (struct sata_host_regs *)uc_priv->mmio_base; 121 int clk = mxc_get_clock(MXC_SATA_CLK); 122 123 cap_save = readl(&(host_mmio->cap)); 124 cap_save |= SATA_HOST_CAP_SSS; 125 126 /* global controller reset */ 127 tmp = readl(&(host_mmio->ghc)); 128 if ((tmp & SATA_HOST_GHC_HR) == 0) 129 writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc)); 130 131 while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR) 132 && --timeout) 133 ; 134 135 if (timeout <= 0) { 136 debug("controller reset failed (0x%x)\n", tmp); 137 return -1; 138 } 139 140 /* Set timer 1ms */ 141 writel(clk / 1000, &(host_mmio->timer1ms)); 142 143 ahci_setup_oobr(uc_priv, 0); 144 145 writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc)); 146 writel(cap_save, &(host_mmio->cap)); 147 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; 148 writel_with_flush((1 << num_ports) - 1, 149 &(host_mmio->pi)); 150 151 /* 152 * Determine which Ports are implemented by the DWC_ahsata, 153 * by reading the PI register. This bit map value aids the 154 * software to determine how many Ports are available and 155 * which Port registers need to be initialized. 156 */ 157 uc_priv->cap = readl(&(host_mmio->cap)); 158 uc_priv->port_map = readl(&(host_mmio->pi)); 159 160 /* Determine how many command slots the HBA supports */ 161 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1; 162 163 debug("cap 0x%x port_map 0x%x n_ports %d\n", 164 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); 165 166 for (i = 0; i < uc_priv->n_ports; i++) { 167 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); 168 port_mmio = 169 (struct sata_port_regs *)uc_priv->port[i].port_mmio; 170 171 /* Ensure that the DWC_ahsata is in idle state */ 172 tmp = readl(&(port_mmio->cmd)); 173 174 /* 175 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR 176 * are all cleared, the Port is in an idle state. 177 */ 178 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | 179 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { 180 181 /* 182 * System software places a Port into the idle state by 183 * clearing P#CMD.ST and waiting for P#CMD.CR to return 184 * 0 when read. 185 */ 186 tmp &= ~SATA_PORT_CMD_ST; 187 writel_with_flush(tmp, &(port_mmio->cmd)); 188 189 /* 190 * spec says 500 msecs for each bit, so 191 * this is slightly incorrect. 192 */ 193 mdelay(500); 194 195 timeout = 1000; 196 while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR) 197 && --timeout) 198 ; 199 200 if (timeout <= 0) { 201 debug("port reset failed (0x%x)\n", tmp); 202 return -1; 203 } 204 } 205 206 /* Spin-up device */ 207 tmp = readl(&(port_mmio->cmd)); 208 writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd)); 209 210 /* Wait for spin-up to finish */ 211 timeout = 1000; 212 while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD) 213 && --timeout) 214 ; 215 if (timeout <= 0) { 216 debug("Spin-Up can't finish!\n"); 217 return -1; 218 } 219 220 for (j = 0; j < 100; ++j) { 221 mdelay(10); 222 tmp = readl(&(port_mmio->ssts)); 223 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || 224 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) 225 break; 226 } 227 228 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ 229 timeout = 1000; 230 while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X) 231 && --timeout) 232 ; 233 if (timeout <= 0) { 234 debug("Can't find DIAG_X set!\n"); 235 return -1; 236 } 237 238 /* 239 * For each implemented Port, clear the P#SERR 240 * register, by writing ones to each implemented\ 241 * bit location. 242 */ 243 tmp = readl(&(port_mmio->serr)); 244 debug("P#SERR 0x%x\n", 245 tmp); 246 writel(tmp, &(port_mmio->serr)); 247 248 /* Ack any pending irq events for this port */ 249 tmp = readl(&(host_mmio->is)); 250 debug("IS 0x%x\n", tmp); 251 if (tmp) 252 writel(tmp, &(host_mmio->is)); 253 254 writel(1 << i, &(host_mmio->is)); 255 256 /* set irq mask (enables interrupts) */ 257 writel(DEF_PORT_IRQ, &(port_mmio->ie)); 258 259 /* register linkup ports */ 260 tmp = readl(&(port_mmio->ssts)); 261 debug("Port %d status: 0x%x\n", i, tmp); 262 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) 263 uc_priv->link_port_map |= (0x01 << i); 264 } 265 266 tmp = readl(&(host_mmio->ghc)); 267 debug("GHC 0x%x\n", tmp); 268 writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc)); 269 tmp = readl(&(host_mmio->ghc)); 270 debug("GHC 0x%x\n", tmp); 271 272 return 0; 273 } 274 275 static void ahci_print_info(struct ahci_uc_priv *uc_priv) 276 { 277 struct sata_host_regs *host_mmio = 278 (struct sata_host_regs *)uc_priv->mmio_base; 279 u32 vers, cap, impl, speed; 280 const char *speed_s; 281 const char *scc_s; 282 283 vers = readl(&(host_mmio->vs)); 284 cap = uc_priv->cap; 285 impl = uc_priv->port_map; 286 287 speed = (cap & SATA_HOST_CAP_ISS_MASK) 288 >> SATA_HOST_CAP_ISS_OFFSET; 289 if (speed == 1) 290 speed_s = "1.5"; 291 else if (speed == 2) 292 speed_s = "3"; 293 else 294 speed_s = "?"; 295 296 scc_s = "SATA"; 297 298 printf("AHCI %02x%02x.%02x%02x " 299 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 300 (vers >> 24) & 0xff, 301 (vers >> 16) & 0xff, 302 (vers >> 8) & 0xff, 303 vers & 0xff, 304 ((cap >> 8) & 0x1f) + 1, 305 (cap & 0x1f) + 1, 306 speed_s, 307 impl, 308 scc_s); 309 310 printf("flags: " 311 "%s%s%s%s%s%s" 312 "%s%s%s%s%s%s%s\n", 313 cap & (1 << 31) ? "64bit " : "", 314 cap & (1 << 30) ? "ncq " : "", 315 cap & (1 << 28) ? "ilck " : "", 316 cap & (1 << 27) ? "stag " : "", 317 cap & (1 << 26) ? "pm " : "", 318 cap & (1 << 25) ? "led " : "", 319 cap & (1 << 24) ? "clo " : "", 320 cap & (1 << 19) ? "nz " : "", 321 cap & (1 << 18) ? "only " : "", 322 cap & (1 << 17) ? "pmp " : "", 323 cap & (1 << 15) ? "pio " : "", 324 cap & (1 << 14) ? "slum " : "", 325 cap & (1 << 13) ? "part " : ""); 326 } 327 328 static int ahci_init_one(int pdev) 329 { 330 int rc; 331 struct ahci_uc_priv *uc_priv = NULL; 332 333 uc_priv = malloc(sizeof(struct ahci_uc_priv)); 334 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 335 uc_priv->dev = pdev; 336 337 uc_priv->host_flags = ATA_FLAG_SATA 338 | ATA_FLAG_NO_LEGACY 339 | ATA_FLAG_MMIO 340 | ATA_FLAG_PIO_DMA 341 | ATA_FLAG_NO_ATAPI; 342 343 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; 344 345 /* initialize adapter */ 346 rc = ahci_host_init(uc_priv); 347 if (rc) 348 goto err_out; 349 350 ahci_print_info(uc_priv); 351 352 /* Save the uc_private struct to block device struct */ 353 sata_dev_desc[pdev].priv = (void *)uc_priv; 354 355 return 0; 356 357 err_out: 358 return rc; 359 } 360 361 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, 362 unsigned char *buf, int buf_len) 363 { 364 struct ahci_ioports *pp = &(uc_priv->port[port]); 365 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 366 u32 sg_count, max_bytes; 367 int i; 368 369 max_bytes = MAX_DATA_BYTES_PER_SG; 370 sg_count = ((buf_len - 1) / max_bytes) + 1; 371 if (sg_count > AHCI_MAX_SG) { 372 printf("Error:Too much sg!\n"); 373 return -1; 374 } 375 376 for (i = 0; i < sg_count; i++) { 377 ahci_sg->addr = 378 cpu_to_le32((u32)buf + i * max_bytes); 379 ahci_sg->addr_hi = 0; 380 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 381 (buf_len < max_bytes 382 ? (buf_len - 1) 383 : (max_bytes - 1))); 384 ahci_sg++; 385 buf_len -= max_bytes; 386 } 387 388 return sg_count; 389 } 390 391 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) 392 { 393 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + 394 AHCI_CMD_SLOT_SZ * cmd_slot); 395 396 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); 397 cmd_hdr->opts = cpu_to_le32(opts); 398 cmd_hdr->status = 0; 399 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 400 #ifdef CONFIG_PHYS_64BIT 401 pp->cmd_slot->tbl_addr_hi = 402 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 403 #endif 404 } 405 406 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) 407 408 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, 409 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len, 410 s32 is_write) 411 { 412 struct ahci_ioports *pp = &(uc_priv->port[port]); 413 struct sata_port_regs *port_mmio = 414 (struct sata_port_regs *)pp->port_mmio; 415 u32 opts; 416 int sg_count = 0, cmd_slot = 0; 417 418 cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci))); 419 if (32 == cmd_slot) { 420 printf("Can't find empty command slot!\n"); 421 return 0; 422 } 423 424 /* Check xfer length */ 425 if (buf_len > MAX_BYTES_PER_TRANS) { 426 printf("Max transfer length is %dB\n\r", 427 MAX_BYTES_PER_TRANS); 428 return 0; 429 } 430 431 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); 432 if (buf && buf_len) 433 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); 434 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); 435 if (is_write) { 436 opts |= 0x40; 437 flush_cache((ulong)buf, buf_len); 438 } 439 ahci_fill_cmd_slot(pp, cmd_slot, opts); 440 441 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); 442 writel_with_flush(1 << cmd_slot, &(port_mmio->ci)); 443 444 if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci), 445 10000, 0x1 << cmd_slot)) { 446 printf("timeout exit!\n"); 447 return -1; 448 } 449 invalidate_dcache_range((int)(pp->cmd_slot), 450 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); 451 debug("ahci_exec_ata_cmd: %d byte transferred.\n", 452 pp->cmd_slot->status); 453 if (!is_write) 454 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len); 455 456 return buf_len; 457 } 458 459 static void ahci_set_feature(u8 dev, u8 port) 460 { 461 struct ahci_uc_priv *uc_priv = 462 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 463 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 464 struct sata_fis_h2d *cfis = &h2d; 465 466 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 467 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 468 cfis->pm_port_c = 1 << 7; 469 cfis->command = ATA_CMD_SET_FEATURES; 470 cfis->features = SETFEATURES_XFER; 471 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e; 472 473 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD); 474 } 475 476 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) 477 { 478 struct ahci_ioports *pp = &(uc_priv->port[port]); 479 struct sata_port_regs *port_mmio = 480 (struct sata_port_regs *)pp->port_mmio; 481 u32 port_status; 482 u32 mem; 483 int timeout = 10000000; 484 485 debug("Enter start port: %d\n", port); 486 port_status = readl(&(port_mmio->ssts)); 487 debug("Port %d status: %x\n", port, port_status); 488 if ((port_status & 0xf) != 0x03) { 489 printf("No Link on this port!\n"); 490 return -1; 491 } 492 493 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); 494 if (!mem) { 495 free(pp); 496 printf("No mem for table!\n"); 497 return -ENOMEM; 498 } 499 500 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ 501 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); 502 503 /* 504 * First item in chunk of DMA memory: 32-slot command table, 505 * 32 bytes each in size 506 */ 507 pp->cmd_slot = (struct ahci_cmd_hdr *)mem; 508 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); 509 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); 510 511 /* 512 * Second item: Received-FIS area, 256-Byte aligned 513 */ 514 pp->rx_fis = mem; 515 mem += AHCI_RX_FIS_SZ; 516 517 /* 518 * Third item: data area for storing a single command 519 * and its scatter-gather table 520 */ 521 pp->cmd_tbl = mem; 522 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); 523 524 mem += AHCI_CMD_TBL_HDR; 525 526 writel_with_flush(0x00004444, &(port_mmio->dmacr)); 527 pp->cmd_tbl_sg = (struct ahci_sg *)mem; 528 writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb)); 529 writel_with_flush(pp->rx_fis, &(port_mmio->fb)); 530 531 /* Enable FRE */ 532 writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))), 533 &(port_mmio->cmd)); 534 535 /* Wait device ready */ 536 while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR | 537 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) 538 && --timeout) 539 ; 540 if (timeout <= 0) { 541 debug("Device not ready for BSY, DRQ and" 542 "ERR in TFD!\n"); 543 return -1; 544 } 545 546 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 547 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 548 PORT_CMD_START, &(port_mmio->cmd)); 549 550 debug("Exit start port %d\n", port); 551 552 return 0; 553 } 554 555 static void dwc_ahsata_print_info(int dev) 556 { 557 struct blk_desc *pdev = &(sata_dev_desc[dev]); 558 559 printf("SATA Device Info:\n\r"); 560 #ifdef CONFIG_SYS_64BIT_LBA 561 printf("S/N: %s\n\rProduct model number: %s\n\r" 562 "Firmware version: %s\n\rCapacity: %lld sectors\n\r", 563 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 564 #else 565 printf("S/N: %s\n\rProduct model number: %s\n\r" 566 "Firmware version: %s\n\rCapacity: %ld sectors\n\r", 567 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 568 #endif 569 } 570 571 static void dwc_ahsata_identify(int dev, u16 *id) 572 { 573 struct ahci_uc_priv *uc_priv = 574 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 575 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 576 struct sata_fis_h2d *cfis = &h2d; 577 u8 port = uc_priv->hard_port_no; 578 579 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 580 581 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 582 cfis->pm_port_c = 0x80; /* is command */ 583 cfis->command = ATA_CMD_ID_ATA; 584 585 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2, 586 READ_CMD); 587 ata_swap_buf_le16(id, ATA_ID_WORDS); 588 } 589 590 static void dwc_ahsata_xfer_mode(int dev, u16 *id) 591 { 592 struct ahci_uc_priv *uc_priv = 593 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 594 595 uc_priv->pio_mask = id[ATA_ID_PIO_MODES]; 596 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES]; 597 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask); 598 } 599 600 static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt, 601 u8 *buffer, int is_write) 602 { 603 struct ahci_uc_priv *uc_priv = 604 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 605 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 606 struct sata_fis_h2d *cfis = &h2d; 607 u8 port = uc_priv->hard_port_no; 608 u32 block; 609 610 block = start; 611 612 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 613 614 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 615 cfis->pm_port_c = 0x80; /* is command */ 616 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; 617 cfis->device = ATA_LBA; 618 619 cfis->device |= (block >> 24) & 0xf; 620 cfis->lba_high = (block >> 16) & 0xff; 621 cfis->lba_mid = (block >> 8) & 0xff; 622 cfis->lba_low = block & 0xff; 623 cfis->sector_count = (u8)(blkcnt & 0xff); 624 625 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 626 ATA_SECT_SIZE * blkcnt, is_write) > 0) 627 return blkcnt; 628 else 629 return 0; 630 } 631 632 static void dwc_ahsata_flush_cache(int dev) 633 { 634 struct ahci_uc_priv *uc_priv = 635 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 636 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 637 struct sata_fis_h2d *cfis = &h2d; 638 u8 port = uc_priv->hard_port_no; 639 640 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 641 642 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 643 cfis->pm_port_c = 0x80; /* is command */ 644 cfis->command = ATA_CMD_FLUSH; 645 646 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 647 } 648 649 static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt, 650 u8 *buffer, int is_write) 651 { 652 struct ahci_uc_priv *uc_priv = 653 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 654 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 655 struct sata_fis_h2d *cfis = &h2d; 656 u8 port = uc_priv->hard_port_no; 657 u64 block; 658 659 block = (u64)start; 660 661 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 662 663 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 664 cfis->pm_port_c = 0x80; /* is command */ 665 666 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT 667 : ATA_CMD_READ_EXT; 668 669 cfis->lba_high_exp = (block >> 40) & 0xff; 670 cfis->lba_mid_exp = (block >> 32) & 0xff; 671 cfis->lba_low_exp = (block >> 24) & 0xff; 672 cfis->lba_high = (block >> 16) & 0xff; 673 cfis->lba_mid = (block >> 8) & 0xff; 674 cfis->lba_low = block & 0xff; 675 cfis->device = ATA_LBA; 676 cfis->sector_count_exp = (blkcnt >> 8) & 0xff; 677 cfis->sector_count = blkcnt & 0xff; 678 679 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 680 ATA_SECT_SIZE * blkcnt, is_write) > 0) 681 return blkcnt; 682 else 683 return 0; 684 } 685 686 static void dwc_ahsata_flush_cache_ext(int dev) 687 { 688 struct ahci_uc_priv *uc_priv = 689 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 690 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 691 struct sata_fis_h2d *cfis = &h2d; 692 u8 port = uc_priv->hard_port_no; 693 694 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 695 696 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 697 cfis->pm_port_c = 0x80; /* is command */ 698 cfis->command = ATA_CMD_FLUSH_EXT; 699 700 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 701 } 702 703 static void dwc_ahsata_init_wcache(int dev, u16 *id) 704 { 705 struct ahci_uc_priv *uc_priv = 706 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 707 708 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) 709 uc_priv->flags |= SATA_FLAG_WCACHE; 710 if (ata_id_has_flush(id)) 711 uc_priv->flags |= SATA_FLAG_FLUSH; 712 if (ata_id_has_flush_ext(id)) 713 uc_priv->flags |= SATA_FLAG_FLUSH_EXT; 714 } 715 716 static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt, 717 const void *buffer, int is_write) 718 { 719 u32 start, blks; 720 u8 *addr; 721 int max_blks; 722 723 start = blknr; 724 blks = blkcnt; 725 addr = (u8 *)buffer; 726 727 max_blks = ATA_MAX_SECTORS_LBA48; 728 729 do { 730 if (blks > max_blks) { 731 if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start, 732 max_blks, addr, is_write)) 733 return 0; 734 start += max_blks; 735 blks -= max_blks; 736 addr += ATA_SECT_SIZE * max_blks; 737 } else { 738 if (blks != dwc_ahsata_rw_cmd_ext(dev, start, 739 blks, addr, is_write)) 740 return 0; 741 start += blks; 742 blks = 0; 743 addr += ATA_SECT_SIZE * blks; 744 } 745 } while (blks != 0); 746 747 return blkcnt; 748 } 749 750 static u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt, 751 const void *buffer, int is_write) 752 { 753 u32 start, blks; 754 u8 *addr; 755 int max_blks; 756 757 start = blknr; 758 blks = blkcnt; 759 addr = (u8 *)buffer; 760 761 max_blks = ATA_MAX_SECTORS; 762 do { 763 if (blks > max_blks) { 764 if (max_blks != dwc_ahsata_rw_cmd(dev, start, 765 max_blks, addr, is_write)) 766 return 0; 767 start += max_blks; 768 blks -= max_blks; 769 addr += ATA_SECT_SIZE * max_blks; 770 } else { 771 if (blks != dwc_ahsata_rw_cmd(dev, start, 772 blks, addr, is_write)) 773 return 0; 774 start += blks; 775 blks = 0; 776 addr += ATA_SECT_SIZE * blks; 777 } 778 } while (blks != 0); 779 780 return blkcnt; 781 } 782 783 int init_sata(int dev) 784 { 785 int i; 786 u32 linkmap; 787 struct ahci_uc_priv *uc_priv = NULL; 788 789 #if defined(CONFIG_MX6) 790 if (!is_mx6dq() && !is_mx6dqp()) 791 return 1; 792 #endif 793 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 794 printf("The sata index %d is out of ranges\n\r", dev); 795 return -1; 796 } 797 798 ahci_init_one(dev); 799 800 uc_priv = (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 801 linkmap = uc_priv->link_port_map; 802 803 if (0 == linkmap) { 804 printf("No port device detected!\n"); 805 return 1; 806 } 807 808 for (i = 0; i < uc_priv->n_ports; i++) { 809 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { 810 if (ahci_port_start(uc_priv, (u8)i)) { 811 printf("Can not start port %d\n", i); 812 return 1; 813 } 814 uc_priv->hard_port_no = i; 815 break; 816 } 817 } 818 819 return 0; 820 } 821 822 int reset_sata(int dev) 823 { 824 struct ahci_uc_priv *uc_priv; 825 struct sata_host_regs *host_mmio; 826 827 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 828 printf("The sata index %d is out of ranges\n\r", dev); 829 return -1; 830 } 831 832 uc_priv = (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 833 if (NULL == uc_priv) 834 /* not initialized, so nothing to reset */ 835 return 0; 836 837 host_mmio = (struct sata_host_regs *)uc_priv->mmio_base; 838 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); 839 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) 840 udelay(100); 841 842 return 0; 843 } 844 845 int sata_port_status(int dev, int port) 846 { 847 struct sata_port_regs *port_mmio; 848 struct ahci_uc_priv *uc_priv = NULL; 849 850 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) 851 return -EINVAL; 852 853 if (sata_dev_desc[dev].priv == NULL) 854 return -ENODEV; 855 856 uc_priv = (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 857 port_mmio = (struct sata_port_regs *)uc_priv->port[port].port_mmio; 858 859 return readl(&(port_mmio->ssts)) & SATA_PORT_SSTS_DET_MASK; 860 } 861 862 /* 863 * SATA interface between low level driver and command layer 864 */ 865 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) 866 { 867 u32 rc; 868 869 if (sata_dev_desc[dev].lba48) 870 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, 871 buffer, READ_CMD); 872 else 873 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, 874 buffer, READ_CMD); 875 return rc; 876 } 877 878 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) 879 { 880 u32 rc; 881 struct ahci_uc_priv *uc_priv = 882 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 883 u32 flags = uc_priv->flags; 884 885 if (sata_dev_desc[dev].lba48) { 886 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, 887 buffer, WRITE_CMD); 888 if ((flags & SATA_FLAG_WCACHE) && 889 (flags & SATA_FLAG_FLUSH_EXT)) 890 dwc_ahsata_flush_cache_ext(dev); 891 } else { 892 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, 893 buffer, WRITE_CMD); 894 if ((flags & SATA_FLAG_WCACHE) && 895 (flags & SATA_FLAG_FLUSH)) 896 dwc_ahsata_flush_cache(dev); 897 } 898 return rc; 899 } 900 901 int scan_sata(int dev) 902 { 903 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; 904 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; 905 u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; 906 u16 *id; 907 u64 n_sectors; 908 struct ahci_uc_priv *uc_priv = 909 (struct ahci_uc_priv *)sata_dev_desc[dev].priv; 910 u8 port = uc_priv->hard_port_no; 911 struct blk_desc *pdev = &(sata_dev_desc[dev]); 912 913 id = (u16 *)memalign(ARCH_DMA_MINALIGN, 914 roundup(ARCH_DMA_MINALIGN, 915 (ATA_ID_WORDS * 2))); 916 if (!id) { 917 printf("id malloc failed\n\r"); 918 return -1; 919 } 920 921 /* Identify device to get information */ 922 dwc_ahsata_identify(dev, id); 923 924 /* Serial number */ 925 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); 926 memcpy(pdev->product, serial, sizeof(serial)); 927 928 /* Firmware version */ 929 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); 930 memcpy(pdev->revision, firmware, sizeof(firmware)); 931 932 /* Product model */ 933 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); 934 memcpy(pdev->vendor, product, sizeof(product)); 935 936 /* Totoal sectors */ 937 n_sectors = ata_id_n_sectors(id); 938 pdev->lba = (u32)n_sectors; 939 940 pdev->type = DEV_TYPE_HARDDISK; 941 pdev->blksz = ATA_SECT_SIZE; 942 pdev->lun = 0 ; 943 944 /* Check if support LBA48 */ 945 if (ata_id_has_lba48(id)) { 946 pdev->lba48 = 1; 947 debug("Device support LBA48\n\r"); 948 } 949 950 /* Get the NCQ queue depth from device */ 951 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK); 952 uc_priv->flags |= ata_id_queue_depth(id); 953 954 /* Get the xfer mode from device */ 955 dwc_ahsata_xfer_mode(dev, id); 956 957 /* Get the write cache status from device */ 958 dwc_ahsata_init_wcache(dev, id); 959 960 /* Set the xfer mode to highest speed */ 961 ahci_set_feature(dev, port); 962 963 free((void *)id); 964 965 dwc_ahsata_print_info(dev); 966 967 is_ready = 1; 968 969 return 0; 970 } 971