1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006. 4 * Author: Jason Jin<Jason.jin@freescale.com> 5 * Zhang Wei<wei.zhang@freescale.com> 6 * 7 * with the reference on libata and ahci drvier in kernel 8 * 9 * This driver provides a SCSI interface to SATA. 10 */ 11 #include <common.h> 12 #include <blk.h> 13 #include <log.h> 14 #include <linux/bitops.h> 15 #include <linux/delay.h> 16 17 #include <command.h> 18 #include <dm.h> 19 #include <pci.h> 20 #include <asm/processor.h> 21 #include <linux/errno.h> 22 #include <asm/io.h> 23 #include <malloc.h> 24 #include <memalign.h> 25 #include <pci.h> 26 #include <scsi.h> 27 #include <libata.h> 28 #include <linux/ctype.h> 29 #include <ahci.h> 30 #include <dm/device-internal.h> 31 #include <dm/lists.h> 32 33 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port); 34 35 #ifndef CONFIG_DM_SCSI 36 struct ahci_uc_priv *probe_ent = NULL; 37 #endif 38 39 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) 40 41 /* 42 * Some controllers limit number of blocks they can read/write at once. 43 * Contemporary SSD devices work much faster if the read/write size is aligned 44 * to a power of 2. Let's set default to 128 and allowing to be overwritten if 45 * needed. 46 */ 47 #ifndef MAX_SATA_BLOCKS_READ_WRITE 48 #define MAX_SATA_BLOCKS_READ_WRITE 0x80 49 #endif 50 51 /* Maximum timeouts for each event */ 52 #define WAIT_MS_SPINUP 20000 53 #define WAIT_MS_DATAIO 10000 54 #define WAIT_MS_FLUSH 5000 55 #define WAIT_MS_LINKUP 200 56 57 #define AHCI_CAP_S64A BIT(31) 58 59 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port) 60 { 61 return base + 0x100 + (port * 0x80); 62 } 63 64 #define msleep(a) udelay(a * 1000) 65 66 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len) 67 { 68 const unsigned long start = begin; 69 const unsigned long end = start + len; 70 71 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); 72 flush_dcache_range(start, end); 73 } 74 75 /* 76 * SATA controller DMAs to physical RAM. Ensure data from the 77 * controller is invalidated from dcache; next access comes from 78 * physical RAM. 79 */ 80 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len) 81 { 82 const unsigned long start = begin; 83 const unsigned long end = start + len; 84 85 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); 86 invalidate_dcache_range(start, end); 87 } 88 89 /* 90 * Ensure data for SATA controller is flushed out of dcache and 91 * written to physical memory. 92 */ 93 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) 94 { 95 ahci_dcache_flush_range((unsigned long)pp->cmd_slot, 96 AHCI_PORT_PRIV_DMA_SZ); 97 } 98 99 static int waiting_for_cmd_completed(void __iomem *offset, 100 int timeout_msec, 101 u32 sign) 102 { 103 int i; 104 u32 status; 105 106 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) 107 msleep(1); 108 109 return (i < timeout_msec) ? 0 : -1; 110 } 111 112 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port) 113 { 114 u32 tmp; 115 int j = 0; 116 void __iomem *port_mmio = uc_priv->port[port].port_mmio; 117 118 /* 119 * Bring up SATA link. 120 * SATA link bringup time is usually less than 1 ms; only very 121 * rarely has it taken between 1-2 ms. Never seen it above 2 ms. 122 */ 123 while (j < WAIT_MS_LINKUP) { 124 tmp = readl(port_mmio + PORT_SCR_STAT); 125 tmp &= PORT_SCR_STAT_DET_MASK; 126 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 127 return 0; 128 udelay(1000); 129 j++; 130 } 131 return 1; 132 } 133 134 #ifdef CONFIG_SUNXI_AHCI 135 /* The sunxi AHCI controller requires this undocumented setup */ 136 static void sunxi_dma_init(void __iomem *port_mmio) 137 { 138 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); 139 } 140 #endif 141 142 int ahci_reset(void __iomem *base) 143 { 144 int i = 1000; 145 u32 __iomem *host_ctl_reg = base + HOST_CTL; 146 u32 tmp = readl(host_ctl_reg); /* global controller reset */ 147 148 if ((tmp & HOST_RESET) == 0) 149 writel_with_flush(tmp | HOST_RESET, host_ctl_reg); 150 151 /* 152 * reset must complete within 1 second, or 153 * the hardware should be considered fried. 154 */ 155 do { 156 udelay(1000); 157 tmp = readl(host_ctl_reg); 158 i--; 159 } while ((i > 0) && (tmp & HOST_RESET)); 160 161 if (i == 0) { 162 printf("controller reset failed (0x%x)\n", tmp); 163 return -1; 164 } 165 166 return 0; 167 } 168 169 static int ahci_host_init(struct ahci_uc_priv *uc_priv) 170 { 171 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 172 # ifdef CONFIG_DM_PCI 173 struct udevice *dev = uc_priv->dev; 174 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 175 # else 176 pci_dev_t pdev = uc_priv->dev; 177 unsigned short vendor; 178 # endif 179 u16 tmp16; 180 #endif 181 void __iomem *mmio = uc_priv->mmio_base; 182 u32 tmp, cap_save, cmd; 183 int i, j, ret; 184 void __iomem *port_mmio; 185 u32 port_map; 186 187 debug("ahci_host_init: start\n"); 188 189 cap_save = readl(mmio + HOST_CAP); 190 cap_save &= ((1 << 28) | (1 << 17)); 191 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ 192 193 ret = ahci_reset(uc_priv->mmio_base); 194 if (ret) 195 return ret; 196 197 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); 198 writel(cap_save, mmio + HOST_CAP); 199 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); 200 201 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 202 # ifdef CONFIG_DM_PCI 203 if (pplat->vendor == PCI_VENDOR_ID_INTEL) { 204 u16 tmp16; 205 206 dm_pci_read_config16(dev, 0x92, &tmp16); 207 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf); 208 } 209 # else 210 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); 211 212 if (vendor == PCI_VENDOR_ID_INTEL) { 213 u16 tmp16; 214 pci_read_config_word(pdev, 0x92, &tmp16); 215 tmp16 |= 0xf; 216 pci_write_config_word(pdev, 0x92, tmp16); 217 } 218 # endif 219 #endif 220 uc_priv->cap = readl(mmio + HOST_CAP); 221 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL); 222 port_map = uc_priv->port_map; 223 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1; 224 225 debug("cap 0x%x port_map 0x%x n_ports %d\n", 226 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); 227 228 #if !defined(CONFIG_DM_SCSI) 229 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) 230 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; 231 #endif 232 233 for (i = 0; i < uc_priv->n_ports; i++) { 234 if (!(port_map & (1 << i))) 235 continue; 236 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i); 237 port_mmio = (u8 *)uc_priv->port[i].port_mmio; 238 239 /* make sure port is not active */ 240 tmp = readl(port_mmio + PORT_CMD); 241 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 242 PORT_CMD_FIS_RX | PORT_CMD_START)) { 243 debug("Port %d is active. Deactivating.\n", i); 244 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 245 PORT_CMD_FIS_RX | PORT_CMD_START); 246 writel_with_flush(tmp, port_mmio + PORT_CMD); 247 248 /* spec says 500 msecs for each bit, so 249 * this is slightly incorrect. 250 */ 251 msleep(500); 252 } 253 254 #ifdef CONFIG_SUNXI_AHCI 255 sunxi_dma_init(port_mmio); 256 #endif 257 258 /* Add the spinup command to whatever mode bits may 259 * already be on in the command register. 260 */ 261 cmd = readl(port_mmio + PORT_CMD); 262 cmd |= PORT_CMD_SPIN_UP; 263 writel_with_flush(cmd, port_mmio + PORT_CMD); 264 265 /* Bring up SATA link. */ 266 ret = ahci_link_up(uc_priv, i); 267 if (ret) { 268 printf("SATA link %d timeout.\n", i); 269 continue; 270 } else { 271 debug("SATA link ok.\n"); 272 } 273 274 /* Clear error status */ 275 tmp = readl(port_mmio + PORT_SCR_ERR); 276 if (tmp) 277 writel(tmp, port_mmio + PORT_SCR_ERR); 278 279 debug("Spinning up device on SATA port %d... ", i); 280 281 j = 0; 282 while (j < WAIT_MS_SPINUP) { 283 tmp = readl(port_mmio + PORT_TFDATA); 284 if (!(tmp & (ATA_BUSY | ATA_DRQ))) 285 break; 286 udelay(1000); 287 tmp = readl(port_mmio + PORT_SCR_STAT); 288 tmp &= PORT_SCR_STAT_DET_MASK; 289 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 290 break; 291 j++; 292 } 293 294 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; 295 if (tmp == PORT_SCR_STAT_DET_COMINIT) { 296 debug("SATA link %d down (COMINIT received), retrying...\n", i); 297 i--; 298 continue; 299 } 300 301 printf("Target spinup took %d ms.\n", j); 302 if (j == WAIT_MS_SPINUP) 303 debug("timeout.\n"); 304 else 305 debug("ok.\n"); 306 307 tmp = readl(port_mmio + PORT_SCR_ERR); 308 debug("PORT_SCR_ERR 0x%x\n", tmp); 309 writel(tmp, port_mmio + PORT_SCR_ERR); 310 311 /* ack any pending irq events for this port */ 312 tmp = readl(port_mmio + PORT_IRQ_STAT); 313 debug("PORT_IRQ_STAT 0x%x\n", tmp); 314 if (tmp) 315 writel(tmp, port_mmio + PORT_IRQ_STAT); 316 317 writel(1 << i, mmio + HOST_IRQ_STAT); 318 319 /* register linkup ports */ 320 tmp = readl(port_mmio + PORT_SCR_STAT); 321 debug("SATA port %d status: 0x%x\n", i, tmp); 322 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) 323 uc_priv->link_port_map |= (0x01 << i); 324 } 325 326 tmp = readl(mmio + HOST_CTL); 327 debug("HOST_CTL 0x%x\n", tmp); 328 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 329 tmp = readl(mmio + HOST_CTL); 330 debug("HOST_CTL 0x%x\n", tmp); 331 #if !defined(CONFIG_DM_SCSI) 332 #ifndef CONFIG_SCSI_AHCI_PLAT 333 # ifdef CONFIG_DM_PCI 334 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16); 335 tmp |= PCI_COMMAND_MASTER; 336 dm_pci_write_config16(dev, PCI_COMMAND, tmp16); 337 # else 338 pci_read_config_word(pdev, PCI_COMMAND, &tmp16); 339 tmp |= PCI_COMMAND_MASTER; 340 pci_write_config_word(pdev, PCI_COMMAND, tmp16); 341 # endif 342 #endif 343 #endif 344 return 0; 345 } 346 347 348 static void ahci_print_info(struct ahci_uc_priv *uc_priv) 349 { 350 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 351 # if defined(CONFIG_DM_PCI) 352 struct udevice *dev = uc_priv->dev; 353 # else 354 pci_dev_t pdev = uc_priv->dev; 355 # endif 356 u16 cc; 357 #endif 358 void __iomem *mmio = uc_priv->mmio_base; 359 u32 vers, cap, cap2, impl, speed; 360 const char *speed_s; 361 const char *scc_s; 362 363 vers = readl(mmio + HOST_VERSION); 364 cap = uc_priv->cap; 365 cap2 = readl(mmio + HOST_CAP2); 366 impl = uc_priv->port_map; 367 368 speed = (cap >> 20) & 0xf; 369 if (speed == 1) 370 speed_s = "1.5"; 371 else if (speed == 2) 372 speed_s = "3"; 373 else if (speed == 3) 374 speed_s = "6"; 375 else 376 speed_s = "?"; 377 378 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI) 379 scc_s = "SATA"; 380 #else 381 # ifdef CONFIG_DM_PCI 382 dm_pci_read_config16(dev, 0x0a, &cc); 383 # else 384 pci_read_config_word(pdev, 0x0a, &cc); 385 # endif 386 if (cc == 0x0101) 387 scc_s = "IDE"; 388 else if (cc == 0x0106) 389 scc_s = "SATA"; 390 else if (cc == 0x0104) 391 scc_s = "RAID"; 392 else 393 scc_s = "unknown"; 394 #endif 395 printf("AHCI %02x%02x.%02x%02x " 396 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 397 (vers >> 24) & 0xff, 398 (vers >> 16) & 0xff, 399 (vers >> 8) & 0xff, 400 vers & 0xff, 401 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); 402 403 printf("flags: " 404 "%s%s%s%s%s%s%s" 405 "%s%s%s%s%s%s%s" 406 "%s%s%s%s%s%s\n", 407 cap & (1 << 31) ? "64bit " : "", 408 cap & (1 << 30) ? "ncq " : "", 409 cap & (1 << 28) ? "ilck " : "", 410 cap & (1 << 27) ? "stag " : "", 411 cap & (1 << 26) ? "pm " : "", 412 cap & (1 << 25) ? "led " : "", 413 cap & (1 << 24) ? "clo " : "", 414 cap & (1 << 19) ? "nz " : "", 415 cap & (1 << 18) ? "only " : "", 416 cap & (1 << 17) ? "pmp " : "", 417 cap & (1 << 16) ? "fbss " : "", 418 cap & (1 << 15) ? "pio " : "", 419 cap & (1 << 14) ? "slum " : "", 420 cap & (1 << 13) ? "part " : "", 421 cap & (1 << 7) ? "ccc " : "", 422 cap & (1 << 6) ? "ems " : "", 423 cap & (1 << 5) ? "sxs " : "", 424 cap2 & (1 << 2) ? "apst " : "", 425 cap2 & (1 << 1) ? "nvmp " : "", 426 cap2 & (1 << 0) ? "boh " : ""); 427 } 428 429 #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT) 430 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) 431 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) 432 # else 433 static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev) 434 # endif 435 { 436 #if !defined(CONFIG_DM_SCSI) 437 u16 vendor; 438 #endif 439 int rc; 440 441 uc_priv->dev = dev; 442 443 uc_priv->host_flags = ATA_FLAG_SATA 444 | ATA_FLAG_NO_LEGACY 445 | ATA_FLAG_MMIO 446 | ATA_FLAG_PIO_DMA 447 | ATA_FLAG_NO_ATAPI; 448 uc_priv->pio_mask = 0x1f; 449 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 450 451 #if !defined(CONFIG_DM_SCSI) 452 #ifdef CONFIG_DM_PCI 453 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 454 PCI_REGION_MEM); 455 456 /* Take from kernel: 457 * JMicron-specific fixup: 458 * make sure we're in AHCI mode 459 */ 460 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor); 461 if (vendor == 0x197b) 462 dm_pci_write_config8(dev, 0x41, 0xa1); 463 #else 464 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5, 465 PCI_REGION_MEM); 466 467 /* Take from kernel: 468 * JMicron-specific fixup: 469 * make sure we're in AHCI mode 470 */ 471 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); 472 if (vendor == 0x197b) 473 pci_write_config_byte(dev, 0x41, 0xa1); 474 #endif 475 #else 476 struct scsi_platdata *plat = dev_get_uclass_platdata(dev); 477 uc_priv->mmio_base = (void *)plat->base; 478 #endif 479 480 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base); 481 /* initialize adapter */ 482 rc = ahci_host_init(uc_priv); 483 if (rc) 484 goto err_out; 485 486 ahci_print_info(uc_priv); 487 488 return 0; 489 490 err_out: 491 return rc; 492 } 493 #endif 494 495 #define MAX_DATA_BYTE_COUNT (4*1024*1024) 496 497 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, 498 unsigned char *buf, int buf_len) 499 { 500 struct ahci_ioports *pp = &(uc_priv->port[port]); 501 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 502 u32 sg_count; 503 int i; 504 505 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; 506 if (sg_count > AHCI_MAX_SG) { 507 printf("Error:Too much sg!\n"); 508 return -1; 509 } 510 511 for (i = 0; i < sg_count; i++) { 512 /* We assume virt=phys */ 513 phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT; 514 515 ahci_sg->addr = cpu_to_le32(lower_32_bits(pa)); 516 ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa)); 517 if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) { 518 printf("Error: DMA address too high\n"); 519 return -1; 520 } 521 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 522 (buf_len < MAX_DATA_BYTE_COUNT 523 ? (buf_len - 1) 524 : (MAX_DATA_BYTE_COUNT - 1))); 525 ahci_sg++; 526 buf_len -= MAX_DATA_BYTE_COUNT; 527 } 528 529 return sg_count; 530 } 531 532 533 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) 534 { 535 pp->cmd_slot->opts = cpu_to_le32(opts); 536 pp->cmd_slot->status = 0; 537 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 538 #ifdef CONFIG_PHYS_64BIT 539 pp->cmd_slot->tbl_addr_hi = 540 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 541 #endif 542 } 543 544 static int wait_spinup(void __iomem *port_mmio) 545 { 546 ulong start; 547 u32 tf_data; 548 549 start = get_timer(0); 550 do { 551 tf_data = readl(port_mmio + PORT_TFDATA); 552 if (!(tf_data & ATA_BUSY)) 553 return 0; 554 } while (get_timer(start) < WAIT_MS_SPINUP); 555 556 return -ETIMEDOUT; 557 } 558 559 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) 560 { 561 struct ahci_ioports *pp = &(uc_priv->port[port]); 562 void __iomem *port_mmio = pp->port_mmio; 563 u64 dma_addr; 564 u32 port_status; 565 void __iomem *mem; 566 567 debug("Enter start port: %d\n", port); 568 port_status = readl(port_mmio + PORT_SCR_STAT); 569 debug("Port %d status: %x\n", port, port_status); 570 if ((port_status & 0xf) != 0x03) { 571 printf("No Link on this port!\n"); 572 return -1; 573 } 574 575 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ); 576 if (!mem) { 577 free(pp); 578 printf("%s: No mem for table!\n", __func__); 579 return -ENOMEM; 580 } 581 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); 582 583 /* 584 * First item in chunk of DMA memory: 32-slot command table, 585 * 32 bytes each in size 586 */ 587 pp->cmd_slot = 588 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); 589 debug("cmd_slot = %p\n", pp->cmd_slot); 590 mem += (AHCI_CMD_SLOT_SZ + 224); 591 592 /* 593 * Second item: Received-FIS area 594 */ 595 pp->rx_fis = virt_to_phys((void *)mem); 596 mem += AHCI_RX_FIS_SZ; 597 598 /* 599 * Third item: data area for storing a single command 600 * and its scatter-gather table 601 */ 602 pp->cmd_tbl = virt_to_phys((void *)mem); 603 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl); 604 605 mem += AHCI_CMD_TBL_HDR; 606 pp->cmd_tbl_sg = 607 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); 608 609 dma_addr = (ulong)pp->cmd_slot; 610 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR); 611 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI); 612 dma_addr = (ulong)pp->rx_fis; 613 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR); 614 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI); 615 616 #ifdef CONFIG_SUNXI_AHCI 617 sunxi_dma_init(port_mmio); 618 #endif 619 620 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 621 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 622 PORT_CMD_START, port_mmio + PORT_CMD); 623 624 debug("Exit start port %d\n", port); 625 626 /* 627 * Make sure interface is not busy based on error and status 628 * information from task file data register before proceeding 629 */ 630 return wait_spinup(port_mmio); 631 } 632 633 634 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis, 635 int fis_len, u8 *buf, int buf_len, u8 is_write) 636 { 637 638 struct ahci_ioports *pp = &(uc_priv->port[port]); 639 void __iomem *port_mmio = pp->port_mmio; 640 u32 opts; 641 u32 port_status; 642 int sg_count; 643 644 debug("Enter %s: for port %d\n", __func__, port); 645 646 if (port > uc_priv->n_ports) { 647 printf("Invalid port number %d\n", port); 648 return -1; 649 } 650 651 port_status = readl(port_mmio + PORT_SCR_STAT); 652 if ((port_status & 0xf) != 0x03) { 653 debug("No Link on port %d!\n", port); 654 return -1; 655 } 656 657 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); 658 659 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); 660 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); 661 ahci_fill_cmd_slot(pp, opts); 662 663 ahci_dcache_flush_sata_cmd(pp); 664 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len); 665 666 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 667 668 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 669 WAIT_MS_DATAIO, 0x1)) { 670 printf("timeout exit!\n"); 671 return -1; 672 } 673 674 ahci_dcache_invalidate_range((unsigned long)buf, 675 (unsigned long)buf_len); 676 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); 677 678 return 0; 679 } 680 681 682 static char *ata_id_strcpy(u16 *target, u16 *src, int len) 683 { 684 int i; 685 for (i = 0; i < len / 2; i++) 686 target[i] = swab16(src[i]); 687 return (char *)target; 688 } 689 690 /* 691 * SCSI INQUIRY command operation. 692 */ 693 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv, 694 struct scsi_cmd *pccb) 695 { 696 static const u8 hdr[] = { 697 0, 698 0, 699 0x5, /* claim SPC-3 version compatibility */ 700 2, 701 95 - 4, 702 }; 703 u8 fis[20]; 704 u16 *idbuf; 705 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); 706 u8 port; 707 708 /* Clean ccb data buffer */ 709 memset(pccb->pdata, 0, pccb->datalen); 710 711 memcpy(pccb->pdata, hdr, sizeof(hdr)); 712 713 if (pccb->datalen <= 35) 714 return 0; 715 716 memset(fis, 0, sizeof(fis)); 717 /* Construct the FIS */ 718 fis[0] = 0x27; /* Host to device FIS. */ 719 fis[1] = 1 << 7; /* Command FIS. */ 720 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ 721 722 /* Read id from sata */ 723 port = pccb->target; 724 725 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis), 726 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) { 727 debug("scsi_ahci: SCSI inquiry command failure.\n"); 728 return -EIO; 729 } 730 731 if (!uc_priv->ataid[port]) { 732 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2); 733 if (!uc_priv->ataid[port]) { 734 printf("%s: No memory for ataid[port]\n", __func__); 735 return -ENOMEM; 736 } 737 } 738 739 idbuf = uc_priv->ataid[port]; 740 741 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); 742 ata_swap_buf_le16(idbuf, ATA_ID_WORDS); 743 744 memcpy(&pccb->pdata[8], "ATA ", 8); 745 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); 746 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); 747 748 #ifdef DEBUG 749 ata_dump_id(idbuf); 750 #endif 751 return 0; 752 } 753 754 755 /* 756 * SCSI READ10/WRITE10 command operation. 757 */ 758 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv, 759 struct scsi_cmd *pccb, u8 is_write) 760 { 761 lbaint_t lba = 0; 762 u16 blocks = 0; 763 u8 fis[20]; 764 u8 *user_buffer = pccb->pdata; 765 u32 user_buffer_size = pccb->datalen; 766 767 /* Retrieve the base LBA number from the ccb structure. */ 768 if (pccb->cmd[0] == SCSI_READ16) { 769 memcpy(&lba, pccb->cmd + 2, 8); 770 lba = be64_to_cpu(lba); 771 } else { 772 u32 temp; 773 memcpy(&temp, pccb->cmd + 2, 4); 774 lba = be32_to_cpu(temp); 775 } 776 777 /* 778 * Retrieve the base LBA number and the block count from 779 * the ccb structure. 780 * 781 * For 10-byte and 16-byte SCSI R/W commands, transfer 782 * length 0 means transfer 0 block of data. 783 * However, for ATA R/W commands, sector count 0 means 784 * 256 or 65536 sectors, not 0 sectors as in SCSI. 785 * 786 * WARNING: one or two older ATA drives treat 0 as 0... 787 */ 788 if (pccb->cmd[0] == SCSI_READ16) 789 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]); 790 else 791 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); 792 793 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n", 794 is_write ? "write" : "read", blocks, lba); 795 796 /* Preset the FIS */ 797 memset(fis, 0, sizeof(fis)); 798 fis[0] = 0x27; /* Host to device FIS. */ 799 fis[1] = 1 << 7; /* Command FIS. */ 800 /* Command byte (read/write). */ 801 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; 802 803 while (blocks) { 804 u16 now_blocks; /* number of blocks per iteration */ 805 u32 transfer_size; /* number of bytes per iteration */ 806 807 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks); 808 809 transfer_size = ATA_SECT_SIZE * now_blocks; 810 if (transfer_size > user_buffer_size) { 811 printf("scsi_ahci: Error: buffer too small.\n"); 812 return -EIO; 813 } 814 815 /* 816 * LBA48 SATA command but only use 32bit address range within 817 * that (unless we've enabled 64bit LBA support). The next 818 * smaller command range (28bit) is too small. 819 */ 820 fis[4] = (lba >> 0) & 0xff; 821 fis[5] = (lba >> 8) & 0xff; 822 fis[6] = (lba >> 16) & 0xff; 823 fis[7] = 1 << 6; /* device reg: set LBA mode */ 824 fis[8] = ((lba >> 24) & 0xff); 825 #ifdef CONFIG_SYS_64BIT_LBA 826 if (pccb->cmd[0] == SCSI_READ16) { 827 fis[9] = ((lba >> 32) & 0xff); 828 fis[10] = ((lba >> 40) & 0xff); 829 } 830 #endif 831 832 fis[3] = 0xe0; /* features */ 833 834 /* Block (sector) count */ 835 fis[12] = (now_blocks >> 0) & 0xff; 836 fis[13] = (now_blocks >> 8) & 0xff; 837 838 /* Read/Write from ahci */ 839 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis, 840 sizeof(fis), user_buffer, transfer_size, 841 is_write)) { 842 debug("scsi_ahci: SCSI %s10 command failure.\n", 843 is_write ? "WRITE" : "READ"); 844 return -EIO; 845 } 846 847 /* If this transaction is a write, do a following flush. 848 * Writes in u-boot are so rare, and the logic to know when is 849 * the last write and do a flush only there is sufficiently 850 * difficult. Just do a flush after every write. This incurs, 851 * usually, one extra flush when the rare writes do happen. 852 */ 853 if (is_write) { 854 if (-EIO == ata_io_flush(uc_priv, pccb->target)) 855 return -EIO; 856 } 857 user_buffer += transfer_size; 858 user_buffer_size -= transfer_size; 859 blocks -= now_blocks; 860 lba += now_blocks; 861 } 862 863 return 0; 864 } 865 866 867 /* 868 * SCSI READ CAPACITY10 command operation. 869 */ 870 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv, 871 struct scsi_cmd *pccb) 872 { 873 u32 cap; 874 u64 cap64; 875 u32 block_size; 876 877 if (!uc_priv->ataid[pccb->target]) { 878 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " 879 "\tNo ATA info!\n" 880 "\tPlease run SCSI command INQUIRY first!\n"); 881 return -EPERM; 882 } 883 884 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]); 885 if (cap64 > 0x100000000ULL) 886 cap64 = 0xffffffff; 887 888 cap = cpu_to_be32(cap64); 889 memcpy(pccb->pdata, &cap, sizeof(cap)); 890 891 block_size = cpu_to_be32((u32)512); 892 memcpy(&pccb->pdata[4], &block_size, 4); 893 894 return 0; 895 } 896 897 898 /* 899 * SCSI READ CAPACITY16 command operation. 900 */ 901 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv, 902 struct scsi_cmd *pccb) 903 { 904 u64 cap; 905 u64 block_size; 906 907 if (!uc_priv->ataid[pccb->target]) { 908 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " 909 "\tNo ATA info!\n" 910 "\tPlease run SCSI command INQUIRY first!\n"); 911 return -EPERM; 912 } 913 914 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]); 915 cap = cpu_to_be64(cap); 916 memcpy(pccb->pdata, &cap, sizeof(cap)); 917 918 block_size = cpu_to_be64((u64)512); 919 memcpy(&pccb->pdata[8], &block_size, 8); 920 921 return 0; 922 } 923 924 925 /* 926 * SCSI TEST UNIT READY command operation. 927 */ 928 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv, 929 struct scsi_cmd *pccb) 930 { 931 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM; 932 } 933 934 935 static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) 936 { 937 struct ahci_uc_priv *uc_priv; 938 #ifdef CONFIG_DM_SCSI 939 uc_priv = dev_get_uclass_priv(dev->parent); 940 #else 941 uc_priv = probe_ent; 942 #endif 943 int ret; 944 945 switch (pccb->cmd[0]) { 946 case SCSI_READ16: 947 case SCSI_READ10: 948 ret = ata_scsiop_read_write(uc_priv, pccb, 0); 949 break; 950 case SCSI_WRITE10: 951 ret = ata_scsiop_read_write(uc_priv, pccb, 1); 952 break; 953 case SCSI_RD_CAPAC10: 954 ret = ata_scsiop_read_capacity10(uc_priv, pccb); 955 break; 956 case SCSI_RD_CAPAC16: 957 ret = ata_scsiop_read_capacity16(uc_priv, pccb); 958 break; 959 case SCSI_TST_U_RDY: 960 ret = ata_scsiop_test_unit_ready(uc_priv, pccb); 961 break; 962 case SCSI_INQUIRY: 963 ret = ata_scsiop_inquiry(uc_priv, pccb); 964 break; 965 default: 966 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); 967 return -ENOTSUPP; 968 } 969 970 if (ret) { 971 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); 972 return ret; 973 } 974 return 0; 975 976 } 977 978 static int ahci_start_ports(struct ahci_uc_priv *uc_priv) 979 { 980 u32 linkmap; 981 int i; 982 983 linkmap = uc_priv->link_port_map; 984 985 for (i = 0; i < uc_priv->n_ports; i++) { 986 if (((linkmap >> i) & 0x01)) { 987 if (ahci_port_start(uc_priv, (u8) i)) { 988 printf("Can not start port %d\n", i); 989 continue; 990 } 991 } 992 } 993 994 return 0; 995 } 996 997 #ifndef CONFIG_DM_SCSI 998 void scsi_low_level_init(int busdevfunc) 999 { 1000 struct ahci_uc_priv *uc_priv; 1001 1002 #ifndef CONFIG_SCSI_AHCI_PLAT 1003 probe_ent = calloc(1, sizeof(struct ahci_uc_priv)); 1004 if (!probe_ent) { 1005 printf("%s: No memory for uc_priv\n", __func__); 1006 return; 1007 } 1008 uc_priv = probe_ent; 1009 # if defined(CONFIG_DM_PCI) 1010 struct udevice *dev; 1011 int ret; 1012 1013 ret = dm_pci_bus_find_bdf(busdevfunc, &dev); 1014 if (ret) 1015 return; 1016 ahci_init_one(uc_priv, dev); 1017 # else 1018 ahci_init_one(uc_priv, busdevfunc); 1019 # endif 1020 #else 1021 uc_priv = probe_ent; 1022 #endif 1023 1024 ahci_start_ports(uc_priv); 1025 } 1026 #endif 1027 1028 #ifndef CONFIG_SCSI_AHCI_PLAT 1029 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) 1030 int achi_init_one_dm(struct udevice *dev) 1031 { 1032 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 1033 1034 return ahci_init_one(uc_priv, dev); 1035 } 1036 #endif 1037 #endif 1038 1039 int achi_start_ports_dm(struct udevice *dev) 1040 { 1041 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 1042 1043 return ahci_start_ports(uc_priv); 1044 } 1045 1046 #ifdef CONFIG_SCSI_AHCI_PLAT 1047 static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base) 1048 { 1049 int rc; 1050 1051 uc_priv->host_flags = ATA_FLAG_SATA 1052 | ATA_FLAG_NO_LEGACY 1053 | ATA_FLAG_MMIO 1054 | ATA_FLAG_PIO_DMA 1055 | ATA_FLAG_NO_ATAPI; 1056 uc_priv->pio_mask = 0x1f; 1057 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 1058 1059 uc_priv->mmio_base = base; 1060 1061 /* initialize adapter */ 1062 rc = ahci_host_init(uc_priv); 1063 if (rc) 1064 goto err_out; 1065 1066 ahci_print_info(uc_priv); 1067 1068 rc = ahci_start_ports(uc_priv); 1069 1070 err_out: 1071 return rc; 1072 } 1073 1074 #ifndef CONFIG_DM_SCSI 1075 int ahci_init(void __iomem *base) 1076 { 1077 struct ahci_uc_priv *uc_priv; 1078 1079 probe_ent = malloc(sizeof(struct ahci_uc_priv)); 1080 if (!probe_ent) { 1081 printf("%s: No memory for uc_priv\n", __func__); 1082 return -ENOMEM; 1083 } 1084 1085 uc_priv = probe_ent; 1086 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 1087 1088 return ahci_init_common(uc_priv, base); 1089 } 1090 #endif 1091 1092 int ahci_init_dm(struct udevice *dev, void __iomem *base) 1093 { 1094 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 1095 1096 return ahci_init_common(uc_priv, base); 1097 } 1098 1099 void __weak scsi_init(void) 1100 { 1101 } 1102 1103 #endif /* CONFIG_SCSI_AHCI_PLAT */ 1104 1105 /* 1106 * In the general case of generic rotating media it makes sense to have a 1107 * flush capability. It probably even makes sense in the case of SSDs because 1108 * one cannot always know for sure what kind of internal cache/flush mechanism 1109 * is embodied therein. At first it was planned to invoke this after the last 1110 * write to disk and before rebooting. In practice, knowing, a priori, which 1111 * is the last write is difficult. Because writing to the disk in u-boot is 1112 * very rare, this flush command will be invoked after every block write. 1113 */ 1114 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port) 1115 { 1116 u8 fis[20]; 1117 struct ahci_ioports *pp = &(uc_priv->port[port]); 1118 void __iomem *port_mmio = pp->port_mmio; 1119 u32 cmd_fis_len = 5; /* five dwords */ 1120 1121 /* Preset the FIS */ 1122 memset(fis, 0, 20); 1123 fis[0] = 0x27; /* Host to device FIS. */ 1124 fis[1] = 1 << 7; /* Command FIS. */ 1125 fis[2] = ATA_CMD_FLUSH_EXT; 1126 1127 memcpy((unsigned char *)pp->cmd_tbl, fis, 20); 1128 ahci_fill_cmd_slot(pp, cmd_fis_len); 1129 ahci_dcache_flush_sata_cmd(pp); 1130 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 1131 1132 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 1133 WAIT_MS_FLUSH, 0x1)) { 1134 debug("scsi_ahci: flush command timeout on port %d.\n", port); 1135 return -EIO; 1136 } 1137 1138 return 0; 1139 } 1140 1141 static int ahci_scsi_bus_reset(struct udevice *dev) 1142 { 1143 /* Not implemented */ 1144 1145 return 0; 1146 } 1147 1148 #ifdef CONFIG_DM_SCSI 1149 int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp) 1150 { 1151 struct udevice *dev; 1152 int ret; 1153 1154 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev); 1155 if (ret) 1156 return ret; 1157 *devp = dev; 1158 1159 return 0; 1160 } 1161 1162 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base) 1163 { 1164 struct ahci_uc_priv *uc_priv; 1165 struct scsi_platdata *uc_plat; 1166 struct udevice *dev; 1167 int ret; 1168 1169 device_find_first_child(ahci_dev, &dev); 1170 if (!dev) 1171 return -ENODEV; 1172 uc_plat = dev_get_uclass_platdata(dev); 1173 uc_plat->base = base; 1174 uc_plat->max_lun = 1; 1175 uc_plat->max_id = 2; 1176 1177 uc_priv = dev_get_uclass_priv(ahci_dev); 1178 ret = ahci_init_one(uc_priv, dev); 1179 if (ret) 1180 return ret; 1181 ret = ahci_start_ports(uc_priv); 1182 if (ret) 1183 return ret; 1184 1185 /* 1186 * scsi_scan_dev() scans devices up-to the number of max_id. 1187 * Update max_id if the number of detected ports exceeds max_id. 1188 * This allows SCSI to scan all detected ports. 1189 */ 1190 uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports, 1191 uc_plat->max_id); 1192 /* If port count is less than max_id, update max_id */ 1193 if (uc_priv->n_ports < uc_plat->max_id) 1194 uc_plat->max_id = uc_priv->n_ports; 1195 1196 return 0; 1197 } 1198 1199 #ifdef CONFIG_DM_PCI 1200 int ahci_probe_scsi_pci(struct udevice *ahci_dev) 1201 { 1202 ulong base; 1203 1204 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5, 1205 PCI_REGION_MEM); 1206 1207 return ahci_probe_scsi(ahci_dev, base); 1208 } 1209 #endif 1210 1211 struct scsi_ops scsi_ops = { 1212 .exec = ahci_scsi_exec, 1213 .bus_reset = ahci_scsi_bus_reset, 1214 }; 1215 1216 U_BOOT_DRIVER(ahci_scsi) = { 1217 .name = "ahci_scsi", 1218 .id = UCLASS_SCSI, 1219 .ops = &scsi_ops, 1220 }; 1221 #else 1222 int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) 1223 { 1224 return ahci_scsi_exec(dev, pccb); 1225 } 1226 1227 __weak int scsi_bus_reset(struct udevice *dev) 1228 { 1229 return ahci_scsi_bus_reset(dev); 1230 1231 return 0; 1232 } 1233 #endif 1234