1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * Author: Jason Jin<Jason.jin@freescale.com> 4 * Zhang Wei<wei.zhang@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 * with the reference on libata and ahci drvier in kernel 9 */ 10 #include <common.h> 11 12 #include <command.h> 13 #include <dm.h> 14 #include <pci.h> 15 #include <asm/processor.h> 16 #include <linux/errno.h> 17 #include <asm/io.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <scsi.h> 21 #include <libata.h> 22 #include <linux/ctype.h> 23 #include <ahci.h> 24 25 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port); 26 27 struct ahci_uc_priv *probe_ent = NULL; 28 29 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) 30 31 /* 32 * Some controllers limit number of blocks they can read/write at once. 33 * Contemporary SSD devices work much faster if the read/write size is aligned 34 * to a power of 2. Let's set default to 128 and allowing to be overwritten if 35 * needed. 36 */ 37 #ifndef MAX_SATA_BLOCKS_READ_WRITE 38 #define MAX_SATA_BLOCKS_READ_WRITE 0x80 39 #endif 40 41 /* Maximum timeouts for each event */ 42 #define WAIT_MS_SPINUP 20000 43 #define WAIT_MS_DATAIO 10000 44 #define WAIT_MS_FLUSH 5000 45 #define WAIT_MS_LINKUP 200 46 47 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port) 48 { 49 return base + 0x100 + (port * 0x80); 50 } 51 52 53 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base, 54 unsigned int port_idx) 55 { 56 base = ahci_port_base(base, port_idx); 57 58 port->cmd_addr = base; 59 port->scr_addr = base + PORT_SCR; 60 } 61 62 63 #define msleep(a) udelay(a * 1000) 64 65 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len) 66 { 67 const unsigned long start = begin; 68 const unsigned long end = start + len; 69 70 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); 71 flush_dcache_range(start, end); 72 } 73 74 /* 75 * SATA controller DMAs to physical RAM. Ensure data from the 76 * controller is invalidated from dcache; next access comes from 77 * physical RAM. 78 */ 79 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len) 80 { 81 const unsigned long start = begin; 82 const unsigned long end = start + len; 83 84 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); 85 invalidate_dcache_range(start, end); 86 } 87 88 /* 89 * Ensure data for SATA controller is flushed out of dcache and 90 * written to physical memory. 91 */ 92 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) 93 { 94 ahci_dcache_flush_range((unsigned long)pp->cmd_slot, 95 AHCI_PORT_PRIV_DMA_SZ); 96 } 97 98 static int waiting_for_cmd_completed(void __iomem *offset, 99 int timeout_msec, 100 u32 sign) 101 { 102 int i; 103 u32 status; 104 105 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) 106 msleep(1); 107 108 return (i < timeout_msec) ? 0 : -1; 109 } 110 111 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port) 112 { 113 u32 tmp; 114 int j = 0; 115 void __iomem *port_mmio = uc_priv->port[port].port_mmio; 116 117 /* 118 * Bring up SATA link. 119 * SATA link bringup time is usually less than 1 ms; only very 120 * rarely has it taken between 1-2 ms. Never seen it above 2 ms. 121 */ 122 while (j < WAIT_MS_LINKUP) { 123 tmp = readl(port_mmio + PORT_SCR_STAT); 124 tmp &= PORT_SCR_STAT_DET_MASK; 125 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 126 return 0; 127 udelay(1000); 128 j++; 129 } 130 return 1; 131 } 132 133 #ifdef CONFIG_SUNXI_AHCI 134 /* The sunxi AHCI controller requires this undocumented setup */ 135 static void sunxi_dma_init(void __iomem *port_mmio) 136 { 137 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); 138 } 139 #endif 140 141 int ahci_reset(void __iomem *base) 142 { 143 int i = 1000; 144 u32 __iomem *host_ctl_reg = base + HOST_CTL; 145 u32 tmp = readl(host_ctl_reg); /* global controller reset */ 146 147 if ((tmp & HOST_RESET) == 0) 148 writel_with_flush(tmp | HOST_RESET, host_ctl_reg); 149 150 /* 151 * reset must complete within 1 second, or 152 * the hardware should be considered fried. 153 */ 154 do { 155 udelay(1000); 156 tmp = readl(host_ctl_reg); 157 i--; 158 } while ((i > 0) && (tmp & HOST_RESET)); 159 160 if (i == 0) { 161 printf("controller reset failed (0x%x)\n", tmp); 162 return -1; 163 } 164 165 return 0; 166 } 167 168 static int ahci_host_init(struct ahci_uc_priv *uc_priv) 169 { 170 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 171 # ifdef CONFIG_DM_PCI 172 struct udevice *dev = uc_priv->dev; 173 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 174 # else 175 pci_dev_t pdev = uc_priv->dev; 176 unsigned short vendor; 177 # endif 178 u16 tmp16; 179 #endif 180 void __iomem *mmio = uc_priv->mmio_base; 181 u32 tmp, cap_save, cmd; 182 int i, j, ret; 183 void __iomem *port_mmio; 184 u32 port_map; 185 186 debug("ahci_host_init: start\n"); 187 188 cap_save = readl(mmio + HOST_CAP); 189 cap_save &= ((1 << 28) | (1 << 17)); 190 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ 191 192 ret = ahci_reset(uc_priv->mmio_base); 193 if (ret) 194 return ret; 195 196 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); 197 writel(cap_save, mmio + HOST_CAP); 198 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); 199 200 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 201 # ifdef CONFIG_DM_PCI 202 if (pplat->vendor == PCI_VENDOR_ID_INTEL) { 203 u16 tmp16; 204 205 dm_pci_read_config16(dev, 0x92, &tmp16); 206 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf); 207 } 208 # else 209 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); 210 211 if (vendor == PCI_VENDOR_ID_INTEL) { 212 u16 tmp16; 213 pci_read_config_word(pdev, 0x92, &tmp16); 214 tmp16 |= 0xf; 215 pci_write_config_word(pdev, 0x92, tmp16); 216 } 217 # endif 218 #endif 219 uc_priv->cap = readl(mmio + HOST_CAP); 220 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL); 221 port_map = uc_priv->port_map; 222 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1; 223 224 debug("cap 0x%x port_map 0x%x n_ports %d\n", 225 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); 226 227 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) 228 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; 229 230 for (i = 0; i < uc_priv->n_ports; i++) { 231 if (!(port_map & (1 << i))) 232 continue; 233 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i); 234 port_mmio = (u8 *)uc_priv->port[i].port_mmio; 235 ahci_setup_port(&uc_priv->port[i], mmio, i); 236 237 /* make sure port is not active */ 238 tmp = readl(port_mmio + PORT_CMD); 239 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 240 PORT_CMD_FIS_RX | PORT_CMD_START)) { 241 debug("Port %d is active. Deactivating.\n", i); 242 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 243 PORT_CMD_FIS_RX | PORT_CMD_START); 244 writel_with_flush(tmp, port_mmio + PORT_CMD); 245 246 /* spec says 500 msecs for each bit, so 247 * this is slightly incorrect. 248 */ 249 msleep(500); 250 } 251 252 #ifdef CONFIG_SUNXI_AHCI 253 sunxi_dma_init(port_mmio); 254 #endif 255 256 /* Add the spinup command to whatever mode bits may 257 * already be on in the command register. 258 */ 259 cmd = readl(port_mmio + PORT_CMD); 260 cmd |= PORT_CMD_SPIN_UP; 261 writel_with_flush(cmd, port_mmio + PORT_CMD); 262 263 /* Bring up SATA link. */ 264 ret = ahci_link_up(uc_priv, i); 265 if (ret) { 266 printf("SATA link %d timeout.\n", i); 267 continue; 268 } else { 269 debug("SATA link ok.\n"); 270 } 271 272 /* Clear error status */ 273 tmp = readl(port_mmio + PORT_SCR_ERR); 274 if (tmp) 275 writel(tmp, port_mmio + PORT_SCR_ERR); 276 277 debug("Spinning up device on SATA port %d... ", i); 278 279 j = 0; 280 while (j < WAIT_MS_SPINUP) { 281 tmp = readl(port_mmio + PORT_TFDATA); 282 if (!(tmp & (ATA_BUSY | ATA_DRQ))) 283 break; 284 udelay(1000); 285 tmp = readl(port_mmio + PORT_SCR_STAT); 286 tmp &= PORT_SCR_STAT_DET_MASK; 287 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 288 break; 289 j++; 290 } 291 292 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; 293 if (tmp == PORT_SCR_STAT_DET_COMINIT) { 294 debug("SATA link %d down (COMINIT received), retrying...\n", i); 295 i--; 296 continue; 297 } 298 299 printf("Target spinup took %d ms.\n", j); 300 if (j == WAIT_MS_SPINUP) 301 debug("timeout.\n"); 302 else 303 debug("ok.\n"); 304 305 tmp = readl(port_mmio + PORT_SCR_ERR); 306 debug("PORT_SCR_ERR 0x%x\n", tmp); 307 writel(tmp, port_mmio + PORT_SCR_ERR); 308 309 /* ack any pending irq events for this port */ 310 tmp = readl(port_mmio + PORT_IRQ_STAT); 311 debug("PORT_IRQ_STAT 0x%x\n", tmp); 312 if (tmp) 313 writel(tmp, port_mmio + PORT_IRQ_STAT); 314 315 writel(1 << i, mmio + HOST_IRQ_STAT); 316 317 /* register linkup ports */ 318 tmp = readl(port_mmio + PORT_SCR_STAT); 319 debug("SATA port %d status: 0x%x\n", i, tmp); 320 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) 321 uc_priv->link_port_map |= (0x01 << i); 322 } 323 324 tmp = readl(mmio + HOST_CTL); 325 debug("HOST_CTL 0x%x\n", tmp); 326 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 327 tmp = readl(mmio + HOST_CTL); 328 debug("HOST_CTL 0x%x\n", tmp); 329 #if !defined(CONFIG_DM_SCSI) 330 #ifndef CONFIG_SCSI_AHCI_PLAT 331 # ifdef CONFIG_DM_PCI 332 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16); 333 tmp |= PCI_COMMAND_MASTER; 334 dm_pci_write_config16(dev, PCI_COMMAND, tmp16); 335 # else 336 pci_read_config_word(pdev, PCI_COMMAND, &tmp16); 337 tmp |= PCI_COMMAND_MASTER; 338 pci_write_config_word(pdev, PCI_COMMAND, tmp16); 339 # endif 340 #endif 341 #endif 342 return 0; 343 } 344 345 346 static void ahci_print_info(struct ahci_uc_priv *uc_priv) 347 { 348 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 349 # if defined(CONFIG_DM_PCI) 350 struct udevice *dev = uc_priv->dev; 351 # else 352 pci_dev_t pdev = uc_priv->dev; 353 # endif 354 u16 cc; 355 #endif 356 void __iomem *mmio = uc_priv->mmio_base; 357 u32 vers, cap, cap2, impl, speed; 358 const char *speed_s; 359 const char *scc_s; 360 361 vers = readl(mmio + HOST_VERSION); 362 cap = uc_priv->cap; 363 cap2 = readl(mmio + HOST_CAP2); 364 impl = uc_priv->port_map; 365 366 speed = (cap >> 20) & 0xf; 367 if (speed == 1) 368 speed_s = "1.5"; 369 else if (speed == 2) 370 speed_s = "3"; 371 else if (speed == 3) 372 speed_s = "6"; 373 else 374 speed_s = "?"; 375 376 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI) 377 scc_s = "SATA"; 378 #else 379 # ifdef CONFIG_DM_PCI 380 dm_pci_read_config16(dev, 0x0a, &cc); 381 # else 382 pci_read_config_word(pdev, 0x0a, &cc); 383 # endif 384 if (cc == 0x0101) 385 scc_s = "IDE"; 386 else if (cc == 0x0106) 387 scc_s = "SATA"; 388 else if (cc == 0x0104) 389 scc_s = "RAID"; 390 else 391 scc_s = "unknown"; 392 #endif 393 printf("AHCI %02x%02x.%02x%02x " 394 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 395 (vers >> 24) & 0xff, 396 (vers >> 16) & 0xff, 397 (vers >> 8) & 0xff, 398 vers & 0xff, 399 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); 400 401 printf("flags: " 402 "%s%s%s%s%s%s%s" 403 "%s%s%s%s%s%s%s" 404 "%s%s%s%s%s%s\n", 405 cap & (1 << 31) ? "64bit " : "", 406 cap & (1 << 30) ? "ncq " : "", 407 cap & (1 << 28) ? "ilck " : "", 408 cap & (1 << 27) ? "stag " : "", 409 cap & (1 << 26) ? "pm " : "", 410 cap & (1 << 25) ? "led " : "", 411 cap & (1 << 24) ? "clo " : "", 412 cap & (1 << 19) ? "nz " : "", 413 cap & (1 << 18) ? "only " : "", 414 cap & (1 << 17) ? "pmp " : "", 415 cap & (1 << 16) ? "fbss " : "", 416 cap & (1 << 15) ? "pio " : "", 417 cap & (1 << 14) ? "slum " : "", 418 cap & (1 << 13) ? "part " : "", 419 cap & (1 << 7) ? "ccc " : "", 420 cap & (1 << 6) ? "ems " : "", 421 cap & (1 << 5) ? "sxs " : "", 422 cap2 & (1 << 2) ? "apst " : "", 423 cap2 & (1 << 1) ? "nvmp " : "", 424 cap2 & (1 << 0) ? "boh " : ""); 425 } 426 427 #ifndef CONFIG_SCSI_AHCI_PLAT 428 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) 429 static int ahci_init_one(struct udevice *dev) 430 # else 431 static int ahci_init_one(pci_dev_t dev) 432 # endif 433 { 434 struct ahci_uc_priv *uc_priv; 435 #if !defined(CONFIG_DM_SCSI) 436 u16 vendor; 437 #endif 438 int rc; 439 440 probe_ent = malloc(sizeof(struct ahci_uc_priv)); 441 if (!probe_ent) { 442 printf("%s: No memory for uc_priv\n", __func__); 443 return -ENOMEM; 444 } 445 446 uc_priv = probe_ent; 447 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 448 uc_priv->dev = dev; 449 450 uc_priv->host_flags = ATA_FLAG_SATA 451 | ATA_FLAG_NO_LEGACY 452 | ATA_FLAG_MMIO 453 | ATA_FLAG_PIO_DMA 454 | ATA_FLAG_NO_ATAPI; 455 uc_priv->pio_mask = 0x1f; 456 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 457 458 #if !defined(CONFIG_DM_SCSI) 459 #ifdef CONFIG_DM_PCI 460 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 461 PCI_REGION_MEM); 462 463 /* Take from kernel: 464 * JMicron-specific fixup: 465 * make sure we're in AHCI mode 466 */ 467 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor); 468 if (vendor == 0x197b) 469 dm_pci_write_config8(dev, 0x41, 0xa1); 470 #else 471 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5, 472 PCI_REGION_MEM); 473 474 /* Take from kernel: 475 * JMicron-specific fixup: 476 * make sure we're in AHCI mode 477 */ 478 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); 479 if (vendor == 0x197b) 480 pci_write_config_byte(dev, 0x41, 0xa1); 481 #endif 482 #else 483 struct scsi_platdata *plat = dev_get_uclass_platdata(dev); 484 uc_priv->mmio_base = (void *)plat->base; 485 #endif 486 487 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base); 488 /* initialize adapter */ 489 rc = ahci_host_init(uc_priv); 490 if (rc) 491 goto err_out; 492 493 ahci_print_info(uc_priv); 494 495 return 0; 496 497 err_out: 498 return rc; 499 } 500 #endif 501 502 #define MAX_DATA_BYTE_COUNT (4*1024*1024) 503 504 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, 505 unsigned char *buf, int buf_len) 506 { 507 struct ahci_ioports *pp = &(uc_priv->port[port]); 508 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 509 u32 sg_count; 510 int i; 511 512 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; 513 if (sg_count > AHCI_MAX_SG) { 514 printf("Error:Too much sg!\n"); 515 return -1; 516 } 517 518 for (i = 0; i < sg_count; i++) { 519 ahci_sg->addr = 520 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); 521 ahci_sg->addr_hi = 0; 522 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 523 (buf_len < MAX_DATA_BYTE_COUNT 524 ? (buf_len - 1) 525 : (MAX_DATA_BYTE_COUNT - 1))); 526 ahci_sg++; 527 buf_len -= MAX_DATA_BYTE_COUNT; 528 } 529 530 return sg_count; 531 } 532 533 534 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) 535 { 536 pp->cmd_slot->opts = cpu_to_le32(opts); 537 pp->cmd_slot->status = 0; 538 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 539 #ifdef CONFIG_PHYS_64BIT 540 pp->cmd_slot->tbl_addr_hi = 541 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 542 #endif 543 } 544 545 static int wait_spinup(void __iomem *port_mmio) 546 { 547 ulong start; 548 u32 tf_data; 549 550 start = get_timer(0); 551 do { 552 tf_data = readl(port_mmio + PORT_TFDATA); 553 if (!(tf_data & ATA_BUSY)) 554 return 0; 555 } while (get_timer(start) < WAIT_MS_SPINUP); 556 557 return -ETIMEDOUT; 558 } 559 560 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) 561 { 562 struct ahci_ioports *pp = &(uc_priv->port[port]); 563 void __iomem *port_mmio = pp->port_mmio; 564 u32 port_status; 565 void __iomem *mem; 566 567 debug("Enter start port: %d\n", port); 568 port_status = readl(port_mmio + PORT_SCR_STAT); 569 debug("Port %d status: %x\n", port, port_status); 570 if ((port_status & 0xf) != 0x03) { 571 printf("No Link on this port!\n"); 572 return -1; 573 } 574 575 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); 576 if (!mem) { 577 free(pp); 578 printf("%s: No mem for table!\n", __func__); 579 return -ENOMEM; 580 } 581 582 /* Aligned to 2048-bytes */ 583 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ); 584 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); 585 586 /* 587 * First item in chunk of DMA memory: 32-slot command table, 588 * 32 bytes each in size 589 */ 590 pp->cmd_slot = 591 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); 592 debug("cmd_slot = %p\n", pp->cmd_slot); 593 mem += (AHCI_CMD_SLOT_SZ + 224); 594 595 /* 596 * Second item: Received-FIS area 597 */ 598 pp->rx_fis = virt_to_phys((void *)mem); 599 mem += AHCI_RX_FIS_SZ; 600 601 /* 602 * Third item: data area for storing a single command 603 * and its scatter-gather table 604 */ 605 pp->cmd_tbl = virt_to_phys((void *)mem); 606 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl); 607 608 mem += AHCI_CMD_TBL_HDR; 609 pp->cmd_tbl_sg = 610 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); 611 612 writel_with_flush((unsigned long)pp->cmd_slot, 613 port_mmio + PORT_LST_ADDR); 614 615 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); 616 617 #ifdef CONFIG_SUNXI_AHCI 618 sunxi_dma_init(port_mmio); 619 #endif 620 621 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 622 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 623 PORT_CMD_START, port_mmio + PORT_CMD); 624 625 debug("Exit start port %d\n", port); 626 627 /* 628 * Make sure interface is not busy based on error and status 629 * information from task file data register before proceeding 630 */ 631 return wait_spinup(port_mmio); 632 } 633 634 635 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis, 636 int fis_len, u8 *buf, int buf_len, u8 is_write) 637 { 638 639 struct ahci_ioports *pp = &(uc_priv->port[port]); 640 void __iomem *port_mmio = pp->port_mmio; 641 u32 opts; 642 u32 port_status; 643 int sg_count; 644 645 debug("Enter %s: for port %d\n", __func__, port); 646 647 if (port > uc_priv->n_ports) { 648 printf("Invalid port number %d\n", port); 649 return -1; 650 } 651 652 port_status = readl(port_mmio + PORT_SCR_STAT); 653 if ((port_status & 0xf) != 0x03) { 654 debug("No Link on port %d!\n", port); 655 return -1; 656 } 657 658 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); 659 660 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); 661 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); 662 ahci_fill_cmd_slot(pp, opts); 663 664 ahci_dcache_flush_sata_cmd(pp); 665 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len); 666 667 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 668 669 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 670 WAIT_MS_DATAIO, 0x1)) { 671 printf("timeout exit!\n"); 672 return -1; 673 } 674 675 ahci_dcache_invalidate_range((unsigned long)buf, 676 (unsigned long)buf_len); 677 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); 678 679 return 0; 680 } 681 682 683 static char *ata_id_strcpy(u16 *target, u16 *src, int len) 684 { 685 int i; 686 for (i = 0; i < len / 2; i++) 687 target[i] = swab16(src[i]); 688 return (char *)target; 689 } 690 691 /* 692 * SCSI INQUIRY command operation. 693 */ 694 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv, 695 struct scsi_cmd *pccb) 696 { 697 static const u8 hdr[] = { 698 0, 699 0, 700 0x5, /* claim SPC-3 version compatibility */ 701 2, 702 95 - 4, 703 }; 704 u8 fis[20]; 705 u16 *idbuf; 706 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); 707 u8 port; 708 709 /* Clean ccb data buffer */ 710 memset(pccb->pdata, 0, pccb->datalen); 711 712 memcpy(pccb->pdata, hdr, sizeof(hdr)); 713 714 if (pccb->datalen <= 35) 715 return 0; 716 717 memset(fis, 0, sizeof(fis)); 718 /* Construct the FIS */ 719 fis[0] = 0x27; /* Host to device FIS. */ 720 fis[1] = 1 << 7; /* Command FIS. */ 721 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ 722 723 /* Read id from sata */ 724 port = pccb->target; 725 726 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis), 727 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) { 728 debug("scsi_ahci: SCSI inquiry command failure.\n"); 729 return -EIO; 730 } 731 732 if (!uc_priv->ataid[port]) { 733 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2); 734 if (!uc_priv->ataid[port]) { 735 printf("%s: No memory for ataid[port]\n", __func__); 736 return -ENOMEM; 737 } 738 } 739 740 idbuf = uc_priv->ataid[port]; 741 742 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); 743 ata_swap_buf_le16(idbuf, ATA_ID_WORDS); 744 745 memcpy(&pccb->pdata[8], "ATA ", 8); 746 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); 747 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); 748 749 #ifdef DEBUG 750 ata_dump_id(idbuf); 751 #endif 752 return 0; 753 } 754 755 756 /* 757 * SCSI READ10/WRITE10 command operation. 758 */ 759 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv, 760 struct scsi_cmd *pccb, u8 is_write) 761 { 762 lbaint_t lba = 0; 763 u16 blocks = 0; 764 u8 fis[20]; 765 u8 *user_buffer = pccb->pdata; 766 u32 user_buffer_size = pccb->datalen; 767 768 /* Retrieve the base LBA number from the ccb structure. */ 769 if (pccb->cmd[0] == SCSI_READ16) { 770 memcpy(&lba, pccb->cmd + 2, 8); 771 lba = be64_to_cpu(lba); 772 } else { 773 u32 temp; 774 memcpy(&temp, pccb->cmd + 2, 4); 775 lba = be32_to_cpu(temp); 776 } 777 778 /* 779 * Retrieve the base LBA number and the block count from 780 * the ccb structure. 781 * 782 * For 10-byte and 16-byte SCSI R/W commands, transfer 783 * length 0 means transfer 0 block of data. 784 * However, for ATA R/W commands, sector count 0 means 785 * 256 or 65536 sectors, not 0 sectors as in SCSI. 786 * 787 * WARNING: one or two older ATA drives treat 0 as 0... 788 */ 789 if (pccb->cmd[0] == SCSI_READ16) 790 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]); 791 else 792 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); 793 794 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n", 795 is_write ? "write" : "read", blocks, lba); 796 797 /* Preset the FIS */ 798 memset(fis, 0, sizeof(fis)); 799 fis[0] = 0x27; /* Host to device FIS. */ 800 fis[1] = 1 << 7; /* Command FIS. */ 801 /* Command byte (read/write). */ 802 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; 803 804 while (blocks) { 805 u16 now_blocks; /* number of blocks per iteration */ 806 u32 transfer_size; /* number of bytes per iteration */ 807 808 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks); 809 810 transfer_size = ATA_SECT_SIZE * now_blocks; 811 if (transfer_size > user_buffer_size) { 812 printf("scsi_ahci: Error: buffer too small.\n"); 813 return -EIO; 814 } 815 816 /* 817 * LBA48 SATA command but only use 32bit address range within 818 * that (unless we've enabled 64bit LBA support). The next 819 * smaller command range (28bit) is too small. 820 */ 821 fis[4] = (lba >> 0) & 0xff; 822 fis[5] = (lba >> 8) & 0xff; 823 fis[6] = (lba >> 16) & 0xff; 824 fis[7] = 1 << 6; /* device reg: set LBA mode */ 825 fis[8] = ((lba >> 24) & 0xff); 826 #ifdef CONFIG_SYS_64BIT_LBA 827 if (pccb->cmd[0] == SCSI_READ16) { 828 fis[9] = ((lba >> 32) & 0xff); 829 fis[10] = ((lba >> 40) & 0xff); 830 } 831 #endif 832 833 fis[3] = 0xe0; /* features */ 834 835 /* Block (sector) count */ 836 fis[12] = (now_blocks >> 0) & 0xff; 837 fis[13] = (now_blocks >> 8) & 0xff; 838 839 /* Read/Write from ahci */ 840 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis, 841 sizeof(fis), user_buffer, transfer_size, 842 is_write)) { 843 debug("scsi_ahci: SCSI %s10 command failure.\n", 844 is_write ? "WRITE" : "READ"); 845 return -EIO; 846 } 847 848 /* If this transaction is a write, do a following flush. 849 * Writes in u-boot are so rare, and the logic to know when is 850 * the last write and do a flush only there is sufficiently 851 * difficult. Just do a flush after every write. This incurs, 852 * usually, one extra flush when the rare writes do happen. 853 */ 854 if (is_write) { 855 if (-EIO == ata_io_flush(uc_priv, pccb->target)) 856 return -EIO; 857 } 858 user_buffer += transfer_size; 859 user_buffer_size -= transfer_size; 860 blocks -= now_blocks; 861 lba += now_blocks; 862 } 863 864 return 0; 865 } 866 867 868 /* 869 * SCSI READ CAPACITY10 command operation. 870 */ 871 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv, 872 struct scsi_cmd *pccb) 873 { 874 u32 cap; 875 u64 cap64; 876 u32 block_size; 877 878 if (!uc_priv->ataid[pccb->target]) { 879 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " 880 "\tNo ATA info!\n" 881 "\tPlease run SCSI command INQUIRY first!\n"); 882 return -EPERM; 883 } 884 885 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]); 886 if (cap64 > 0x100000000ULL) 887 cap64 = 0xffffffff; 888 889 cap = cpu_to_be32(cap64); 890 memcpy(pccb->pdata, &cap, sizeof(cap)); 891 892 block_size = cpu_to_be32((u32)512); 893 memcpy(&pccb->pdata[4], &block_size, 4); 894 895 return 0; 896 } 897 898 899 /* 900 * SCSI READ CAPACITY16 command operation. 901 */ 902 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv, 903 struct scsi_cmd *pccb) 904 { 905 u64 cap; 906 u64 block_size; 907 908 if (!uc_priv->ataid[pccb->target]) { 909 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " 910 "\tNo ATA info!\n" 911 "\tPlease run SCSI command INQUIRY first!\n"); 912 return -EPERM; 913 } 914 915 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]); 916 cap = cpu_to_be64(cap); 917 memcpy(pccb->pdata, &cap, sizeof(cap)); 918 919 block_size = cpu_to_be64((u64)512); 920 memcpy(&pccb->pdata[8], &block_size, 8); 921 922 return 0; 923 } 924 925 926 /* 927 * SCSI TEST UNIT READY command operation. 928 */ 929 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv, 930 struct scsi_cmd *pccb) 931 { 932 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM; 933 } 934 935 936 int scsi_exec(struct scsi_cmd *pccb) 937 { 938 struct ahci_uc_priv *uc_priv = probe_ent; 939 int ret; 940 941 switch (pccb->cmd[0]) { 942 case SCSI_READ16: 943 case SCSI_READ10: 944 ret = ata_scsiop_read_write(uc_priv, pccb, 0); 945 break; 946 case SCSI_WRITE10: 947 ret = ata_scsiop_read_write(uc_priv, pccb, 1); 948 break; 949 case SCSI_RD_CAPAC10: 950 ret = ata_scsiop_read_capacity10(uc_priv, pccb); 951 break; 952 case SCSI_RD_CAPAC16: 953 ret = ata_scsiop_read_capacity16(uc_priv, pccb); 954 break; 955 case SCSI_TST_U_RDY: 956 ret = ata_scsiop_test_unit_ready(uc_priv, pccb); 957 break; 958 case SCSI_INQUIRY: 959 ret = ata_scsiop_inquiry(uc_priv, pccb); 960 break; 961 default: 962 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); 963 return false; 964 } 965 966 if (ret) { 967 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); 968 return false; 969 } 970 return true; 971 972 } 973 974 static int ahci_start_ports(struct ahci_uc_priv *uc_priv) 975 { 976 u32 linkmap; 977 int i; 978 979 linkmap = uc_priv->link_port_map; 980 981 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { 982 if (((linkmap >> i) & 0x01)) { 983 if (ahci_port_start(uc_priv, (u8) i)) { 984 printf("Can not start port %d\n", i); 985 continue; 986 } 987 } 988 } 989 990 return 0; 991 } 992 993 #if defined(CONFIG_DM_SCSI) 994 void scsi_low_level_init(int busdevfunc, struct udevice *dev) 995 #else 996 void scsi_low_level_init(int busdevfunc) 997 #endif 998 { 999 struct ahci_uc_priv *uc_priv; 1000 1001 #ifndef CONFIG_SCSI_AHCI_PLAT 1002 # if defined(CONFIG_DM_PCI) 1003 struct udevice *dev; 1004 int ret; 1005 1006 ret = dm_pci_bus_find_bdf(busdevfunc, &dev); 1007 if (ret) 1008 return; 1009 ahci_init_one(dev); 1010 # elif defined(CONFIG_DM_SCSI) 1011 ahci_init_one(dev); 1012 # else 1013 ahci_init_one(busdevfunc); 1014 # endif 1015 #endif 1016 uc_priv = probe_ent; 1017 1018 ahci_start_ports(uc_priv); 1019 } 1020 1021 #ifdef CONFIG_SCSI_AHCI_PLAT 1022 int ahci_init(void __iomem *base) 1023 { 1024 struct ahci_uc_priv *uc_priv; 1025 int rc = 0; 1026 1027 probe_ent = malloc(sizeof(struct ahci_uc_priv)); 1028 if (!probe_ent) { 1029 printf("%s: No memory for uc_priv\n", __func__); 1030 return -ENOMEM; 1031 } 1032 1033 uc_priv = probe_ent; 1034 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 1035 1036 uc_priv->host_flags = ATA_FLAG_SATA 1037 | ATA_FLAG_NO_LEGACY 1038 | ATA_FLAG_MMIO 1039 | ATA_FLAG_PIO_DMA 1040 | ATA_FLAG_NO_ATAPI; 1041 uc_priv->pio_mask = 0x1f; 1042 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 1043 1044 uc_priv->mmio_base = base; 1045 1046 /* initialize adapter */ 1047 rc = ahci_host_init(uc_priv); 1048 if (rc) 1049 goto err_out; 1050 1051 ahci_print_info(uc_priv); 1052 1053 rc = ahci_start_ports(uc_priv); 1054 1055 err_out: 1056 return rc; 1057 } 1058 1059 void __weak scsi_init(void) 1060 { 1061 } 1062 1063 #endif 1064 1065 /* 1066 * In the general case of generic rotating media it makes sense to have a 1067 * flush capability. It probably even makes sense in the case of SSDs because 1068 * one cannot always know for sure what kind of internal cache/flush mechanism 1069 * is embodied therein. At first it was planned to invoke this after the last 1070 * write to disk and before rebooting. In practice, knowing, a priori, which 1071 * is the last write is difficult. Because writing to the disk in u-boot is 1072 * very rare, this flush command will be invoked after every block write. 1073 */ 1074 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port) 1075 { 1076 u8 fis[20]; 1077 struct ahci_ioports *pp = &(uc_priv->port[port]); 1078 void __iomem *port_mmio = pp->port_mmio; 1079 u32 cmd_fis_len = 5; /* five dwords */ 1080 1081 /* Preset the FIS */ 1082 memset(fis, 0, 20); 1083 fis[0] = 0x27; /* Host to device FIS. */ 1084 fis[1] = 1 << 7; /* Command FIS. */ 1085 fis[2] = ATA_CMD_FLUSH_EXT; 1086 1087 memcpy((unsigned char *)pp->cmd_tbl, fis, 20); 1088 ahci_fill_cmd_slot(pp, cmd_fis_len); 1089 ahci_dcache_flush_sata_cmd(pp); 1090 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 1091 1092 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 1093 WAIT_MS_FLUSH, 0x1)) { 1094 debug("scsi_ahci: flush command timeout on port %d.\n", port); 1095 return -EIO; 1096 } 1097 1098 return 0; 1099 } 1100 1101 1102 __weak void scsi_bus_reset(void) 1103 { 1104 /*Not implement*/ 1105 } 1106