1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * Author: Jason Jin<Jason.jin@freescale.com> 4 * Zhang Wei<wei.zhang@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 * with the reference on libata and ahci drvier in kernel 9 */ 10 #include <common.h> 11 12 #include <command.h> 13 #include <dm.h> 14 #include <pci.h> 15 #include <asm/processor.h> 16 #include <linux/errno.h> 17 #include <asm/io.h> 18 #include <malloc.h> 19 #include <memalign.h> 20 #include <scsi.h> 21 #include <libata.h> 22 #include <linux/ctype.h> 23 #include <ahci.h> 24 25 static int ata_io_flush(u8 port); 26 27 struct ahci_uc_priv *probe_ent = NULL; 28 u16 *ataid[AHCI_MAX_PORTS]; 29 30 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) 31 32 /* 33 * Some controllers limit number of blocks they can read/write at once. 34 * Contemporary SSD devices work much faster if the read/write size is aligned 35 * to a power of 2. Let's set default to 128 and allowing to be overwritten if 36 * needed. 37 */ 38 #ifndef MAX_SATA_BLOCKS_READ_WRITE 39 #define MAX_SATA_BLOCKS_READ_WRITE 0x80 40 #endif 41 42 /* Maximum timeouts for each event */ 43 #define WAIT_MS_SPINUP 20000 44 #define WAIT_MS_DATAIO 10000 45 #define WAIT_MS_FLUSH 5000 46 #define WAIT_MS_LINKUP 200 47 48 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port) 49 { 50 return base + 0x100 + (port * 0x80); 51 } 52 53 54 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base, 55 unsigned int port_idx) 56 { 57 base = ahci_port_base(base, port_idx); 58 59 port->cmd_addr = base; 60 port->scr_addr = base + PORT_SCR; 61 } 62 63 64 #define msleep(a) udelay(a * 1000) 65 66 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len) 67 { 68 const unsigned long start = begin; 69 const unsigned long end = start + len; 70 71 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); 72 flush_dcache_range(start, end); 73 } 74 75 /* 76 * SATA controller DMAs to physical RAM. Ensure data from the 77 * controller is invalidated from dcache; next access comes from 78 * physical RAM. 79 */ 80 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len) 81 { 82 const unsigned long start = begin; 83 const unsigned long end = start + len; 84 85 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); 86 invalidate_dcache_range(start, end); 87 } 88 89 /* 90 * Ensure data for SATA controller is flushed out of dcache and 91 * written to physical memory. 92 */ 93 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) 94 { 95 ahci_dcache_flush_range((unsigned long)pp->cmd_slot, 96 AHCI_PORT_PRIV_DMA_SZ); 97 } 98 99 static int waiting_for_cmd_completed(void __iomem *offset, 100 int timeout_msec, 101 u32 sign) 102 { 103 int i; 104 u32 status; 105 106 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) 107 msleep(1); 108 109 return (i < timeout_msec) ? 0 : -1; 110 } 111 112 int __weak ahci_link_up(struct ahci_uc_priv *probe_ent, u8 port) 113 { 114 u32 tmp; 115 int j = 0; 116 void __iomem *port_mmio = probe_ent->port[port].port_mmio; 117 118 /* 119 * Bring up SATA link. 120 * SATA link bringup time is usually less than 1 ms; only very 121 * rarely has it taken between 1-2 ms. Never seen it above 2 ms. 122 */ 123 while (j < WAIT_MS_LINKUP) { 124 tmp = readl(port_mmio + PORT_SCR_STAT); 125 tmp &= PORT_SCR_STAT_DET_MASK; 126 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 127 return 0; 128 udelay(1000); 129 j++; 130 } 131 return 1; 132 } 133 134 #ifdef CONFIG_SUNXI_AHCI 135 /* The sunxi AHCI controller requires this undocumented setup */ 136 static void sunxi_dma_init(void __iomem *port_mmio) 137 { 138 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); 139 } 140 #endif 141 142 int ahci_reset(void __iomem *base) 143 { 144 int i = 1000; 145 u32 __iomem *host_ctl_reg = base + HOST_CTL; 146 u32 tmp = readl(host_ctl_reg); /* global controller reset */ 147 148 if ((tmp & HOST_RESET) == 0) 149 writel_with_flush(tmp | HOST_RESET, host_ctl_reg); 150 151 /* 152 * reset must complete within 1 second, or 153 * the hardware should be considered fried. 154 */ 155 do { 156 udelay(1000); 157 tmp = readl(host_ctl_reg); 158 i--; 159 } while ((i > 0) && (tmp & HOST_RESET)); 160 161 if (i == 0) { 162 printf("controller reset failed (0x%x)\n", tmp); 163 return -1; 164 } 165 166 return 0; 167 } 168 169 static int ahci_host_init(struct ahci_uc_priv *probe_ent) 170 { 171 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 172 # ifdef CONFIG_DM_PCI 173 struct udevice *dev = probe_ent->dev; 174 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 175 # else 176 pci_dev_t pdev = probe_ent->dev; 177 unsigned short vendor; 178 # endif 179 u16 tmp16; 180 #endif 181 void __iomem *mmio = probe_ent->mmio_base; 182 u32 tmp, cap_save, cmd; 183 int i, j, ret; 184 void __iomem *port_mmio; 185 u32 port_map; 186 187 debug("ahci_host_init: start\n"); 188 189 cap_save = readl(mmio + HOST_CAP); 190 cap_save &= ((1 << 28) | (1 << 17)); 191 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ 192 193 ret = ahci_reset(probe_ent->mmio_base); 194 if (ret) 195 return ret; 196 197 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); 198 writel(cap_save, mmio + HOST_CAP); 199 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); 200 201 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 202 # ifdef CONFIG_DM_PCI 203 if (pplat->vendor == PCI_VENDOR_ID_INTEL) { 204 u16 tmp16; 205 206 dm_pci_read_config16(dev, 0x92, &tmp16); 207 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf); 208 } 209 # else 210 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); 211 212 if (vendor == PCI_VENDOR_ID_INTEL) { 213 u16 tmp16; 214 pci_read_config_word(pdev, 0x92, &tmp16); 215 tmp16 |= 0xf; 216 pci_write_config_word(pdev, 0x92, tmp16); 217 } 218 # endif 219 #endif 220 probe_ent->cap = readl(mmio + HOST_CAP); 221 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); 222 port_map = probe_ent->port_map; 223 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; 224 225 debug("cap 0x%x port_map 0x%x n_ports %d\n", 226 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); 227 228 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) 229 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; 230 231 for (i = 0; i < probe_ent->n_ports; i++) { 232 if (!(port_map & (1 << i))) 233 continue; 234 probe_ent->port[i].port_mmio = ahci_port_base(mmio, i); 235 port_mmio = (u8 *) probe_ent->port[i].port_mmio; 236 ahci_setup_port(&probe_ent->port[i], mmio, i); 237 238 /* make sure port is not active */ 239 tmp = readl(port_mmio + PORT_CMD); 240 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 241 PORT_CMD_FIS_RX | PORT_CMD_START)) { 242 debug("Port %d is active. Deactivating.\n", i); 243 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 244 PORT_CMD_FIS_RX | PORT_CMD_START); 245 writel_with_flush(tmp, port_mmio + PORT_CMD); 246 247 /* spec says 500 msecs for each bit, so 248 * this is slightly incorrect. 249 */ 250 msleep(500); 251 } 252 253 #ifdef CONFIG_SUNXI_AHCI 254 sunxi_dma_init(port_mmio); 255 #endif 256 257 /* Add the spinup command to whatever mode bits may 258 * already be on in the command register. 259 */ 260 cmd = readl(port_mmio + PORT_CMD); 261 cmd |= PORT_CMD_SPIN_UP; 262 writel_with_flush(cmd, port_mmio + PORT_CMD); 263 264 /* Bring up SATA link. */ 265 ret = ahci_link_up(probe_ent, i); 266 if (ret) { 267 printf("SATA link %d timeout.\n", i); 268 continue; 269 } else { 270 debug("SATA link ok.\n"); 271 } 272 273 /* Clear error status */ 274 tmp = readl(port_mmio + PORT_SCR_ERR); 275 if (tmp) 276 writel(tmp, port_mmio + PORT_SCR_ERR); 277 278 debug("Spinning up device on SATA port %d... ", i); 279 280 j = 0; 281 while (j < WAIT_MS_SPINUP) { 282 tmp = readl(port_mmio + PORT_TFDATA); 283 if (!(tmp & (ATA_BUSY | ATA_DRQ))) 284 break; 285 udelay(1000); 286 tmp = readl(port_mmio + PORT_SCR_STAT); 287 tmp &= PORT_SCR_STAT_DET_MASK; 288 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 289 break; 290 j++; 291 } 292 293 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; 294 if (tmp == PORT_SCR_STAT_DET_COMINIT) { 295 debug("SATA link %d down (COMINIT received), retrying...\n", i); 296 i--; 297 continue; 298 } 299 300 printf("Target spinup took %d ms.\n", j); 301 if (j == WAIT_MS_SPINUP) 302 debug("timeout.\n"); 303 else 304 debug("ok.\n"); 305 306 tmp = readl(port_mmio + PORT_SCR_ERR); 307 debug("PORT_SCR_ERR 0x%x\n", tmp); 308 writel(tmp, port_mmio + PORT_SCR_ERR); 309 310 /* ack any pending irq events for this port */ 311 tmp = readl(port_mmio + PORT_IRQ_STAT); 312 debug("PORT_IRQ_STAT 0x%x\n", tmp); 313 if (tmp) 314 writel(tmp, port_mmio + PORT_IRQ_STAT); 315 316 writel(1 << i, mmio + HOST_IRQ_STAT); 317 318 /* register linkup ports */ 319 tmp = readl(port_mmio + PORT_SCR_STAT); 320 debug("SATA port %d status: 0x%x\n", i, tmp); 321 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) 322 probe_ent->link_port_map |= (0x01 << i); 323 } 324 325 tmp = readl(mmio + HOST_CTL); 326 debug("HOST_CTL 0x%x\n", tmp); 327 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 328 tmp = readl(mmio + HOST_CTL); 329 debug("HOST_CTL 0x%x\n", tmp); 330 #if !defined(CONFIG_DM_SCSI) 331 #ifndef CONFIG_SCSI_AHCI_PLAT 332 # ifdef CONFIG_DM_PCI 333 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16); 334 tmp |= PCI_COMMAND_MASTER; 335 dm_pci_write_config16(dev, PCI_COMMAND, tmp16); 336 # else 337 pci_read_config_word(pdev, PCI_COMMAND, &tmp16); 338 tmp |= PCI_COMMAND_MASTER; 339 pci_write_config_word(pdev, PCI_COMMAND, tmp16); 340 # endif 341 #endif 342 #endif 343 return 0; 344 } 345 346 347 static void ahci_print_info(struct ahci_uc_priv *probe_ent) 348 { 349 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) 350 # if defined(CONFIG_DM_PCI) 351 struct udevice *dev = probe_ent->dev; 352 # else 353 pci_dev_t pdev = probe_ent->dev; 354 # endif 355 u16 cc; 356 #endif 357 void __iomem *mmio = probe_ent->mmio_base; 358 u32 vers, cap, cap2, impl, speed; 359 const char *speed_s; 360 const char *scc_s; 361 362 vers = readl(mmio + HOST_VERSION); 363 cap = probe_ent->cap; 364 cap2 = readl(mmio + HOST_CAP2); 365 impl = probe_ent->port_map; 366 367 speed = (cap >> 20) & 0xf; 368 if (speed == 1) 369 speed_s = "1.5"; 370 else if (speed == 2) 371 speed_s = "3"; 372 else if (speed == 3) 373 speed_s = "6"; 374 else 375 speed_s = "?"; 376 377 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI) 378 scc_s = "SATA"; 379 #else 380 # ifdef CONFIG_DM_PCI 381 dm_pci_read_config16(dev, 0x0a, &cc); 382 # else 383 pci_read_config_word(pdev, 0x0a, &cc); 384 # endif 385 if (cc == 0x0101) 386 scc_s = "IDE"; 387 else if (cc == 0x0106) 388 scc_s = "SATA"; 389 else if (cc == 0x0104) 390 scc_s = "RAID"; 391 else 392 scc_s = "unknown"; 393 #endif 394 printf("AHCI %02x%02x.%02x%02x " 395 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 396 (vers >> 24) & 0xff, 397 (vers >> 16) & 0xff, 398 (vers >> 8) & 0xff, 399 vers & 0xff, 400 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); 401 402 printf("flags: " 403 "%s%s%s%s%s%s%s" 404 "%s%s%s%s%s%s%s" 405 "%s%s%s%s%s%s\n", 406 cap & (1 << 31) ? "64bit " : "", 407 cap & (1 << 30) ? "ncq " : "", 408 cap & (1 << 28) ? "ilck " : "", 409 cap & (1 << 27) ? "stag " : "", 410 cap & (1 << 26) ? "pm " : "", 411 cap & (1 << 25) ? "led " : "", 412 cap & (1 << 24) ? "clo " : "", 413 cap & (1 << 19) ? "nz " : "", 414 cap & (1 << 18) ? "only " : "", 415 cap & (1 << 17) ? "pmp " : "", 416 cap & (1 << 16) ? "fbss " : "", 417 cap & (1 << 15) ? "pio " : "", 418 cap & (1 << 14) ? "slum " : "", 419 cap & (1 << 13) ? "part " : "", 420 cap & (1 << 7) ? "ccc " : "", 421 cap & (1 << 6) ? "ems " : "", 422 cap & (1 << 5) ? "sxs " : "", 423 cap2 & (1 << 2) ? "apst " : "", 424 cap2 & (1 << 1) ? "nvmp " : "", 425 cap2 & (1 << 0) ? "boh " : ""); 426 } 427 428 #ifndef CONFIG_SCSI_AHCI_PLAT 429 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI) 430 static int ahci_init_one(struct udevice *dev) 431 # else 432 static int ahci_init_one(pci_dev_t dev) 433 # endif 434 { 435 #if !defined(CONFIG_DM_SCSI) 436 u16 vendor; 437 #endif 438 int rc; 439 440 probe_ent = malloc(sizeof(struct ahci_uc_priv)); 441 if (!probe_ent) { 442 printf("%s: No memory for probe_ent\n", __func__); 443 return -ENOMEM; 444 } 445 446 memset(probe_ent, 0, sizeof(struct ahci_uc_priv)); 447 probe_ent->dev = dev; 448 449 probe_ent->host_flags = ATA_FLAG_SATA 450 | ATA_FLAG_NO_LEGACY 451 | ATA_FLAG_MMIO 452 | ATA_FLAG_PIO_DMA 453 | ATA_FLAG_NO_ATAPI; 454 probe_ent->pio_mask = 0x1f; 455 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 456 457 #if !defined(CONFIG_DM_SCSI) 458 #ifdef CONFIG_DM_PCI 459 probe_ent->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 460 PCI_REGION_MEM); 461 462 /* Take from kernel: 463 * JMicron-specific fixup: 464 * make sure we're in AHCI mode 465 */ 466 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor); 467 if (vendor == 0x197b) 468 dm_pci_write_config8(dev, 0x41, 0xa1); 469 #else 470 probe_ent->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5, 471 PCI_REGION_MEM); 472 473 /* Take from kernel: 474 * JMicron-specific fixup: 475 * make sure we're in AHCI mode 476 */ 477 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); 478 if (vendor == 0x197b) 479 pci_write_config_byte(dev, 0x41, 0xa1); 480 #endif 481 #else 482 struct scsi_platdata *plat = dev_get_uclass_platdata(dev); 483 probe_ent->mmio_base = (void *)plat->base; 484 #endif 485 486 debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base); 487 /* initialize adapter */ 488 rc = ahci_host_init(probe_ent); 489 if (rc) 490 goto err_out; 491 492 ahci_print_info(probe_ent); 493 494 return 0; 495 496 err_out: 497 return rc; 498 } 499 #endif 500 501 #define MAX_DATA_BYTE_COUNT (4*1024*1024) 502 503 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) 504 { 505 struct ahci_ioports *pp = &(probe_ent->port[port]); 506 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 507 u32 sg_count; 508 int i; 509 510 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; 511 if (sg_count > AHCI_MAX_SG) { 512 printf("Error:Too much sg!\n"); 513 return -1; 514 } 515 516 for (i = 0; i < sg_count; i++) { 517 ahci_sg->addr = 518 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT); 519 ahci_sg->addr_hi = 0; 520 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 521 (buf_len < MAX_DATA_BYTE_COUNT 522 ? (buf_len - 1) 523 : (MAX_DATA_BYTE_COUNT - 1))); 524 ahci_sg++; 525 buf_len -= MAX_DATA_BYTE_COUNT; 526 } 527 528 return sg_count; 529 } 530 531 532 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) 533 { 534 pp->cmd_slot->opts = cpu_to_le32(opts); 535 pp->cmd_slot->status = 0; 536 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 537 #ifdef CONFIG_PHYS_64BIT 538 pp->cmd_slot->tbl_addr_hi = 539 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 540 #endif 541 } 542 543 static int wait_spinup(void __iomem *port_mmio) 544 { 545 ulong start; 546 u32 tf_data; 547 548 start = get_timer(0); 549 do { 550 tf_data = readl(port_mmio + PORT_TFDATA); 551 if (!(tf_data & ATA_BUSY)) 552 return 0; 553 } while (get_timer(start) < WAIT_MS_SPINUP); 554 555 return -ETIMEDOUT; 556 } 557 558 static int ahci_port_start(u8 port) 559 { 560 struct ahci_ioports *pp = &(probe_ent->port[port]); 561 void __iomem *port_mmio = pp->port_mmio; 562 u32 port_status; 563 void __iomem *mem; 564 565 debug("Enter start port: %d\n", port); 566 port_status = readl(port_mmio + PORT_SCR_STAT); 567 debug("Port %d status: %x\n", port, port_status); 568 if ((port_status & 0xf) != 0x03) { 569 printf("No Link on this port!\n"); 570 return -1; 571 } 572 573 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); 574 if (!mem) { 575 free(pp); 576 printf("%s: No mem for table!\n", __func__); 577 return -ENOMEM; 578 } 579 580 /* Aligned to 2048-bytes */ 581 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ); 582 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); 583 584 /* 585 * First item in chunk of DMA memory: 32-slot command table, 586 * 32 bytes each in size 587 */ 588 pp->cmd_slot = 589 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); 590 debug("cmd_slot = %p\n", pp->cmd_slot); 591 mem += (AHCI_CMD_SLOT_SZ + 224); 592 593 /* 594 * Second item: Received-FIS area 595 */ 596 pp->rx_fis = virt_to_phys((void *)mem); 597 mem += AHCI_RX_FIS_SZ; 598 599 /* 600 * Third item: data area for storing a single command 601 * and its scatter-gather table 602 */ 603 pp->cmd_tbl = virt_to_phys((void *)mem); 604 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl); 605 606 mem += AHCI_CMD_TBL_HDR; 607 pp->cmd_tbl_sg = 608 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); 609 610 writel_with_flush((unsigned long)pp->cmd_slot, 611 port_mmio + PORT_LST_ADDR); 612 613 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); 614 615 #ifdef CONFIG_SUNXI_AHCI 616 sunxi_dma_init(port_mmio); 617 #endif 618 619 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 620 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 621 PORT_CMD_START, port_mmio + PORT_CMD); 622 623 debug("Exit start port %d\n", port); 624 625 /* 626 * Make sure interface is not busy based on error and status 627 * information from task file data register before proceeding 628 */ 629 return wait_spinup(port_mmio); 630 } 631 632 633 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, 634 int buf_len, u8 is_write) 635 { 636 637 struct ahci_ioports *pp = &(probe_ent->port[port]); 638 void __iomem *port_mmio = pp->port_mmio; 639 u32 opts; 640 u32 port_status; 641 int sg_count; 642 643 debug("Enter %s: for port %d\n", __func__, port); 644 645 if (port > probe_ent->n_ports) { 646 printf("Invalid port number %d\n", port); 647 return -1; 648 } 649 650 port_status = readl(port_mmio + PORT_SCR_STAT); 651 if ((port_status & 0xf) != 0x03) { 652 debug("No Link on port %d!\n", port); 653 return -1; 654 } 655 656 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); 657 658 sg_count = ahci_fill_sg(port, buf, buf_len); 659 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); 660 ahci_fill_cmd_slot(pp, opts); 661 662 ahci_dcache_flush_sata_cmd(pp); 663 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len); 664 665 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 666 667 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 668 WAIT_MS_DATAIO, 0x1)) { 669 printf("timeout exit!\n"); 670 return -1; 671 } 672 673 ahci_dcache_invalidate_range((unsigned long)buf, 674 (unsigned long)buf_len); 675 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); 676 677 return 0; 678 } 679 680 681 static char *ata_id_strcpy(u16 *target, u16 *src, int len) 682 { 683 int i; 684 for (i = 0; i < len / 2; i++) 685 target[i] = swab16(src[i]); 686 return (char *)target; 687 } 688 689 /* 690 * SCSI INQUIRY command operation. 691 */ 692 static int ata_scsiop_inquiry(struct scsi_cmd *pccb) 693 { 694 static const u8 hdr[] = { 695 0, 696 0, 697 0x5, /* claim SPC-3 version compatibility */ 698 2, 699 95 - 4, 700 }; 701 u8 fis[20]; 702 u16 *idbuf; 703 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS); 704 u8 port; 705 706 /* Clean ccb data buffer */ 707 memset(pccb->pdata, 0, pccb->datalen); 708 709 memcpy(pccb->pdata, hdr, sizeof(hdr)); 710 711 if (pccb->datalen <= 35) 712 return 0; 713 714 memset(fis, 0, sizeof(fis)); 715 /* Construct the FIS */ 716 fis[0] = 0x27; /* Host to device FIS. */ 717 fis[1] = 1 << 7; /* Command FIS. */ 718 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */ 719 720 /* Read id from sata */ 721 port = pccb->target; 722 723 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid, 724 ATA_ID_WORDS * 2, 0)) { 725 debug("scsi_ahci: SCSI inquiry command failure.\n"); 726 return -EIO; 727 } 728 729 if (!ataid[port]) { 730 ataid[port] = malloc(ATA_ID_WORDS * 2); 731 if (!ataid[port]) { 732 printf("%s: No memory for ataid[port]\n", __func__); 733 return -ENOMEM; 734 } 735 } 736 737 idbuf = ataid[port]; 738 739 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2); 740 ata_swap_buf_le16(idbuf, ATA_ID_WORDS); 741 742 memcpy(&pccb->pdata[8], "ATA ", 8); 743 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16); 744 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4); 745 746 #ifdef DEBUG 747 ata_dump_id(idbuf); 748 #endif 749 return 0; 750 } 751 752 753 /* 754 * SCSI READ10/WRITE10 command operation. 755 */ 756 static int ata_scsiop_read_write(struct scsi_cmd *pccb, u8 is_write) 757 { 758 lbaint_t lba = 0; 759 u16 blocks = 0; 760 u8 fis[20]; 761 u8 *user_buffer = pccb->pdata; 762 u32 user_buffer_size = pccb->datalen; 763 764 /* Retrieve the base LBA number from the ccb structure. */ 765 if (pccb->cmd[0] == SCSI_READ16) { 766 memcpy(&lba, pccb->cmd + 2, 8); 767 lba = be64_to_cpu(lba); 768 } else { 769 u32 temp; 770 memcpy(&temp, pccb->cmd + 2, 4); 771 lba = be32_to_cpu(temp); 772 } 773 774 /* 775 * Retrieve the base LBA number and the block count from 776 * the ccb structure. 777 * 778 * For 10-byte and 16-byte SCSI R/W commands, transfer 779 * length 0 means transfer 0 block of data. 780 * However, for ATA R/W commands, sector count 0 means 781 * 256 or 65536 sectors, not 0 sectors as in SCSI. 782 * 783 * WARNING: one or two older ATA drives treat 0 as 0... 784 */ 785 if (pccb->cmd[0] == SCSI_READ16) 786 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]); 787 else 788 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); 789 790 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n", 791 is_write ? "write" : "read", blocks, lba); 792 793 /* Preset the FIS */ 794 memset(fis, 0, sizeof(fis)); 795 fis[0] = 0x27; /* Host to device FIS. */ 796 fis[1] = 1 << 7; /* Command FIS. */ 797 /* Command byte (read/write). */ 798 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; 799 800 while (blocks) { 801 u16 now_blocks; /* number of blocks per iteration */ 802 u32 transfer_size; /* number of bytes per iteration */ 803 804 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks); 805 806 transfer_size = ATA_SECT_SIZE * now_blocks; 807 if (transfer_size > user_buffer_size) { 808 printf("scsi_ahci: Error: buffer too small.\n"); 809 return -EIO; 810 } 811 812 /* 813 * LBA48 SATA command but only use 32bit address range within 814 * that (unless we've enabled 64bit LBA support). The next 815 * smaller command range (28bit) is too small. 816 */ 817 fis[4] = (lba >> 0) & 0xff; 818 fis[5] = (lba >> 8) & 0xff; 819 fis[6] = (lba >> 16) & 0xff; 820 fis[7] = 1 << 6; /* device reg: set LBA mode */ 821 fis[8] = ((lba >> 24) & 0xff); 822 #ifdef CONFIG_SYS_64BIT_LBA 823 if (pccb->cmd[0] == SCSI_READ16) { 824 fis[9] = ((lba >> 32) & 0xff); 825 fis[10] = ((lba >> 40) & 0xff); 826 } 827 #endif 828 829 fis[3] = 0xe0; /* features */ 830 831 /* Block (sector) count */ 832 fis[12] = (now_blocks >> 0) & 0xff; 833 fis[13] = (now_blocks >> 8) & 0xff; 834 835 /* Read/Write from ahci */ 836 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), 837 user_buffer, transfer_size, 838 is_write)) { 839 debug("scsi_ahci: SCSI %s10 command failure.\n", 840 is_write ? "WRITE" : "READ"); 841 return -EIO; 842 } 843 844 /* If this transaction is a write, do a following flush. 845 * Writes in u-boot are so rare, and the logic to know when is 846 * the last write and do a flush only there is sufficiently 847 * difficult. Just do a flush after every write. This incurs, 848 * usually, one extra flush when the rare writes do happen. 849 */ 850 if (is_write) { 851 if (-EIO == ata_io_flush(pccb->target)) 852 return -EIO; 853 } 854 user_buffer += transfer_size; 855 user_buffer_size -= transfer_size; 856 blocks -= now_blocks; 857 lba += now_blocks; 858 } 859 860 return 0; 861 } 862 863 864 /* 865 * SCSI READ CAPACITY10 command operation. 866 */ 867 static int ata_scsiop_read_capacity10(struct scsi_cmd *pccb) 868 { 869 u32 cap; 870 u64 cap64; 871 u32 block_size; 872 873 if (!ataid[pccb->target]) { 874 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " 875 "\tNo ATA info!\n" 876 "\tPlease run SCSI command INQUIRY first!\n"); 877 return -EPERM; 878 } 879 880 cap64 = ata_id_n_sectors(ataid[pccb->target]); 881 if (cap64 > 0x100000000ULL) 882 cap64 = 0xffffffff; 883 884 cap = cpu_to_be32(cap64); 885 memcpy(pccb->pdata, &cap, sizeof(cap)); 886 887 block_size = cpu_to_be32((u32)512); 888 memcpy(&pccb->pdata[4], &block_size, 4); 889 890 return 0; 891 } 892 893 894 /* 895 * SCSI READ CAPACITY16 command operation. 896 */ 897 static int ata_scsiop_read_capacity16(struct scsi_cmd *pccb) 898 { 899 u64 cap; 900 u64 block_size; 901 902 if (!ataid[pccb->target]) { 903 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " 904 "\tNo ATA info!\n" 905 "\tPlease run SCSI command INQUIRY first!\n"); 906 return -EPERM; 907 } 908 909 cap = ata_id_n_sectors(ataid[pccb->target]); 910 cap = cpu_to_be64(cap); 911 memcpy(pccb->pdata, &cap, sizeof(cap)); 912 913 block_size = cpu_to_be64((u64)512); 914 memcpy(&pccb->pdata[8], &block_size, 8); 915 916 return 0; 917 } 918 919 920 /* 921 * SCSI TEST UNIT READY command operation. 922 */ 923 static int ata_scsiop_test_unit_ready(struct scsi_cmd *pccb) 924 { 925 return (ataid[pccb->target]) ? 0 : -EPERM; 926 } 927 928 929 int scsi_exec(struct scsi_cmd *pccb) 930 { 931 int ret; 932 933 switch (pccb->cmd[0]) { 934 case SCSI_READ16: 935 case SCSI_READ10: 936 ret = ata_scsiop_read_write(pccb, 0); 937 break; 938 case SCSI_WRITE10: 939 ret = ata_scsiop_read_write(pccb, 1); 940 break; 941 case SCSI_RD_CAPAC10: 942 ret = ata_scsiop_read_capacity10(pccb); 943 break; 944 case SCSI_RD_CAPAC16: 945 ret = ata_scsiop_read_capacity16(pccb); 946 break; 947 case SCSI_TST_U_RDY: 948 ret = ata_scsiop_test_unit_ready(pccb); 949 break; 950 case SCSI_INQUIRY: 951 ret = ata_scsiop_inquiry(pccb); 952 break; 953 default: 954 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); 955 return false; 956 } 957 958 if (ret) { 959 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); 960 return false; 961 } 962 return true; 963 964 } 965 966 #if defined(CONFIG_DM_SCSI) 967 void scsi_low_level_init(int busdevfunc, struct udevice *dev) 968 #else 969 void scsi_low_level_init(int busdevfunc) 970 #endif 971 { 972 int i; 973 u32 linkmap; 974 975 #ifndef CONFIG_SCSI_AHCI_PLAT 976 # if defined(CONFIG_DM_PCI) 977 struct udevice *dev; 978 int ret; 979 980 ret = dm_pci_bus_find_bdf(busdevfunc, &dev); 981 if (ret) 982 return; 983 ahci_init_one(dev); 984 # elif defined(CONFIG_DM_SCSI) 985 ahci_init_one(dev); 986 # else 987 ahci_init_one(busdevfunc); 988 # endif 989 #endif 990 991 linkmap = probe_ent->link_port_map; 992 993 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { 994 if (((linkmap >> i) & 0x01)) { 995 if (ahci_port_start((u8) i)) { 996 printf("Can not start port %d\n", i); 997 continue; 998 } 999 } 1000 } 1001 } 1002 1003 #ifdef CONFIG_SCSI_AHCI_PLAT 1004 int ahci_init(void __iomem *base) 1005 { 1006 int i, rc = 0; 1007 u32 linkmap; 1008 1009 probe_ent = malloc(sizeof(struct ahci_uc_priv)); 1010 if (!probe_ent) { 1011 printf("%s: No memory for probe_ent\n", __func__); 1012 return -ENOMEM; 1013 } 1014 1015 memset(probe_ent, 0, sizeof(struct ahci_uc_priv)); 1016 1017 probe_ent->host_flags = ATA_FLAG_SATA 1018 | ATA_FLAG_NO_LEGACY 1019 | ATA_FLAG_MMIO 1020 | ATA_FLAG_PIO_DMA 1021 | ATA_FLAG_NO_ATAPI; 1022 probe_ent->pio_mask = 0x1f; 1023 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 1024 1025 probe_ent->mmio_base = base; 1026 1027 /* initialize adapter */ 1028 rc = ahci_host_init(probe_ent); 1029 if (rc) 1030 goto err_out; 1031 1032 ahci_print_info(probe_ent); 1033 1034 linkmap = probe_ent->link_port_map; 1035 1036 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { 1037 if (((linkmap >> i) & 0x01)) { 1038 if (ahci_port_start((u8) i)) { 1039 printf("Can not start port %d\n", i); 1040 continue; 1041 } 1042 } 1043 } 1044 err_out: 1045 return rc; 1046 } 1047 1048 void __weak scsi_init(void) 1049 { 1050 } 1051 1052 #endif 1053 1054 /* 1055 * In the general case of generic rotating media it makes sense to have a 1056 * flush capability. It probably even makes sense in the case of SSDs because 1057 * one cannot always know for sure what kind of internal cache/flush mechanism 1058 * is embodied therein. At first it was planned to invoke this after the last 1059 * write to disk and before rebooting. In practice, knowing, a priori, which 1060 * is the last write is difficult. Because writing to the disk in u-boot is 1061 * very rare, this flush command will be invoked after every block write. 1062 */ 1063 static int ata_io_flush(u8 port) 1064 { 1065 u8 fis[20]; 1066 struct ahci_ioports *pp = &(probe_ent->port[port]); 1067 void __iomem *port_mmio = pp->port_mmio; 1068 u32 cmd_fis_len = 5; /* five dwords */ 1069 1070 /* Preset the FIS */ 1071 memset(fis, 0, 20); 1072 fis[0] = 0x27; /* Host to device FIS. */ 1073 fis[1] = 1 << 7; /* Command FIS. */ 1074 fis[2] = ATA_CMD_FLUSH_EXT; 1075 1076 memcpy((unsigned char *)pp->cmd_tbl, fis, 20); 1077 ahci_fill_cmd_slot(pp, cmd_fis_len); 1078 ahci_dcache_flush_sata_cmd(pp); 1079 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 1080 1081 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 1082 WAIT_MS_FLUSH, 0x1)) { 1083 debug("scsi_ahci: flush command timeout on port %d.\n", port); 1084 return -EIO; 1085 } 1086 1087 return 0; 1088 } 1089 1090 1091 __weak void scsi_bus_reset(void) 1092 { 1093 /*Not implement*/ 1094 } 1095