1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2021, Rockchip Electronics Co., Ltd 4 * 5 * Rockchip SARADC driver for U-Boot 6 */ 7 8 #include <common.h> 9 #include <adc.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <linux/iopoll.h> 13 #include <errno.h> 14 #include <asm/io.h> 15 #include <reset.h> 16 17 #define SARADC2_EN_END_INT BIT(0) 18 #define SARADC2_START BIT(4) 19 #define SARADC2_SINGLE_MODE BIT(5) 20 21 #define SARADC_TIMEOUT (100 * 1000) 22 23 struct rockchip_saradc_regs { 24 u32 conv_con; 25 u32 t_pd_soc; 26 u32 t_as_soc; 27 u32 t_das_soc; 28 u32 t_sel_soc; 29 u32 high_comp0; 30 u32 high_comp1; 31 u32 high_comp2; 32 u32 high_comp3; 33 u32 high_comp4; 34 u32 high_comp5; 35 u32 reserved0044; 36 u32 high_comp7; 37 u32 high_comp8; 38 u32 high_comp9; 39 u32 high_comp10; 40 u32 high_comp11; 41 u32 high_comp12; 42 u32 high_comp13; 43 u32 high_comp14; 44 u32 high_comp15; 45 u32 low_comp0; 46 u32 low_comp1; 47 u32 low_comp2; 48 u32 low_comp3; 49 u32 low_comp4; 50 u32 low_comp5; 51 u32 low_comp6; 52 u32 low_comp7; 53 u32 low_comp8; 54 u32 low_comp9; 55 u32 low_comp10; 56 u32 low_comp11; 57 u32 low_comp12; 58 u32 low_comp13; 59 u32 low_comp14; 60 u32 low_comp15; 61 u32 debounce; 62 u32 ht_int_en; 63 u32 lt_int_en; 64 u32 reserved0160[24]; 65 u32 mt_int_en; 66 u32 end_int_en; 67 u32 st_con; 68 u32 status; 69 u32 end_int_st; 70 u32 ht_int_st; 71 u32 lt_int_st; 72 u32 mt_int_st; 73 u32 data0; 74 u32 data1; 75 u32 data2; 76 u32 data3; 77 u32 data4; 78 u32 data5; 79 u32 data6; 80 u32 data7; 81 u32 data8; 82 u32 data9; 83 u32 data10; 84 u32 data11; 85 u32 data12; 86 u32 data13; 87 u32 data14; 88 u32 data15; 89 u32 auto_ch_en; 90 }; 91 92 struct rockchip_saradc_data { 93 int num_bits; 94 int num_channels; 95 unsigned long clk_rate; 96 int das_soc_data; 97 }; 98 99 struct rockchip_saradc_priv { 100 struct rockchip_saradc_regs *regs; 101 int active_channel; 102 const struct rockchip_saradc_data *data; 103 struct reset_ctl rst; 104 }; 105 106 static int rockchip_saradc_channel_data(struct udevice *dev, int channel, 107 unsigned int *data) 108 { 109 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 110 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); 111 u32 status; 112 113 if (channel != priv->active_channel) { 114 pr_err("Requested channel is not active!"); 115 return -EINVAL; 116 } 117 118 /* Wait for end conversion interrupt status. */ 119 if (readl_poll_timeout(&priv->regs->end_int_st, status, 120 status & SARADC2_EN_END_INT, SARADC_TIMEOUT)) { 121 pr_err("Wait for end conversion interrupt status timeout!\n"); 122 return -ETIMEDOUT; 123 } 124 125 /* Clear irq. */ 126 writel(0x1, &priv->regs->end_int_st); 127 128 *data = readl(&priv->regs->data0 + priv->active_channel); 129 *data &= uc_pdata->data_mask; 130 131 return 0; 132 } 133 134 static int rockchip_saradc_start_channel(struct udevice *dev, int channel) 135 { 136 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 137 int val; 138 139 if (channel < 0 || channel >= priv->data->num_channels) { 140 pr_err("Requested channel is invalid!"); 141 return -EINVAL; 142 } 143 144 #if CONFIG_IS_ENABLED(DM_RESET) 145 reset_assert(&priv->rst); 146 udelay(10); 147 reset_deassert(&priv->rst); 148 #endif 149 writel(0x20, &priv->regs->t_pd_soc); 150 if (priv->data->das_soc_data) 151 writel(priv->data->das_soc_data, &priv->regs->t_das_soc); 152 else 153 writel(0xc, &priv->regs->t_das_soc); 154 val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT; 155 writel(val, &priv->regs->end_int_en); 156 val = SARADC2_START | SARADC2_SINGLE_MODE | channel; 157 writel(val << 16 | val, &priv->regs->conv_con); 158 159 udelay(100); 160 161 priv->active_channel = channel; 162 163 return 0; 164 } 165 166 static int rockchip_saradc_stop(struct udevice *dev) 167 { 168 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 169 170 priv->active_channel = -1; 171 172 return 0; 173 } 174 175 static int rockchip_saradc_probe(struct udevice *dev) 176 { 177 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 178 struct clk clk; 179 int ret; 180 181 #if CONFIG_IS_ENABLED(DM_RESET) 182 ret = reset_get_by_name(dev, "saradc-apb", &priv->rst); 183 if (ret) { 184 debug("reset_get_by_name() failed: %d\n", ret); 185 return ret; 186 } 187 #endif 188 189 ret = clk_get_by_index(dev, 0, &clk); 190 if (ret) 191 return ret; 192 193 ret = clk_set_rate(&clk, priv->data->clk_rate); 194 if (IS_ERR_VALUE(ret)) 195 return ret; 196 197 /* Wait until pll stable */ 198 mdelay(5); 199 200 priv->active_channel = -1; 201 202 return 0; 203 } 204 205 static int rockchip_saradc_ofdata_to_platdata(struct udevice *dev) 206 { 207 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); 208 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 209 struct rockchip_saradc_data *data; 210 211 data = (struct rockchip_saradc_data *)dev_get_driver_data(dev); 212 priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev); 213 if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) { 214 pr_err("Dev: %s - can't get address!", dev->name); 215 return -ENODATA; 216 } 217 218 priv->data = data; 219 uc_pdata->data_mask = (1 << priv->data->num_bits) - 1; 220 uc_pdata->data_format = ADC_DATA_FORMAT_BIN; 221 uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; 222 uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; 223 224 return 0; 225 } 226 227 static const struct adc_ops rockchip_saradc_ops = { 228 .start_channel = rockchip_saradc_start_channel, 229 .channel_data = rockchip_saradc_channel_data, 230 .stop = rockchip_saradc_stop, 231 }; 232 233 static const struct rockchip_saradc_data rk3588_saradc_data = { 234 .num_bits = 12, 235 .num_channels = 8, 236 .clk_rate = 1000000, 237 }; 238 239 static const struct rockchip_saradc_data rk3562_saradc_data = { 240 .num_bits = 10, 241 .num_channels = 8, 242 .clk_rate = 1000000, 243 }; 244 245 static const struct rockchip_saradc_data rv1106_saradc_data = { 246 .num_bits = 10, 247 .num_channels = 2, 248 .clk_rate = 1000000, 249 }; 250 251 static const struct rockchip_saradc_data rv1103b_saradc_data = { 252 .num_bits = 10, 253 .num_channels = 1, 254 .clk_rate = 1000000, 255 }; 256 257 static const struct rockchip_saradc_data rv1126b_saradc_data = { 258 .num_bits = 13, 259 .num_channels = 8, 260 .clk_rate = 24000000, 261 .das_soc_data = 0x14, 262 }; 263 264 static const struct udevice_id rockchip_saradc_ids[] = { 265 { 266 .compatible = "rockchip,rk3588-saradc", 267 .data = (ulong)&rk3588_saradc_data 268 }, 269 { 270 .compatible = "rockchip,rk3528-saradc", 271 .data = (ulong)&rk3588_saradc_data 272 }, 273 { 274 .compatible = "rockchip,rk3562-saradc", 275 .data = (ulong)&rk3562_saradc_data 276 }, 277 { 278 .compatible = "rockchip,rv1106-saradc", 279 .data = (ulong)&rv1106_saradc_data 280 }, 281 { 282 .compatible = "rockchip,rv1103b-saradc", 283 .data = (ulong)&rv1103b_saradc_data 284 }, 285 { 286 .compatible = "rockchip,rv1126b-saradc", 287 .data = (ulong)&rv1126b_saradc_data 288 }, 289 { } 290 }; 291 292 U_BOOT_DRIVER(rockchip_saradc_v2) = { 293 .name = "rockchip_saradc_v2", 294 .id = UCLASS_ADC, 295 .of_match = rockchip_saradc_ids, 296 .ops = &rockchip_saradc_ops, 297 .probe = rockchip_saradc_probe, 298 .ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata, 299 .priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv), 300 }; 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