1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2021, Rockchip Electronics Co., Ltd 4 * 5 * Rockchip SARADC driver for U-Boot 6 */ 7 8 #include <common.h> 9 #include <adc.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <asm/io.h> 14 15 #define SARADC2_EN_END_INT BIT(0) 16 #define SARADC2_START BIT(4) 17 #define SARADC2_SINGLE_MODE BIT(5) 18 19 #define SARADC_TIMEOUT (100 * 1000) 20 21 struct rockchip_saradc_regs { 22 u32 conv_con; 23 u32 t_pd_soc; 24 u32 t_as_soc; 25 u32 t_das_soc; 26 u32 t_sel_soc; 27 u32 high_comp0; 28 u32 high_comp1; 29 u32 high_comp2; 30 u32 high_comp3; 31 u32 high_comp4; 32 u32 high_comp5; 33 u32 reserved0044; 34 u32 high_comp7; 35 u32 high_comp8; 36 u32 high_comp9; 37 u32 high_comp10; 38 u32 high_comp11; 39 u32 high_comp12; 40 u32 high_comp13; 41 u32 high_comp14; 42 u32 high_comp15; 43 u32 low_comp0; 44 u32 low_comp1; 45 u32 low_comp2; 46 u32 low_comp3; 47 u32 low_comp4; 48 u32 low_comp5; 49 u32 low_comp6; 50 u32 low_comp7; 51 u32 low_comp8; 52 u32 low_comp9; 53 u32 low_comp10; 54 u32 low_comp11; 55 u32 low_comp12; 56 u32 low_comp13; 57 u32 low_comp14; 58 u32 low_comp15; 59 u32 debounce; 60 u32 ht_int_en; 61 u32 lt_int_en; 62 u32 reserved0160[24]; 63 u32 mt_int_en; 64 u32 end_int_en; 65 u32 st_con; 66 u32 status; 67 u32 end_int_st; 68 u32 ht_int_st; 69 u32 lt_int_st; 70 u32 mt_int_st; 71 u32 data0; 72 u32 data1; 73 u32 data2; 74 u32 data3; 75 u32 data4; 76 u32 data5; 77 u32 data6; 78 u32 data7; 79 u32 data8; 80 u32 data9; 81 u32 data10; 82 u32 data11; 83 u32 data12; 84 u32 data13; 85 u32 data14; 86 u32 data15; 87 u32 auto_ch_en; 88 }; 89 90 struct rockchip_saradc_data { 91 int num_bits; 92 int num_channels; 93 unsigned long clk_rate; 94 }; 95 96 struct rockchip_saradc_priv { 97 struct rockchip_saradc_regs *regs; 98 int active_channel; 99 const struct rockchip_saradc_data *data; 100 }; 101 102 static int rockchip_saradc_channel_data(struct udevice *dev, int channel, 103 unsigned int *data) 104 { 105 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 106 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); 107 int offset; 108 109 if (channel != priv->active_channel) { 110 pr_err("Requested channel is not active!"); 111 return -EINVAL; 112 } 113 114 /* Clear irq */ 115 writel(0x1, priv->regs->end_int_st); 116 117 offset = priv->active_channel * 0x4; 118 119 *data = readl(priv->regs->data0 + offset); 120 *data &= uc_pdata->data_mask; 121 122 return 0; 123 } 124 125 static int rockchip_saradc_start_channel(struct udevice *dev, int channel) 126 { 127 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 128 int val; 129 130 if (channel < 0 || channel >= priv->data->num_channels) { 131 pr_err("Requested channel is invalid!"); 132 return -EINVAL; 133 } 134 135 val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT; 136 writel(val, priv->regs->end_int_en); 137 val = SARADC2_START | SARADC2_SINGLE_MODE | channel; 138 writel(val << 16 | val, priv->regs->conv_con); 139 140 priv->active_channel = channel; 141 142 return 0; 143 } 144 145 static int rockchip_saradc_stop(struct udevice *dev) 146 { 147 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 148 149 priv->active_channel = -1; 150 151 return 0; 152 } 153 154 static int rockchip_saradc_probe(struct udevice *dev) 155 { 156 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 157 struct clk clk; 158 int ret; 159 160 ret = clk_get_by_index(dev, 0, &clk); 161 if (ret) 162 return ret; 163 164 ret = clk_set_rate(&clk, priv->data->clk_rate); 165 if (IS_ERR_VALUE(ret)) 166 return ret; 167 168 priv->active_channel = -1; 169 170 return 0; 171 } 172 173 static int rockchip_saradc_ofdata_to_platdata(struct udevice *dev) 174 { 175 struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); 176 struct rockchip_saradc_priv *priv = dev_get_priv(dev); 177 struct rockchip_saradc_data *data; 178 179 data = (struct rockchip_saradc_data *)dev_get_driver_data(dev); 180 priv->regs = (struct rockchip_saradc_regs *)dev_read_addr(dev); 181 if (priv->regs == (struct rockchip_saradc_regs *)FDT_ADDR_T_NONE) { 182 pr_err("Dev: %s - can't get address!", dev->name); 183 return -ENODATA; 184 } 185 186 priv->data = data; 187 uc_pdata->data_mask = (1 << priv->data->num_bits) - 1; 188 uc_pdata->data_format = ADC_DATA_FORMAT_BIN; 189 uc_pdata->data_timeout_us = SARADC_TIMEOUT / 5; 190 uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1; 191 192 return 0; 193 } 194 195 static const struct adc_ops rockchip_saradc_ops = { 196 .start_channel = rockchip_saradc_start_channel, 197 .channel_data = rockchip_saradc_channel_data, 198 .stop = rockchip_saradc_stop, 199 }; 200 201 static const struct rockchip_saradc_data rk3588_saradc_data = { 202 .num_bits = 12, 203 .num_channels = 8, 204 .clk_rate = 1000000, 205 }; 206 207 static const struct udevice_id rockchip_saradc_ids[] = { 208 { .compatible = "rockchip,saradc-3588", 209 .data = (ulong)&rk3588_saradc_data }, 210 { } 211 }; 212 213 U_BOOT_DRIVER(rockchip_saradc_v2) = { 214 .name = "rockchip_saradc_v2", 215 .id = UCLASS_ADC, 216 .of_match = rockchip_saradc_ids, 217 .ops = &rockchip_saradc_ops, 218 .probe = rockchip_saradc_probe, 219 .ofdata_to_platdata = rockchip_saradc_ofdata_to_platdata, 220 .priv_auto_alloc_size = sizeof(struct rockchip_saradc_priv), 221 }; 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