1*75219d57SThomas Chou* UART (Universal Asynchronous Receiver/Transmitter) 2*75219d57SThomas Chou 3*75219d57SThomas ChouRequired properties: 4*75219d57SThomas Chou- compatible : one of: 5*75219d57SThomas Chou - "ns8250" 6*75219d57SThomas Chou - "ns16450" 7*75219d57SThomas Chou - "ns16550a" 8*75219d57SThomas Chou - "ns16550" 9*75219d57SThomas Chou - "ns16750" 10*75219d57SThomas Chou - "ns16850" 11*75219d57SThomas Chou - For Tegra20, must contain "nvidia,tegra20-uart" 12*75219d57SThomas Chou - For other Tegra, must contain '"nvidia,<chip>-uart", 13*75219d57SThomas Chou "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124, 14*75219d57SThomas Chou tegra132, or tegra210. 15*75219d57SThomas Chou - "nxp,lpc3220-uart" 16*75219d57SThomas Chou - "ralink,rt2880-uart" 17*75219d57SThomas Chou - "ibm,qpace-nwp-serial" 18*75219d57SThomas Chou - "altr,16550-FIFO32" 19*75219d57SThomas Chou - "altr,16550-FIFO64" 20*75219d57SThomas Chou - "altr,16550-FIFO128" 21*75219d57SThomas Chou - "fsl,16550-FIFO64" 22*75219d57SThomas Chou - "fsl,ns16550" 23*75219d57SThomas Chou - "serial" if the port type is unknown. 24*75219d57SThomas Chou- reg : offset and length of the register set for the device. 25*75219d57SThomas Chou- interrupts : should contain uart interrupt. 26*75219d57SThomas Chou- clock-frequency : the input clock frequency for the UART 27*75219d57SThomas Chou or 28*75219d57SThomas Chou clocks phandle to refer to the clk used as per Documentation/devicetree 29*75219d57SThomas Chou /bindings/clock/clock-bindings.txt 30*75219d57SThomas Chou 31*75219d57SThomas ChouOptional properties: 32*75219d57SThomas Chou- current-speed : the current active speed of the UART. 33*75219d57SThomas Chou- reg-offset : offset to apply to the mapbase from the start of the registers. 34*75219d57SThomas Chou- reg-shift : quantity to shift the register offsets by. 35*75219d57SThomas Chou- reg-io-width : the size (in bytes) of the IO accesses that should be 36*75219d57SThomas Chou performed on the device. There are some systems that require 32-bit 37*75219d57SThomas Chou accesses to the UART (e.g. TI davinci). 38*75219d57SThomas Chou- used-by-rtas : set to indicate that the port is in use by the OpenFirmware 39*75219d57SThomas Chou RTAS and should not be registered. 40*75219d57SThomas Chou- no-loopback-test: set to indicate that the port does not implements loopback 41*75219d57SThomas Chou test mode 42*75219d57SThomas Chou- fifo-size: the fifo size of the UART. 43*75219d57SThomas Chou- auto-flow-control: one way to enable automatic flow control support. The 44*75219d57SThomas Chou driver is allowed to detect support for the capability even without this 45*75219d57SThomas Chou property. 46*75219d57SThomas Chou 47*75219d57SThomas ChouNote: 48*75219d57SThomas Chou* fsl,ns16550: 49*75219d57SThomas Chou ------------ 50*75219d57SThomas Chou Freescale DUART is very similar to the PC16552D (and to a 51*75219d57SThomas Chou pair of NS16550A), albeit with some nonstandard behavior such as 52*75219d57SThomas Chou erratum A-004737 (relating to incorrect BRK handling). 53*75219d57SThomas Chou 54*75219d57SThomas Chou Represents a single port that is compatible with the DUART found 55*75219d57SThomas Chou on many Freescale chips (examples include mpc8349, mpc8548, 56*75219d57SThomas Chou mpc8641d, p4080 and ls2085a). 57*75219d57SThomas Chou 58*75219d57SThomas ChouExample: 59*75219d57SThomas Chou 60*75219d57SThomas Chou uart@80230000 { 61*75219d57SThomas Chou compatible = "ns8250"; 62*75219d57SThomas Chou reg = <0x80230000 0x100>; 63*75219d57SThomas Chou clock-frequency = <3686400>; 64*75219d57SThomas Chou interrupts = <10>; 65*75219d57SThomas Chou reg-shift = <2>; 66*75219d57SThomas Chou }; 67