1*5910955fSBin MengIntel Interrupt Router Device Binding 2*5910955fSBin Meng===================================== 3*5910955fSBin Meng 4*5910955fSBin MengThe device tree node which describes the operation of the Intel Interrupt Router 5*5910955fSBin Mengdevice is as follows: 6*5910955fSBin Meng 7*5910955fSBin MengRequired properties : 8*5910955fSBin Meng- reg : Specifies the interrupt router's PCI configuration space address as 9*5910955fSBin Meng defined by the Open Firmware spec. 10*5910955fSBin Meng- compatible = "intel,irq-router" 11*5910955fSBin Meng- intel,pirq-config : Specifies the IRQ routing register programming mechanism. 12*5910955fSBin Meng Valid values are: 13*5910955fSBin Meng "pci": IRQ routing is controlled by PCI configuration registers 14*5910955fSBin Meng "ibase": IRQ routing is in the memory-mapped IBASE register block 15*5910955fSBin Meng- intel,ibase-offset : IBASE register offset in the interrupt router's PCI 16*5910955fSBin Meng configuration space, required only if intel,pirq-config = "ibase". 17*5910955fSBin Meng- intel,pirq-link : Specifies the PIRQ link information with two cells. The 18*5910955fSBin Meng first cell is the register offset that controls the first PIRQ link routing. 19*5910955fSBin Meng The second cell is the total number of PIRQ links the router supports. 20*5910955fSBin Meng- intel,pirq-mask : Specifies the IRQ mask reprenting the 16 IRQs in 8259 PIC. 21*5910955fSBin Meng Bit N is 1 means IRQ N is available to be routed. 22*5910955fSBin Meng- intel,pirq-routing : Specifies all PCI devices' IRQ routing information, 23*5910955fSBin Meng encoded as 3 cells a group for a device. The first cell is the device's PCI 24*5910955fSBin Meng bus number, device number and function number encoding with PCI_BDF() macro. 25*5910955fSBin Meng The second cell is the PCI interrupt pin used by this device. The last cell 26*5910955fSBin Meng is which PIRQ line the PCI interrupt pin is routed to. 27*5910955fSBin Meng 28*5910955fSBin Meng 29*5910955fSBin MengExample 30*5910955fSBin Meng------- 31*5910955fSBin Meng 32*5910955fSBin Meng#include <dt-bindings/interrupt-router/intel-irq.h> 33*5910955fSBin Meng 34*5910955fSBin Meng irq-router@1f,0 { 35*5910955fSBin Meng reg = <0x0000f800 0 0 0 0>; 36*5910955fSBin Meng compatible = "intel,irq-router"; 37*5910955fSBin Meng intel,pirq-config = "pci"; 38*5910955fSBin Meng intel,pirq-link = <0x60 8>; 39*5910955fSBin Meng intel,pirq-mask = <0xdef8>; 40*5910955fSBin Meng intel,pirq-routing = < 41*5910955fSBin Meng PCI_BDF(0, 2, 0) INTA PIRQA 42*5910955fSBin Meng PCI_BDF(0, 3, 0) INTA PIRQB 43*5910955fSBin Meng PCI_BDF(0, 8, 0) INTA PIRQC 44*5910955fSBin Meng PCI_BDF(0, 8, 1) INTB PIRQD 45*5910955fSBin Meng PCI_BDF(1, 6, 0) INTA PIRQE 46*5910955fSBin Meng PCI_BDF(1, 6, 1) INTB PIRQF 47*5910955fSBin Meng PCI_BDF(1, 6, 2) INTC PIRQG 48*5910955fSBin Meng PCI_BDF(1, 6, 3) INTD PIRQH 49*5910955fSBin Meng >; 50*5910955fSBin Meng }; 51