xref: /rk3399_rockchip-uboot/doc/device-tree-bindings/firmware/nvidia,tegra186-bpmp.txt (revision 7b9cb4940575f3b2d368d56ca06d3c0330af4c4b)

NVIDIA Tegra Boot and Power Management Processor (BPMP)

The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU. The binding document
defines the resources that would be used by the BPMP firmware driver,
which can create the interprocessor communication (IPC) between the CPU
and BPMP.

Required properties:
- name : Should be bpmp
- compatible
    Array of strings
    One of:
    - "nvidia,tegra186-bpmp"
- mboxes : The phandle of mailbox controller and the mailbox specifier.
- shmem : List of the phandle of the TX and RX shared memory area that
	  the IPC between CPU and BPMP is based on.
- #clock-cells : Should be 1.
- #power-domain-cells : Should be 1.
- #reset-cells : Should be 1.

This node is a mailbox consumer. See the following files for details of
the mailbox subsystem, and the specifiers implemented by the relevant
provider(s):

- .../mailbox/mailbox.txt
- .../mailbox/nvidia,tegra186-hsp.txt

This node is a clock, power domain, and reset provider. See the following
files for general documentation of those features, and the specifiers
implemented by this node:

- .../clock/clock-bindings.txt
- <dt-bindings/clock/tegra186-clock.h>
- ../power/power_domain.txt
- <dt-bindings/power/tegra186-powergate.h>
- .../reset/reset.txt
- <dt-bindings/reset/tegra186-reset.h>

The shared memory bindings for BPMP
-----------------------------------

The shared memory area for the IPC TX and RX between CPU and BPMP are
predefined and work on top of sysram, which is an SRAM inside the chip.

See ".../sram/sram.txt" for the bindings.

Example:

hsp_top0: hsp@03c00000 {
	...
	#mbox-cells = <2>;
};

sysram@30000000 {
	compatible = "nvidia,tegra186-sysram", "mmio-sram";
	reg = <0x0 0x30000000 0x0 0x50000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;

	cpu_bpmp_tx: bpmp_shmem@4e000 {
		compatible = "nvidia,tegra186-bpmp-shmem";
		reg = <0x0 0x4e000 0x0 0x1000>;
	};

	cpu_bpmp_rx: bpmp_shmem@4f000 {
		compatible = "nvidia,tegra186-bpmp-shmem";
		reg = <0x0 0x4f000 0x0 0x1000>;
	};
};

bpmp {
	compatible = "nvidia,tegra186-bpmp";
	mboxes = <&hsp_top0 HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>;
	shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
	#clock-cells = <1>;
	#power-domain-cells = <1>;
	#reset-cells = <1>;
};