1# 2# Copyright (C) 2015 Google. Inc 3# Written by Simon Glass <sjg@chromium.org> 4# 5# SPDX-License-Identifier: GPL-2.0+ 6# 7 8U-Boot on Rockchip 9================== 10 11There are several repositories available with versions of U-Boot that support 12many Rockchip devices [1] [2]. 13 14The current mainline support is experimental only and is not useful for 15anything. It should provide a base on which to build. 16 17So far only support for the RK3288 is provided. 18 19 20Prerequisites 21============= 22 23You will need: 24 25 - Firefly RK3288 baord 26 - Power connection to 5V using the supplied micro-USB power cable 27 - Separate USB serial cable attached to your computer and the Firefly 28 (connect to the micro-USB connector below the logo) 29 - rkflashtool [3] 30 - openssl (sudo apt-get install openssl) 31 - Serial UART connection [4] 32 - Suitable ARM cross compiler, e.g.: 33 sudo apt-get install gcc-4.7-arm-linux-gnueabi 34 35 36Building 37======== 38 39At present three RK3288 boards are supported: 40 41 - Firefly RK3288 - use firefly-rk3288 configuration 42 - Radxa Rock Pro - also uses firefly-rk3288 configuration 43 - Haier Chromebook - use chromebook_jerry configuration 44 45For example: 46 47 CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all 48 49(or you can use another cross compiler if you prefer) 50 51Note that the Radxa Rock Pro uses the Firefly configuration for now as 52device tree files are not yet available for the Rock Pro. Clearly the two 53have hardware differences, so this approach will break down as more drivers 54are added. 55 56 57Writing to the board with USB 58============================= 59 60For USB to work you must get your board into ROM boot mode, either by erasing 61your MMC or (perhaps) holding the recovery button when you boot the board. 62To erase your MMC, you can boot into Linux and type (as root) 63 64 dd if=/dev/zero of=/dev/mmcblk0 bs=1M 65 66Connect your board's OTG port to your computer. 67 68To create a suitable image and write it to the board: 69 70 ./firefly-rk3288/tools/mkimage -T rkimage -d ./firefly-rk3288/spl/u-boot-spl-dtb.bin out 71 cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | rkflashtool l 72 73If all goes well you should something like: 74 75 U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 10:06:49) 76 Card did not respond to voltage select! 77 spl: mmc init failed with error: -17 78 ### ERROR ### Please RESET the board ### 79 80You will need to reset the board before each time you try. Yes, that's all 81it does so far. If support for the Rockchip USB protocol or DFU were added 82in SPL then we could in principle load U-Boot and boot to a prompt from USB 83as several other platforms do. However it does not seem to be possible to 84use the existing boot ROM code from SPL. 85 86 87Booting from an SD card 88======================= 89 90To write an image that boots from an SD card (assumed to be /dev/sdc): 91 92 ./firefly-rk3288/tools/mkimage -T rksd -d firefly-rk3288/spl/u-boot-spl-dtb.bin out 93 sudo dd if=out of=/dev/sdc 94 sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256 95 96This puts the Rockchip header and SPL image first and then places the U-Boot 97image at block 256 (i.e. 128KB from the start of the SD card). This 98corresponds with this setting in U-Boot: 99 100 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 101 102Put this SD (or micro-SD) card into your board and reset it. You should see 103something like: 104 105 U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) 106 107 108 U-Boot 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) 109 110 DRAM: 2 GiB 111 MMC: 112 Using default environment 113 114 In: serial@ff690000 115 Out: serial@ff690000 116 Err: serial@ff690000 117 => 118 119 120Booting from SPI 121================ 122 123To write an image that boots from SPI flash (e.g. for the Haier Chromebook): 124 125 ./chromebook_jerry/tools/mkimage -T rkspi -d chromebook_jerry/spl/u-boot-spl-dtb.bin out 126 dd if=spl.bin of=out.bin bs=128K conv=sync 127 cat chromebook_jerry/u-boot-dtb.img out.bin 128 dd if=out.bin of=out.bin.pad bs=4M conv=sync 129 130This converts the SPL image to the required SPI format by adding the Rockchip 131header and skipping every 2KB block. Then the U-Boot image is written at 132offset 128KB and the whole image is padded to 4MB which is the SPI flash size. 133The position of U-Boot is controlled with this setting in U-Boot: 134 135 #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) 136 137If you have a Dediprog em100pro connected then you can write the image with: 138 139 sudo em100 -s -c GD25LQ32 -d out.bin.pad -r 140 141When booting you should see something like: 142 143 U-Boot SPL 2015.07-rc2-00215-g9a58220-dirty (Jun 23 2015 - 12:11:32) 144 145 146 U-Boot 2015.07-rc2-00215-g9a58220-dirty (Jun 23 2015 - 12:11:32 -0600) 147 148 Model: Google Jerry 149 DRAM: 2 GiB 150 MMC: 151 Using default environment 152 153 In: serial@ff690000 154 Out: serial@ff690000 155 Err: serial@ff690000 156 => 157 158 159Future work 160=========== 161 162Immediate priorities are: 163 164- MMC support (in U-Boot itself) 165- GPIO (driver exists but is lightly tested) 166- I2C (driver exists but is non-functional) 167- USB host 168- USB device 169- PMIC and regulators (only ACT8846 is supported at present) 170- LCD and HDMI 171- Run CPU at full speed 172- Ethernet 173- NAND flash 174- Support for other Rockchip parts 175- Boot U-Boot proper over USB OTG (at present only SPL works) 176 177 178Development Notes 179================= 180 181There are plenty of patches in the links below to help with this work. 182 183[1] https://github.com/rkchrome/uboot.git 184[2] https://github.com/linux-rockchip/u-boot-rockchip.git branch u-boot-rk3288 185[3] https://github.com/linux-rockchip/rkflashtool.git 186[4] http://wiki.t-firefly.com/index.php/Firefly-RK3288/Serial_debug/en 187 188rkimage 189------- 190 191rkimage.c produces an SPL image suitable for sending directly to the boot ROM 192over USB OTG. This is a very simple format - just the string RK32 (as 4 bytes) 193followed by u-boot-spl-dtb.bin. 194 195The boot ROM loads image to 0xff704000 which is in the internal SRAM. The SRAM 196starts at 0xff700000 and extends to 0xff718000 where we put the stack. 197 198rksd 199---- 200 201rksd.c produces an image consisting of 32KB of empty space, a header and 202u-boot-spl-dtb.bin. The header is defined by 'struct header0_info' although 203most of the fields are unused by U-Boot. We just need to specify the 204signature, a flag and the block offset and size of the SPL image. 205 206The header occupies a single block but we pad it out to 4 blocks. The header 207is encoding using RC4 with the key 7c4e0304550509072d2c7b38170d1711. The SPL 208image can be encoded too but we don't do that. 209 210The maximum size of u-boot-spl-dtb.bin which the boot ROM will read is 32KB, 211or 0x40 blocks. This is a severe and annoying limitation. There may be a way 212around this limitation, since there is plenty of SRAM, but at present the 213board refuses to boot if this limit is exceeded. 214 215The image produced is padded up to a block boundary (512 bytes). It should be 216written to the start of an SD card using dd. 217 218Since this image is set to load U-Boot from the SD card at block offset, 219CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR, dd should be used to write 220u-boot-dtb.img to the SD card at that offset. See above for instructions. 221 222rkspi 223----- 224 225rkspi.c produces an image consisting of a header and u-boot-spl-dtb.bin. The 226resulting image is then spread out so that only the first 2KB of each 4KB 227sector is used. The header is the same as with rksd and the maximum size is 228also 32KB (before spreading). The image should be written to the start of 229SPI flash. 230 231See above for instructions on how to write a SPI image. 232 233 234Device tree and driver model 235---------------------------- 236 237Where possible driver model is used to provide a structure to the 238functionality. Device tree is used for configuration. However these have an 239overhead and in SPL with a 32KB size limit some shortcuts have been taken. 240In general all Rockchip drivers should use these features, with SPL-specific 241modifications where required. 242 243 244-- 245Simon Glass <sjg@chromium.org> 24624 June 2015 247