1NAND FLASH commands and notes 2 3See NOTE below!!! 4 5# (C) Copyright 2003 6# Dave Ellis, SIXNET, dge@sixnetio.com 7# 8# See file CREDITS for list of people who contributed to this 9# project. 10# 11# This program is free software; you can redistribute it and/or 12# modify it under the terms of the GNU General Public License as 13# published by the Free Software Foundation; either version 2 of 14# the License, or (at your option) any later version. 15# 16# This program is distributed in the hope that it will be useful, 17# but WITHOUT ANY WARRANTY; without even the implied warranty of 18# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19# GNU General Public License for more details. 20# 21# You should have received a copy of the GNU General Public License 22# along with this program; if not, write to the Free Software 23# Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24# MA 02111-1307 USA 25 26Commands: 27 28 nand bad 29 Print a list of all of the bad blocks in the current device. 30 31 nand device 32 Print information about the current NAND device. 33 34 nand device num 35 Make device `num' the current device and print information about it. 36 37 nand erase off size 38 nand erase clean [off size] 39 Erase `size' bytes starting at offset `off'. Only complete erase 40 blocks can be erased. 41 42 If `clean' is specified, a JFFS2-style clean marker is written to 43 each block after it is erased. If `clean' is specified without an 44 offset or size, the entire flash is erased. 45 46 This command will not erase blocks that are marked bad. There is 47 a debug option in cmd_nand.c to allow bad blocks to be erased. 48 Please read the warning there before using it, as blocks marked 49 bad by the manufacturer must _NEVER_ be erased. 50 51 nand info 52 Print information about all of the NAND devices found. 53 54 nand read addr ofs size 55 Read `size' bytes from `ofs' in NAND flash to `addr'. If a page 56 cannot be read because it is marked bad or an uncorrectable data 57 error is found the command stops with an error. 58 59 nand read.jffs2 addr ofs size 60 Like `read', but the data for blocks that are marked bad is read as 61 0xff. This gives a readable JFFS2 image that can be processed by 62 the JFFS2 commands such as ls and fsload. 63 64 nand read.oob addr ofs size 65 Read `size' bytes from the out-of-band data area corresponding to 66 `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of 67 data for one 512-byte page or 2 256-byte pages. There is no check 68 for bad blocks or ECC errors. 69 70 nand write addr ofs size 71 Write `size' bytes from `addr' to `ofs' in NAND flash. If a page 72 cannot be written because it is marked bad or the write fails the 73 command stops with an error. 74 75 nand write.jffs2 addr ofs size 76 Like `write', but blocks that are marked bad are skipped and the 77 is written to the next block instead. This allows writing writing 78 a JFFS2 image, as long as the image is short enough to fit even 79 after skipping the bad blocks. Compact images, such as those 80 produced by mkfs.jffs2 should work well, but loading an image copied 81 from another flash is going to be trouble if there are any bad blocks. 82 83 nand write.oob addr ofs size 84 Write `size' bytes from `addr' to the out-of-band data area 85 corresponding to `ofs' in NAND flash. This is limited to the 16 bytes 86 of data for one 512-byte page or 2 256-byte pages. There is no check 87 for bad blocks. 88 89Configuration Options: 90 91 CFG_CMD_NAND 92 A good one to add to CONFIG_COMMANDS since it enables NAND support. 93 94 CONFIG_MTD_NAND_ECC_JFFS2 95 Define this if you want the Error Correction Code information in 96 the out-of-band data to be formatted to match the JFFS2 file system. 97 CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for 98 someone to implement. 99 100 CFG_MAX_NAND_DEVICE 101 The maximum number of NAND devices you want to support. 102 103NAND Interface: 104 105 #define NAND_WAIT_READY(nand) 106 Wait until the NAND flash is ready. Typically this would be a 107 loop waiting for the READY/BUSY line from the flash to indicate it 108 it is ready. 109 110 #define WRITE_NAND_COMMAND(d, adr) 111 Write the command byte `d' to the flash at `adr' with the 112 CLE (command latch enable) line true. If your board uses writes to 113 different addresses to control CLE and ALE, you can modify `adr' 114 to be the appropriate address here. If your board uses I/O registers 115 to control them, it is probably better to let NAND_CTL_SETCLE() 116 and company do it. 117 118 #define WRITE_NAND_ADDRESS(d, adr) 119 Write the address byte `d' to the flash at `adr' with the 120 ALE (address latch enable) line true. If your board uses writes to 121 different addresses to control CLE and ALE, you can modify `adr' 122 to be the appropriate address here. If your board uses I/O registers 123 to control them, it is probably better to let NAND_CTL_SETALE() 124 and company do it. 125 126 #define WRITE_NAND(d, adr) 127 Write the data byte `d' to the flash at `adr' with the 128 ALE and CLE lines false. If your board uses writes to 129 different addresses to control CLE and ALE, you can modify `adr' 130 to be the appropriate address here. If your board uses I/O registers 131 to control them, it is probably better to let NAND_CTL_CLRALE() 132 and company do it. 133 134 #define READ_NAND(adr) 135 Read a data byte from the flash at `adr' with the 136 ALE and CLE lines false. If your board uses reads from 137 different addresses to control CLE and ALE, you can modify `adr' 138 to be the appropriate address here. If your board uses I/O registers 139 to control them, it is probably better to let NAND_CTL_CLRALE() 140 and company do it. 141 142 #define NAND_DISABLE_CE(nand) 143 Set CE (Chip Enable) low to enable the NAND flash. 144 145 #define NAND_ENABLE_CE(nand) 146 Set CE (Chip Enable) high to disable the NAND flash. 147 148 #define NAND_CTL_CLRALE(nandptr) 149 Set ALE (address latch enable) low. If ALE control is handled by 150 WRITE_NAND_ADDRESS() this can be empty. 151 152 #define NAND_CTL_SETALE(nandptr) 153 Set ALE (address latch enable) high. If ALE control is handled by 154 WRITE_NAND_ADDRESS() this can be empty. 155 156 #define NAND_CTL_CLRCLE(nandptr) 157 Set CLE (command latch enable) low. If CLE control is handled by 158 WRITE_NAND_ADDRESS() this can be empty. 159 160 #define NAND_CTL_SETCLE(nandptr) 161 Set CLE (command latch enable) high. If CLE control is handled by 162 WRITE_NAND_ADDRESS() this can be empty. 163 164More Definitions: 165 166 These definitions are needed in the board configuration for now, but 167 may really belong in a header file. 168 TODO: Figure which ones are truly configuration settings and rename 169 them to CFG_NAND_... and move the rest somewhere appropriate. 170 171 #define SECTORSIZE 512 172 #define ADDR_COLUMN 1 173 #define ADDR_PAGE 2 174 #define ADDR_COLUMN_PAGE 3 175 #define NAND_ChipID_UNKNOWN 0x00 176 #define NAND_MAX_FLOORS 1 177 #define NAND_MAX_CHIPS 1 178 179 180NOTE: 181===== 182 183We now use a complete rewrite of the NAND code based on what is in 1842.6.12 Linux kernel. 185 186The old NAND handling code has been re-factored and is now confined 187to only board-specific files and - unfortunately - to the DoC code 188(see below). A new configuration variable has been introduced: 189CFG_NAND_LEGACY, which has to be defined in the board config file if 190that board uses legacy code. If CFG_NAND_LEGACY is defined, the board 191specific config.mk file should also have "BOARDLIBS = 192drivers/nand_legacy/libnand_legacy.a". For boards using the new NAND 193approach (PPChameleon and netstar at the moment) no variable is 194necessary, but the config.mk should have "BOARDLIBS = 195drivers/nand/libnand.a". 196 197The necessary changes have been made to all affected boards, and no 198build breakage has been introduced, except for NETTA and NETTA_ISDN 199targets from MAKEALL. This is due to the fact that these two boards 200use JFFS, which has been adopted to use the new NAND, and at the same 201time use NAND in legacy mode. The breakage will disappear when the 202board-specific code is changed to the new NAND. 203 204As mentioned above, the legacy code is still used by the DoC subsystem. 205The consequence of this is that the legacy NAND can't be removed from 206the tree until the DoC is ported to use the new NAND support (or boards 207with DoC will break). 208 209 210Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006 211 212JFFS2 related commands: 213 214 implement "nand erase clean" and old "nand erase" 215 using both the new code which is able to skip bad blocks 216 "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob. 217 218 "nand write.jffs2" 219 like "nand write" but skip found bad eraseblocks 220 221 "nand read.jffs2" 222 like "nand read" but skip found bad eraseblocks 223 224Miscellaneous and testing commands: 225 "markbad [offset]" 226 create an artificial bad block (for testing bad block handling) 227 228 "scrub [offset length]" 229 like "erase" but don't skip bad block. Instead erase them. 230 DANGEROUS!!! Factory set bad blocks will be lost. Use only 231 to remove artificial bad blocks created with the "markbad" command. 232 233 234NAND locking command (for chips with active LOCKPRE pin) 235 236 "nand lock" 237 set NAND chip to lock state (all pages locked) 238 239 "nand lock tight" 240 set NAND chip to lock tight state (software can't change locking anymore) 241 242 "nand lock status" 243 displays current locking status of all pages 244 245 "nand unlock [offset] [size]" 246 unlock consecutive area (can be called multiple times for different areas) 247 248 249I have tested the code with board containing 128MiB NAND large page chips 250and 32MiB small page chips. 251