1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <malloc.h> 22 #include <linux/compat.h> 23 #include <linux/ctype.h> 24 #include <linux/fb.h> 25 #include <linux/hdmi.h> 26 #include <linux/string.h> 27 28 #define EDID_EST_TIMINGS 16 29 #define EDID_STD_TIMINGS 8 30 #define EDID_DETAILED_TIMINGS 4 31 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 32 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 33 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 34 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 35 #define version_greater(edid, maj, min) \ 36 (((edid)->version > (maj)) || \ 37 ((edid)->version == (maj) && (edid)->revision > (min))) 38 39 /* 40 * EDID blocks out in the wild have a variety of bugs, try to collect 41 * them here (note that userspace may work around broken monitors first, 42 * but fixes should make their way here so that the kernel "just works" 43 * on as many displays as possible). 44 */ 45 46 /* First detailed mode wrong, use largest 60Hz mode */ 47 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 48 /* Reported 135MHz pixel clock is too high, needs adjustment */ 49 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 50 /* Prefer the largest mode at 75 Hz */ 51 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 52 /* Detail timing is in cm not mm */ 53 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 54 /* Detailed timing descriptors have bogus size values, so just take the 55 * maximum size and use that. 56 */ 57 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 58 /* Monitor forgot to set the first detailed is preferred bit. */ 59 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 60 /* use +hsync +vsync for detailed mode */ 61 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 62 /* Force reduced-blanking timings for detailed modes */ 63 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 64 /* Force 8bpc */ 65 #define EDID_QUIRK_FORCE_8BPC BIT(8) 66 /* Force 12bpc */ 67 #define EDID_QUIRK_FORCE_12BPC BIT(9) 68 /* Force 6bpc */ 69 #define EDID_QUIRK_FORCE_6BPC BIT(10) 70 /* Force 10bpc */ 71 #define EDID_QUIRK_FORCE_10BPC BIT(11) 72 73 struct detailed_mode_closure { 74 struct edid *edid; 75 struct hdmi_edid_data *data; 76 u32 quirks; 77 int modes; 78 }; 79 80 #define LEVEL_DMT 0 81 #define LEVEL_GTF 1 82 #define LEVEL_GTF2 2 83 #define LEVEL_CVT 3 84 85 static struct edid_quirk { 86 char vendor[4]; 87 int product_id; 88 u32 quirks; 89 } edid_quirk_list[] = { 90 /* Acer AL1706 */ 91 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 92 /* Acer F51 */ 93 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Unknown Acer */ 95 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 96 97 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 98 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 99 100 /* Belinea 10 15 55 */ 101 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 102 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 103 104 /* Envision Peripherals, Inc. EN-7100e */ 105 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 106 /* Envision EN2028 */ 107 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 108 109 /* Funai Electronics PM36B */ 110 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 111 EDID_QUIRK_DETAILED_IN_CM }, 112 113 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 114 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 115 116 /* LG Philips LCD LP154W01-A5 */ 117 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 118 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 119 120 /* Philips 107p5 CRT */ 121 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 122 123 /* Proview AY765C */ 124 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 125 126 /* Samsung SyncMaster 205BW. Note: irony */ 127 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 128 /* Samsung SyncMaster 22[5-6]BW */ 129 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 130 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 131 132 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 133 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 134 135 /* ViewSonic VA2026w */ 136 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 137 138 /* Medion MD 30217 PG */ 139 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 140 141 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 142 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 143 144 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 145 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 146 }; 147 148 /* 149 * Probably taken from CEA-861 spec. 150 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 151 * 152 * Index using the VIC. 153 */ 154 static const struct drm_display_mode edid_cea_modes[] = { 155 /* 0 - dummy, VICs start at 1 */ 156 { }, 157 /* 1 - 640x480@60Hz */ 158 { DRM_MODE(25175, 640, 656, 159 752, 800, 480, 490, 492, 525, 0, 160 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 161 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 162 /* 2 - 720x480@60Hz */ 163 { DRM_MODE(27000, 720, 736, 164 798, 858, 480, 489, 495, 525, 0, 165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 166 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 167 /* 3 - 720x480@60Hz */ 168 { DRM_MODE(27000, 720, 736, 169 798, 858, 480, 489, 495, 525, 0, 170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 171 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 172 /* 4 - 1280x720@60Hz */ 173 { DRM_MODE(74250, 1280, 1390, 174 1430, 1650, 720, 725, 730, 750, 0, 175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 176 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 177 /* 5 - 1920x1080i@60Hz */ 178 { DRM_MODE(74250, 1920, 2008, 179 2052, 2200, 1080, 1084, 1094, 1125, 0, 180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 181 DRM_MODE_FLAG_INTERLACE), 182 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 183 /* 6 - 720(1440)x480i@60Hz */ 184 { DRM_MODE(13500, 720, 739, 185 801, 858, 480, 488, 494, 525, 0, 186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 187 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 188 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 189 /* 7 - 720(1440)x480i@60Hz */ 190 { DRM_MODE(13500, 720, 739, 191 801, 858, 480, 488, 494, 525, 0, 192 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 193 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 194 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 195 /* 8 - 720(1440)x240@60Hz */ 196 { DRM_MODE(13500, 720, 739, 197 801, 858, 240, 244, 247, 262, 0, 198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 199 DRM_MODE_FLAG_DBLCLK), 200 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 201 /* 9 - 720(1440)x240@60Hz */ 202 { DRM_MODE(13500, 720, 739, 203 801, 858, 240, 244, 247, 262, 0, 204 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 205 DRM_MODE_FLAG_DBLCLK), 206 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 207 /* 10 - 2880x480i@60Hz */ 208 { DRM_MODE(54000, 2880, 2956, 209 3204, 3432, 480, 488, 494, 525, 0, 210 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 211 DRM_MODE_FLAG_INTERLACE), 212 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 213 /* 11 - 2880x480i@60Hz */ 214 { DRM_MODE(54000, 2880, 2956, 215 3204, 3432, 480, 488, 494, 525, 0, 216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 217 DRM_MODE_FLAG_INTERLACE), 218 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 219 /* 12 - 2880x240@60Hz */ 220 { DRM_MODE(54000, 2880, 2956, 221 3204, 3432, 240, 244, 247, 262, 0, 222 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 223 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 224 /* 13 - 2880x240@60Hz */ 225 { DRM_MODE(54000, 2880, 2956, 226 3204, 3432, 240, 244, 247, 262, 0, 227 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 228 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 229 /* 14 - 1440x480@60Hz */ 230 { DRM_MODE(54000, 1440, 1472, 231 1596, 1716, 480, 489, 495, 525, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 233 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 234 /* 15 - 1440x480@60Hz */ 235 { DRM_MODE(54000, 1440, 1472, 236 1596, 1716, 480, 489, 495, 525, 0, 237 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 238 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 239 /* 16 - 1920x1080@60Hz */ 240 { DRM_MODE(148500, 1920, 2008, 241 2052, 2200, 1080, 1084, 1089, 1125, 0, 242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 243 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 244 /* 17 - 720x576@50Hz */ 245 { DRM_MODE(27000, 720, 732, 246 796, 864, 576, 581, 586, 625, 0, 247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 248 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 249 /* 18 - 720x576@50Hz */ 250 { DRM_MODE(27000, 720, 732, 251 796, 864, 576, 581, 586, 625, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 253 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 254 /* 19 - 1280x720@50Hz */ 255 { DRM_MODE(74250, 1280, 1720, 256 1760, 1980, 720, 725, 730, 750, 0, 257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 258 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 259 /* 20 - 1920x1080i@50Hz */ 260 { DRM_MODE(74250, 1920, 2448, 261 2492, 2640, 1080, 1084, 1094, 1125, 0, 262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 263 DRM_MODE_FLAG_INTERLACE), 264 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 265 /* 21 - 720(1440)x576i@50Hz */ 266 { DRM_MODE(13500, 720, 732, 267 795, 864, 576, 580, 586, 625, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 269 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 270 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 271 /* 22 - 720(1440)x576i@50Hz */ 272 { DRM_MODE(13500, 720, 732, 273 795, 864, 576, 580, 586, 625, 0, 274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 275 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 276 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 277 /* 23 - 720(1440)x288@50Hz */ 278 { DRM_MODE(13500, 720, 732, 279 795, 864, 288, 290, 293, 312, 0, 280 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 281 DRM_MODE_FLAG_DBLCLK), 282 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 283 /* 24 - 720(1440)x288@50Hz */ 284 { DRM_MODE(13500, 720, 732, 285 795, 864, 288, 290, 293, 312, 0, 286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 287 DRM_MODE_FLAG_DBLCLK), 288 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 289 /* 25 - 2880x576i@50Hz */ 290 { DRM_MODE(54000, 2880, 2928, 291 3180, 3456, 576, 580, 586, 625, 0, 292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 293 DRM_MODE_FLAG_INTERLACE), 294 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 295 /* 26 - 2880x576i@50Hz */ 296 { DRM_MODE(54000, 2880, 2928, 297 3180, 3456, 576, 580, 586, 625, 0, 298 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 299 DRM_MODE_FLAG_INTERLACE), 300 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 301 /* 27 - 2880x288@50Hz */ 302 { DRM_MODE(54000, 2880, 2928, 303 3180, 3456, 288, 290, 293, 312, 0, 304 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 305 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 306 /* 28 - 2880x288@50Hz */ 307 { DRM_MODE(54000, 2880, 2928, 308 3180, 3456, 288, 290, 293, 312, 0, 309 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 310 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 311 /* 29 - 1440x576@50Hz */ 312 { DRM_MODE(54000, 1440, 1464, 313 1592, 1728, 576, 581, 586, 625, 0, 314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 315 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 316 /* 30 - 1440x576@50Hz */ 317 { DRM_MODE(54000, 1440, 1464, 318 1592, 1728, 576, 581, 586, 625, 0, 319 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 320 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 321 /* 31 - 1920x1080@50Hz */ 322 { DRM_MODE(148500, 1920, 2448, 323 2492, 2640, 1080, 1084, 1089, 1125, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 325 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 326 /* 32 - 1920x1080@24Hz */ 327 { DRM_MODE(74250, 1920, 2558, 328 2602, 2750, 1080, 1084, 1089, 1125, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 330 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 331 /* 33 - 1920x1080@25Hz */ 332 { DRM_MODE(74250, 1920, 2448, 333 2492, 2640, 1080, 1084, 1089, 1125, 0, 334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 335 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 336 /* 34 - 1920x1080@30Hz */ 337 { DRM_MODE(74250, 1920, 2008, 338 2052, 2200, 1080, 1084, 1089, 1125, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 340 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 341 /* 35 - 2880x480@60Hz */ 342 { DRM_MODE(108000, 2880, 2944, 343 3192, 3432, 480, 489, 495, 525, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 345 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 346 /* 36 - 2880x480@60Hz */ 347 { DRM_MODE(108000, 2880, 2944, 348 3192, 3432, 480, 489, 495, 525, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 350 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 351 /* 37 - 2880x576@50Hz */ 352 { DRM_MODE(108000, 2880, 2928, 353 3184, 3456, 576, 581, 586, 625, 0, 354 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 355 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 356 /* 38 - 2880x576@50Hz */ 357 { DRM_MODE(108000, 2880, 2928, 358 3184, 3456, 576, 581, 586, 625, 0, 359 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 360 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 361 /* 39 - 1920x1080i@50Hz */ 362 { DRM_MODE(72000, 1920, 1952, 363 2120, 2304, 1080, 1126, 1136, 1250, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 365 DRM_MODE_FLAG_INTERLACE), 366 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 367 /* 40 - 1920x1080i@100Hz */ 368 { DRM_MODE(148500, 1920, 2448, 369 2492, 2640, 1080, 1084, 1094, 1125, 0, 370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 371 DRM_MODE_FLAG_INTERLACE), 372 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 373 /* 41 - 1280x720@100Hz */ 374 { DRM_MODE(148500, 1280, 1720, 375 1760, 1980, 720, 725, 730, 750, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 377 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 378 /* 42 - 720x576@100Hz */ 379 { DRM_MODE(54000, 720, 732, 380 796, 864, 576, 581, 586, 625, 0, 381 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 382 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 383 /* 43 - 720x576@100Hz */ 384 { DRM_MODE(54000, 720, 732, 385 796, 864, 576, 581, 586, 625, 0, 386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 387 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 388 /* 44 - 720(1440)x576i@100Hz */ 389 { DRM_MODE(27000, 720, 732, 390 795, 864, 576, 580, 586, 625, 0, 391 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 392 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 393 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 394 /* 45 - 720(1440)x576i@100Hz */ 395 { DRM_MODE(27000, 720, 732, 396 795, 864, 576, 580, 586, 625, 0, 397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 398 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 399 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 400 /* 46 - 1920x1080i@120Hz */ 401 { DRM_MODE(148500, 1920, 2008, 402 2052, 2200, 1080, 1084, 1094, 1125, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 404 DRM_MODE_FLAG_INTERLACE), 405 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 406 /* 47 - 1280x720@120Hz */ 407 { DRM_MODE(148500, 1280, 1390, 408 1430, 1650, 720, 725, 730, 750, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 410 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 411 /* 48 - 720x480@120Hz */ 412 { DRM_MODE(54000, 720, 736, 413 798, 858, 480, 489, 495, 525, 0, 414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 415 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 416 /* 49 - 720x480@120Hz */ 417 { DRM_MODE(54000, 720, 736, 418 798, 858, 480, 489, 495, 525, 0, 419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 420 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 421 /* 50 - 720(1440)x480i@120Hz */ 422 { DRM_MODE(27000, 720, 739, 423 801, 858, 480, 488, 494, 525, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 425 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 426 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 427 /* 51 - 720(1440)x480i@120Hz */ 428 { DRM_MODE(27000, 720, 739, 429 801, 858, 480, 488, 494, 525, 0, 430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 431 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 432 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 433 /* 52 - 720x576@200Hz */ 434 { DRM_MODE(108000, 720, 732, 435 796, 864, 576, 581, 586, 625, 0, 436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 437 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 438 /* 53 - 720x576@200Hz */ 439 { DRM_MODE(108000, 720, 732, 440 796, 864, 576, 581, 586, 625, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 442 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 443 /* 54 - 720(1440)x576i@200Hz */ 444 { DRM_MODE(54000, 720, 732, 445 795, 864, 576, 580, 586, 625, 0, 446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 447 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 448 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 449 /* 55 - 720(1440)x576i@200Hz */ 450 { DRM_MODE(54000, 720, 732, 451 795, 864, 576, 580, 586, 625, 0, 452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 453 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 454 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 455 /* 56 - 720x480@240Hz */ 456 { DRM_MODE(108000, 720, 736, 457 798, 858, 480, 489, 495, 525, 0, 458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 459 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 460 /* 57 - 720x480@240Hz */ 461 { DRM_MODE(108000, 720, 736, 462 798, 858, 480, 489, 495, 525, 0, 463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 464 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 465 /* 58 - 720(1440)x480i@240 */ 466 { DRM_MODE(54000, 720, 739, 467 801, 858, 480, 488, 494, 525, 0, 468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 469 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 470 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 471 /* 59 - 720(1440)x480i@240 */ 472 { DRM_MODE(54000, 720, 739, 473 801, 858, 480, 488, 494, 525, 0, 474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 475 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 476 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 477 /* 60 - 1280x720@24Hz */ 478 { DRM_MODE(59400, 1280, 3040, 479 3080, 3300, 720, 725, 730, 750, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 481 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 482 /* 61 - 1280x720@25Hz */ 483 { DRM_MODE(74250, 1280, 3700, 484 3740, 3960, 720, 725, 730, 750, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 486 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 487 /* 62 - 1280x720@30Hz */ 488 { DRM_MODE(74250, 1280, 3040, 489 3080, 3300, 720, 725, 730, 750, 0, 490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 491 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 492 /* 63 - 1920x1080@120Hz */ 493 { DRM_MODE(297000, 1920, 2008, 494 2052, 2200, 1080, 1084, 1089, 1125, 0, 495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 496 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 497 /* 64 - 1920x1080@100Hz */ 498 { DRM_MODE(297000, 1920, 2448, 499 2492, 2640, 1080, 1084, 1089, 1125, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 501 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 502 /* 65 - 1280x720@24Hz */ 503 { DRM_MODE(59400, 1280, 3040, 504 3080, 3300, 720, 725, 730, 750, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 506 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 507 /* 66 - 1280x720@25Hz */ 508 { DRM_MODE(74250, 1280, 3700, 509 3740, 3960, 720, 725, 730, 750, 0, 510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 511 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 512 /* 67 - 1280x720@30Hz */ 513 { DRM_MODE(74250, 1280, 3040, 514 3080, 3300, 720, 725, 730, 750, 0, 515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 516 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 517 /* 68 - 1280x720@50Hz */ 518 { DRM_MODE(74250, 1280, 1720, 519 1760, 1980, 720, 725, 730, 750, 0, 520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 521 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 522 /* 69 - 1280x720@60Hz */ 523 { DRM_MODE(74250, 1280, 1390, 524 1430, 1650, 720, 725, 730, 750, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 526 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 527 /* 70 - 1280x720@100Hz */ 528 { DRM_MODE(148500, 1280, 1720, 529 1760, 1980, 720, 725, 730, 750, 0, 530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 531 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 532 /* 71 - 1280x720@120Hz */ 533 { DRM_MODE(148500, 1280, 1390, 534 1430, 1650, 720, 725, 730, 750, 0, 535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 536 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 537 /* 72 - 1920x1080@24Hz */ 538 { DRM_MODE(74250, 1920, 2558, 539 2602, 2750, 1080, 1084, 1089, 1125, 0, 540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 541 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 542 /* 73 - 1920x1080@25Hz */ 543 { DRM_MODE(74250, 1920, 2448, 544 2492, 2640, 1080, 1084, 1089, 1125, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 546 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 547 /* 74 - 1920x1080@30Hz */ 548 { DRM_MODE(74250, 1920, 2008, 549 2052, 2200, 1080, 1084, 1089, 1125, 0, 550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 551 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 552 /* 75 - 1920x1080@50Hz */ 553 { DRM_MODE(148500, 1920, 2448, 554 2492, 2640, 1080, 1084, 1089, 1125, 0, 555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 556 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 557 /* 76 - 1920x1080@60Hz */ 558 { DRM_MODE(148500, 1920, 2008, 559 2052, 2200, 1080, 1084, 1089, 1125, 0, 560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 561 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 562 /* 77 - 1920x1080@100Hz */ 563 { DRM_MODE(297000, 1920, 2448, 564 2492, 2640, 1080, 1084, 1089, 1125, 0, 565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 566 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 567 /* 78 - 1920x1080@120Hz */ 568 { DRM_MODE(297000, 1920, 2008, 569 2052, 2200, 1080, 1084, 1089, 1125, 0, 570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 571 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 572 /* 79 - 1680x720@24Hz */ 573 { DRM_MODE(59400, 1680, 3040, 574 3080, 3300, 720, 725, 730, 750, 0, 575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 576 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 577 /* 80 - 1680x720@25Hz */ 578 { DRM_MODE(59400, 1680, 2908, 579 2948, 3168, 720, 725, 730, 750, 0, 580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 581 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 582 /* 81 - 1680x720@30Hz */ 583 { DRM_MODE(59400, 1680, 2380, 584 2420, 2640, 720, 725, 730, 750, 0, 585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 586 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 587 /* 82 - 1680x720@50Hz */ 588 { DRM_MODE(82500, 1680, 1940, 589 1980, 2200, 720, 725, 730, 750, 0, 590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 591 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 592 /* 83 - 1680x720@60Hz */ 593 { DRM_MODE(99000, 1680, 1940, 594 1980, 2200, 720, 725, 730, 750, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 596 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 597 /* 84 - 1680x720@100Hz */ 598 { DRM_MODE(165000, 1680, 1740, 599 1780, 2000, 720, 725, 730, 825, 0, 600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 601 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 602 /* 85 - 1680x720@120Hz */ 603 { DRM_MODE(198000, 1680, 1740, 604 1780, 2000, 720, 725, 730, 825, 0, 605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 606 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 607 /* 86 - 2560x1080@24Hz */ 608 { DRM_MODE(99000, 2560, 3558, 609 3602, 3750, 1080, 1084, 1089, 1100, 0, 610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 611 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 612 /* 87 - 2560x1080@25Hz */ 613 { DRM_MODE(90000, 2560, 3008, 614 3052, 3200, 1080, 1084, 1089, 1125, 0, 615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 616 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 617 /* 88 - 2560x1080@30Hz */ 618 { DRM_MODE(118800, 2560, 3328, 619 3372, 3520, 1080, 1084, 1089, 1125, 0, 620 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 621 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 622 /* 89 - 2560x1080@50Hz */ 623 { DRM_MODE(185625, 2560, 3108, 624 3152, 3300, 1080, 1084, 1089, 1125, 0, 625 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 626 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 627 /* 90 - 2560x1080@60Hz */ 628 { DRM_MODE(198000, 2560, 2808, 629 2852, 3000, 1080, 1084, 1089, 1100, 0, 630 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 631 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 632 /* 91 - 2560x1080@100Hz */ 633 { DRM_MODE(371250, 2560, 2778, 634 2822, 2970, 1080, 1084, 1089, 1250, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 636 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 637 /* 92 - 2560x1080@120Hz */ 638 { DRM_MODE(495000, 2560, 3108, 639 3152, 3300, 1080, 1084, 1089, 1250, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 641 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 642 /* 93 - 3840x2160p@24Hz 16:9 */ 643 { DRM_MODE(297000, 3840, 5116, 644 5204, 5500, 2160, 2168, 2178, 2250, 0, 645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 646 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 647 /* 94 - 3840x2160p@25Hz 16:9 */ 648 { DRM_MODE(297000, 3840, 4896, 649 4984, 5280, 2160, 2168, 2178, 2250, 0, 650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 651 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 652 /* 95 - 3840x2160p@30Hz 16:9 */ 653 { DRM_MODE(297000, 3840, 4016, 654 4104, 4400, 2160, 2168, 2178, 2250, 0, 655 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 656 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 657 /* 96 - 3840x2160p@50Hz 16:9 */ 658 { DRM_MODE(594000, 3840, 4896, 659 4984, 5280, 2160, 2168, 2178, 2250, 0, 660 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 661 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 662 /* 97 - 3840x2160p@60Hz 16:9 */ 663 { DRM_MODE(594000, 3840, 4016, 664 4104, 4400, 2160, 2168, 2178, 2250, 0, 665 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 666 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 667 /* 98 - 4096x2160p@24Hz 256:135 */ 668 { DRM_MODE(297000, 4096, 5116, 669 5204, 5500, 2160, 2168, 2178, 2250, 0, 670 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 671 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 672 /* 99 - 4096x2160p@25Hz 256:135 */ 673 { DRM_MODE(297000, 4096, 5064, 674 5152, 5280, 2160, 2168, 2178, 2250, 0, 675 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 676 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 677 /* 100 - 4096x2160p@30Hz 256:135 */ 678 { DRM_MODE(297000, 4096, 4184, 679 4272, 4400, 2160, 2168, 2178, 2250, 0, 680 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 681 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 682 /* 101 - 4096x2160p@50Hz 256:135 */ 683 { DRM_MODE(594000, 4096, 5064, 684 5152, 5280, 2160, 2168, 2178, 2250, 0, 685 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 686 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 687 /* 102 - 4096x2160p@60Hz 256:135 */ 688 { DRM_MODE(594000, 4096, 4184, 689 4272, 4400, 2160, 2168, 2178, 2250, 0, 690 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 692 /* 103 - 3840x2160p@24Hz 64:27 */ 693 { DRM_MODE(297000, 3840, 5116, 694 5204, 5500, 2160, 2168, 2178, 2250, 0, 695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 696 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 697 /* 104 - 3840x2160p@25Hz 64:27 */ 698 { DRM_MODE(297000, 3840, 4016, 699 4104, 4400, 2160, 2168, 2178, 2250, 0, 700 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 701 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 702 /* 105 - 3840x2160p@30Hz 64:27 */ 703 { DRM_MODE(297000, 3840, 4016, 704 4104, 4400, 2160, 2168, 2178, 2250, 0, 705 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 706 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 707 /* 106 - 3840x2160p@50Hz 64:27 */ 708 { DRM_MODE(594000, 3840, 4896, 709 4984, 5280, 2160, 2168, 2178, 2250, 0, 710 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 711 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 712 /* 107 - 3840x2160p@60Hz 64:27 */ 713 { DRM_MODE(594000, 3840, 4016, 714 4104, 4400, 2160, 2168, 2178, 2250, 0, 715 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 717 }; 718 719 /* 720 * HDMI 1.4 4k modes. Index using the VIC. 721 */ 722 static const struct drm_display_mode edid_4k_modes[] = { 723 /* 0 - dummy, VICs start at 1 */ 724 { }, 725 /* 1 - 3840x2160@30Hz */ 726 { DRM_MODE(297000, 727 3840, 4016, 4104, 4400, 728 2160, 2168, 2178, 2250, 0, 729 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 730 .vrefresh = 30, }, 731 /* 2 - 3840x2160@25Hz */ 732 { DRM_MODE(297000, 733 3840, 4896, 4984, 5280, 734 2160, 2168, 2178, 2250, 0, 735 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 736 .vrefresh = 25, }, 737 /* 3 - 3840x2160@24Hz */ 738 { DRM_MODE(297000, 739 3840, 5116, 5204, 5500, 740 2160, 2168, 2178, 2250, 0, 741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 742 .vrefresh = 24, }, 743 /* 4 - 4096x2160@24Hz (SMPTE) */ 744 { DRM_MODE(297000, 745 4096, 5116, 5204, 5500, 746 2160, 2168, 2178, 2250, 0, 747 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 748 .vrefresh = 24, }, 749 }; 750 751 /* 752 * Autogenerated from the DMT spec. 753 * This table is copied from xfree86/modes/xf86EdidModes.c. 754 */ 755 static const struct drm_display_mode drm_dmt_modes[] = { 756 /* 0x01 - 640x350@85Hz */ 757 { DRM_MODE(31500, 640, 672, 758 736, 832, 350, 382, 385, 445, 0, 759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 760 /* 0x02 - 640x400@85Hz */ 761 { DRM_MODE(31500, 640, 672, 762 736, 832, 400, 401, 404, 445, 0, 763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 764 /* 0x03 - 720x400@85Hz */ 765 { DRM_MODE(35500, 720, 756, 766 828, 936, 400, 401, 404, 446, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 768 /* 0x04 - 640x480@60Hz */ 769 { DRM_MODE(25175, 640, 656, 770 752, 800, 480, 490, 492, 525, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 772 /* 0x05 - 640x480@72Hz */ 773 { DRM_MODE(31500, 640, 664, 774 704, 832, 480, 489, 492, 520, 0, 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 776 /* 0x06 - 640x480@75Hz */ 777 { DRM_MODE(31500, 640, 656, 778 720, 840, 480, 481, 484, 500, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 780 /* 0x07 - 640x480@85Hz */ 781 { DRM_MODE(36000, 640, 696, 782 752, 832, 480, 481, 484, 509, 0, 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 784 /* 0x08 - 800x600@56Hz */ 785 { DRM_MODE(36000, 800, 824, 786 896, 1024, 600, 601, 603, 625, 0, 787 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 788 /* 0x09 - 800x600@60Hz */ 789 { DRM_MODE(40000, 800, 840, 790 968, 1056, 600, 601, 605, 628, 0, 791 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 792 /* 0x0a - 800x600@72Hz */ 793 { DRM_MODE(50000, 800, 856, 794 976, 1040, 600, 637, 643, 666, 0, 795 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 796 /* 0x0b - 800x600@75Hz */ 797 { DRM_MODE(49500, 800, 816, 798 896, 1056, 600, 601, 604, 625, 0, 799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 800 /* 0x0c - 800x600@85Hz */ 801 { DRM_MODE(56250, 800, 832, 802 896, 1048, 600, 601, 604, 631, 0, 803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 804 /* 0x0d - 800x600@120Hz RB */ 805 { DRM_MODE(73250, 800, 848, 806 880, 960, 600, 603, 607, 636, 0, 807 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 808 /* 0x0e - 848x480@60Hz */ 809 { DRM_MODE(33750, 848, 864, 810 976, 1088, 480, 486, 494, 517, 0, 811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 812 /* 0x0f - 1024x768@43Hz, interlace */ 813 { DRM_MODE(44900, 1024, 1032, 814 1208, 1264, 768, 768, 772, 817, 0, 815 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 816 DRM_MODE_FLAG_INTERLACE) }, 817 /* 0x10 - 1024x768@60Hz */ 818 { DRM_MODE(65000, 1024, 1048, 819 1184, 1344, 768, 771, 777, 806, 0, 820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 821 /* 0x11 - 1024x768@70Hz */ 822 { DRM_MODE(75000, 1024, 1048, 823 1184, 1328, 768, 771, 777, 806, 0, 824 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 825 /* 0x12 - 1024x768@75Hz */ 826 { DRM_MODE(78750, 1024, 1040, 827 1136, 1312, 768, 769, 772, 800, 0, 828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 829 /* 0x13 - 1024x768@85Hz */ 830 { DRM_MODE(94500, 1024, 1072, 831 1168, 1376, 768, 769, 772, 808, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 833 /* 0x14 - 1024x768@120Hz RB */ 834 { DRM_MODE(115500, 1024, 1072, 835 1104, 1184, 768, 771, 775, 813, 0, 836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 837 /* 0x15 - 1152x864@75Hz */ 838 { DRM_MODE(108000, 1152, 1216, 839 1344, 1600, 864, 865, 868, 900, 0, 840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 841 /* 0x55 - 1280x720@60Hz */ 842 { DRM_MODE(74250, 1280, 1390, 843 1430, 1650, 720, 725, 730, 750, 0, 844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 845 /* 0x16 - 1280x768@60Hz RB */ 846 { DRM_MODE(68250, 1280, 1328, 847 1360, 1440, 768, 771, 778, 790, 0, 848 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 849 /* 0x17 - 1280x768@60Hz */ 850 { DRM_MODE(79500, 1280, 1344, 851 1472, 1664, 768, 771, 778, 798, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 853 /* 0x18 - 1280x768@75Hz */ 854 { DRM_MODE(102250, 1280, 1360, 855 1488, 1696, 768, 771, 778, 805, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 857 /* 0x19 - 1280x768@85Hz */ 858 { DRM_MODE(117500, 1280, 1360, 859 1496, 1712, 768, 771, 778, 809, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 861 /* 0x1a - 1280x768@120Hz RB */ 862 { DRM_MODE(140250, 1280, 1328, 863 1360, 1440, 768, 771, 778, 813, 0, 864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 865 /* 0x1b - 1280x800@60Hz RB */ 866 { DRM_MODE(71000, 1280, 1328, 867 1360, 1440, 800, 803, 809, 823, 0, 868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 869 /* 0x1c - 1280x800@60Hz */ 870 { DRM_MODE(83500, 1280, 1352, 871 1480, 1680, 800, 803, 809, 831, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 873 /* 0x1d - 1280x800@75Hz */ 874 { DRM_MODE(106500, 1280, 1360, 875 1488, 1696, 800, 803, 809, 838, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 877 /* 0x1e - 1280x800@85Hz */ 878 { DRM_MODE(122500, 1280, 1360, 879 1496, 1712, 800, 803, 809, 843, 0, 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 881 /* 0x1f - 1280x800@120Hz RB */ 882 { DRM_MODE(146250, 1280, 1328, 883 1360, 1440, 800, 803, 809, 847, 0, 884 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 885 /* 0x20 - 1280x960@60Hz */ 886 { DRM_MODE(108000, 1280, 1376, 887 1488, 1800, 960, 961, 964, 1000, 0, 888 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 889 /* 0x21 - 1280x960@85Hz */ 890 { DRM_MODE(148500, 1280, 1344, 891 1504, 1728, 960, 961, 964, 1011, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 893 /* 0x22 - 1280x960@120Hz RB */ 894 { DRM_MODE(175500, 1280, 1328, 895 1360, 1440, 960, 963, 967, 1017, 0, 896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 897 /* 0x23 - 1280x1024@60Hz */ 898 { DRM_MODE(108000, 1280, 1328, 899 1440, 1688, 1024, 1025, 1028, 1066, 0, 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 901 /* 0x24 - 1280x1024@75Hz */ 902 { DRM_MODE(135000, 1280, 1296, 903 1440, 1688, 1024, 1025, 1028, 1066, 0, 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 905 /* 0x25 - 1280x1024@85Hz */ 906 { DRM_MODE(157500, 1280, 1344, 907 1504, 1728, 1024, 1025, 1028, 1072, 0, 908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 909 /* 0x26 - 1280x1024@120Hz RB */ 910 { DRM_MODE(187250, 1280, 1328, 911 1360, 1440, 1024, 1027, 1034, 1084, 0, 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 913 /* 0x27 - 1360x768@60Hz */ 914 { DRM_MODE(85500, 1360, 1424, 915 1536, 1792, 768, 771, 777, 795, 0, 916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 917 /* 0x28 - 1360x768@120Hz RB */ 918 { DRM_MODE(148250, 1360, 1408, 919 1440, 1520, 768, 771, 776, 813, 0, 920 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 921 /* 0x51 - 1366x768@60Hz */ 922 { DRM_MODE(85500, 1366, 1436, 923 1579, 1792, 768, 771, 774, 798, 0, 924 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 925 /* 0x56 - 1366x768@60Hz */ 926 { DRM_MODE(72000, 1366, 1380, 927 1436, 1500, 768, 769, 772, 800, 0, 928 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 929 /* 0x29 - 1400x1050@60Hz RB */ 930 { DRM_MODE(101000, 1400, 1448, 931 1480, 1560, 1050, 1053, 1057, 1080, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 933 /* 0x2a - 1400x1050@60Hz */ 934 { DRM_MODE(121750, 1400, 1488, 935 1632, 1864, 1050, 1053, 1057, 1089, 0, 936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 937 /* 0x2b - 1400x1050@75Hz */ 938 { DRM_MODE(156000, 1400, 1504, 939 1648, 1896, 1050, 1053, 1057, 1099, 0, 940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 941 /* 0x2c - 1400x1050@85Hz */ 942 { DRM_MODE(179500, 1400, 1504, 943 1656, 1912, 1050, 1053, 1057, 1105, 0, 944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 945 /* 0x2d - 1400x1050@120Hz RB */ 946 { DRM_MODE(208000, 1400, 1448, 947 1480, 1560, 1050, 1053, 1057, 1112, 0, 948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 949 /* 0x2e - 1440x900@60Hz RB */ 950 { DRM_MODE(88750, 1440, 1488, 951 1520, 1600, 900, 903, 909, 926, 0, 952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 953 /* 0x2f - 1440x900@60Hz */ 954 { DRM_MODE(106500, 1440, 1520, 955 1672, 1904, 900, 903, 909, 934, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 957 /* 0x30 - 1440x900@75Hz */ 958 { DRM_MODE(136750, 1440, 1536, 959 1688, 1936, 900, 903, 909, 942, 0, 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 961 /* 0x31 - 1440x900@85Hz */ 962 { DRM_MODE(157000, 1440, 1544, 963 1696, 1952, 900, 903, 909, 948, 0, 964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 965 /* 0x32 - 1440x900@120Hz RB */ 966 { DRM_MODE(182750, 1440, 1488, 967 1520, 1600, 900, 903, 909, 953, 0, 968 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 969 /* 0x53 - 1600x900@60Hz */ 970 { DRM_MODE(108000, 1600, 1624, 971 1704, 1800, 900, 901, 904, 1000, 0, 972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 973 /* 0x33 - 1600x1200@60Hz */ 974 { DRM_MODE(162000, 1600, 1664, 975 1856, 2160, 1200, 1201, 1204, 1250, 0, 976 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 977 /* 0x34 - 1600x1200@65Hz */ 978 { DRM_MODE(175500, 1600, 1664, 979 1856, 2160, 1200, 1201, 1204, 1250, 0, 980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 981 /* 0x35 - 1600x1200@70Hz */ 982 { DRM_MODE(189000, 1600, 1664, 983 1856, 2160, 1200, 1201, 1204, 1250, 0, 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 985 /* 0x36 - 1600x1200@75Hz */ 986 { DRM_MODE(202500, 1600, 1664, 987 1856, 2160, 1200, 1201, 1204, 1250, 0, 988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 989 /* 0x37 - 1600x1200@85Hz */ 990 { DRM_MODE(229500, 1600, 1664, 991 1856, 2160, 1200, 1201, 1204, 1250, 0, 992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 993 /* 0x38 - 1600x1200@120Hz RB */ 994 { DRM_MODE(268250, 1600, 1648, 995 1680, 1760, 1200, 1203, 1207, 1271, 0, 996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 997 /* 0x39 - 1680x1050@60Hz RB */ 998 { DRM_MODE(119000, 1680, 1728, 999 1760, 1840, 1050, 1053, 1059, 1080, 0, 1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1001 /* 0x3a - 1680x1050@60Hz */ 1002 { DRM_MODE(146250, 1680, 1784, 1003 1960, 2240, 1050, 1053, 1059, 1089, 0, 1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1005 /* 0x3b - 1680x1050@75Hz */ 1006 { DRM_MODE(187000, 1680, 1800, 1007 1976, 2272, 1050, 1053, 1059, 1099, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1009 /* 0x3c - 1680x1050@85Hz */ 1010 { DRM_MODE(214750, 1680, 1808, 1011 1984, 2288, 1050, 1053, 1059, 1105, 0, 1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1013 /* 0x3d - 1680x1050@120Hz RB */ 1014 { DRM_MODE(245500, 1680, 1728, 1015 1760, 1840, 1050, 1053, 1059, 1112, 0, 1016 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1017 /* 0x3e - 1792x1344@60Hz */ 1018 { DRM_MODE(204750, 1792, 1920, 1019 2120, 2448, 1344, 1345, 1348, 1394, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1021 /* 0x3f - 1792x1344@75Hz */ 1022 { DRM_MODE(261000, 1792, 1888, 1023 2104, 2456, 1344, 1345, 1348, 1417, 0, 1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1025 /* 0x40 - 1792x1344@120Hz RB */ 1026 { DRM_MODE(333250, 1792, 1840, 1027 1872, 1952, 1344, 1347, 1351, 1423, 0, 1028 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1029 /* 0x41 - 1856x1392@60Hz */ 1030 { DRM_MODE(218250, 1856, 1952, 1031 2176, 2528, 1392, 1393, 1396, 1439, 0, 1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1033 /* 0x42 - 1856x1392@75Hz */ 1034 { DRM_MODE(288000, 1856, 1984, 1035 2208, 2560, 1392, 1393, 1396, 1500, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1037 /* 0x43 - 1856x1392@120Hz RB */ 1038 { DRM_MODE(356500, 1856, 1904, 1039 1936, 2016, 1392, 1395, 1399, 1474, 0, 1040 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1041 /* 0x52 - 1920x1080@60Hz */ 1042 { DRM_MODE(148500, 1920, 2008, 1043 2052, 2200, 1080, 1084, 1089, 1125, 0, 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1045 /* 0x44 - 1920x1200@60Hz RB */ 1046 { DRM_MODE(154000, 1920, 1968, 1047 2000, 2080, 1200, 1203, 1209, 1235, 0, 1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1049 /* 0x45 - 1920x1200@60Hz */ 1050 { DRM_MODE(193250, 1920, 2056, 1051 2256, 2592, 1200, 1203, 1209, 1245, 0, 1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1053 /* 0x46 - 1920x1200@75Hz */ 1054 { DRM_MODE(245250, 1920, 2056, 1055 2264, 2608, 1200, 1203, 1209, 1255, 0, 1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1057 /* 0x47 - 1920x1200@85Hz */ 1058 { DRM_MODE(281250, 1920, 2064, 1059 2272, 2624, 1200, 1203, 1209, 1262, 0, 1060 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1061 /* 0x48 - 1920x1200@120Hz RB */ 1062 { DRM_MODE(317000, 1920, 1968, 1063 2000, 2080, 1200, 1203, 1209, 1271, 0, 1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1065 /* 0x49 - 1920x1440@60Hz */ 1066 { DRM_MODE(234000, 1920, 2048, 1067 2256, 2600, 1440, 1441, 1444, 1500, 0, 1068 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1069 /* 0x4a - 1920x1440@75Hz */ 1070 { DRM_MODE(297000, 1920, 2064, 1071 2288, 2640, 1440, 1441, 1444, 1500, 0, 1072 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1073 /* 0x4b - 1920x1440@120Hz RB */ 1074 { DRM_MODE(380500, 1920, 1968, 1075 2000, 2080, 1440, 1443, 1447, 1525, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1077 /* 0x54 - 2048x1152@60Hz */ 1078 { DRM_MODE(162000, 2048, 2074, 1079 2154, 2250, 1152, 1153, 1156, 1200, 0, 1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1081 /* 0x4c - 2560x1600@60Hz RB */ 1082 { DRM_MODE(268500, 2560, 2608, 1083 2640, 2720, 1600, 1603, 1609, 1646, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1085 /* 0x4d - 2560x1600@60Hz */ 1086 { DRM_MODE(348500, 2560, 2752, 1087 3032, 3504, 1600, 1603, 1609, 1658, 0, 1088 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1089 /* 0x4e - 2560x1600@75Hz */ 1090 { DRM_MODE(443250, 2560, 2768, 1091 3048, 3536, 1600, 1603, 1609, 1672, 0, 1092 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1093 /* 0x4f - 2560x1600@85Hz */ 1094 { DRM_MODE(505250, 2560, 2768, 1095 3048, 3536, 1600, 1603, 1609, 1682, 0, 1096 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1097 /* 0x50 - 2560x1600@120Hz RB */ 1098 { DRM_MODE(552750, 2560, 2608, 1099 2640, 2720, 1600, 1603, 1609, 1694, 0, 1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1101 /* 0x57 - 4096x2160@60Hz RB */ 1102 { DRM_MODE(556744, 4096, 4104, 1103 4136, 4176, 2160, 2208, 2216, 2222, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1105 /* 0x58 - 4096x2160@59.94Hz RB */ 1106 { DRM_MODE(556188, 4096, 4104, 1107 4136, 4176, 2160, 2208, 2216, 2222, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1109 }; 1110 1111 /* 1112 * These more or less come from the DMT spec. The 720x400 modes are 1113 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1114 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1115 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1116 * mode. 1117 * 1118 * The DMT modes have been fact-checked; the rest are mild guesses. 1119 */ 1120 static const struct drm_display_mode edid_est_modes[] = { 1121 /* 800x600@60Hz */ 1122 { DRM_MODE(40000, 800, 840, 1123 968, 1056, 600, 601, 605, 628, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1125 /* 800x600@56Hz */ 1126 { DRM_MODE(36000, 800, 824, 1127 896, 1024, 600, 601, 603, 625, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1129 /* 640x480@75Hz */ 1130 { DRM_MODE(31500, 640, 656, 1131 720, 840, 480, 481, 484, 500, 0, 1132 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1133 /* 640x480@72Hz */ 1134 { DRM_MODE(31500, 640, 664, 1135 704, 832, 480, 489, 492, 520, 0, 1136 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1137 /* 640x480@67Hz */ 1138 { DRM_MODE(30240, 640, 704, 1139 768, 864, 480, 483, 486, 525, 0, 1140 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1141 /* 640x480@60Hz */ 1142 { DRM_MODE(25175, 640, 656, 1143 752, 800, 480, 490, 492, 525, 0, 1144 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1145 /* 720x400@88Hz */ 1146 { DRM_MODE(35500, 720, 738, 1147 846, 900, 400, 421, 423, 449, 0, 1148 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1149 /* 720x400@70Hz */ 1150 { DRM_MODE(28320, 720, 738, 1151 846, 900, 400, 412, 414, 449, 0, 1152 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1153 /* 1280x1024@75Hz */ 1154 { DRM_MODE(135000, 1280, 1296, 1155 1440, 1688, 1024, 1025, 1028, 1066, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1157 /* 1024x768@75Hz */ 1158 { DRM_MODE(78750, 1024, 1040, 1159 1136, 1312, 768, 769, 772, 800, 0, 1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1161 /* 1024x768@70Hz */ 1162 { DRM_MODE(75000, 1024, 1048, 1163 1184, 1328, 768, 771, 777, 806, 0, 1164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1165 /* 1024x768@60Hz */ 1166 { DRM_MODE(65000, 1024, 1048, 1167 1184, 1344, 768, 771, 777, 806, 0, 1168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1169 /* 1024x768@43Hz */ 1170 { DRM_MODE(44900, 1024, 1032, 1171 1208, 1264, 768, 768, 776, 817, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1173 DRM_MODE_FLAG_INTERLACE) }, 1174 /* 832x624@75Hz */ 1175 { DRM_MODE(57284, 832, 864, 1176 928, 1152, 624, 625, 628, 667, 0, 1177 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1178 /* 800x600@75Hz */ 1179 { DRM_MODE(49500, 800, 816, 1180 896, 1056, 600, 601, 604, 625, 0, 1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1182 /* 800x600@72Hz */ 1183 { DRM_MODE(50000, 800, 856, 1184 976, 1040, 600, 637, 643, 666, 0, 1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1186 /* 1152x864@75Hz */ 1187 { DRM_MODE(108000, 1152, 1216, 1188 1344, 1600, 864, 865, 868, 900, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1190 }; 1191 1192 struct minimode { 1193 short w; 1194 short h; 1195 short r; 1196 short rb; 1197 }; 1198 1199 static const struct minimode est3_modes[] = { 1200 /* byte 6 */ 1201 { 640, 350, 85, 0 }, 1202 { 640, 400, 85, 0 }, 1203 { 720, 400, 85, 0 }, 1204 { 640, 480, 85, 0 }, 1205 { 848, 480, 60, 0 }, 1206 { 800, 600, 85, 0 }, 1207 { 1024, 768, 85, 0 }, 1208 { 1152, 864, 75, 0 }, 1209 /* byte 7 */ 1210 { 1280, 768, 60, 1 }, 1211 { 1280, 768, 60, 0 }, 1212 { 1280, 768, 75, 0 }, 1213 { 1280, 768, 85, 0 }, 1214 { 1280, 960, 60, 0 }, 1215 { 1280, 960, 85, 0 }, 1216 { 1280, 1024, 60, 0 }, 1217 { 1280, 1024, 85, 0 }, 1218 /* byte 8 */ 1219 { 1360, 768, 60, 0 }, 1220 { 1440, 900, 60, 1 }, 1221 { 1440, 900, 60, 0 }, 1222 { 1440, 900, 75, 0 }, 1223 { 1440, 900, 85, 0 }, 1224 { 1400, 1050, 60, 1 }, 1225 { 1400, 1050, 60, 0 }, 1226 { 1400, 1050, 75, 0 }, 1227 /* byte 9 */ 1228 { 1400, 1050, 85, 0 }, 1229 { 1680, 1050, 60, 1 }, 1230 { 1680, 1050, 60, 0 }, 1231 { 1680, 1050, 75, 0 }, 1232 { 1680, 1050, 85, 0 }, 1233 { 1600, 1200, 60, 0 }, 1234 { 1600, 1200, 65, 0 }, 1235 { 1600, 1200, 70, 0 }, 1236 /* byte 10 */ 1237 { 1600, 1200, 75, 0 }, 1238 { 1600, 1200, 85, 0 }, 1239 { 1792, 1344, 60, 0 }, 1240 { 1792, 1344, 75, 0 }, 1241 { 1856, 1392, 60, 0 }, 1242 { 1856, 1392, 75, 0 }, 1243 { 1920, 1200, 60, 1 }, 1244 { 1920, 1200, 60, 0 }, 1245 /* byte 11 */ 1246 { 1920, 1200, 75, 0 }, 1247 { 1920, 1200, 85, 0 }, 1248 { 1920, 1440, 60, 0 }, 1249 { 1920, 1440, 75, 0 }, 1250 }; 1251 1252 static const struct minimode extra_modes[] = { 1253 { 1024, 576, 60, 0 }, 1254 { 1366, 768, 60, 0 }, 1255 { 1600, 900, 60, 0 }, 1256 { 1680, 945, 60, 0 }, 1257 { 1920, 1080, 60, 0 }, 1258 { 2048, 1152, 60, 0 }, 1259 { 2048, 1536, 60, 0 }, 1260 }; 1261 1262 int edid_check_info(struct edid1_info *edid_info) 1263 { 1264 if ((edid_info == NULL) || (edid_info->version == 0)) 1265 return -1; 1266 1267 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1268 return -1; 1269 1270 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1271 return -1; 1272 1273 return 0; 1274 } 1275 1276 int edid_check_checksum(u8 *edid_block) 1277 { 1278 u8 checksum = 0; 1279 int i; 1280 1281 for (i = 0; i < 128; i++) 1282 checksum += edid_block[i]; 1283 1284 return (checksum == 0) ? 0 : -EINVAL; 1285 } 1286 1287 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1288 unsigned int *hmax, unsigned int *vmin, 1289 unsigned int *vmax) 1290 { 1291 int i; 1292 struct edid_monitor_descriptor *monitor; 1293 1294 *hmin = *hmax = *vmin = *vmax = 0; 1295 if (edid_check_info(edid)) 1296 return -1; 1297 1298 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1299 monitor = &edid->monitor_details.descriptor[i]; 1300 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1301 *hmin = monitor->data.range_data.horizontal_min; 1302 *hmax = monitor->data.range_data.horizontal_max; 1303 *vmin = monitor->data.range_data.vertical_min; 1304 *vmax = monitor->data.range_data.vertical_max; 1305 return 0; 1306 } 1307 } 1308 return -1; 1309 } 1310 1311 /* Set all parts of a timing entry to the same value */ 1312 static void set_entry(struct timing_entry *entry, u32 value) 1313 { 1314 entry->min = value; 1315 entry->typ = value; 1316 entry->max = value; 1317 } 1318 1319 /** 1320 * decode_timing() - Decoding an 18-byte detailed timing record 1321 * 1322 * @buf: Pointer to EDID detailed timing record 1323 * @timing: Place to put timing 1324 */ 1325 static void decode_timing(u8 *buf, struct display_timing *timing) 1326 { 1327 uint x_mm, y_mm; 1328 unsigned int ha, hbl, hso, hspw, hborder; 1329 unsigned int va, vbl, vso, vspw, vborder; 1330 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1331 1332 /* Edid contains pixel clock in terms of 10KHz */ 1333 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1334 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1335 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1336 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1337 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1338 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1339 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1340 hborder = buf[15]; 1341 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1342 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1343 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1344 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1345 vborder = buf[16]; 1346 1347 set_entry(&timing->hactive, ha); 1348 set_entry(&timing->hfront_porch, hso); 1349 set_entry(&timing->hback_porch, hbl - hso - hspw); 1350 set_entry(&timing->hsync_len, hspw); 1351 1352 set_entry(&timing->vactive, va); 1353 set_entry(&timing->vfront_porch, vso); 1354 set_entry(&timing->vback_porch, vbl - vso - vspw); 1355 set_entry(&timing->vsync_len, vspw); 1356 1357 timing->flags = 0; 1358 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1359 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1360 else 1361 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1362 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1363 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1364 else 1365 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1366 1367 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1368 timing->flags = DISPLAY_FLAGS_INTERLACED; 1369 1370 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1371 " %04x %04x %04x %04x hborder %x\n" 1372 " %04x %04x %04x %04x vborder %x\n", 1373 timing->pixelclock.typ, 1374 x_mm, y_mm, 1375 ha, ha + hso, ha + hso + hspw, 1376 ha + hbl, hborder, 1377 va, va + vso, va + vso + vspw, 1378 va + vbl, vborder); 1379 } 1380 1381 /** 1382 * decode_mode() - Decoding an 18-byte detailed timing record 1383 * 1384 * @buf: Pointer to EDID detailed timing record 1385 * @timing: Place to put timing 1386 */ 1387 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1388 { 1389 uint x_mm, y_mm; 1390 unsigned int ha, hbl, hso, hspw, hborder; 1391 unsigned int va, vbl, vso, vspw, vborder; 1392 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1393 1394 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1395 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1396 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1397 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1398 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1399 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1400 hborder = buf[15]; 1401 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1402 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1403 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1404 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1405 vborder = buf[16]; 1406 1407 /* Edid contains pixel clock in terms of 10KHz */ 1408 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1409 mode->hdisplay = ha; 1410 mode->hsync_start = ha + hso; 1411 mode->hsync_end = ha + hso + hspw; 1412 mode->htotal = ha + hbl; 1413 mode->vdisplay = va; 1414 mode->vsync_start = va + vso; 1415 mode->vsync_end = va + vso + vspw; 1416 mode->vtotal = va + vbl; 1417 1418 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1419 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1420 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1421 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1422 1423 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1424 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1425 1426 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1427 " %04d %04d %04d %04d hborder %d\n" 1428 " %04d %04d %04d %04d vborder %d\n", 1429 mode->clock, 1430 x_mm, y_mm, mode->flags, 1431 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1432 mode->htotal, hborder, 1433 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1434 mode->vtotal, vborder); 1435 } 1436 1437 /** 1438 * edid_vendor - match a string against EDID's obfuscated vendor field 1439 * @edid: EDID to match 1440 * @vendor: vendor string 1441 * 1442 * Returns true if @vendor is in @edid, false otherwise 1443 */ 1444 static bool edid_vendor(struct edid *edid, char *vendor) 1445 { 1446 char edid_vendor[3]; 1447 1448 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1449 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1450 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1451 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1452 1453 return !strncmp(edid_vendor, vendor, 3); 1454 } 1455 1456 /** 1457 * Check if HDMI vendor specific data block is present in CEA block 1458 * @param info CEA extension block 1459 * @return true if block is found 1460 */ 1461 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1462 { 1463 u8 end, i = 0; 1464 1465 /* check for end of data block */ 1466 end = info->dtd_offset; 1467 if (end == 0) 1468 end = sizeof(info->data); 1469 if (end < 4 || end > sizeof(info->data)) 1470 return false; 1471 end -= 4; 1472 1473 while (i < end) { 1474 /* Look for vendor specific data block of appropriate size */ 1475 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1476 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1477 u8 *db = &info->data[i + 1]; 1478 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1479 1480 if (oui == HDMI_IEEE_OUI) 1481 return true; 1482 } 1483 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1484 } 1485 1486 return false; 1487 } 1488 1489 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1490 { 1491 int refresh = 0; 1492 unsigned int calc_val; 1493 1494 if (mode->vrefresh > 0) { 1495 refresh = mode->vrefresh; 1496 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1497 int vtotal; 1498 1499 vtotal = mode->vtotal; 1500 /* work out vrefresh the value will be x1000 */ 1501 calc_val = (mode->clock * 1000); 1502 calc_val /= mode->htotal; 1503 refresh = (calc_val + vtotal / 2) / vtotal; 1504 1505 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1506 refresh *= 2; 1507 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1508 refresh /= 2; 1509 if (mode->vscan > 1) 1510 refresh /= mode->vscan; 1511 } 1512 return refresh; 1513 } 1514 1515 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1516 int *panel_bits_per_colourp) 1517 { 1518 struct edid1_info *edid = (struct edid1_info *)buf; 1519 bool timing_done; 1520 int i; 1521 1522 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1523 debug("%s: Invalid buffer\n", __func__); 1524 return -EINVAL; 1525 } 1526 1527 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1528 debug("%s: No preferred timing\n", __func__); 1529 return -ENOENT; 1530 } 1531 1532 /* Look for detailed timing */ 1533 timing_done = false; 1534 for (i = 0; i < 4; i++) { 1535 struct edid_monitor_descriptor *desc; 1536 1537 desc = &edid->monitor_details.descriptor[i]; 1538 if (desc->zero_flag_1 != 0) { 1539 decode_mode((u8 *)desc, mode); 1540 timing_done = true; 1541 break; 1542 } 1543 } 1544 if (!timing_done) 1545 return -EINVAL; 1546 1547 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1548 debug("%s: Not a digital display\n", __func__); 1549 return -ENOSYS; 1550 } 1551 if (edid->version != 1 || edid->revision < 4) { 1552 debug("%s: EDID version %d.%d does not have required info\n", 1553 __func__, edid->version, edid->revision); 1554 *panel_bits_per_colourp = -1; 1555 } else { 1556 *panel_bits_per_colourp = 1557 ((edid->video_input_definition & 0x70) >> 3) + 4; 1558 } 1559 1560 return 0; 1561 } 1562 1563 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 1564 int *panel_bits_per_colourp) 1565 { 1566 struct edid1_info *edid = (struct edid1_info *)buf; 1567 bool timing_done; 1568 int i; 1569 1570 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1571 debug("%s: Invalid buffer\n", __func__); 1572 return -EINVAL; 1573 } 1574 1575 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1576 debug("%s: No preferred timing\n", __func__); 1577 return -ENOENT; 1578 } 1579 1580 /* Look for detailed timing */ 1581 timing_done = false; 1582 for (i = 0; i < 4; i++) { 1583 struct edid_monitor_descriptor *desc; 1584 1585 desc = &edid->monitor_details.descriptor[i]; 1586 if (desc->zero_flag_1 != 0) { 1587 decode_timing((u8 *)desc, timing); 1588 timing_done = true; 1589 break; 1590 } 1591 } 1592 if (!timing_done) 1593 return -EINVAL; 1594 1595 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1596 debug("%s: Not a digital display\n", __func__); 1597 return -ENOSYS; 1598 } 1599 if (edid->version != 1 || edid->revision < 4) { 1600 debug("%s: EDID version %d.%d does not have required info\n", 1601 __func__, edid->version, edid->revision); 1602 *panel_bits_per_colourp = -1; 1603 } else { 1604 *panel_bits_per_colourp = 1605 ((edid->video_input_definition & 0x70) >> 3) + 4; 1606 } 1607 1608 timing->hdmi_monitor = false; 1609 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 1610 struct edid_cea861_info *info = 1611 (struct edid_cea861_info *)(buf + sizeof(*edid)); 1612 1613 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 1614 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 1615 } 1616 1617 return 0; 1618 } 1619 1620 /** 1621 * Snip the tailing whitespace/return of a string. 1622 * 1623 * @param string The string to be snipped 1624 * @return the snipped string 1625 */ 1626 static char *snip(char *string) 1627 { 1628 char *s; 1629 1630 /* 1631 * This is always a 13 character buffer 1632 * and it's not always terminated. 1633 */ 1634 string[12] = '\0'; 1635 s = &string[strlen(string) - 1]; 1636 1637 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 1638 *s == '\0')) 1639 *(s--) = '\0'; 1640 1641 return string; 1642 } 1643 1644 /** 1645 * Print an EDID monitor descriptor block 1646 * 1647 * @param monitor The EDID monitor descriptor block 1648 * @have_timing Modifies to 1 if the desciptor contains timing info 1649 */ 1650 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 1651 unsigned int *have_timing) 1652 { 1653 unsigned char *bytes = (unsigned char *)monitor; 1654 struct edid_detailed_timing *timing = 1655 (struct edid_detailed_timing *)monitor; 1656 1657 if (bytes[0] == 0 && bytes[1] == 0) { 1658 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 1659 printf("Monitor serial number: %s\n", 1660 snip(monitor->data.string)); 1661 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 1662 printf("Monitor ID: %s\n", 1663 snip(monitor->data.string)); 1664 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 1665 printf("Monitor name: %s\n", 1666 snip(monitor->data.string)); 1667 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 1668 printf("Monitor range limits, horizontal sync: " 1669 "%d-%d kHz, vertical refresh: " 1670 "%d-%d Hz, max pixel clock: " 1671 "%d MHz\n", 1672 monitor->data.range_data.horizontal_min, 1673 monitor->data.range_data.horizontal_max, 1674 monitor->data.range_data.vertical_min, 1675 monitor->data.range_data.vertical_max, 1676 monitor->data.range_data.pixel_clock_max * 10); 1677 } else { 1678 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 1679 u32 h_total, v_total, vfreq; 1680 1681 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 1682 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 1683 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 1684 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 1685 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 1686 1687 h_total = h_active + h_blanking; 1688 v_total = v_active + v_blanking; 1689 if (v_total > 0 && h_total > 0) 1690 vfreq = pixclock / (v_total * h_total); 1691 else 1692 vfreq = 1; /* Error case */ 1693 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 1694 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 1695 *have_timing = 1; 1696 } 1697 } 1698 1699 /** 1700 * Get the manufacturer name from an EDID info. 1701 * 1702 * @param edid_info The EDID info to be printed 1703 * @param name Returns the string of the manufacturer name 1704 */ 1705 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 1706 { 1707 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 1708 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 1709 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 1710 name[3] = '\0'; 1711 } 1712 1713 void edid_print_info(struct edid1_info *edid_info) 1714 { 1715 int i; 1716 char manufacturer[4]; 1717 unsigned int have_timing = 0; 1718 u32 serial_number; 1719 1720 if (edid_check_info(edid_info)) { 1721 printf("Not a valid EDID\n"); 1722 return; 1723 } 1724 1725 printf("EDID version: %d.%d\n", 1726 edid_info->version, edid_info->revision); 1727 1728 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 1729 1730 edid_get_manufacturer_name(edid_info, manufacturer); 1731 printf("Manufacturer: %s\n", manufacturer); 1732 1733 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 1734 if (serial_number != 0xffffffff) { 1735 if (strcmp(manufacturer, "MAG") == 0) 1736 serial_number -= 0x7000000; 1737 if (strcmp(manufacturer, "OQI") == 0) 1738 serial_number -= 456150000; 1739 if (strcmp(manufacturer, "VSC") == 0) 1740 serial_number -= 640000000; 1741 } 1742 printf("Serial number: %08x\n", serial_number); 1743 printf("Manufactured in week: %d year: %d\n", 1744 edid_info->week, edid_info->year + 1990); 1745 1746 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 1747 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 1748 "digital signal, " : "analog signal, ", 1749 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 1750 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 1751 ", blank to black" : "", 1752 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 1753 ", separate sync" : "", 1754 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 1755 ", composite sync" : "", 1756 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 1757 ", sync on green" : "", 1758 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 1759 ", serration v" : ""); 1760 1761 printf("Monitor is %s\n", 1762 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 1763 1764 printf("Maximum visible display size: %d cm x %d cm\n", 1765 edid_info->max_size_horizontal, 1766 edid_info->max_size_vertical); 1767 1768 printf("Power management features: %s%s, %s%s, %s%s\n", 1769 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 1770 "" : "no ", "active off", 1771 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 1772 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 1773 1774 printf("Estabilished timings:\n"); 1775 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 1776 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 1777 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 1778 printf("\t720x400\t\t88 Hz (XGA2)\n"); 1779 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 1780 printf("\t640x480\t\t60 Hz (VGA)\n"); 1781 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 1782 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 1783 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 1784 printf("\t640x480\t\t72 Hz (VESA)\n"); 1785 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 1786 printf("\t640x480\t\t75 Hz (VESA)\n"); 1787 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 1788 printf("\t800x600\t\t56 Hz (VESA)\n"); 1789 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 1790 printf("\t800x600\t\t60 Hz (VESA)\n"); 1791 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 1792 printf("\t800x600\t\t72 Hz (VESA)\n"); 1793 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 1794 printf("\t800x600\t\t75 Hz (VESA)\n"); 1795 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 1796 printf("\t832x624\t\t75 Hz (Mac II)\n"); 1797 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 1798 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 1799 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 1800 printf("\t1024x768\t60 Hz (VESA)\n"); 1801 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 1802 printf("\t1024x768\t70 Hz (VESA)\n"); 1803 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 1804 printf("\t1024x768\t75 Hz (VESA)\n"); 1805 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 1806 printf("\t1280x1024\t75 (VESA)\n"); 1807 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 1808 printf("\t1152x870\t75 (Mac II)\n"); 1809 1810 /* Standard timings. */ 1811 printf("Standard timings:\n"); 1812 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 1813 unsigned int aspect = 10000; 1814 unsigned int x, y; 1815 unsigned char xres, vfreq; 1816 1817 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 1818 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 1819 if ((xres != vfreq) || 1820 ((xres != 0) && (xres != 1)) || 1821 ((vfreq != 0) && (vfreq != 1))) { 1822 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 1823 i)) { 1824 case ASPECT_625: 1825 aspect = 6250; 1826 break; 1827 case ASPECT_75: 1828 aspect = 7500; 1829 break; 1830 case ASPECT_8: 1831 aspect = 8000; 1832 break; 1833 case ASPECT_5625: 1834 aspect = 5625; 1835 break; 1836 } 1837 x = (xres + 31) * 8; 1838 y = x * aspect / 10000; 1839 printf("\t%dx%d%c\t%d Hz\n", x, y, 1840 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 1841 have_timing = 1; 1842 } 1843 } 1844 1845 /* Detailed timing information. */ 1846 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 1847 i++) { 1848 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 1849 &have_timing); 1850 } 1851 1852 if (!have_timing) 1853 printf("\tNone\n"); 1854 } 1855 1856 /** 1857 * drm_mode_create - create a new display mode 1858 * 1859 * Create a new, cleared drm_display_mode. 1860 * 1861 * Returns: 1862 * Pointer to new mode on success, NULL on error. 1863 */ 1864 static struct drm_display_mode *drm_mode_create(void) 1865 { 1866 struct drm_display_mode *nmode; 1867 1868 nmode = malloc(sizeof(struct drm_display_mode)); 1869 memset(nmode, 0, sizeof(struct drm_display_mode)); 1870 if (!nmode) 1871 return NULL; 1872 1873 return nmode; 1874 } 1875 1876 /** 1877 * drm_mode_destroy - remove a mode 1878 * @mode: mode to remove 1879 * 1880 */ 1881 static void drm_mode_destroy(struct drm_display_mode *mode) 1882 { 1883 if (!mode) 1884 return; 1885 1886 kfree(mode); 1887 } 1888 1889 /** 1890 * drm_cvt_mode -create a modeline based on the CVT algorithm 1891 * @hdisplay: hdisplay size 1892 * @vdisplay: vdisplay size 1893 * @vrefresh: vrefresh rate 1894 * @reduced: whether to use reduced blanking 1895 * @interlaced: whether to compute an interlaced mode 1896 * @margins: whether to add margins (borders) 1897 * 1898 * This function is called to generate the modeline based on CVT algorithm 1899 * according to the hdisplay, vdisplay, vrefresh. 1900 * It is based from the VESA(TM) Coordinated Video Timing Generator by 1901 * Graham Loveridge April 9, 2003 available at 1902 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 1903 * 1904 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 1905 * What I have done is to translate it by using integer calculation. 1906 * 1907 * Returns: 1908 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 1909 * The display mode object is allocated with drm_mode_create(). Returns NULL 1910 * when no mode could be allocated. 1911 */ 1912 static 1913 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 1914 bool reduced, bool interlaced, 1915 bool margins) 1916 { 1917 #define HV_FACTOR 1000 1918 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 1919 #define CVT_MARGIN_PERCENTAGE 18 1920 /* 2) character cell horizontal granularity (pixels) - default 8 */ 1921 #define CVT_H_GRANULARITY 8 1922 /* 3) Minimum vertical porch (lines) - default 3 */ 1923 #define CVT_MIN_V_PORCH 3 1924 /* 4) Minimum number of vertical back porch lines - default 6 */ 1925 #define CVT_MIN_V_BPORCH 6 1926 /* Pixel Clock step (kHz) */ 1927 #define CVT_CLOCK_STEP 250 1928 struct drm_display_mode *drm_mode; 1929 unsigned int vfieldrate, hperiod; 1930 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 1931 int interlace; 1932 1933 /* allocate the drm_display_mode structure. If failure, we will 1934 * return directly 1935 */ 1936 drm_mode = drm_mode_create(); 1937 if (!drm_mode) 1938 return NULL; 1939 1940 /* the CVT default refresh rate is 60Hz */ 1941 if (!vrefresh) 1942 vrefresh = 60; 1943 1944 /* the required field fresh rate */ 1945 if (interlaced) 1946 vfieldrate = vrefresh * 2; 1947 else 1948 vfieldrate = vrefresh; 1949 1950 /* horizontal pixels */ 1951 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 1952 1953 /* determine the left&right borders */ 1954 hmargin = 0; 1955 if (margins) { 1956 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1957 hmargin -= hmargin % CVT_H_GRANULARITY; 1958 } 1959 /* find the total active pixels */ 1960 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 1961 1962 /* find the number of lines per field */ 1963 if (interlaced) 1964 vdisplay_rnd = vdisplay / 2; 1965 else 1966 vdisplay_rnd = vdisplay; 1967 1968 /* find the top & bottom borders */ 1969 vmargin = 0; 1970 if (margins) 1971 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1972 1973 drm_mode->vdisplay = vdisplay + 2 * vmargin; 1974 1975 /* Interlaced */ 1976 if (interlaced) 1977 interlace = 1; 1978 else 1979 interlace = 0; 1980 1981 /* Determine VSync Width from aspect ratio */ 1982 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 1983 vsync = 4; 1984 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 1985 vsync = 5; 1986 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 1987 vsync = 6; 1988 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 1989 vsync = 7; 1990 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 1991 vsync = 7; 1992 else /* custom */ 1993 vsync = 10; 1994 1995 if (!reduced) { 1996 /* simplify the GTF calculation */ 1997 /* 4) Minimum time of vertical sync + back porch interval 1998 * default 550.0 1999 */ 2000 int tmp1, tmp2; 2001 #define CVT_MIN_VSYNC_BP 550 2002 /* 3) Nominal HSync width (% of line period) - default 8 */ 2003 #define CVT_HSYNC_PERCENTAGE 8 2004 unsigned int hblank_percentage; 2005 int vsyncandback_porch, hblank; 2006 2007 /* estimated the horizontal period */ 2008 tmp1 = HV_FACTOR * 1000000 - 2009 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2010 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2011 interlace; 2012 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2013 2014 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2015 /* 9. Find number of lines in sync + backporch */ 2016 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2017 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2018 else 2019 vsyncandback_porch = tmp1; 2020 /* 10. Find number of lines in back porch 2021 * vback_porch = vsyncandback_porch - vsync; 2022 */ 2023 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2024 vsyncandback_porch + CVT_MIN_V_PORCH; 2025 /* 5) Definition of Horizontal blanking time limitation */ 2026 /* Gradient (%/kHz) - default 600 */ 2027 #define CVT_M_FACTOR 600 2028 /* Offset (%) - default 40 */ 2029 #define CVT_C_FACTOR 40 2030 /* Blanking time scaling factor - default 128 */ 2031 #define CVT_K_FACTOR 128 2032 /* Scaling factor weighting - default 20 */ 2033 #define CVT_J_FACTOR 20 2034 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2035 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2036 CVT_J_FACTOR) 2037 /* 12. Find ideal blanking duty cycle from formula */ 2038 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2039 hperiod / 1000; 2040 /* 13. Blanking time */ 2041 if (hblank_percentage < 20 * HV_FACTOR) 2042 hblank_percentage = 20 * HV_FACTOR; 2043 hblank = drm_mode->hdisplay * hblank_percentage / 2044 (100 * HV_FACTOR - hblank_percentage); 2045 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2046 /* 14. find the total pixels per line */ 2047 drm_mode->htotal = drm_mode->hdisplay + hblank; 2048 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2049 drm_mode->hsync_start = drm_mode->hsync_end - 2050 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2051 drm_mode->hsync_start += CVT_H_GRANULARITY - 2052 drm_mode->hsync_start % CVT_H_GRANULARITY; 2053 /* fill the Vsync values */ 2054 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2055 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2056 } else { 2057 /* Reduced blanking */ 2058 /* Minimum vertical blanking interval time - default 460 */ 2059 #define CVT_RB_MIN_VBLANK 460 2060 /* Fixed number of clocks for horizontal sync */ 2061 #define CVT_RB_H_SYNC 32 2062 /* Fixed number of clocks for horizontal blanking */ 2063 #define CVT_RB_H_BLANK 160 2064 /* Fixed number of lines for vertical front porch - default 3*/ 2065 #define CVT_RB_VFPORCH 3 2066 int vbilines; 2067 int tmp1, tmp2; 2068 /* 8. Estimate Horizontal period. */ 2069 tmp1 = HV_FACTOR * 1000000 - 2070 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2071 tmp2 = vdisplay_rnd + 2 * vmargin; 2072 hperiod = tmp1 / (tmp2 * vfieldrate); 2073 /* 9. Find number of lines in vertical blanking */ 2074 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2075 /* 10. Check if vertical blanking is sufficient */ 2076 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2077 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2078 /* 11. Find total number of lines in vertical field */ 2079 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2080 /* 12. Find total number of pixels in a line */ 2081 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2082 /* Fill in HSync values */ 2083 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2084 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2085 /* Fill in VSync values */ 2086 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2087 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2088 } 2089 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2090 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2091 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2092 /* 18/16. Find actual vertical frame frequency */ 2093 /* ignore - just set the mode flag for interlaced */ 2094 if (interlaced) { 2095 drm_mode->vtotal *= 2; 2096 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2097 } 2098 2099 if (reduced) 2100 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2101 DRM_MODE_FLAG_NVSYNC); 2102 else 2103 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2104 DRM_MODE_FLAG_NHSYNC); 2105 2106 return drm_mode; 2107 } 2108 2109 static int 2110 cea_db_payload_len(const u8 *db) 2111 { 2112 return db[0] & 0x1f; 2113 } 2114 2115 static int 2116 cea_db_extended_tag(const u8 *db) 2117 { 2118 return db[1]; 2119 } 2120 2121 static int 2122 cea_db_tag(const u8 *db) 2123 { 2124 return db[0] >> 5; 2125 } 2126 2127 #define for_each_cea_db(cea, i, start, end) \ 2128 for ((i) = (start); (i) < (end) && (i) + \ 2129 cea_db_payload_len(&(cea)[(i)]) < \ 2130 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2131 2132 static int 2133 cea_revision(const u8 *cea) 2134 { 2135 return cea[1]; 2136 } 2137 2138 static int 2139 cea_db_offsets(const u8 *cea, int *start, int *end) 2140 { 2141 /* Data block offset in CEA extension block */ 2142 *start = 4; 2143 *end = cea[2]; 2144 if (*end == 0) 2145 *end = 127; 2146 if (*end < 4 || *end > 127) 2147 return -ERANGE; 2148 2149 /* 2150 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2151 */ 2152 if (*end != 4) { 2153 int i; 2154 2155 i = *start; 2156 while (i < (*end) && 2157 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2158 i += cea_db_payload_len(&(cea)[i]) + 1; 2159 2160 if (cea_db_payload_len(&(cea)[i]) && 2161 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2162 (*end)++; 2163 } 2164 2165 return 0; 2166 } 2167 2168 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2169 { 2170 int hdmi_id; 2171 2172 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2173 return false; 2174 2175 if (cea_db_payload_len(db) < 5) 2176 return false; 2177 2178 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2179 2180 return hdmi_id == HDMI_IEEE_OUI; 2181 } 2182 2183 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2184 { 2185 unsigned int oui; 2186 2187 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2188 return false; 2189 2190 if (cea_db_payload_len(db) < 7) 2191 return false; 2192 2193 oui = db[3] << 16 | db[2] << 8 | db[1]; 2194 2195 return oui == HDMI_FORUM_IEEE_OUI; 2196 } 2197 2198 static bool cea_db_is_y420cmdb(const u8 *db) 2199 { 2200 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2201 return false; 2202 2203 if (!cea_db_payload_len(db)) 2204 return false; 2205 2206 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2207 return false; 2208 2209 return true; 2210 } 2211 2212 static bool cea_db_is_y420vdb(const u8 *db) 2213 { 2214 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2215 return false; 2216 2217 if (!cea_db_payload_len(db)) 2218 return false; 2219 2220 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2221 return false; 2222 2223 return true; 2224 } 2225 2226 static bool drm_valid_hdmi_vic(u8 vic) 2227 { 2228 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2229 } 2230 2231 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2232 const struct drm_display_mode *mode) 2233 { 2234 struct drm_display_mode *mode_buf = data->mode_buf; 2235 2236 mode_buf[(data->modes)++] = *mode; 2237 } 2238 2239 static bool drm_valid_cea_vic(u8 vic) 2240 { 2241 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2242 } 2243 2244 static u8 svd_to_vic(u8 svd) 2245 { 2246 /* 0-6 bit vic, 7th bit native mode indicator */ 2247 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2248 return svd & 127; 2249 2250 return svd; 2251 } 2252 2253 static struct drm_display_mode * 2254 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2255 u8 video_index) 2256 { 2257 struct drm_display_mode *newmode; 2258 u8 vic; 2259 2260 if (!video_db || video_index >= video_len) 2261 return NULL; 2262 2263 /* CEA modes are numbered 1..127 */ 2264 vic = svd_to_vic(video_db[video_index]); 2265 if (!drm_valid_cea_vic(vic)) 2266 return NULL; 2267 2268 newmode = drm_mode_create(); 2269 if (!newmode) 2270 return NULL; 2271 2272 *newmode = edid_cea_modes[vic]; 2273 newmode->vrefresh = 0; 2274 2275 return newmode; 2276 } 2277 2278 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2279 { 2280 unsigned long *p = map + BIT_WORD(start); 2281 const unsigned int size = start + len; 2282 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2283 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2284 2285 while (len - bits_to_set >= 0) { 2286 *p |= mask_to_set; 2287 len -= bits_to_set; 2288 bits_to_set = BITS_PER_LONG; 2289 mask_to_set = ~0UL; 2290 p++; 2291 } 2292 if (len) { 2293 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2294 *p |= mask_to_set; 2295 } 2296 } 2297 2298 static void 2299 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2300 { 2301 u8 vic = svd_to_vic(svd); 2302 2303 if (!drm_valid_cea_vic(vic)) 2304 return; 2305 2306 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2307 } 2308 2309 static int 2310 do_cea_modes(const u8 *db, u8 len, struct drm_hdmi_info *hdmi, 2311 struct hdmi_edid_data *data) 2312 { 2313 int i, modes = 0; 2314 2315 for (i = 0; i < len; i++) { 2316 struct drm_display_mode *mode; 2317 2318 mode = drm_display_mode_from_vic_index(db, len, i); 2319 if (mode) { 2320 /* 2321 * YCBCR420 capability block contains a bitmap which 2322 * gives the index of CEA modes from CEA VDB, which 2323 * can support YCBCR 420 sampling output also (apart 2324 * from RGB/YCBCR444 etc). 2325 * For example, if the bit 0 in bitmap is set, 2326 * first mode in VDB can support YCBCR420 output too. 2327 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2328 */ 2329 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2330 drm_add_cmdb_modes(db[i], hdmi); 2331 drm_add_hdmi_modes(data, mode); 2332 drm_mode_destroy(mode); 2333 modes++; 2334 } 2335 } 2336 2337 return modes; 2338 } 2339 2340 /* 2341 * do_y420vdb_modes - Parse YCBCR 420 only modes 2342 * @data: the structure that save parsed hdmi edid data 2343 * @svds: start of the data block of CEA YCBCR 420 VDB 2344 * @svds_len: length of the CEA YCBCR 420 VDB 2345 * @hdmi: runtime information about the connected HDMI sink 2346 * 2347 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2348 * which contains modes which can be supported in YCBCR 420 2349 * output format only. 2350 */ 2351 static 2352 int do_y420vdb_modes(const u8 *svds, u8 svds_len, struct drm_hdmi_info *hdmi, 2353 struct hdmi_edid_data *data) 2354 { 2355 int modes = 0, i; 2356 2357 for (i = 0; i < svds_len; i++) { 2358 u8 vic = svd_to_vic(svds[i]); 2359 2360 if (!drm_valid_cea_vic(vic)) 2361 continue; 2362 2363 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2364 drm_add_hdmi_modes(data, &edid_cea_modes[vic]); 2365 modes++; 2366 } 2367 2368 return modes; 2369 } 2370 2371 struct stereo_mandatory_mode { 2372 int width, height, vrefresh; 2373 unsigned int flags; 2374 }; 2375 2376 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2377 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2378 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2379 { 1920, 1080, 50, 2380 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2381 { 1920, 1080, 60, 2382 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2383 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2384 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2385 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2386 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2387 }; 2388 2389 static bool 2390 stereo_match_mandatory(const struct drm_display_mode *mode, 2391 const struct stereo_mandatory_mode *stereo_mode) 2392 { 2393 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2394 2395 return mode->hdisplay == stereo_mode->width && 2396 mode->vdisplay == stereo_mode->height && 2397 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2398 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2399 } 2400 2401 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2402 { 2403 const struct drm_display_mode *mode; 2404 int num = data->modes, modes = 0, i, k; 2405 2406 for (k = 0; k < num; k++) { 2407 mode = &data->mode_buf[k]; 2408 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2409 const struct stereo_mandatory_mode *mandatory; 2410 struct drm_display_mode *new_mode; 2411 2412 if (!stereo_match_mandatory(mode, 2413 &stereo_mandatory_modes[i])) 2414 continue; 2415 2416 mandatory = &stereo_mandatory_modes[i]; 2417 new_mode = drm_mode_create(); 2418 if (!new_mode) 2419 continue; 2420 2421 *new_mode = *mode; 2422 new_mode->flags |= mandatory->flags; 2423 drm_add_hdmi_modes(data, new_mode); 2424 drm_mode_destroy(new_mode); 2425 modes++; 2426 } 2427 } 2428 2429 return modes; 2430 } 2431 2432 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2433 const u8 *video_db, u8 video_len, u8 video_index) 2434 { 2435 struct drm_display_mode *newmode; 2436 int modes = 0; 2437 2438 if (structure & (1 << 0)) { 2439 newmode = drm_display_mode_from_vic_index(video_db, 2440 video_len, 2441 video_index); 2442 if (newmode) { 2443 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2444 drm_add_hdmi_modes(data, newmode); 2445 modes++; 2446 drm_mode_destroy(newmode); 2447 } 2448 } 2449 if (structure & (1 << 6)) { 2450 newmode = drm_display_mode_from_vic_index(video_db, 2451 video_len, 2452 video_index); 2453 if (newmode) { 2454 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2455 drm_add_hdmi_modes(data, newmode); 2456 modes++; 2457 drm_mode_destroy(newmode); 2458 } 2459 } 2460 if (structure & (1 << 8)) { 2461 newmode = drm_display_mode_from_vic_index(video_db, 2462 video_len, 2463 video_index); 2464 if (newmode) { 2465 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2466 drm_add_hdmi_modes(data, newmode); 2467 modes++; 2468 drm_mode_destroy(newmode); 2469 } 2470 } 2471 2472 return modes; 2473 } 2474 2475 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2476 { 2477 if (!drm_valid_hdmi_vic(vic)) { 2478 debug("Unknown HDMI VIC: %d\n", vic); 2479 return 0; 2480 } 2481 2482 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2483 2484 return 1; 2485 } 2486 2487 /* 2488 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2489 * @db: start of the CEA vendor specific block 2490 * @len: length of the CEA block payload, ie. one can access up to db[len] 2491 * 2492 * Parses the HDMI VSDB looking for modes to add to @data. This function 2493 * also adds the stereo 3d modes when applicable. 2494 */ 2495 static int 2496 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2497 struct hdmi_edid_data *data) 2498 { 2499 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2500 u8 vic_len, hdmi_3d_len = 0; 2501 u16 mask; 2502 u16 structure_all; 2503 2504 if (len < 8) 2505 goto out; 2506 2507 /* no HDMI_Video_Present */ 2508 if (!(db[8] & (1 << 5))) 2509 goto out; 2510 2511 /* Latency_Fields_Present */ 2512 if (db[8] & (1 << 7)) 2513 offset += 2; 2514 2515 /* I_Latency_Fields_Present */ 2516 if (db[8] & (1 << 6)) 2517 offset += 2; 2518 2519 /* the declared length is not long enough for the 2 first bytes 2520 * of additional video format capabilities 2521 */ 2522 if (len < (8 + offset + 2)) 2523 goto out; 2524 2525 /* 3D_Present */ 2526 offset++; 2527 if (db[8 + offset] & (1 << 7)) { 2528 modes += add_hdmi_mandatory_stereo_modes(data); 2529 2530 /* 3D_Multi_present */ 2531 multi_present = (db[8 + offset] & 0x60) >> 5; 2532 } 2533 2534 offset++; 2535 vic_len = db[8 + offset] >> 5; 2536 hdmi_3d_len = db[8 + offset] & 0x1f; 2537 2538 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2539 u8 vic; 2540 2541 vic = db[9 + offset + i]; 2542 modes += add_hdmi_mode(data, vic); 2543 } 2544 2545 offset += 1 + vic_len; 2546 2547 if (multi_present == 1) 2548 multi_len = 2; 2549 else if (multi_present == 2) 2550 multi_len = 4; 2551 else 2552 multi_len = 0; 2553 2554 if (len < (8 + offset + hdmi_3d_len - 1)) 2555 goto out; 2556 2557 if (hdmi_3d_len < multi_len) 2558 goto out; 2559 2560 if (multi_present == 1 || multi_present == 2) { 2561 /* 3D_Structure_ALL */ 2562 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2563 2564 /* check if 3D_MASK is present */ 2565 if (multi_present == 2) 2566 mask = (db[10 + offset] << 8) | db[11 + offset]; 2567 else 2568 mask = 0xffff; 2569 2570 for (i = 0; i < 16; i++) { 2571 if (mask & (1 << i)) 2572 modes += add_3d_struct_modes(data, 2573 structure_all, 2574 video_db, 2575 video_len, i); 2576 } 2577 } 2578 2579 offset += multi_len; 2580 2581 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2582 int vic_index; 2583 struct drm_display_mode *newmode = NULL; 2584 unsigned int newflag = 0; 2585 bool detail_present; 2586 2587 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2588 2589 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2590 break; 2591 2592 /* 2D_VIC_order_X */ 2593 vic_index = db[8 + offset + i] >> 4; 2594 2595 /* 3D_Structure_X */ 2596 switch (db[8 + offset + i] & 0x0f) { 2597 case 0: 2598 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2599 break; 2600 case 6: 2601 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2602 break; 2603 case 8: 2604 /* 3D_Detail_X */ 2605 if ((db[9 + offset + i] >> 4) == 1) 2606 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2607 break; 2608 } 2609 2610 if (newflag != 0) { 2611 newmode = drm_display_mode_from_vic_index( 2612 video_db, 2613 video_len, 2614 vic_index); 2615 2616 if (newmode) { 2617 newmode->flags |= newflag; 2618 drm_add_hdmi_modes(data, newmode); 2619 modes++; 2620 drm_mode_destroy(newmode); 2621 } 2622 } 2623 2624 if (detail_present) 2625 i++; 2626 } 2627 2628 out: 2629 return modes; 2630 } 2631 2632 /** 2633 * edid_get_quirks - return quirk flags for a given EDID 2634 * @edid: EDID to process 2635 * 2636 * This tells subsequent routines what fixes they need to apply. 2637 */ 2638 static u32 edid_get_quirks(struct edid *edid) 2639 { 2640 struct edid_quirk *quirk; 2641 int i; 2642 2643 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2644 quirk = &edid_quirk_list[i]; 2645 2646 if (edid_vendor(edid, quirk->vendor) && 2647 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2648 return quirk->quirks; 2649 } 2650 2651 return 0; 2652 } 2653 2654 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 2655 const u8 *db) 2656 { 2657 struct drm_display_info *info = &data->display_info; 2658 struct drm_hdmi_info *hdmi = &info->hdmi; 2659 u8 map_len = cea_db_payload_len(db) - 1; 2660 u8 count; 2661 u64 map = 0; 2662 2663 if (map_len == 0) { 2664 /* All CEA modes support ycbcr420 sampling also.*/ 2665 hdmi->y420_cmdb_map = U64_MAX; 2666 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2667 return; 2668 } 2669 2670 /* 2671 * This map indicates which of the existing CEA block modes 2672 * from VDB can support YCBCR420 output too. So if bit=0 is 2673 * set, first mode from VDB can support YCBCR420 output too. 2674 * We will parse and keep this map, before parsing VDB itself 2675 * to avoid going through the same block again and again. 2676 * 2677 * Spec is not clear about max possible size of this block. 2678 * Clamping max bitmap block size at 8 bytes. Every byte can 2679 * address 8 CEA modes, in this way this map can address 2680 * 8*8 = first 64 SVDs. 2681 */ 2682 if (map_len > 8) 2683 map_len = 8; 2684 2685 for (count = 0; count < map_len; count++) 2686 map |= (u64)db[2 + count] << (8 * count); 2687 2688 if (map) 2689 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2690 2691 hdmi->y420_cmdb_map = map; 2692 } 2693 2694 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 2695 const u8 *db) 2696 { 2697 u8 dc_mask; 2698 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2699 2700 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 2701 hdmi->y420_dc_modes |= dc_mask; 2702 } 2703 2704 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 2705 const u8 *hf_vsdb) 2706 { 2707 struct drm_display_info *display = &data->display_info; 2708 struct drm_hdmi_info *hdmi = &display->hdmi; 2709 2710 if (hf_vsdb[6] & 0x80) { 2711 hdmi->scdc.supported = true; 2712 if (hf_vsdb[6] & 0x40) 2713 hdmi->scdc.read_request = true; 2714 } 2715 2716 /* 2717 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 2718 * And as per the spec, three factors confirm this: 2719 * * Availability of a HF-VSDB block in EDID (check) 2720 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 2721 * * SCDC support available (let's check) 2722 * Lets check it out. 2723 */ 2724 2725 if (hf_vsdb[5]) { 2726 /* max clock is 5000 KHz times block value */ 2727 u32 max_tmds_clock = hf_vsdb[5] * 5000; 2728 struct drm_scdc *scdc = &hdmi->scdc; 2729 2730 if (max_tmds_clock > 340000) { 2731 display->max_tmds_clock = max_tmds_clock; 2732 debug("HF-VSDB: max TMDS clock %d kHz\n", 2733 display->max_tmds_clock); 2734 } 2735 2736 if (scdc->supported) { 2737 scdc->scrambling.supported = true; 2738 2739 /* Few sinks support scrambling for cloks < 340M */ 2740 if ((hf_vsdb[6] & 0x8)) 2741 scdc->scrambling.low_rates = true; 2742 } 2743 } 2744 2745 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 2746 } 2747 2748 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 2749 const u8 *hdmi) 2750 { 2751 struct drm_display_info *info = &data->display_info; 2752 unsigned int dc_bpc = 0; 2753 2754 /* HDMI supports at least 8 bpc */ 2755 info->bpc = 8; 2756 2757 if (cea_db_payload_len(hdmi) < 6) 2758 return; 2759 2760 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 2761 dc_bpc = 10; 2762 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 2763 debug("HDMI sink does deep color 30.\n"); 2764 } 2765 2766 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 2767 dc_bpc = 12; 2768 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 2769 debug("HDMI sink does deep color 36.\n"); 2770 } 2771 2772 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 2773 dc_bpc = 16; 2774 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 2775 debug("HDMI sink does deep color 48.\n"); 2776 } 2777 2778 if (dc_bpc == 0) { 2779 debug("No deep color support on this HDMI sink.\n"); 2780 return; 2781 } 2782 2783 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 2784 info->bpc = dc_bpc; 2785 2786 /* YCRCB444 is optional according to spec. */ 2787 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 2788 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 2789 debug("HDMI sink does YCRCB444 in deep color.\n"); 2790 } 2791 2792 /* 2793 * Spec says that if any deep color mode is supported at all, 2794 * then deep color 36 bit must be supported. 2795 */ 2796 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 2797 debug("HDMI sink should do DC_36, but does not!\n"); 2798 } 2799 2800 /* 2801 * Search EDID for CEA extension block. 2802 */ 2803 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2804 { 2805 u8 *edid_ext = NULL; 2806 int i; 2807 2808 /* No EDID or EDID extensions */ 2809 if (!edid || !edid->extensions) 2810 return NULL; 2811 2812 /* Find CEA extension */ 2813 for (i = 0; i < edid->extensions; i++) { 2814 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 2815 if (edid_ext[0] == ext_id) 2816 break; 2817 } 2818 2819 if (i == edid->extensions) 2820 return NULL; 2821 2822 return edid_ext; 2823 } 2824 2825 static u8 *drm_find_cea_extension(struct edid *edid) 2826 { 2827 return drm_find_edid_extension(edid, 0x02); 2828 } 2829 2830 #define AUDIO_BLOCK 0x01 2831 #define VIDEO_BLOCK 0x02 2832 #define VENDOR_BLOCK 0x03 2833 #define SPEAKER_BLOCK 0x04 2834 #define EDID_BASIC_AUDIO BIT(6) 2835 2836 /** 2837 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 2838 * @edid: monitor EDID information 2839 * 2840 * Parse the CEA extension according to CEA-861-B. 2841 * 2842 * Return: True if the monitor is HDMI, false if not or unknown. 2843 */ 2844 bool drm_detect_hdmi_monitor(struct edid *edid) 2845 { 2846 u8 *edid_ext; 2847 int i; 2848 int start_offset, end_offset; 2849 2850 edid_ext = drm_find_cea_extension(edid); 2851 if (!edid_ext) 2852 return false; 2853 2854 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2855 return false; 2856 2857 /* 2858 * Because HDMI identifier is in Vendor Specific Block, 2859 * search it from all data blocks of CEA extension. 2860 */ 2861 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2862 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 2863 return true; 2864 } 2865 2866 return false; 2867 } 2868 2869 /** 2870 * drm_detect_monitor_audio - check monitor audio capability 2871 * @edid: EDID block to scan 2872 * 2873 * Monitor should have CEA extension block. 2874 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 2875 * audio' only. If there is any audio extension block and supported 2876 * audio format, assume at least 'basic audio' support, even if 'basic 2877 * audio' is not defined in EDID. 2878 * 2879 * Return: True if the monitor supports audio, false otherwise. 2880 */ 2881 bool drm_detect_monitor_audio(struct edid *edid) 2882 { 2883 u8 *edid_ext; 2884 int i, j; 2885 bool has_audio = false; 2886 int start_offset, end_offset; 2887 2888 edid_ext = drm_find_cea_extension(edid); 2889 if (!edid_ext) 2890 goto end; 2891 2892 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 2893 2894 if (has_audio) { 2895 printf("Monitor has basic audio support\n"); 2896 goto end; 2897 } 2898 2899 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2900 goto end; 2901 2902 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2903 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 2904 has_audio = true; 2905 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 2906 j += 3) 2907 debug("CEA audio format %d\n", 2908 (edid_ext[i + j] >> 3) & 0xf); 2909 goto end; 2910 } 2911 } 2912 end: 2913 return has_audio; 2914 } 2915 2916 static void 2917 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 2918 { 2919 struct drm_display_info *info = &data->display_info; 2920 u8 len = cea_db_payload_len(db); 2921 2922 if (len >= 6) 2923 info->dvi_dual = db[6] & 1; 2924 if (len >= 7) 2925 info->max_tmds_clock = db[7] * 5000; 2926 2927 drm_parse_hdmi_deep_color_info(data, db); 2928 } 2929 2930 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 2931 struct edid *edid) 2932 { 2933 struct drm_display_info *info = &data->display_info; 2934 const u8 *edid_ext; 2935 int i, start, end; 2936 2937 edid_ext = drm_find_cea_extension(edid); 2938 if (!edid_ext) 2939 return; 2940 2941 info->cea_rev = edid_ext[1]; 2942 2943 /* The existence of a CEA block should imply RGB support */ 2944 info->color_formats = DRM_COLOR_FORMAT_RGB444; 2945 if (edid_ext[3] & EDID_CEA_YCRCB444) 2946 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 2947 if (edid_ext[3] & EDID_CEA_YCRCB422) 2948 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 2949 2950 if (cea_db_offsets(edid_ext, &start, &end)) 2951 return; 2952 2953 for_each_cea_db(edid_ext, i, start, end) { 2954 const u8 *db = &edid_ext[i]; 2955 2956 if (cea_db_is_hdmi_vsdb(db)) 2957 drm_parse_hdmi_vsdb_video(data, db); 2958 if (cea_db_is_hdmi_forum_vsdb(db)) 2959 drm_parse_hdmi_forum_vsdb(data, db); 2960 if (cea_db_is_y420cmdb(db)) 2961 drm_parse_y420cmdb_bitmap(data, db); 2962 } 2963 } 2964 2965 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 2966 { 2967 struct drm_display_info *info = &data->display_info; 2968 2969 info->width_mm = edid->width_cm * 10; 2970 info->height_mm = edid->height_cm * 10; 2971 2972 /* driver figures it out in this case */ 2973 info->bpc = 0; 2974 info->color_formats = 0; 2975 info->cea_rev = 0; 2976 info->max_tmds_clock = 0; 2977 info->dvi_dual = false; 2978 info->edid_hdmi_dc_modes = 0; 2979 2980 memset(&info->hdmi, 0, sizeof(info->hdmi)); 2981 2982 if (edid->revision < 3) 2983 return; 2984 2985 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 2986 return; 2987 2988 drm_parse_cea_ext(data, edid); 2989 2990 /* 2991 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 2992 * 2993 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 2994 * tells us to assume 8 bpc color depth if the EDID doesn't have 2995 * extensions which tell otherwise. 2996 */ 2997 if ((info->bpc == 0) && (edid->revision < 4) && 2998 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 2999 info->bpc = 8; 3000 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3001 } 3002 3003 /* Only defined for 1.4 with digital displays */ 3004 if (edid->revision < 4) 3005 return; 3006 3007 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3008 case DRM_EDID_DIGITAL_DEPTH_6: 3009 info->bpc = 6; 3010 break; 3011 case DRM_EDID_DIGITAL_DEPTH_8: 3012 info->bpc = 8; 3013 break; 3014 case DRM_EDID_DIGITAL_DEPTH_10: 3015 info->bpc = 10; 3016 break; 3017 case DRM_EDID_DIGITAL_DEPTH_12: 3018 info->bpc = 12; 3019 break; 3020 case DRM_EDID_DIGITAL_DEPTH_14: 3021 info->bpc = 14; 3022 break; 3023 case DRM_EDID_DIGITAL_DEPTH_16: 3024 info->bpc = 16; 3025 break; 3026 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3027 default: 3028 info->bpc = 0; 3029 break; 3030 } 3031 3032 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3033 info->bpc); 3034 3035 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3036 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3037 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3038 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3039 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3040 } 3041 3042 static 3043 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3044 { 3045 const u8 *cea = drm_find_cea_extension(edid); 3046 const u8 *db, *hdmi = NULL, *video = NULL; 3047 u8 dbl, hdmi_len, video_len = 0; 3048 int modes = 0; 3049 3050 if (cea && cea_revision(cea) >= 3) { 3051 int i, start, end; 3052 3053 if (cea_db_offsets(cea, &start, &end)) 3054 return 0; 3055 3056 for_each_cea_db(cea, i, start, end) { 3057 db = &cea[i]; 3058 dbl = cea_db_payload_len(db); 3059 3060 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3061 video = db + 1; 3062 video_len = dbl; 3063 modes += do_cea_modes(video, dbl, 3064 &data->hdmi_info, data); 3065 } else if (cea_db_is_hdmi_vsdb(db)) { 3066 hdmi = db; 3067 hdmi_len = dbl; 3068 } else if (cea_db_is_y420vdb(db)) { 3069 const u8 *vdb420 = &db[2]; 3070 3071 /* Add 4:2:0(only) modes present in EDID */ 3072 modes += do_y420vdb_modes(vdb420, dbl - 1, 3073 &data->hdmi_info, 3074 data); 3075 } 3076 } 3077 } 3078 3079 /* 3080 * We parse the HDMI VSDB after having added the cea modes as we will 3081 * be patching their flags when the sink supports stereo 3D. 3082 */ 3083 if (hdmi) 3084 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3085 video_len, data); 3086 3087 return modes; 3088 } 3089 3090 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3091 3092 static 3093 void cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3094 { 3095 int i, n = 0; 3096 u8 d = ext[0x02]; 3097 u8 *det_base = ext + d; 3098 3099 n = (127 - d) / 18; 3100 for (i = 0; i < n; i++) 3101 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3102 } 3103 3104 static 3105 void vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3106 { 3107 unsigned int i, n = min((int)ext[0x02], 6); 3108 u8 *det_base = ext + 5; 3109 3110 if (ext[0x01] != 1) 3111 return; /* unknown version */ 3112 3113 for (i = 0; i < n; i++) 3114 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3115 } 3116 3117 static 3118 void drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3119 { 3120 int i; 3121 struct edid *edid = (struct edid *)raw_edid; 3122 3123 if (!edid) 3124 return; 3125 3126 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3127 cb(&edid->detailed_timings[i], closure); 3128 3129 for (i = 1; i <= raw_edid[0x7e]; i++) { 3130 u8 *ext = raw_edid + (i * EDID_SIZE); 3131 3132 switch (*ext) { 3133 case CEA_EXT: 3134 cea_for_each_detailed_block(ext, cb, closure); 3135 break; 3136 case VTB_EXT: 3137 vtb_for_each_detailed_block(ext, cb, closure); 3138 break; 3139 default: 3140 break; 3141 } 3142 } 3143 } 3144 3145 /* 3146 * EDID is delightfully ambiguous about how interlaced modes are to be 3147 * encoded. Our internal representation is of frame height, but some 3148 * HDTV detailed timings are encoded as field height. 3149 * 3150 * The format list here is from CEA, in frame size. Technically we 3151 * should be checking refresh rate too. Whatever. 3152 */ 3153 static void 3154 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3155 struct detailed_pixel_timing *pt) 3156 { 3157 int i; 3158 3159 static const struct { 3160 int w, h; 3161 } cea_interlaced[] = { 3162 { 1920, 1080 }, 3163 { 720, 480 }, 3164 { 1440, 480 }, 3165 { 2880, 480 }, 3166 { 720, 576 }, 3167 { 1440, 576 }, 3168 { 2880, 576 }, 3169 }; 3170 3171 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3172 return; 3173 3174 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3175 if ((mode->hdisplay == cea_interlaced[i].w) && 3176 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3177 mode->vdisplay *= 2; 3178 mode->vsync_start *= 2; 3179 mode->vsync_end *= 2; 3180 mode->vtotal *= 2; 3181 mode->vtotal |= 1; 3182 } 3183 } 3184 3185 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3186 } 3187 3188 /** 3189 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3190 * @edid: EDID block 3191 * @timing: EDID detailed timing info 3192 * @quirks: quirks to apply 3193 * 3194 * An EDID detailed timing block contains enough info for us to create and 3195 * return a new struct drm_display_mode. 3196 */ 3197 static 3198 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3199 struct detailed_timing *timing, 3200 u32 quirks) 3201 { 3202 struct drm_display_mode *mode; 3203 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3204 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3205 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3206 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3207 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3208 unsigned hsync_offset = 3209 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3210 pt->hsync_offset_lo; 3211 unsigned hsync_pulse_width = 3212 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3213 pt->hsync_pulse_width_lo; 3214 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3215 2 | pt->vsync_offset_pulse_width_lo >> 4; 3216 unsigned vsync_pulse_width = 3217 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3218 (pt->vsync_offset_pulse_width_lo & 0xf); 3219 3220 /* ignore tiny modes */ 3221 if (hactive < 64 || vactive < 64) 3222 return NULL; 3223 3224 if (pt->misc & DRM_EDID_PT_STEREO) { 3225 debug("stereo mode not supported\n"); 3226 return NULL; 3227 } 3228 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3229 debug("composite sync not supported\n"); 3230 3231 /* it is incorrect if hsync/vsync width is zero */ 3232 if (!hsync_pulse_width || !vsync_pulse_width) { 3233 debug("Incorrect Detailed timing. " 3234 "Wrong Hsync/Vsync pulse width\n"); 3235 return NULL; 3236 } 3237 3238 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3239 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3240 if (!mode) 3241 return NULL; 3242 3243 goto set_refresh; 3244 } 3245 3246 mode = drm_mode_create(); 3247 if (!mode) 3248 return NULL; 3249 3250 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3251 timing->pixel_clock = cpu_to_le16(1088); 3252 3253 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3254 3255 mode->hdisplay = hactive; 3256 mode->hsync_start = mode->hdisplay + hsync_offset; 3257 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3258 mode->htotal = mode->hdisplay + hblank; 3259 3260 mode->vdisplay = vactive; 3261 mode->vsync_start = mode->vdisplay + vsync_offset; 3262 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3263 mode->vtotal = mode->vdisplay + vblank; 3264 3265 /* Some EDIDs have bogus h/vtotal values */ 3266 if (mode->hsync_end > mode->htotal) 3267 mode->htotal = mode->hsync_end + 1; 3268 if (mode->vsync_end > mode->vtotal) 3269 mode->vtotal = mode->vsync_end + 1; 3270 3271 drm_mode_do_interlace_quirk(mode, pt); 3272 3273 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3274 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3275 DRM_EDID_PT_VSYNC_POSITIVE; 3276 3277 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3278 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3279 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3280 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3281 3282 set_refresh: 3283 3284 mode->vrefresh = drm_get_vrefresh(mode); 3285 3286 return mode; 3287 } 3288 3289 /* 3290 * Calculate the alternate clock for the CEA mode 3291 * (60Hz vs. 59.94Hz etc.) 3292 */ 3293 static unsigned int 3294 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3295 { 3296 unsigned int clock = cea_mode->clock; 3297 3298 if (cea_mode->vrefresh % 6 != 0) 3299 return clock; 3300 3301 /* 3302 * edid_cea_modes contains the 59.94Hz 3303 * variant for 240 and 480 line modes, 3304 * and the 60Hz variant otherwise. 3305 */ 3306 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3307 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3308 else 3309 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3310 3311 return clock; 3312 } 3313 3314 /** 3315 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3316 * @mode1: first mode 3317 * @mode2: second mode 3318 * 3319 * Check to see if @mode1 and @mode2 are equivalent, but 3320 * don't check the pixel clocks nor the stereo layout. 3321 * 3322 * Returns: 3323 * True if the modes are equal, false otherwise. 3324 */ 3325 3326 static 3327 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3328 const struct drm_display_mode *mode2) 3329 { 3330 unsigned int flags_mask = 3331 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3332 3333 if (mode1->hdisplay == mode2->hdisplay && 3334 mode1->hsync_start == mode2->hsync_start && 3335 mode1->hsync_end == mode2->hsync_end && 3336 mode1->htotal == mode2->htotal && 3337 mode1->vdisplay == mode2->vdisplay && 3338 mode1->vsync_start == mode2->vsync_start && 3339 mode1->vsync_end == mode2->vsync_end && 3340 mode1->vtotal == mode2->vtotal && 3341 mode1->vscan == mode2->vscan && 3342 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3343 return true; 3344 3345 return false; 3346 } 3347 3348 /** 3349 * drm_mode_equal_no_clocks - test modes for equality 3350 * @mode1: first mode 3351 * @mode2: second mode 3352 * 3353 * Check to see if @mode1 and @mode2 are equivalent, but 3354 * don't check the pixel clocks. 3355 * 3356 * Returns: 3357 * True if the modes are equal, false otherwise. 3358 */ 3359 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3360 const struct drm_display_mode *mode2) 3361 { 3362 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3363 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3364 return false; 3365 3366 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3367 } 3368 3369 static 3370 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3371 unsigned int clock_tolerance) 3372 { 3373 u8 vic; 3374 3375 if (!to_match->clock) 3376 return 0; 3377 3378 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3379 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 3380 unsigned int clock1, clock2; 3381 3382 /* Check both 60Hz and 59.94Hz */ 3383 clock1 = cea_mode->clock; 3384 clock2 = cea_mode_alternate_clock(cea_mode); 3385 3386 if (abs(to_match->clock - clock1) > clock_tolerance && 3387 abs(to_match->clock - clock2) > clock_tolerance) 3388 continue; 3389 3390 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3391 return vic; 3392 } 3393 3394 return 0; 3395 } 3396 3397 static unsigned int 3398 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3399 { 3400 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3401 return hdmi_mode->clock; 3402 3403 return cea_mode_alternate_clock(hdmi_mode); 3404 } 3405 3406 static 3407 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3408 unsigned int clock_tolerance) 3409 { 3410 u8 vic; 3411 3412 if (!to_match->clock) 3413 return 0; 3414 3415 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3416 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3417 unsigned int clock1, clock2; 3418 3419 /* Make sure to also match alternate clocks */ 3420 clock1 = hdmi_mode->clock; 3421 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3422 3423 if (abs(to_match->clock - clock1) > clock_tolerance && 3424 abs(to_match->clock - clock2) > clock_tolerance) 3425 continue; 3426 3427 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3428 return vic; 3429 } 3430 3431 return 0; 3432 } 3433 3434 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3435 { 3436 const struct drm_display_mode *cea_mode; 3437 int clock1, clock2, clock; 3438 u8 vic; 3439 const char *type; 3440 3441 /* 3442 * allow 5kHz clock difference either way to account for 3443 * the 10kHz clock resolution limit of detailed timings. 3444 */ 3445 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3446 if (drm_valid_cea_vic(vic)) { 3447 type = "CEA"; 3448 cea_mode = &edid_cea_modes[vic]; 3449 clock1 = cea_mode->clock; 3450 clock2 = cea_mode_alternate_clock(cea_mode); 3451 } else { 3452 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3453 if (drm_valid_hdmi_vic(vic)) { 3454 type = "HDMI"; 3455 cea_mode = &edid_4k_modes[vic]; 3456 clock1 = cea_mode->clock; 3457 clock2 = hdmi_mode_alternate_clock(cea_mode); 3458 } else { 3459 return; 3460 } 3461 } 3462 3463 /* pick whichever is closest */ 3464 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3465 clock = clock1; 3466 else 3467 clock = clock2; 3468 3469 if (mode->clock == clock) 3470 return; 3471 3472 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3473 type, vic, mode->clock, clock); 3474 mode->clock = clock; 3475 } 3476 3477 static void 3478 do_detailed_mode(struct detailed_timing *timing, void *c) 3479 { 3480 struct detailed_mode_closure *closure = c; 3481 struct drm_display_mode *newmode; 3482 3483 if (timing->pixel_clock) { 3484 newmode = drm_mode_detailed( 3485 closure->edid, timing, 3486 closure->quirks); 3487 if (!newmode) 3488 return; 3489 3490 /* 3491 * Detailed modes are limited to 10kHz pixel clock resolution, 3492 * so fix up anything that looks like CEA/HDMI mode, 3493 * but the clock is just slightly off. 3494 */ 3495 fixup_detailed_cea_mode_clock(newmode); 3496 drm_add_hdmi_modes(closure->data, newmode); 3497 drm_mode_destroy(newmode); 3498 closure->modes++; 3499 } 3500 } 3501 3502 /* 3503 * add_detailed_modes - Add modes from detailed timings 3504 * @data: attached data 3505 * @edid: EDID block to scan 3506 * @quirks: quirks to apply 3507 */ 3508 static int 3509 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 3510 u32 quirks) 3511 { 3512 struct detailed_mode_closure closure = { 3513 .data = data, 3514 .edid = edid, 3515 .quirks = quirks, 3516 }; 3517 3518 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3519 3520 return closure.modes; 3521 } 3522 3523 static int drm_cvt_modes(struct hdmi_edid_data *data, 3524 struct detailed_timing *timing) 3525 { 3526 int i, j, modes = 0; 3527 struct drm_display_mode *newmode; 3528 struct cvt_timing *cvt; 3529 const int rates[] = { 60, 85, 75, 60, 50 }; 3530 const u8 empty[3] = { 0, 0, 0 }; 3531 3532 for (i = 0; i < 4; i++) { 3533 int uninitialized_var(width), height; 3534 3535 cvt = &timing->data.other_data.data.cvt[i]; 3536 3537 if (!memcmp(cvt->code, empty, 3)) 3538 continue; 3539 3540 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3541 switch (cvt->code[1] & 0x0c) { 3542 case 0x00: 3543 width = height * 4 / 3; 3544 break; 3545 case 0x04: 3546 width = height * 16 / 9; 3547 break; 3548 case 0x08: 3549 width = height * 16 / 10; 3550 break; 3551 case 0x0c: 3552 width = height * 15 / 9; 3553 break; 3554 } 3555 3556 for (j = 1; j < 5; j++) { 3557 if (cvt->code[2] & (1 << j)) { 3558 newmode = drm_cvt_mode(width, height, 3559 rates[j], j == 0, 3560 false, false); 3561 if (newmode) { 3562 drm_add_hdmi_modes(data, newmode); 3563 modes++; 3564 drm_mode_destroy(newmode); 3565 } 3566 } 3567 } 3568 } 3569 3570 return modes; 3571 } 3572 3573 static void 3574 do_cvt_mode(struct detailed_timing *timing, void *c) 3575 { 3576 struct detailed_mode_closure *closure = c; 3577 struct detailed_non_pixel *data = &timing->data.other_data; 3578 3579 if (data->type == EDID_DETAIL_CVT_3BYTE) 3580 closure->modes += drm_cvt_modes(closure->data, timing); 3581 } 3582 3583 static int 3584 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 3585 { 3586 struct detailed_mode_closure closure = { 3587 .data = data, 3588 .edid = edid, 3589 }; 3590 3591 if (version_greater(edid, 1, 2)) 3592 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3593 3594 /* XXX should also look for CVT codes in VTB blocks */ 3595 3596 return closure.modes; 3597 } 3598 3599 static void 3600 find_gtf2(struct detailed_timing *t, void *data) 3601 { 3602 u8 *r = (u8 *)t; 3603 3604 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 3605 *(u8 **)data = r; 3606 } 3607 3608 /* Secondary GTF curve kicks in above some break frequency */ 3609 static int 3610 drm_gtf2_hbreak(struct edid *edid) 3611 { 3612 u8 *r = NULL; 3613 3614 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3615 return r ? (r[12] * 2) : 0; 3616 } 3617 3618 static int 3619 drm_gtf2_2c(struct edid *edid) 3620 { 3621 u8 *r = NULL; 3622 3623 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3624 return r ? r[13] : 0; 3625 } 3626 3627 static int 3628 drm_gtf2_m(struct edid *edid) 3629 { 3630 u8 *r = NULL; 3631 3632 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3633 return r ? (r[15] << 8) + r[14] : 0; 3634 } 3635 3636 static int 3637 drm_gtf2_k(struct edid *edid) 3638 { 3639 u8 *r = NULL; 3640 3641 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3642 return r ? r[16] : 0; 3643 } 3644 3645 static int 3646 drm_gtf2_2j(struct edid *edid) 3647 { 3648 u8 *r = NULL; 3649 3650 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3651 return r ? r[17] : 0; 3652 } 3653 3654 /** 3655 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 3656 * @edid: EDID block to scan 3657 */ 3658 static int standard_timing_level(struct edid *edid) 3659 { 3660 if (edid->revision >= 2) { 3661 if (edid->revision >= 4 && 3662 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 3663 return LEVEL_CVT; 3664 if (drm_gtf2_hbreak(edid)) 3665 return LEVEL_GTF2; 3666 return LEVEL_GTF; 3667 } 3668 return LEVEL_DMT; 3669 } 3670 3671 /* 3672 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3673 * monitors fill with ascii space (0x20) instead. 3674 */ 3675 static int 3676 bad_std_timing(u8 a, u8 b) 3677 { 3678 return (a == 0x00 && b == 0x00) || 3679 (a == 0x01 && b == 0x01) || 3680 (a == 0x20 && b == 0x20); 3681 } 3682 3683 static void 3684 is_rb(struct detailed_timing *t, void *data) 3685 { 3686 u8 *r = (u8 *)t; 3687 3688 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 3689 if (r[15] & 0x10) 3690 *(bool *)data = true; 3691 } 3692 3693 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3694 static bool 3695 drm_monitor_supports_rb(struct edid *edid) 3696 { 3697 if (edid->revision >= 4) { 3698 bool ret = false; 3699 3700 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 3701 return ret; 3702 } 3703 3704 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3705 } 3706 3707 static bool 3708 mode_is_rb(const struct drm_display_mode *mode) 3709 { 3710 return (mode->htotal - mode->hdisplay == 160) && 3711 (mode->hsync_end - mode->hdisplay == 80) && 3712 (mode->hsync_end - mode->hsync_start == 32) && 3713 (mode->vsync_start - mode->vdisplay == 3); 3714 } 3715 3716 /* 3717 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3718 * @hsize: Mode width 3719 * @vsize: Mode height 3720 * @fresh: Mode refresh rate 3721 * @rb: Mode reduced-blanking-ness 3722 * 3723 * Walk the DMT mode list looking for a match for the given parameters. 3724 * 3725 * Return: A newly allocated copy of the mode, or NULL if not found. 3726 */ 3727 static struct drm_display_mode *drm_mode_find_dmt( 3728 int hsize, int vsize, int fresh, 3729 bool rb) 3730 { 3731 int i; 3732 struct drm_display_mode *newmode; 3733 3734 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3735 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3736 3737 if (hsize != ptr->hdisplay) 3738 continue; 3739 if (vsize != ptr->vdisplay) 3740 continue; 3741 if (fresh != drm_get_vrefresh(ptr)) 3742 continue; 3743 if (rb != mode_is_rb(ptr)) 3744 continue; 3745 3746 newmode = drm_mode_create(); 3747 *newmode = *ptr; 3748 return newmode; 3749 } 3750 3751 return NULL; 3752 } 3753 3754 static struct drm_display_mode * 3755 drm_gtf_mode_complex(int hdisplay, int vdisplay, 3756 int vrefresh, bool interlaced, int margins, 3757 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 3758 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 3759 #define GTF_MARGIN_PERCENTAGE 18 3760 /* 2) character cell horizontal granularity (pixels) - default 8 */ 3761 #define GTF_CELL_GRAN 8 3762 /* 3) Minimum vertical porch (lines) - default 3 */ 3763 #define GTF_MIN_V_PORCH 1 3764 /* width of vsync in lines */ 3765 #define V_SYNC_RQD 3 3766 /* width of hsync as % of total line */ 3767 #define H_SYNC_PERCENT 8 3768 /* min time of vsync + back porch (microsec) */ 3769 #define MIN_VSYNC_PLUS_BP 550 3770 /* C' and M' are part of the Blanking Duty Cycle computation */ 3771 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 3772 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 3773 struct drm_display_mode *drm_mode; 3774 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 3775 int top_margin, bottom_margin; 3776 int interlace; 3777 unsigned int hfreq_est; 3778 int vsync_plus_bp; 3779 unsigned int vtotal_lines; 3780 int left_margin, right_margin; 3781 unsigned int total_active_pixels, ideal_duty_cycle; 3782 unsigned int hblank, total_pixels, pixel_freq; 3783 int hsync, hfront_porch, vodd_front_porch_lines; 3784 unsigned int tmp1, tmp2; 3785 3786 drm_mode = drm_mode_create(); 3787 if (!drm_mode) 3788 return NULL; 3789 3790 /* 1. In order to give correct results, the number of horizontal 3791 * pixels requested is first processed to ensure that it is divisible 3792 * by the character size, by rounding it to the nearest character 3793 * cell boundary: 3794 */ 3795 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3796 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 3797 3798 /* 2. If interlace is requested, the number of vertical lines assumed 3799 * by the calculation must be halved, as the computation calculates 3800 * the number of vertical lines per field. 3801 */ 3802 if (interlaced) 3803 vdisplay_rnd = vdisplay / 2; 3804 else 3805 vdisplay_rnd = vdisplay; 3806 3807 /* 3. Find the frame rate required: */ 3808 if (interlaced) 3809 vfieldrate_rqd = vrefresh * 2; 3810 else 3811 vfieldrate_rqd = vrefresh; 3812 3813 /* 4. Find number of lines in Top margin: */ 3814 top_margin = 0; 3815 if (margins) 3816 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3817 1000; 3818 /* 5. Find number of lines in bottom margin: */ 3819 bottom_margin = top_margin; 3820 3821 /* 6. If interlace is required, then set variable interlace: */ 3822 if (interlaced) 3823 interlace = 1; 3824 else 3825 interlace = 0; 3826 3827 /* 7. Estimate the Horizontal frequency */ 3828 { 3829 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 3830 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 3831 2 + interlace; 3832 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 3833 } 3834 3835 /* 8. Find the number of lines in V sync + back porch */ 3836 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 3837 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 3838 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 3839 /* 9. Find the number of lines in V back porch alone: 3840 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 3841 */ 3842 /* 10. Find the total number of lines in Vertical field period: */ 3843 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 3844 vsync_plus_bp + GTF_MIN_V_PORCH; 3845 /* 11. Estimate the Vertical field frequency: 3846 * vfieldrate_est = hfreq_est / vtotal_lines; 3847 */ 3848 3849 /* 12. Find the actual horizontal period: 3850 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 3851 */ 3852 /* 13. Find the actual Vertical field frequency: 3853 * vfield_rate = hfreq_est / vtotal_lines; 3854 */ 3855 /* 14. Find the Vertical frame frequency: 3856 * if (interlaced) 3857 * vframe_rate = vfield_rate / 2; 3858 * else 3859 * vframe_rate = vfield_rate; 3860 */ 3861 /* 15. Find number of pixels in left margin: */ 3862 if (margins) 3863 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3864 1000; 3865 else 3866 left_margin = 0; 3867 3868 /* 16.Find number of pixels in right margin: */ 3869 right_margin = left_margin; 3870 /* 17.Find total number of active pixels in image and left and right */ 3871 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 3872 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 3873 ideal_duty_cycle = GTF_C_PRIME * 1000 - 3874 (GTF_M_PRIME * 1000000 / hfreq_est); 3875 /* 19.Find the number of pixels in the blanking time to the nearest 3876 * double character cell: 3877 */ 3878 hblank = total_active_pixels * ideal_duty_cycle / 3879 (100000 - ideal_duty_cycle); 3880 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 3881 hblank = hblank * 2 * GTF_CELL_GRAN; 3882 /* 20.Find total number of pixels: */ 3883 total_pixels = total_active_pixels + hblank; 3884 /* 21.Find pixel clock frequency: */ 3885 pixel_freq = total_pixels * hfreq_est / 1000; 3886 /* Stage 1 computations are now complete; I should really pass 3887 * the results to another function and do the Stage 2 computations, 3888 * but I only need a few more values so I'll just append the 3889 * computations here for now 3890 */ 3891 3892 /* 17. Find the number of pixels in the horizontal sync period: */ 3893 hsync = H_SYNC_PERCENT * total_pixels / 100; 3894 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3895 hsync = hsync * GTF_CELL_GRAN; 3896 /* 18. Find the number of pixels in horizontal front porch period */ 3897 hfront_porch = hblank / 2 - hsync; 3898 /* 36. Find the number of lines in the odd front porch period: */ 3899 vodd_front_porch_lines = GTF_MIN_V_PORCH; 3900 3901 /* finally, pack the results in the mode struct */ 3902 drm_mode->hdisplay = hdisplay_rnd; 3903 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 3904 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 3905 drm_mode->htotal = total_pixels; 3906 drm_mode->vdisplay = vdisplay_rnd; 3907 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 3908 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 3909 drm_mode->vtotal = vtotal_lines; 3910 3911 drm_mode->clock = pixel_freq; 3912 3913 if (interlaced) { 3914 drm_mode->vtotal *= 2; 3915 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 3916 } 3917 3918 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 3919 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 3920 else 3921 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 3922 3923 return drm_mode; 3924 } 3925 3926 /** 3927 * drm_gtf_mode - create the mode based on the GTF algorithm 3928 * @hdisplay: hdisplay size 3929 * @vdisplay: vdisplay size 3930 * @vrefresh: vrefresh rate. 3931 * @interlaced: whether to compute an interlaced mode 3932 * @margins: desired margin (borders) size 3933 * 3934 * return the mode based on GTF algorithm 3935 * 3936 * This function is to create the mode based on the GTF algorithm. 3937 * Generalized Timing Formula is derived from: 3938 * GTF Spreadsheet by Andy Morrish (1/5/97) 3939 * available at http://www.vesa.org 3940 * 3941 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 3942 * What I have done is to translate it by using integer calculation. 3943 * I also refer to the function of fb_get_mode in the file of 3944 * drivers/video/fbmon.c 3945 * 3946 * Standard GTF parameters: 3947 * M = 600 3948 * C = 40 3949 * K = 128 3950 * J = 20 3951 * 3952 * Returns: 3953 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 3954 * The display mode object is allocated with drm_mode_create(). Returns NULL 3955 * when no mode could be allocated. 3956 */ 3957 static struct drm_display_mode * 3958 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 3959 bool interlaced, int margins) 3960 { 3961 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 3962 interlaced, margins, 3963 600, 40 * 2, 128, 20 * 2); 3964 } 3965 3966 /** drm_mode_hsync - get the hsync of a mode 3967 * @mode: mode 3968 * 3969 * Returns: 3970 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 3971 * value first if it is not yet set. 3972 */ 3973 static int drm_mode_hsync(const struct drm_display_mode *mode) 3974 { 3975 unsigned int calc_val; 3976 3977 if (mode->htotal < 0) 3978 return 0; 3979 3980 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 3981 calc_val += 500; /* round to 1000Hz */ 3982 calc_val /= 1000; /* truncate to kHz */ 3983 3984 return calc_val; 3985 } 3986 3987 /** 3988 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 3989 * @data: the structure that save parsed hdmi edid data 3990 * @edid: EDID block to scan 3991 * @t: standard timing params 3992 * 3993 * Take the standard timing params (in this case width, aspect, and refresh) 3994 * and convert them into a real mode using CVT/GTF/DMT. 3995 */ 3996 static struct drm_display_mode * 3997 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 3998 struct std_timing *t) 3999 { 4000 struct drm_display_mode *mode = NULL; 4001 int i, hsize, vsize; 4002 int vrefresh_rate; 4003 int num = data->modes; 4004 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4005 >> EDID_TIMING_ASPECT_SHIFT; 4006 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4007 >> EDID_TIMING_VFREQ_SHIFT; 4008 int timing_level = standard_timing_level(edid); 4009 4010 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4011 return NULL; 4012 4013 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4014 hsize = t->hsize * 8 + 248; 4015 /* vrefresh_rate = vfreq + 60 */ 4016 vrefresh_rate = vfreq + 60; 4017 /* the vdisplay is calculated based on the aspect ratio */ 4018 if (aspect_ratio == 0) { 4019 if (edid->revision < 3) 4020 vsize = hsize; 4021 else 4022 vsize = (hsize * 10) / 16; 4023 } else if (aspect_ratio == 1) { 4024 vsize = (hsize * 3) / 4; 4025 } else if (aspect_ratio == 2) { 4026 vsize = (hsize * 4) / 5; 4027 } else { 4028 vsize = (hsize * 9) / 16; 4029 } 4030 4031 /* HDTV hack, part 1 */ 4032 if (vrefresh_rate == 60 && 4033 ((hsize == 1360 && vsize == 765) || 4034 (hsize == 1368 && vsize == 769))) { 4035 hsize = 1366; 4036 vsize = 768; 4037 } 4038 4039 /* 4040 * If we already has a mode for this size and refresh 4041 * rate (because it came from detailed or CVT info), use that 4042 * instead. This way we don't have to guess at interlace or 4043 * reduced blanking. 4044 */ 4045 for (i = 0; i < num; i++) 4046 if (data->mode_buf[i].hdisplay == hsize && 4047 data->mode_buf[i].hdisplay && 4048 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4049 return NULL; 4050 4051 /* HDTV hack, part 2 */ 4052 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4053 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4054 false); 4055 mode->hdisplay = 1366; 4056 mode->hsync_start = mode->hsync_start - 1; 4057 mode->hsync_end = mode->hsync_end - 1; 4058 return mode; 4059 } 4060 4061 /* check whether it can be found in default mode table */ 4062 if (drm_monitor_supports_rb(edid)) { 4063 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4064 true); 4065 if (mode) 4066 return mode; 4067 } 4068 4069 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4070 if (mode) 4071 return mode; 4072 4073 /* okay, generate it */ 4074 switch (timing_level) { 4075 case LEVEL_DMT: 4076 break; 4077 case LEVEL_GTF: 4078 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4079 break; 4080 case LEVEL_GTF2: 4081 /* 4082 * This is potentially wrong if there's ever a monitor with 4083 * more than one ranges section, each claiming a different 4084 * secondary GTF curve. Please don't do that. 4085 */ 4086 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4087 if (!mode) 4088 return NULL; 4089 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4090 drm_mode_destroy(mode); 4091 mode = drm_gtf_mode_complex(hsize, vsize, 4092 vrefresh_rate, 0, 0, 4093 drm_gtf2_m(edid), 4094 drm_gtf2_2c(edid), 4095 drm_gtf2_k(edid), 4096 drm_gtf2_2j(edid)); 4097 } 4098 break; 4099 case LEVEL_CVT: 4100 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4101 false); 4102 break; 4103 } 4104 4105 return mode; 4106 } 4107 4108 static void 4109 do_standard_modes(struct detailed_timing *timing, void *c) 4110 { 4111 struct detailed_mode_closure *closure = c; 4112 struct detailed_non_pixel *data = &timing->data.other_data; 4113 struct edid *edid = closure->edid; 4114 4115 if (data->type == EDID_DETAIL_STD_MODES) { 4116 int i; 4117 4118 for (i = 0; i < 6; i++) { 4119 struct std_timing *std; 4120 struct drm_display_mode *newmode; 4121 4122 std = &data->data.timings[i]; 4123 newmode = drm_mode_std(closure->data, edid, std); 4124 if (newmode) { 4125 drm_add_hdmi_modes(closure->data, newmode); 4126 closure->modes++; 4127 drm_mode_destroy(newmode); 4128 } 4129 } 4130 } 4131 } 4132 4133 /** 4134 * add_standard_modes - get std. modes from EDID and add them 4135 * @data: data to add mode(s) to 4136 * @edid: EDID block to scan 4137 * 4138 * Standard modes can be calculated using the appropriate standard (DMT, 4139 * GTF or CVT. Grab them from @edid and add them to the list. 4140 */ 4141 static int 4142 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4143 { 4144 int i, modes = 0; 4145 struct detailed_mode_closure closure = { 4146 .data = data, 4147 .edid = edid, 4148 }; 4149 4150 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4151 struct drm_display_mode *newmode; 4152 4153 newmode = drm_mode_std(data, edid, 4154 &edid->standard_timings[i]); 4155 if (newmode) { 4156 drm_add_hdmi_modes(data, newmode); 4157 modes++; 4158 drm_mode_destroy(newmode); 4159 } 4160 } 4161 4162 if (version_greater(edid, 1, 0)) 4163 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4164 &closure); 4165 4166 /* XXX should also look for standard codes in VTB blocks */ 4167 4168 return modes + closure.modes; 4169 } 4170 4171 static int 4172 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4173 { 4174 int i, j, m, modes = 0; 4175 struct drm_display_mode *mode; 4176 u8 *est = ((u8 *)timing) + 6; 4177 4178 for (i = 0; i < 6; i++) { 4179 for (j = 7; j >= 0; j--) { 4180 m = (i * 8) + (7 - j); 4181 if (m >= ARRAY_SIZE(est3_modes)) 4182 break; 4183 if (est[i] & (1 << j)) { 4184 mode = drm_mode_find_dmt( 4185 est3_modes[m].w, 4186 est3_modes[m].h, 4187 est3_modes[m].r, 4188 est3_modes[m].rb); 4189 if (mode) { 4190 drm_add_hdmi_modes(data, mode); 4191 modes++; 4192 drm_mode_destroy(mode); 4193 } 4194 } 4195 } 4196 } 4197 4198 return modes; 4199 } 4200 4201 static void 4202 do_established_modes(struct detailed_timing *timing, void *c) 4203 { 4204 struct detailed_mode_closure *closure = c; 4205 struct detailed_non_pixel *data = &timing->data.other_data; 4206 4207 if (data->type == EDID_DETAIL_EST_TIMINGS) 4208 closure->modes += drm_est3_modes(closure->data, timing); 4209 } 4210 4211 /** 4212 * add_established_modes - get est. modes from EDID and add them 4213 * @data: data to add mode(s) to 4214 * @edid: EDID block to scan 4215 * 4216 * Each EDID block contains a bitmap of the supported "established modes" list 4217 * (defined above). Tease them out and add them to the modes list. 4218 */ 4219 static int 4220 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4221 { 4222 unsigned long est_bits = edid->established_timings.t1 | 4223 (edid->established_timings.t2 << 8) | 4224 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4225 int i, modes = 0; 4226 struct detailed_mode_closure closure = { 4227 .data = data, 4228 .edid = edid, 4229 }; 4230 4231 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4232 if (est_bits & (1 << i)) { 4233 struct drm_display_mode *newmode = drm_mode_create(); 4234 *newmode = edid_est_modes[i]; 4235 if (newmode) { 4236 drm_add_hdmi_modes(data, newmode); 4237 modes++; 4238 drm_mode_destroy(newmode); 4239 } 4240 } 4241 } 4242 4243 if (version_greater(edid, 1, 0)) 4244 drm_for_each_detailed_block((u8 *)edid, 4245 do_established_modes, &closure); 4246 4247 return modes + closure.modes; 4248 } 4249 4250 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4251 { 4252 u8 vic; 4253 4254 if (!to_match->clock) 4255 return 0; 4256 4257 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4258 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4259 unsigned int clock1, clock2; 4260 4261 /* Make sure to also match alternate clocks */ 4262 clock1 = hdmi_mode->clock; 4263 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4264 4265 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4266 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4267 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4268 return vic; 4269 } 4270 return 0; 4271 } 4272 4273 static int 4274 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4275 { 4276 struct drm_display_mode *mode; 4277 int i, num, modes = 0; 4278 4279 /* Don't add CEA modes if the CEA extension block is missing */ 4280 if (!drm_find_cea_extension(edid)) 4281 return 0; 4282 4283 /* 4284 * Go through all probed modes and create a new mode 4285 * with the alternate clock for certain CEA modes. 4286 */ 4287 num = data->modes; 4288 4289 for (i = 0; i < num; i++) { 4290 const struct drm_display_mode *cea_mode = NULL; 4291 struct drm_display_mode *newmode; 4292 u8 vic; 4293 unsigned int clock1, clock2; 4294 4295 mode = &data->mode_buf[i]; 4296 vic = drm_match_cea_mode(mode); 4297 4298 if (drm_valid_cea_vic(vic)) { 4299 cea_mode = &edid_cea_modes[vic]; 4300 clock2 = cea_mode_alternate_clock(cea_mode); 4301 } else { 4302 vic = drm_match_hdmi_mode(mode); 4303 if (drm_valid_hdmi_vic(vic)) { 4304 cea_mode = &edid_4k_modes[vic]; 4305 clock2 = hdmi_mode_alternate_clock(cea_mode); 4306 } 4307 } 4308 4309 if (!cea_mode) 4310 continue; 4311 4312 clock1 = cea_mode->clock; 4313 4314 if (clock1 == clock2) 4315 continue; 4316 4317 if (mode->clock != clock1 && mode->clock != clock2) 4318 continue; 4319 4320 newmode = drm_mode_create(); 4321 *newmode = *cea_mode; 4322 if (!newmode) 4323 continue; 4324 4325 /* Carry over the stereo flags */ 4326 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4327 4328 /* 4329 * The current mode could be either variant. Make 4330 * sure to pick the "other" clock for the new mode. 4331 */ 4332 if (mode->clock != clock1) 4333 newmode->clock = clock1; 4334 else 4335 newmode->clock = clock2; 4336 4337 drm_add_hdmi_modes(data, newmode); 4338 modes++; 4339 drm_mode_destroy(newmode); 4340 } 4341 4342 return modes; 4343 } 4344 4345 static u8 *drm_find_displayid_extension(struct edid *edid) 4346 { 4347 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4348 } 4349 4350 static int validate_displayid(u8 *displayid, int length, int idx) 4351 { 4352 int i; 4353 u8 csum = 0; 4354 struct displayid_hdr *base; 4355 4356 base = (struct displayid_hdr *)&displayid[idx]; 4357 4358 debug("base revision 0x%x, length %d, %d %d\n", 4359 base->rev, base->bytes, base->prod_id, base->ext_count); 4360 4361 if (base->bytes + 5 > length - idx) 4362 return -EINVAL; 4363 for (i = idx; i <= base->bytes + 5; i++) 4364 csum += displayid[i]; 4365 if (csum) { 4366 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4367 return -EINVAL; 4368 } 4369 return 0; 4370 } 4371 4372 static struct 4373 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4374 *timings) 4375 { 4376 struct drm_display_mode *mode; 4377 unsigned pixel_clock = (timings->pixel_clock[0] | 4378 (timings->pixel_clock[1] << 8) | 4379 (timings->pixel_clock[2] << 16)); 4380 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4381 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4382 unsigned hsync = (timings->hsync[0] | 4383 (timings->hsync[1] & 0x7f) << 8) + 1; 4384 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4385 unsigned vactive = (timings->vactive[0] | 4386 timings->vactive[1] << 8) + 1; 4387 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4388 unsigned vsync = (timings->vsync[0] | 4389 (timings->vsync[1] & 0x7f) << 8) + 1; 4390 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4391 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4392 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4393 4394 mode = drm_mode_create(); 4395 if (!mode) 4396 return NULL; 4397 4398 mode->clock = pixel_clock * 10; 4399 mode->hdisplay = hactive; 4400 mode->hsync_start = mode->hdisplay + hsync; 4401 mode->hsync_end = mode->hsync_start + hsync_width; 4402 mode->htotal = mode->hdisplay + hblank; 4403 4404 mode->vdisplay = vactive; 4405 mode->vsync_start = mode->vdisplay + vsync; 4406 mode->vsync_end = mode->vsync_start + vsync_width; 4407 mode->vtotal = mode->vdisplay + vblank; 4408 4409 mode->flags = 0; 4410 mode->flags |= 4411 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4412 mode->flags |= 4413 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4414 4415 if (timings->flags & 0x80) 4416 mode->vrefresh = drm_get_vrefresh(mode); 4417 4418 return mode; 4419 } 4420 4421 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 4422 struct displayid_block *block) 4423 { 4424 struct displayid_detailed_timing_block *det; 4425 int i; 4426 int num_timings; 4427 struct drm_display_mode *newmode; 4428 int num_modes = 0; 4429 4430 det = (struct displayid_detailed_timing_block *)block; 4431 /* blocks must be multiple of 20 bytes length */ 4432 if (block->num_bytes % 20) 4433 return 0; 4434 4435 num_timings = block->num_bytes / 20; 4436 for (i = 0; i < num_timings; i++) { 4437 struct displayid_detailed_timings_1 *timings = 4438 &det->timings[i]; 4439 4440 newmode = drm_displayid_detailed(timings); 4441 if (!newmode) 4442 continue; 4443 4444 drm_add_hdmi_modes(data, newmode); 4445 num_modes++; 4446 drm_mode_destroy(newmode); 4447 } 4448 return num_modes; 4449 } 4450 4451 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 4452 struct edid *edid) 4453 { 4454 u8 *displayid; 4455 int ret; 4456 int idx = 1; 4457 int length = EDID_SIZE; 4458 struct displayid_block *block; 4459 int num_modes = 0; 4460 4461 displayid = drm_find_displayid_extension(edid); 4462 if (!displayid) 4463 return 0; 4464 4465 ret = validate_displayid(displayid, length, idx); 4466 if (ret) 4467 return 0; 4468 4469 idx += sizeof(struct displayid_hdr); 4470 while (block = (struct displayid_block *)&displayid[idx], 4471 idx + sizeof(struct displayid_block) <= length && 4472 idx + sizeof(struct displayid_block) + block->num_bytes <= 4473 length && block->num_bytes > 0) { 4474 idx += block->num_bytes + sizeof(struct displayid_block); 4475 switch (block->tag) { 4476 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4477 num_modes += 4478 add_displayid_detailed_1_modes(data, block); 4479 break; 4480 } 4481 } 4482 return num_modes; 4483 } 4484 4485 static bool 4486 mode_in_hsync_range(const struct drm_display_mode *mode, 4487 struct edid *edid, u8 *t) 4488 { 4489 int hsync, hmin, hmax; 4490 4491 hmin = t[7]; 4492 if (edid->revision >= 4) 4493 hmin += ((t[4] & 0x04) ? 255 : 0); 4494 hmax = t[8]; 4495 if (edid->revision >= 4) 4496 hmax += ((t[4] & 0x08) ? 255 : 0); 4497 hsync = drm_mode_hsync(mode); 4498 4499 return (hsync <= hmax && hsync >= hmin); 4500 } 4501 4502 static bool 4503 mode_in_vsync_range(const struct drm_display_mode *mode, 4504 struct edid *edid, u8 *t) 4505 { 4506 int vsync, vmin, vmax; 4507 4508 vmin = t[5]; 4509 if (edid->revision >= 4) 4510 vmin += ((t[4] & 0x01) ? 255 : 0); 4511 vmax = t[6]; 4512 if (edid->revision >= 4) 4513 vmax += ((t[4] & 0x02) ? 255 : 0); 4514 vsync = drm_get_vrefresh(mode); 4515 4516 return (vsync <= vmax && vsync >= vmin); 4517 } 4518 4519 static u32 4520 range_pixel_clock(struct edid *edid, u8 *t) 4521 { 4522 /* unspecified */ 4523 if (t[9] == 0 || t[9] == 255) 4524 return 0; 4525 4526 /* 1.4 with CVT support gives us real precision, yay */ 4527 if (edid->revision >= 4 && t[10] == 0x04) 4528 return (t[9] * 10000) - ((t[12] >> 2) * 250); 4529 4530 /* 1.3 is pathetic, so fuzz up a bit */ 4531 return t[9] * 10000 + 5001; 4532 } 4533 4534 static bool 4535 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 4536 struct detailed_timing *timing) 4537 { 4538 u32 max_clock; 4539 u8 *t = (u8 *)timing; 4540 4541 if (!mode_in_hsync_range(mode, edid, t)) 4542 return false; 4543 4544 if (!mode_in_vsync_range(mode, edid, t)) 4545 return false; 4546 4547 max_clock = range_pixel_clock(edid, t); 4548 if (max_clock) 4549 if (mode->clock > max_clock) 4550 return false; 4551 4552 /* 1.4 max horizontal check */ 4553 if (edid->revision >= 4 && t[10] == 0x04) 4554 if (t[13] && mode->hdisplay > 8 * 4555 (t[13] + (256 * (t[12] & 0x3)))) 4556 return false; 4557 4558 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 4559 return false; 4560 4561 return true; 4562 } 4563 4564 static bool valid_inferred_mode(struct hdmi_edid_data *data, 4565 const struct drm_display_mode *mode) 4566 { 4567 const struct drm_display_mode *m; 4568 bool ok = false; 4569 int i; 4570 4571 for (i = 0; i < data->modes; i++) { 4572 m = &data->mode_buf[i]; 4573 if (mode->hdisplay == m->hdisplay && 4574 mode->vdisplay == m->vdisplay && 4575 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 4576 return false; /* duplicated */ 4577 if (mode->hdisplay <= m->hdisplay && 4578 mode->vdisplay <= m->vdisplay) 4579 ok = true; 4580 } 4581 return ok; 4582 } 4583 4584 static int 4585 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4586 struct detailed_timing *timing) 4587 { 4588 int i, modes = 0; 4589 4590 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4591 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 4592 valid_inferred_mode(data, drm_dmt_modes + i)) { 4593 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 4594 modes++; 4595 } 4596 } 4597 4598 return modes; 4599 } 4600 4601 /* fix up 1366x768 mode from 1368x768; 4602 * GFT/CVT can't express 1366 width which isn't dividable by 8 4603 */ 4604 static void fixup_mode_1366x768(struct drm_display_mode *mode) 4605 { 4606 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 4607 mode->hdisplay = 1366; 4608 mode->hsync_start--; 4609 mode->hsync_end--; 4610 } 4611 } 4612 4613 static int 4614 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4615 struct detailed_timing *timing) 4616 { 4617 int i, modes = 0; 4618 struct drm_display_mode *newmode; 4619 4620 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4621 const struct minimode *m = &extra_modes[i]; 4622 4623 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 4624 if (!newmode) 4625 return modes; 4626 4627 fixup_mode_1366x768(newmode); 4628 if (!mode_in_range(newmode, edid, timing) || 4629 !valid_inferred_mode(data, newmode)) { 4630 drm_mode_destroy(newmode); 4631 continue; 4632 } 4633 4634 drm_add_hdmi_modes(data, newmode); 4635 modes++; 4636 drm_mode_destroy(newmode); 4637 } 4638 4639 return modes; 4640 } 4641 4642 static int 4643 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4644 struct detailed_timing *timing) 4645 { 4646 int i, modes = 0; 4647 struct drm_display_mode *newmode; 4648 bool rb = drm_monitor_supports_rb(edid); 4649 4650 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4651 const struct minimode *m = &extra_modes[i]; 4652 4653 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 4654 if (!newmode) 4655 return modes; 4656 4657 fixup_mode_1366x768(newmode); 4658 if (!mode_in_range(newmode, edid, timing) || 4659 !valid_inferred_mode(data, newmode)) { 4660 drm_mode_destroy(newmode); 4661 continue; 4662 } 4663 4664 drm_add_hdmi_modes(data, newmode); 4665 modes++; 4666 drm_mode_destroy(newmode); 4667 } 4668 4669 return modes; 4670 } 4671 4672 static void 4673 do_inferred_modes(struct detailed_timing *timing, void *c) 4674 { 4675 struct detailed_mode_closure *closure = c; 4676 struct detailed_non_pixel *data = &timing->data.other_data; 4677 struct detailed_data_monitor_range *range = &data->data.range; 4678 4679 if (data->type != EDID_DETAIL_MONITOR_RANGE) 4680 return; 4681 4682 closure->modes += drm_dmt_modes_for_range(closure->data, 4683 closure->edid, 4684 timing); 4685 4686 if (!version_greater(closure->edid, 1, 1)) 4687 return; /* GTF not defined yet */ 4688 4689 switch (range->flags) { 4690 case 0x02: /* secondary gtf, XXX could do more */ 4691 case 0x00: /* default gtf */ 4692 closure->modes += drm_gtf_modes_for_range(closure->data, 4693 closure->edid, 4694 timing); 4695 break; 4696 case 0x04: /* cvt, only in 1.4+ */ 4697 if (!version_greater(closure->edid, 1, 3)) 4698 break; 4699 4700 closure->modes += drm_cvt_modes_for_range(closure->data, 4701 closure->edid, 4702 timing); 4703 break; 4704 case 0x01: /* just the ranges, no formula */ 4705 default: 4706 break; 4707 } 4708 } 4709 4710 static int 4711 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 4712 { 4713 struct detailed_mode_closure closure = { 4714 .data = data, 4715 .edid = edid, 4716 }; 4717 4718 if (version_greater(edid, 1, 0)) 4719 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 4720 &closure); 4721 4722 return closure.modes; 4723 } 4724 4725 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 4726 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 4727 4728 /** 4729 * edid_fixup_preferred - set preferred modes based on quirk list 4730 * @data: the structure that save parsed hdmi edid data 4731 * @quirks: quirks list 4732 * 4733 * Walk the mode list, clearing the preferred status 4734 * on existing modes and setting it anew for the right mode ala @quirks. 4735 */ 4736 static void edid_fixup_preferred(struct hdmi_edid_data *data, 4737 u32 quirks) 4738 { 4739 struct drm_display_mode *cur_mode, *preferred_mode; 4740 int i, target_refresh = 0; 4741 int num = data->modes; 4742 int cur_vrefresh, preferred_vrefresh; 4743 4744 if (!num) 4745 return; 4746 4747 preferred_mode = data->preferred_mode; 4748 4749 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 4750 target_refresh = 60; 4751 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 4752 target_refresh = 75; 4753 4754 for (i = 0; i < num; i++) { 4755 cur_mode = &data->mode_buf[i]; 4756 4757 if (cur_mode == preferred_mode) 4758 continue; 4759 4760 /* Largest mode is preferred */ 4761 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 4762 preferred_mode = cur_mode; 4763 4764 cur_vrefresh = cur_mode->vrefresh ? 4765 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 4766 preferred_vrefresh = preferred_mode->vrefresh ? 4767 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 4768 /* At a given size, try to get closest to target refresh */ 4769 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 4770 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 4771 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 4772 preferred_mode = cur_mode; 4773 } 4774 } 4775 data->preferred_mode = preferred_mode; 4776 } 4777 4778 static const u8 edid_header[] = { 4779 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 4780 }; 4781 4782 /** 4783 * drm_edid_header_is_valid - sanity check the header of the base EDID block 4784 * @raw_edid: pointer to raw base EDID block 4785 * 4786 * Sanity check the header of the base EDID block. 4787 * 4788 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 4789 */ 4790 static int drm_edid_header_is_valid(const u8 *raw_edid) 4791 { 4792 int i, score = 0; 4793 4794 for (i = 0; i < sizeof(edid_header); i++) 4795 if (raw_edid[i] == edid_header[i]) 4796 score++; 4797 4798 return score; 4799 } 4800 4801 static int drm_edid_block_checksum(const u8 *raw_edid) 4802 { 4803 int i; 4804 u8 csum = 0; 4805 4806 for (i = 0; i < EDID_SIZE; i++) 4807 csum += raw_edid[i]; 4808 4809 return csum; 4810 } 4811 4812 static bool drm_edid_is_zero(const u8 *in_edid, int length) 4813 { 4814 if (memchr_inv(in_edid, 0, length)) 4815 return false; 4816 4817 return true; 4818 } 4819 4820 /** 4821 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 4822 * @raw_edid: pointer to raw EDID block 4823 * @block: type of block to validate (0 for base, extension otherwise) 4824 * @print_bad_edid: if true, dump bad EDID blocks to the console 4825 * @edid_corrupt: if true, the header or checksum is invalid 4826 * 4827 * Validate a base or extension EDID block and optionally dump bad blocks to 4828 * the console. 4829 * 4830 * Return: True if the block is valid, false otherwise. 4831 */ 4832 static 4833 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 4834 bool *edid_corrupt) 4835 { 4836 u8 csum; 4837 int edid_fixup = 6; 4838 struct edid *edid = (struct edid *)raw_edid; 4839 4840 if ((!raw_edid)) 4841 return false; 4842 4843 if (block == 0) { 4844 int score = drm_edid_header_is_valid(raw_edid); 4845 4846 if (score == 8) { 4847 if (edid_corrupt) 4848 *edid_corrupt = false; 4849 } else if (score >= edid_fixup) { 4850 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 4851 * The corrupt flag needs to be set here otherwise, the 4852 * fix-up code here will correct the problem, the 4853 * checksum is correct and the test fails 4854 */ 4855 if (edid_corrupt) 4856 *edid_corrupt = true; 4857 debug("Fixing header, your hardware may be failing\n"); 4858 memcpy(raw_edid, edid_header, sizeof(edid_header)); 4859 } else { 4860 if (edid_corrupt) 4861 *edid_corrupt = true; 4862 goto bad; 4863 } 4864 } 4865 4866 csum = drm_edid_block_checksum(raw_edid); 4867 if (csum) { 4868 if (print_bad_edid) { 4869 debug("EDID checksum is invalid, remainder is %d\n", 4870 csum); 4871 } 4872 4873 if (edid_corrupt) 4874 *edid_corrupt = true; 4875 4876 /* allow CEA to slide through, switches mangle this */ 4877 if (raw_edid[0] != 0x02) 4878 goto bad; 4879 } 4880 4881 /* per-block-type checks */ 4882 switch (raw_edid[0]) { 4883 case 0: /* base */ 4884 if (edid->version != 1) { 4885 debug("EDID has major version %d, instead of 1\n", 4886 edid->version); 4887 goto bad; 4888 } 4889 4890 if (edid->revision > 4) 4891 debug("minor > 4, assuming backward compatibility\n"); 4892 break; 4893 4894 default: 4895 break; 4896 } 4897 4898 return true; 4899 4900 bad: 4901 if (print_bad_edid) { 4902 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 4903 debug("EDID block is all zeroes\n"); 4904 } else { 4905 debug("Raw EDID:\n"); 4906 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 4907 raw_edid, EDID_SIZE, false); 4908 } 4909 } 4910 return false; 4911 } 4912 4913 /** 4914 * drm_edid_is_valid - sanity check EDID data 4915 * @edid: EDID data 4916 * 4917 * Sanity-check an entire EDID record (including extensions) 4918 * 4919 * Return: True if the EDID data is valid, false otherwise. 4920 */ 4921 static bool drm_edid_is_valid(struct edid *edid) 4922 { 4923 int i; 4924 u8 *raw = (u8 *)edid; 4925 4926 if (!edid) 4927 return false; 4928 4929 for (i = 0; i <= edid->extensions; i++) 4930 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 4931 return false; 4932 4933 return true; 4934 } 4935 4936 /** 4937 * drm_add_edid_modes - add modes from EDID data, if available 4938 * @data: data we're probing 4939 * @edid: EDID data 4940 * 4941 * Add the specified modes to the data's mode list. 4942 * 4943 * Return: The number of modes added or 0 if we couldn't find any. 4944 */ 4945 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 4946 { 4947 int num_modes = 0; 4948 u32 quirks; 4949 struct edid *edid = (struct edid *)raw_edid; 4950 4951 if (!edid) { 4952 debug("no edid\n"); 4953 return 0; 4954 } 4955 4956 if (!drm_edid_is_valid(edid)) { 4957 debug("EDID invalid\n"); 4958 return 0; 4959 } 4960 4961 if (!data->mode_buf) { 4962 debug("mode buff is null\n"); 4963 return 0; 4964 } 4965 4966 quirks = edid_get_quirks(edid); 4967 /* 4968 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4969 * To avoid multiple parsing of same block, lets parse that map 4970 * from sink info, before parsing CEA modes. 4971 */ 4972 drm_add_display_info(data, edid); 4973 4974 /* 4975 * EDID spec says modes should be preferred in this order: 4976 * - preferred detailed mode 4977 * - other detailed modes from base block 4978 * - detailed modes from extension blocks 4979 * - CVT 3-byte code modes 4980 * - standard timing codes 4981 * - established timing codes 4982 * - modes inferred from GTF or CVT range information 4983 * 4984 * We get this pretty much right. 4985 * 4986 * XXX order for additional mode types in extension blocks? 4987 */ 4988 num_modes += add_detailed_modes(data, edid, quirks); 4989 num_modes += add_cvt_modes(data, edid); 4990 num_modes += add_standard_modes(data, edid); 4991 num_modes += add_established_modes(data, edid); 4992 num_modes += add_cea_modes(data, edid); 4993 num_modes += add_alternate_cea_modes(data, edid); 4994 num_modes += add_displayid_detailed_modes(data, edid); 4995 4996 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4997 num_modes += add_inferred_modes(data, edid); 4998 4999 if (num_modes > 0) 5000 data->preferred_mode = &data->mode_buf[0]; 5001 5002 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5003 edid_fixup_preferred(data, quirks); 5004 5005 if (quirks & EDID_QUIRK_FORCE_6BPC) 5006 data->display_info.bpc = 6; 5007 5008 if (quirks & EDID_QUIRK_FORCE_8BPC) 5009 data->display_info.bpc = 8; 5010 5011 if (quirks & EDID_QUIRK_FORCE_10BPC) 5012 data->display_info.bpc = 10; 5013 5014 if (quirks & EDID_QUIRK_FORCE_12BPC) 5015 data->display_info.bpc = 12; 5016 5017 return num_modes; 5018 } 5019 5020 static int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5021 { 5022 memset(frame, 0, sizeof(*frame)); 5023 5024 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5025 frame->version = 2; 5026 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5027 5028 return 0; 5029 } 5030 5031 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5032 { 5033 u8 vic; 5034 5035 if (!to_match->clock) { 5036 printf("can't find to match\n"); 5037 return 0; 5038 } 5039 5040 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 5041 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 5042 unsigned int clock1, clock2; 5043 5044 /* Check both 60Hz and 59.94Hz */ 5045 clock1 = cea_mode->clock; 5046 clock2 = cea_mode_alternate_clock(cea_mode); 5047 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5048 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5049 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5050 return vic; 5051 } 5052 5053 return 0; 5054 } 5055 5056 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5057 { 5058 return edid_cea_modes[video_code].picture_aspect_ratio; 5059 } 5060 5061 int 5062 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5063 struct drm_display_mode *mode, 5064 bool is_hdmi2_sink) 5065 { 5066 int err; 5067 5068 if (!frame || !mode) 5069 return -EINVAL; 5070 5071 err = hdmi_avi_infoframe_init(frame); 5072 if (err < 0) 5073 return err; 5074 5075 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5076 frame->pixel_repeat = 1; 5077 5078 frame->video_code = drm_match_cea_mode(mode); 5079 5080 /* 5081 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5082 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5083 * have to make sure we dont break HDMI 1.4 sinks. 5084 */ 5085 if (!is_hdmi2_sink && frame->video_code > 64) 5086 frame->video_code = 0; 5087 5088 /* 5089 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5090 * we should send its VIC in vendor infoframes, else send the 5091 * VIC in AVI infoframes. Lets check if this mode is present in 5092 * HDMI 1.4b 4K modes 5093 */ 5094 if (frame->video_code) { 5095 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5096 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5097 5098 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5099 frame->video_code = 0; 5100 } 5101 5102 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5103 5104 /* 5105 * Populate picture aspect ratio from either 5106 * user input (if specified) or from the CEA mode list. 5107 */ 5108 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5109 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5110 frame->picture_aspect = mode->picture_aspect_ratio; 5111 else if (frame->video_code > 0) 5112 frame->picture_aspect = drm_get_cea_aspect_ratio( 5113 frame->video_code); 5114 5115 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5116 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5117 5118 return 0; 5119 } 5120 5121 /** 5122 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5123 * @frame: HDMI vendor infoframe 5124 * 5125 * Returns 0 on success or a negative error code on failure. 5126 */ 5127 static int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5128 { 5129 memset(frame, 0, sizeof(*frame)); 5130 5131 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5132 frame->version = 1; 5133 5134 frame->oui = HDMI_IEEE_OUI; 5135 5136 /* 5137 * 0 is a valid value for s3d_struct, so we use a special "not set" 5138 * value 5139 */ 5140 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5141 5142 return 0; 5143 } 5144 5145 static enum hdmi_3d_structure 5146 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5147 { 5148 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5149 5150 switch (layout) { 5151 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5152 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5153 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5154 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5155 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5156 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5157 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5158 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5159 case DRM_MODE_FLAG_3D_L_DEPTH: 5160 return HDMI_3D_STRUCTURE_L_DEPTH; 5161 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5162 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5163 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5164 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5165 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5166 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5167 default: 5168 return HDMI_3D_STRUCTURE_INVALID; 5169 } 5170 } 5171 5172 int 5173 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5174 struct drm_display_mode *mode) 5175 { 5176 int err; 5177 u32 s3d_flags; 5178 u8 vic; 5179 5180 if (!frame || !mode) 5181 return -EINVAL; 5182 5183 vic = drm_match_hdmi_mode(mode); 5184 5185 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5186 5187 if (!vic && !s3d_flags) 5188 return -EINVAL; 5189 5190 if (vic && s3d_flags) 5191 return -EINVAL; 5192 5193 err = hdmi_vendor_infoframe_init(frame); 5194 if (err < 0) 5195 return err; 5196 5197 if (vic) 5198 frame->vic = vic; 5199 else 5200 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5201 5202 return 0; 5203 } 5204 5205 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5206 { 5207 u8 csum = 0; 5208 size_t i; 5209 5210 /* compute checksum */ 5211 for (i = 0; i < size; i++) 5212 csum += ptr[i]; 5213 5214 return 256 - csum; 5215 } 5216 5217 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5218 { 5219 u8 *ptr = buffer; 5220 5221 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5222 } 5223 5224 /** 5225 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 5226 * @frame: HDMI infoframe 5227 * @buffer: destination buffer 5228 * @size: size of buffer 5229 * 5230 * Packs the information contained in the @frame structure into a binary 5231 * representation that can be written into the corresponding controller 5232 * registers. Also computes the checksum as required by section 5.3.5 of 5233 * the HDMI 1.4 specification. 5234 * 5235 * Returns the number of bytes packed into the binary buffer or a negative 5236 * error code on failure. 5237 */ 5238 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 5239 void *buffer, size_t size) 5240 { 5241 u8 *ptr = buffer; 5242 size_t length; 5243 5244 /* empty info frame */ 5245 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 5246 return -EINVAL; 5247 5248 /* only one of those can be supplied */ 5249 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 5250 return -EINVAL; 5251 5252 /* for side by side (half) we also need to provide 3D_Ext_Data */ 5253 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5254 frame->length = 6; 5255 else 5256 frame->length = 5; 5257 5258 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5259 5260 if (size < length) 5261 return -ENOSPC; 5262 5263 memset(buffer, 0, size); 5264 5265 ptr[0] = frame->type; 5266 ptr[1] = frame->version; 5267 ptr[2] = frame->length; 5268 ptr[3] = 0; /* checksum */ 5269 5270 /* HDMI OUI */ 5271 ptr[4] = 0x03; 5272 ptr[5] = 0x0c; 5273 ptr[6] = 0x00; 5274 5275 if (frame->vic) { 5276 ptr[7] = 0x1 << 5; /* video format */ 5277 ptr[8] = frame->vic; 5278 } else { 5279 ptr[7] = 0x2 << 5; /* video format */ 5280 ptr[8] = (frame->s3d_struct & 0xf) << 4; 5281 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5282 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 5283 } 5284 5285 hdmi_infoframe_set_checksum(buffer, length); 5286 5287 return length; 5288 } 5289