1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <hexdump.h> 22 #include <malloc.h> 23 #include <linux/compat.h> 24 #include <linux/ctype.h> 25 #include <linux/fb.h> 26 #include <linux/hdmi.h> 27 #include <linux/string.h> 28 29 #define EDID_EST_TIMINGS 16 30 #define EDID_STD_TIMINGS 8 31 #define EDID_DETAILED_TIMINGS 4 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 bool preferred; 78 u32 quirks; 79 int modes; 80 }; 81 82 #define LEVEL_DMT 0 83 #define LEVEL_GTF 1 84 #define LEVEL_GTF2 2 85 #define LEVEL_CVT 3 86 87 static struct edid_quirk { 88 char vendor[4]; 89 int product_id; 90 u32 quirks; 91 } edid_quirk_list[] = { 92 /* Acer AL1706 */ 93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Acer F51 */ 95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Unknown Acer */ 97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 98 99 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 100 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 116 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 146 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 147 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Probably taken from CEA-861 spec. 152 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 153 * 154 * Index using the VIC. 155 */ 156 /* 157 * From CEA/CTA-861 spec. 158 * Do not access directly, instead always use cea_mode_for_vic(). 159 */ 160 static const struct drm_display_mode edid_cea_modes_1[] = { 161 /* 0 - dummy, VICs start at 1 */ 162 { }, 163 /* 1 - 640x480@60Hz */ 164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 165 752, 800, 480, 490, 492, 525, 0, 166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 167 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 168 /* 2 - 720x480@60Hz */ 169 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 170 798, 858, 480, 489, 495, 525, 0, 171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 172 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 173 /* 3 - 720x480@60Hz */ 174 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 175 798, 858, 480, 489, 495, 525, 0, 176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 177 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 178 /* 4 - 1280x720@60Hz */ 179 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 180 1430, 1650, 720, 725, 730, 750, 0, 181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 182 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 183 /* 5 - 1920x1080i@60Hz */ 184 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 185 2052, 2200, 1080, 1084, 1094, 1125, 0, 186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 187 DRM_MODE_FLAG_INTERLACE), 188 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 189 /* 6 - 720(1440)x480i@60Hz */ 190 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 191 801, 858, 480, 488, 494, 525, 0, 192 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 193 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 194 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 195 /* 7 - 720(1440)x480i@60Hz */ 196 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 197 801, 858, 480, 488, 494, 525, 0, 198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 199 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 200 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 201 /* 8 - 720(1440)x240@60Hz */ 202 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 203 801, 858, 240, 244, 247, 262, 0, 204 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 205 DRM_MODE_FLAG_DBLCLK), 206 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 207 /* 9 - 720(1440)x240@60Hz */ 208 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 209 801, 858, 240, 244, 247, 262, 0, 210 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 211 DRM_MODE_FLAG_DBLCLK), 212 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 213 /* 10 - 2880x480i@60Hz */ 214 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 215 3204, 3432, 480, 488, 494, 525, 0, 216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 217 DRM_MODE_FLAG_INTERLACE), 218 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 219 /* 11 - 2880x480i@60Hz */ 220 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 221 3204, 3432, 480, 488, 494, 525, 0, 222 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 223 DRM_MODE_FLAG_INTERLACE), 224 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 225 /* 12 - 2880x240@60Hz */ 226 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 227 3204, 3432, 240, 244, 247, 262, 0, 228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 229 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 230 /* 13 - 2880x240@60Hz */ 231 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 232 3204, 3432, 240, 244, 247, 262, 0, 233 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 234 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 235 /* 14 - 1440x480@60Hz */ 236 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 237 1596, 1716, 480, 489, 495, 525, 0, 238 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 239 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 240 /* 15 - 1440x480@60Hz */ 241 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 242 1596, 1716, 480, 489, 495, 525, 0, 243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 244 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 245 /* 16 - 1920x1080@60Hz */ 246 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 247 2052, 2200, 1080, 1084, 1089, 1125, 0, 248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 249 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 250 /* 17 - 720x576@50Hz */ 251 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 252 796, 864, 576, 581, 586, 625, 0, 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 254 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 255 /* 18 - 720x576@50Hz */ 256 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 257 796, 864, 576, 581, 586, 625, 0, 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 259 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 260 /* 19 - 1280x720@50Hz */ 261 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 262 1760, 1980, 720, 725, 730, 750, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 264 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 265 /* 20 - 1920x1080i@50Hz */ 266 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 267 2492, 2640, 1080, 1084, 1094, 1125, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 269 DRM_MODE_FLAG_INTERLACE), 270 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 271 /* 21 - 720(1440)x576i@50Hz */ 272 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 273 795, 864, 576, 580, 586, 625, 0, 274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 275 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 276 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 277 /* 22 - 720(1440)x576i@50Hz */ 278 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 279 795, 864, 576, 580, 586, 625, 0, 280 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 281 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 282 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 283 /* 23 - 720(1440)x288@50Hz */ 284 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 285 795, 864, 288, 290, 293, 312, 0, 286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 287 DRM_MODE_FLAG_DBLCLK), 288 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 289 /* 24 - 720(1440)x288@50Hz */ 290 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 291 795, 864, 288, 290, 293, 312, 0, 292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 293 DRM_MODE_FLAG_DBLCLK), 294 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 295 /* 25 - 2880x576i@50Hz */ 296 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 297 3180, 3456, 576, 580, 586, 625, 0, 298 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 299 DRM_MODE_FLAG_INTERLACE), 300 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 301 /* 26 - 2880x576i@50Hz */ 302 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 303 3180, 3456, 576, 580, 586, 625, 0, 304 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 305 DRM_MODE_FLAG_INTERLACE), 306 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 307 /* 27 - 2880x288@50Hz */ 308 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 309 3180, 3456, 288, 290, 293, 312, 0, 310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 311 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 312 /* 28 - 2880x288@50Hz */ 313 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 314 3180, 3456, 288, 290, 293, 312, 0, 315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 316 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 317 /* 29 - 1440x576@50Hz */ 318 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 319 1592, 1728, 576, 581, 586, 625, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 321 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 322 /* 30 - 1440x576@50Hz */ 323 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 324 1592, 1728, 576, 581, 586, 625, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 326 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 327 /* 31 - 1920x1080@50Hz */ 328 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 329 2492, 2640, 1080, 1084, 1089, 1125, 0, 330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 331 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 332 /* 32 - 1920x1080@24Hz */ 333 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 334 2602, 2750, 1080, 1084, 1089, 1125, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 336 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 337 /* 33 - 1920x1080@25Hz */ 338 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 339 2492, 2640, 1080, 1084, 1089, 1125, 0, 340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 341 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 342 /* 34 - 1920x1080@30Hz */ 343 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 344 2052, 2200, 1080, 1084, 1089, 1125, 0, 345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 346 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 347 /* 35 - 2880x480@60Hz */ 348 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 349 3192, 3432, 480, 489, 495, 525, 0, 350 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 351 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 352 /* 36 - 2880x480@60Hz */ 353 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 354 3192, 3432, 480, 489, 495, 525, 0, 355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 356 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 357 /* 37 - 2880x576@50Hz */ 358 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 359 3184, 3456, 576, 581, 586, 625, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 361 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 362 /* 38 - 2880x576@50Hz */ 363 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 364 3184, 3456, 576, 581, 586, 625, 0, 365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 366 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 367 /* 39 - 1920x1080i@50Hz */ 368 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 369 2120, 2304, 1080, 1126, 1136, 1250, 0, 370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 371 DRM_MODE_FLAG_INTERLACE), 372 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 373 /* 40 - 1920x1080i@100Hz */ 374 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 375 2492, 2640, 1080, 1084, 1094, 1125, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 377 DRM_MODE_FLAG_INTERLACE), 378 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 379 /* 41 - 1280x720@100Hz */ 380 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 381 1760, 1980, 720, 725, 730, 750, 0, 382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 383 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 384 /* 42 - 720x576@100Hz */ 385 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 386 796, 864, 576, 581, 586, 625, 0, 387 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 388 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 389 /* 43 - 720x576@100Hz */ 390 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 391 796, 864, 576, 581, 586, 625, 0, 392 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 393 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 394 /* 44 - 720(1440)x576i@100Hz */ 395 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 396 795, 864, 576, 580, 586, 625, 0, 397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 398 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 399 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 400 /* 45 - 720(1440)x576i@100Hz */ 401 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 402 795, 864, 576, 580, 586, 625, 0, 403 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 404 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 405 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 406 /* 46 - 1920x1080i@120Hz */ 407 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 408 2052, 2200, 1080, 1084, 1094, 1125, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 410 DRM_MODE_FLAG_INTERLACE), 411 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 412 /* 47 - 1280x720@120Hz */ 413 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 414 1430, 1650, 720, 725, 730, 750, 0, 415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 416 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 417 /* 48 - 720x480@120Hz */ 418 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 419 798, 858, 480, 489, 495, 525, 0, 420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 421 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 422 /* 49 - 720x480@120Hz */ 423 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 424 798, 858, 480, 489, 495, 525, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 426 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 427 /* 50 - 720(1440)x480i@120Hz */ 428 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 429 801, 858, 480, 488, 494, 525, 0, 430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 431 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 432 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 433 /* 51 - 720(1440)x480i@120Hz */ 434 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 435 801, 858, 480, 488, 494, 525, 0, 436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 437 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 438 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 439 /* 52 - 720x576@200Hz */ 440 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 441 796, 864, 576, 581, 586, 625, 0, 442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 443 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 444 /* 53 - 720x576@200Hz */ 445 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 446 796, 864, 576, 581, 586, 625, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 448 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 449 /* 54 - 720(1440)x576i@200Hz */ 450 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 451 795, 864, 576, 580, 586, 625, 0, 452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 453 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 454 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 455 /* 55 - 720(1440)x576i@200Hz */ 456 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 457 795, 864, 576, 580, 586, 625, 0, 458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 459 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 460 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 461 /* 56 - 720x480@240Hz */ 462 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 463 798, 858, 480, 489, 495, 525, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 465 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 466 /* 57 - 720x480@240Hz */ 467 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 468 798, 858, 480, 489, 495, 525, 0, 469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 470 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 471 /* 58 - 720(1440)x480i@240 */ 472 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 473 801, 858, 480, 488, 494, 525, 0, 474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 475 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 476 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 477 /* 59 - 720(1440)x480i@240 */ 478 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 479 801, 858, 480, 488, 494, 525, 0, 480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 481 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 482 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 483 /* 60 - 1280x720@24Hz */ 484 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 485 3080, 3300, 720, 725, 730, 750, 0, 486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 487 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 488 /* 61 - 1280x720@25Hz */ 489 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 490 3740, 3960, 720, 725, 730, 750, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 492 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 493 /* 62 - 1280x720@30Hz */ 494 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 495 3080, 3300, 720, 725, 730, 750, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 497 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 498 /* 63 - 1920x1080@120Hz */ 499 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 500 2052, 2200, 1080, 1084, 1089, 1125, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 502 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 503 /* 64 - 1920x1080@100Hz */ 504 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 505 2492, 2640, 1080, 1084, 1089, 1125, 0, 506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 507 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 508 /* 65 - 1280x720@24Hz */ 509 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 510 3080, 3300, 720, 725, 730, 750, 0, 511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 512 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 513 /* 66 - 1280x720@25Hz */ 514 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 515 3740, 3960, 720, 725, 730, 750, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 517 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 518 /* 67 - 1280x720@30Hz */ 519 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 520 3080, 3300, 720, 725, 730, 750, 0, 521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 522 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 523 /* 68 - 1280x720@50Hz */ 524 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 525 1760, 1980, 720, 725, 730, 750, 0, 526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 527 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 528 /* 69 - 1280x720@60Hz */ 529 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 530 1430, 1650, 720, 725, 730, 750, 0, 531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 532 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 533 /* 70 - 1280x720@100Hz */ 534 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 535 1760, 1980, 720, 725, 730, 750, 0, 536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 537 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 538 /* 71 - 1280x720@120Hz */ 539 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 540 1430, 1650, 720, 725, 730, 750, 0, 541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 542 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 543 /* 72 - 1920x1080@24Hz */ 544 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 545 2602, 2750, 1080, 1084, 1089, 1125, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 547 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 548 /* 73 - 1920x1080@25Hz */ 549 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 550 2492, 2640, 1080, 1084, 1089, 1125, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 552 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 553 /* 74 - 1920x1080@30Hz */ 554 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 555 2052, 2200, 1080, 1084, 1089, 1125, 0, 556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 557 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 558 /* 75 - 1920x1080@50Hz */ 559 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 560 2492, 2640, 1080, 1084, 1089, 1125, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 562 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 563 /* 76 - 1920x1080@60Hz */ 564 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 565 2052, 2200, 1080, 1084, 1089, 1125, 0, 566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 567 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 568 /* 77 - 1920x1080@100Hz */ 569 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 570 2492, 2640, 1080, 1084, 1089, 1125, 0, 571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 572 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 573 /* 78 - 1920x1080@120Hz */ 574 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 575 2052, 2200, 1080, 1084, 1089, 1125, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 577 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 578 /* 79 - 1680x720@24Hz */ 579 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 580 3080, 3300, 720, 725, 730, 750, 0, 581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 582 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 583 /* 80 - 1680x720@25Hz */ 584 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 585 2948, 3168, 720, 725, 730, 750, 0, 586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 587 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 588 /* 81 - 1680x720@30Hz */ 589 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 590 2420, 2640, 720, 725, 730, 750, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 592 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 593 /* 82 - 1680x720@50Hz */ 594 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 595 1980, 2200, 720, 725, 730, 750, 0, 596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 597 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 598 /* 83 - 1680x720@60Hz */ 599 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 600 1980, 2200, 720, 725, 730, 750, 0, 601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 602 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 603 /* 84 - 1680x720@100Hz */ 604 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 605 1780, 2000, 720, 725, 730, 825, 0, 606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 607 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 608 /* 85 - 1680x720@120Hz */ 609 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 610 1780, 2000, 720, 725, 730, 825, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 612 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 613 /* 86 - 2560x1080@24Hz */ 614 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 615 3602, 3750, 1080, 1084, 1089, 1100, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 617 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 618 /* 87 - 2560x1080@25Hz */ 619 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 620 3052, 3200, 1080, 1084, 1089, 1125, 0, 621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 622 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 623 /* 88 - 2560x1080@30Hz */ 624 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 625 3372, 3520, 1080, 1084, 1089, 1125, 0, 626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 627 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 628 /* 89 - 2560x1080@50Hz */ 629 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 630 3152, 3300, 1080, 1084, 1089, 1125, 0, 631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 632 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 633 /* 90 - 2560x1080@60Hz */ 634 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 635 2852, 3000, 1080, 1084, 1089, 1100, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 637 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 638 /* 91 - 2560x1080@100Hz */ 639 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 640 2822, 2970, 1080, 1084, 1089, 1250, 0, 641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 642 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 643 /* 92 - 2560x1080@120Hz */ 644 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 645 3152, 3300, 1080, 1084, 1089, 1250, 0, 646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 647 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 648 /* 93 - 3840x2160p@24Hz 16:9 */ 649 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 650 5204, 5500, 2160, 2168, 2178, 2250, 0, 651 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 652 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 653 /* 94 - 3840x2160p@25Hz 16:9 */ 654 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 655 4984, 5280, 2160, 2168, 2178, 2250, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 657 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 658 /* 95 - 3840x2160p@30Hz 16:9 */ 659 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 660 4104, 4400, 2160, 2168, 2178, 2250, 0, 661 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 662 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 663 /* 96 - 3840x2160p@50Hz 16:9 */ 664 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 665 4984, 5280, 2160, 2168, 2178, 2250, 0, 666 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 667 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 668 /* 97 - 3840x2160p@60Hz 16:9 */ 669 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 670 4104, 4400, 2160, 2168, 2178, 2250, 0, 671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 672 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 673 /* 98 - 4096x2160p@24Hz 256:135 */ 674 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 675 5204, 5500, 2160, 2168, 2178, 2250, 0, 676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 677 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 678 /* 99 - 4096x2160p@25Hz 256:135 */ 679 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 680 5152, 5280, 2160, 2168, 2178, 2250, 0, 681 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 682 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 683 /* 100 - 4096x2160p@30Hz 256:135 */ 684 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 685 4272, 4400, 2160, 2168, 2178, 2250, 0, 686 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 687 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 688 /* 101 - 4096x2160p@50Hz 256:135 */ 689 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 690 5152, 5280, 2160, 2168, 2178, 2250, 0, 691 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 692 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 693 /* 102 - 4096x2160p@60Hz 256:135 */ 694 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 695 4272, 4400, 2160, 2168, 2178, 2250, 0, 696 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 698 /* 103 - 3840x2160p@24Hz 64:27 */ 699 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 700 5204, 5500, 2160, 2168, 2178, 2250, 0, 701 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 702 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 703 /* 104 - 3840x2160p@25Hz 64:27 */ 704 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 705 4104, 4400, 2160, 2168, 2178, 2250, 0, 706 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 707 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 708 /* 105 - 3840x2160p@30Hz 64:27 */ 709 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 710 4104, 4400, 2160, 2168, 2178, 2250, 0, 711 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 712 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 713 /* 106 - 3840x2160p@50Hz 64:27 */ 714 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 715 4984, 5280, 2160, 2168, 2178, 2250, 0, 716 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 717 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 718 /* 107 - 3840x2160p@60Hz 64:27 */ 719 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 720 4104, 4400, 2160, 2168, 2178, 2250, 0, 721 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 723 /* 108 - 1280x720@48Hz 16:9 */ 724 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 725 2280, 2500, 720, 725, 730, 750, 0, 726 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 727 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 728 /* 109 - 1280x720@48Hz 64:27 */ 729 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 730 2280, 2500, 720, 725, 730, 750, 0, 731 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 732 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 733 /* 110 - 1680x720@48Hz 64:27 */ 734 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 735 2530, 2750, 720, 725, 730, 750, 0, 736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 737 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 738 /* 111 - 1920x1080@48Hz 16:9 */ 739 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 740 2602, 2750, 1080, 1084, 1089, 1125, 0, 741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 742 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 743 /* 112 - 1920x1080@48Hz 64:27 */ 744 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 745 2602, 2750, 1080, 1084, 1089, 1125, 0, 746 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 747 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 748 /* 113 - 2560x1080@48Hz 64:27 */ 749 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 750 3602, 3750, 1080, 1084, 1089, 1100, 0, 751 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 752 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 753 /* 114 - 3840x2160@48Hz 16:9 */ 754 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 755 5204, 5500, 2160, 2168, 2178, 2250, 0, 756 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 757 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 758 /* 115 - 4096x2160@48Hz 256:135 */ 759 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 760 5204, 5500, 2160, 2168, 2178, 2250, 0, 761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 762 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 763 /* 116 - 3840x2160@48Hz 64:27 */ 764 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 765 5204, 5500, 2160, 2168, 2178, 2250, 0, 766 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 767 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 768 /* 117 - 3840x2160@100Hz 16:9 */ 769 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 770 4984, 5280, 2160, 2168, 2178, 2250, 0, 771 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 772 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 773 /* 118 - 3840x2160@120Hz 16:9 */ 774 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 775 4104, 4400, 2160, 2168, 2178, 2250, 0, 776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 777 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 778 /* 119 - 3840x2160@100Hz 64:27 */ 779 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 780 4984, 5280, 2160, 2168, 2178, 2250, 0, 781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 782 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 783 /* 120 - 3840x2160@120Hz 64:27 */ 784 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 785 4104, 4400, 2160, 2168, 2178, 2250, 0, 786 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 787 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 788 /* 121 - 5120x2160@24Hz 64:27 */ 789 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 790 7204, 7500, 2160, 2168, 2178, 2200, 0, 791 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 792 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 793 /* 122 - 5120x2160@25Hz 64:27 */ 794 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 795 6904, 7200, 2160, 2168, 2178, 2200, 0, 796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 797 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 798 /* 123 - 5120x2160@30Hz 64:27 */ 799 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 800 5872, 6000, 2160, 2168, 2178, 2200, 0, 801 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 802 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 803 /* 124 - 5120x2160@48Hz 64:27 */ 804 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 805 5954, 6250, 2160, 2168, 2178, 2475, 0, 806 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 807 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 808 /* 125 - 5120x2160@50Hz 64:27 */ 809 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 810 6304, 6600, 2160, 2168, 2178, 2250, 0, 811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 813 /* 126 - 5120x2160@60Hz 64:27 */ 814 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 815 5372, 5500, 2160, 2168, 2178, 2250, 0, 816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 817 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 818 /* 127 - 5120x2160@100Hz 64:27 */ 819 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 820 6304, 6600, 2160, 2168, 2178, 2250, 0, 821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 822 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 823 }; 824 825 static const struct drm_display_mode edid_cea_modes_193[] = { 826 /* 193 - 5120x2160@120Hz 64:27 */ 827 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 828 5372, 5500, 2160, 2168, 2178, 2250, 0, 829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 830 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 831 /* 194 - 7680x4320@24Hz 16:9 */ 832 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 833 10408, 11000, 4320, 4336, 4356, 4500, 0, 834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 835 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 836 /* 195 - 7680x4320@25Hz 16:9 */ 837 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 838 10208, 10800, 4320, 4336, 4356, 4400, 0, 839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 840 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 841 /* 196 - 7680x4320@30Hz 16:9 */ 842 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 843 8408, 9000, 4320, 4336, 4356, 4400, 0, 844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 845 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 846 /* 197 - 7680x4320@48Hz 16:9 */ 847 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 848 10408, 11000, 4320, 4336, 4356, 4500, 0, 849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 850 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 198 - 7680x4320@50Hz 16:9 */ 852 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 853 10208, 10800, 4320, 4336, 4356, 4400, 0, 854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 856 /* 199 - 7680x4320@60Hz 16:9 */ 857 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 858 8408, 9000, 4320, 4336, 4356, 4400, 0, 859 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 860 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 861 /* 200 - 7680x4320@100Hz 16:9 */ 862 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 863 9968, 10560, 4320, 4336, 4356, 4500, 0, 864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 865 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 866 /* 201 - 7680x4320@120Hz 16:9 */ 867 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 868 8208, 8800, 4320, 4336, 4356, 4500, 0, 869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 870 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 871 /* 202 - 7680x4320@24Hz 64:27 */ 872 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 873 10408, 11000, 4320, 4336, 4356, 4500, 0, 874 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 875 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 876 /* 203 - 7680x4320@25Hz 64:27 */ 877 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 878 10208, 10800, 4320, 4336, 4356, 4400, 0, 879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 880 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 881 /* 204 - 7680x4320@30Hz 64:27 */ 882 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 883 8408, 9000, 4320, 4336, 4356, 4400, 0, 884 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 885 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 886 /* 205 - 7680x4320@48Hz 64:27 */ 887 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 888 10408, 11000, 4320, 4336, 4356, 4500, 0, 889 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 890 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 891 /* 206 - 7680x4320@50Hz 64:27 */ 892 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 893 10208, 10800, 4320, 4336, 4356, 4400, 0, 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 895 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 896 /* 207 - 7680x4320@60Hz 64:27 */ 897 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 898 8408, 9000, 4320, 4336, 4356, 4400, 0, 899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 900 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 901 /* 208 - 7680x4320@100Hz 64:27 */ 902 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 903 9968, 10560, 4320, 4336, 4356, 4500, 0, 904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 905 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 906 /* 209 - 7680x4320@120Hz 64:27 */ 907 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 908 8208, 8800, 4320, 4336, 4356, 4500, 0, 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 910 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 911 /* 210 - 10240x4320@24Hz 64:27 */ 912 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 913 11908, 12500, 4320, 4336, 4356, 4950, 0, 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 915 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 916 /* 211 - 10240x4320@25Hz 64:27 */ 917 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 918 12908, 13500, 4320, 4336, 4356, 4400, 0, 919 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 920 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 921 /* 212 - 10240x4320@30Hz 64:27 */ 922 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 923 10704, 11000, 4320, 4336, 4356, 4500, 0, 924 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 925 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 926 /* 213 - 10240x4320@48Hz 64:27 */ 927 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 928 11908, 12500, 4320, 4336, 4356, 4950, 0, 929 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 930 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 931 /* 214 - 10240x4320@50Hz 64:27 */ 932 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 933 12908, 13500, 4320, 4336, 4356, 4400, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 935 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 936 /* 215 - 10240x4320@60Hz 64:27 */ 937 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 938 10704, 11000, 4320, 4336, 4356, 4500, 0, 939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 940 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 941 /* 216 - 10240x4320@100Hz 64:27 */ 942 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 943 12608, 13200, 4320, 4336, 4356, 4500, 0, 944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 945 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 946 /* 217 - 10240x4320@120Hz 64:27 */ 947 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 948 10704, 11000, 4320, 4336, 4356, 4500, 0, 949 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 950 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 951 /* 218 - 4096x2160@100Hz 256:135 */ 952 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 953 4984, 5280, 2160, 2168, 2178, 2250, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 955 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 956 /* 219 - 4096x2160@120Hz 256:135 */ 957 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 958 4272, 4400, 2160, 2168, 2178, 2250, 0, 959 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 960 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 961 }; 962 963 /* 964 * HDMI 1.4 4k modes. Index using the VIC. 965 */ 966 static const struct drm_display_mode edid_4k_modes[] = { 967 /* 0 - dummy, VICs start at 1 */ 968 { }, 969 /* 1 - 3840x2160@30Hz */ 970 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 971 3840, 4016, 4104, 4400, 972 2160, 2168, 2178, 2250, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 974 .vrefresh = 30, }, 975 /* 2 - 3840x2160@25Hz */ 976 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 977 3840, 4896, 4984, 5280, 978 2160, 2168, 2178, 2250, 0, 979 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 980 .vrefresh = 25, }, 981 /* 3 - 3840x2160@24Hz */ 982 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 983 3840, 5116, 5204, 5500, 984 2160, 2168, 2178, 2250, 0, 985 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 986 .vrefresh = 24, }, 987 /* 4 - 4096x2160@24Hz (SMPTE) */ 988 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 989 4096, 5116, 5204, 5500, 990 2160, 2168, 2178, 2250, 0, 991 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 992 .vrefresh = 24, }, 993 }; 994 995 /* 996 * Autogenerated from the DMT spec. 997 * This table is copied from xfree86/modes/xf86EdidModes.c. 998 */ 999 static const struct drm_display_mode drm_dmt_modes[] = { 1000 /* 0x01 - 640x350@85Hz */ 1001 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1002 736, 832, 350, 382, 385, 445, 0, 1003 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1004 /* 0x02 - 640x400@85Hz */ 1005 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1006 736, 832, 400, 401, 404, 445, 0, 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1008 /* 0x03 - 720x400@85Hz */ 1009 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 1010 828, 936, 400, 401, 404, 446, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1012 /* 0x04 - 640x480@60Hz */ 1013 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1014 752, 800, 480, 490, 492, 525, 0, 1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1016 /* 0x05 - 640x480@72Hz */ 1017 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1018 704, 832, 480, 489, 492, 520, 0, 1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1020 /* 0x06 - 640x480@75Hz */ 1021 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1022 720, 840, 480, 481, 484, 500, 0, 1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1024 /* 0x07 - 640x480@85Hz */ 1025 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 1026 752, 832, 480, 481, 484, 509, 0, 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1028 /* 0x08 - 800x600@56Hz */ 1029 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1030 896, 1024, 600, 601, 603, 625, 0, 1031 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1032 /* 0x09 - 800x600@60Hz */ 1033 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1034 968, 1056, 600, 601, 605, 628, 0, 1035 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1036 /* 0x0a - 800x600@72Hz */ 1037 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1038 976, 1040, 600, 637, 643, 666, 0, 1039 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1040 /* 0x0b - 800x600@75Hz */ 1041 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1042 896, 1056, 600, 601, 604, 625, 0, 1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1044 /* 0x0c - 800x600@85Hz */ 1045 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 1046 896, 1048, 600, 601, 604, 631, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1048 /* 0x0d - 800x600@120Hz RB */ 1049 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 1050 880, 960, 600, 603, 607, 636, 0, 1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1052 /* 0x0e - 848x480@60Hz */ 1053 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 1054 976, 1088, 480, 486, 494, 517, 0, 1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1056 /* 0x0f - 1024x768@43Hz, interlace */ 1057 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1058 1208, 1264, 768, 768, 772, 817, 0, 1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1060 DRM_MODE_FLAG_INTERLACE) }, 1061 /* 0x10 - 1024x768@60Hz */ 1062 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1063 1184, 1344, 768, 771, 777, 806, 0, 1064 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1065 /* 0x11 - 1024x768@70Hz */ 1066 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1067 1184, 1328, 768, 771, 777, 806, 0, 1068 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1069 /* 0x12 - 1024x768@75Hz */ 1070 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1071 1136, 1312, 768, 769, 772, 800, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1073 /* 0x13 - 1024x768@85Hz */ 1074 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 1075 1168, 1376, 768, 769, 772, 808, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1077 /* 0x14 - 1024x768@120Hz RB */ 1078 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 1079 1104, 1184, 768, 771, 775, 813, 0, 1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1081 /* 0x15 - 1152x864@75Hz */ 1082 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1083 1344, 1600, 864, 865, 868, 900, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1085 /* 0x55 - 1280x720@60Hz */ 1086 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1087 1430, 1650, 720, 725, 730, 750, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1089 /* 0x16 - 1280x768@60Hz RB */ 1090 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 1091 1360, 1440, 768, 771, 778, 790, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1093 /* 0x17 - 1280x768@60Hz */ 1094 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 1095 1472, 1664, 768, 771, 778, 798, 0, 1096 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1097 /* 0x18 - 1280x768@75Hz */ 1098 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 1099 1488, 1696, 768, 771, 778, 805, 0, 1100 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1101 /* 0x19 - 1280x768@85Hz */ 1102 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 1103 1496, 1712, 768, 771, 778, 809, 0, 1104 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1105 /* 0x1a - 1280x768@120Hz RB */ 1106 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 1107 1360, 1440, 768, 771, 778, 813, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1109 /* 0x1b - 1280x800@60Hz RB */ 1110 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 1111 1360, 1440, 800, 803, 809, 823, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1113 /* 0x1c - 1280x800@60Hz */ 1114 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 1115 1480, 1680, 800, 803, 809, 831, 0, 1116 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1117 /* 0x1d - 1280x800@75Hz */ 1118 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 1119 1488, 1696, 800, 803, 809, 838, 0, 1120 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1121 /* 0x1e - 1280x800@85Hz */ 1122 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 1123 1496, 1712, 800, 803, 809, 843, 0, 1124 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1125 /* 0x1f - 1280x800@120Hz RB */ 1126 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 1127 1360, 1440, 800, 803, 809, 847, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1129 /* 0x20 - 1280x960@60Hz */ 1130 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 1131 1488, 1800, 960, 961, 964, 1000, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1133 /* 0x21 - 1280x960@85Hz */ 1134 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 1135 1504, 1728, 960, 961, 964, 1011, 0, 1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1137 /* 0x22 - 1280x960@120Hz RB */ 1138 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 1139 1360, 1440, 960, 963, 967, 1017, 0, 1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1141 /* 0x23 - 1280x1024@60Hz */ 1142 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 1143 1440, 1688, 1024, 1025, 1028, 1066, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1145 /* 0x24 - 1280x1024@75Hz */ 1146 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1147 1440, 1688, 1024, 1025, 1028, 1066, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1149 /* 0x25 - 1280x1024@85Hz */ 1150 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 1151 1504, 1728, 1024, 1025, 1028, 1072, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1153 /* 0x26 - 1280x1024@120Hz RB */ 1154 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 1155 1360, 1440, 1024, 1027, 1034, 1084, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1157 /* 0x27 - 1360x768@60Hz */ 1158 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 1159 1536, 1792, 768, 771, 777, 795, 0, 1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1161 /* 0x28 - 1360x768@120Hz RB */ 1162 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 1163 1440, 1520, 768, 771, 776, 813, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1165 /* 0x51 - 1366x768@60Hz */ 1166 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 1167 1579, 1792, 768, 771, 774, 798, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1169 /* 0x56 - 1366x768@60Hz */ 1170 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 1171 1436, 1500, 768, 769, 772, 800, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1173 /* 0x29 - 1400x1050@60Hz RB */ 1174 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 1175 1480, 1560, 1050, 1053, 1057, 1080, 0, 1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1177 /* 0x2a - 1400x1050@60Hz */ 1178 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 1179 1632, 1864, 1050, 1053, 1057, 1089, 0, 1180 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1181 /* 0x2b - 1400x1050@75Hz */ 1182 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 1183 1648, 1896, 1050, 1053, 1057, 1099, 0, 1184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1185 /* 0x2c - 1400x1050@85Hz */ 1186 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 1187 1656, 1912, 1050, 1053, 1057, 1105, 0, 1188 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1189 /* 0x2d - 1400x1050@120Hz RB */ 1190 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 1191 1480, 1560, 1050, 1053, 1057, 1112, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1193 /* 0x2e - 1440x900@60Hz RB */ 1194 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 1195 1520, 1600, 900, 903, 909, 926, 0, 1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1197 /* 0x2f - 1440x900@60Hz */ 1198 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 1199 1672, 1904, 900, 903, 909, 934, 0, 1200 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1201 /* 0x30 - 1440x900@75Hz */ 1202 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 1203 1688, 1936, 900, 903, 909, 942, 0, 1204 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1205 /* 0x31 - 1440x900@85Hz */ 1206 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 1207 1696, 1952, 900, 903, 909, 948, 0, 1208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1209 /* 0x32 - 1440x900@120Hz RB */ 1210 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 1211 1520, 1600, 900, 903, 909, 953, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1213 /* 0x53 - 1600x900@60Hz */ 1214 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 1215 1704, 1800, 900, 901, 904, 1000, 0, 1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1217 /* 0x33 - 1600x1200@60Hz */ 1218 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 1219 1856, 2160, 1200, 1201, 1204, 1250, 0, 1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1221 /* 0x34 - 1600x1200@65Hz */ 1222 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 1223 1856, 2160, 1200, 1201, 1204, 1250, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1225 /* 0x35 - 1600x1200@70Hz */ 1226 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 1227 1856, 2160, 1200, 1201, 1204, 1250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1229 /* 0x36 - 1600x1200@75Hz */ 1230 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 1231 1856, 2160, 1200, 1201, 1204, 1250, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1233 /* 0x37 - 1600x1200@85Hz */ 1234 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 1235 1856, 2160, 1200, 1201, 1204, 1250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1237 /* 0x38 - 1600x1200@120Hz RB */ 1238 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 1239 1680, 1760, 1200, 1203, 1207, 1271, 0, 1240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1241 /* 0x39 - 1680x1050@60Hz RB */ 1242 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1243 1760, 1840, 1050, 1053, 1059, 1080, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1245 /* 0x3a - 1680x1050@60Hz */ 1246 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1247 1960, 2240, 1050, 1053, 1059, 1089, 0, 1248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1249 /* 0x3b - 1680x1050@75Hz */ 1250 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1251 1976, 2272, 1050, 1053, 1059, 1099, 0, 1252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1253 /* 0x3c - 1680x1050@85Hz */ 1254 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1255 1984, 2288, 1050, 1053, 1059, 1105, 0, 1256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1257 /* 0x3d - 1680x1050@120Hz RB */ 1258 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1259 1760, 1840, 1050, 1053, 1059, 1112, 0, 1260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1261 /* 0x3e - 1792x1344@60Hz */ 1262 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1263 2120, 2448, 1344, 1345, 1348, 1394, 0, 1264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1265 /* 0x3f - 1792x1344@75Hz */ 1266 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1267 2104, 2456, 1344, 1345, 1348, 1417, 0, 1268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1269 /* 0x40 - 1792x1344@120Hz RB */ 1270 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1271 1872, 1952, 1344, 1347, 1351, 1423, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1273 /* 0x41 - 1856x1392@60Hz */ 1274 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1275 2176, 2528, 1392, 1393, 1396, 1439, 0, 1276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1277 /* 0x42 - 1856x1392@75Hz */ 1278 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1279 2208, 2560, 1392, 1393, 1396, 1500, 0, 1280 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1281 /* 0x43 - 1856x1392@120Hz RB */ 1282 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1283 1936, 2016, 1392, 1395, 1399, 1474, 0, 1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1285 /* 0x52 - 1920x1080@60Hz */ 1286 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1287 2052, 2200, 1080, 1084, 1089, 1125, 0, 1288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1289 /* 0x44 - 1920x1200@60Hz RB */ 1290 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1291 2000, 2080, 1200, 1203, 1209, 1235, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1293 /* 0x45 - 1920x1200@60Hz */ 1294 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1295 2256, 2592, 1200, 1203, 1209, 1245, 0, 1296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1297 /* 0x46 - 1920x1200@75Hz */ 1298 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1299 2264, 2608, 1200, 1203, 1209, 1255, 0, 1300 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1301 /* 0x47 - 1920x1200@85Hz */ 1302 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1303 2272, 2624, 1200, 1203, 1209, 1262, 0, 1304 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1305 /* 0x48 - 1920x1200@120Hz RB */ 1306 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1307 2000, 2080, 1200, 1203, 1209, 1271, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1309 /* 0x49 - 1920x1440@60Hz */ 1310 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1311 2256, 2600, 1440, 1441, 1444, 1500, 0, 1312 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1313 /* 0x4a - 1920x1440@75Hz */ 1314 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1315 2288, 2640, 1440, 1441, 1444, 1500, 0, 1316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1317 /* 0x4b - 1920x1440@120Hz RB */ 1318 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1319 2000, 2080, 1440, 1443, 1447, 1525, 0, 1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1321 /* 0x54 - 2048x1152@60Hz */ 1322 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1323 2154, 2250, 1152, 1153, 1156, 1200, 0, 1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1325 /* 0x4c - 2560x1600@60Hz RB */ 1326 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1327 2640, 2720, 1600, 1603, 1609, 1646, 0, 1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1329 /* 0x4d - 2560x1600@60Hz */ 1330 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1331 3032, 3504, 1600, 1603, 1609, 1658, 0, 1332 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1333 /* 0x4e - 2560x1600@75Hz */ 1334 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1335 3048, 3536, 1600, 1603, 1609, 1672, 0, 1336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1337 /* 0x4f - 2560x1600@85Hz */ 1338 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1339 3048, 3536, 1600, 1603, 1609, 1682, 0, 1340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1341 /* 0x50 - 2560x1600@120Hz RB */ 1342 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1343 2640, 2720, 1600, 1603, 1609, 1694, 0, 1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1345 /* 0x57 - 4096x2160@60Hz RB */ 1346 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1347 4136, 4176, 2160, 2208, 2216, 2222, 0, 1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1349 /* 0x58 - 4096x2160@59.94Hz RB */ 1350 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1351 4136, 4176, 2160, 2208, 2216, 2222, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1353 }; 1354 1355 /* 1356 * These more or less come from the DMT spec. The 720x400 modes are 1357 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1358 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1359 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1360 * mode. 1361 * 1362 * The DMT modes have been fact-checked; the rest are mild guesses. 1363 */ 1364 static const struct drm_display_mode edid_est_modes[] = { 1365 /* 800x600@60Hz */ 1366 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1367 968, 1056, 600, 601, 605, 628, 0, 1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1369 /* 800x600@56Hz */ 1370 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1371 896, 1024, 600, 601, 603, 625, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1373 /* 640x480@75Hz */ 1374 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1375 720, 840, 480, 481, 484, 500, 0, 1376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1377 /* 640x480@72Hz */ 1378 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1379 704, 832, 480, 489, 492, 520, 0, 1380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1381 /* 640x480@67Hz */ 1382 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1383 768, 864, 480, 483, 486, 525, 0, 1384 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1385 /* 640x480@60Hz */ 1386 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1387 752, 800, 480, 490, 492, 525, 0, 1388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1389 /* 720x400@88Hz */ 1390 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1391 846, 900, 400, 421, 423, 449, 0, 1392 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1393 /* 720x400@70Hz */ 1394 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1395 846, 900, 400, 412, 414, 449, 0, 1396 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1397 /* 1280x1024@75Hz */ 1398 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1399 1440, 1688, 1024, 1025, 1028, 1066, 0, 1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1401 /* 1024x768@75Hz */ 1402 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1403 1136, 1312, 768, 769, 772, 800, 0, 1404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1405 /* 1024x768@70Hz */ 1406 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1407 1184, 1328, 768, 771, 777, 806, 0, 1408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1409 /* 1024x768@60Hz */ 1410 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1411 1184, 1344, 768, 771, 777, 806, 0, 1412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1413 /* 1024x768@43Hz */ 1414 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1415 1208, 1264, 768, 768, 776, 817, 0, 1416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1417 DRM_MODE_FLAG_INTERLACE) }, 1418 /* 832x624@75Hz */ 1419 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1420 928, 1152, 624, 625, 628, 667, 0, 1421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1422 /* 800x600@75Hz */ 1423 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1424 896, 1056, 600, 601, 604, 625, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1426 /* 800x600@72Hz */ 1427 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1428 976, 1040, 600, 637, 643, 666, 0, 1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1430 /* 1152x864@75Hz */ 1431 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1432 1344, 1600, 864, 865, 868, 900, 0, 1433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1434 }; 1435 1436 #define DRM_BASE_MODE(c, hd, hss, hse, ht, vd, vss, vse, vt, vs, f) \ 1437 .clock = (c), \ 1438 .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ 1439 .htotal = (ht), .vdisplay = (vd), \ 1440 .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ 1441 .vscan = (vs), .flags = (f) 1442 1443 static const struct base_drm_display_mode resolution_white[] = { 1444 /* 0. vic:2 - 720x480@60Hz */ 1445 { DRM_BASE_MODE(27000, 720, 736, 1446 798, 858, 480, 489, 495, 525, 0, 1447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1448 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1449 /* 1. vic:3 - 720x480@60Hz */ 1450 { DRM_BASE_MODE(27000, 720, 736, 1451 798, 858, 480, 489, 495, 525, 0, 1452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1453 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1454 /* 1024x768@60Hz */ 1455 { DRM_BASE_MODE(65000, 1024, 1048, 1456 1184, 1344, 768, 771, 777, 806, 0, 1457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1458 /* 2. vic:4 - 1280x720@60Hz */ 1459 { DRM_BASE_MODE(74250, 1280, 1390, 1460 1430, 1650, 720, 725, 730, 750, 0, 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1462 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1463 /* 3. vic:5 - 1920x1080i@60Hz */ 1464 { DRM_BASE_MODE(74250, 1920, 2008, 1465 2052, 2200, 1080, 1084, 1094, 1125, 0, 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1467 DRM_MODE_FLAG_INTERLACE), 1468 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1469 /* 4. vic:6 - 720(1440)x480i@60Hz */ 1470 { DRM_BASE_MODE(13500, 720, 739, 1471 801, 858, 480, 488, 494, 525, 0, 1472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1473 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1474 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1475 /* 5. vic:16 - 1920x1080@60Hz */ 1476 { DRM_BASE_MODE(148500, 1920, 2008, 1477 2052, 2200, 1080, 1084, 1089, 1125, 0, 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1479 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1480 /* 6. vic:17 - 720x576@50Hz */ 1481 { DRM_BASE_MODE(27000, 720, 732, 1482 796, 864, 576, 581, 586, 625, 0, 1483 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1484 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1485 /* 7. vic:18 - 720x576@50Hz */ 1486 { DRM_BASE_MODE(27000, 720, 732, 1487 796, 864, 576, 581, 586, 625, 0, 1488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1489 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1490 /* 8. vic:19 - 1280x720@50Hz */ 1491 { DRM_BASE_MODE(74250, 1280, 1720, 1492 1760, 1980, 720, 725, 730, 750, 0, 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1494 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1495 /* 9. vic:20 - 1920x1080i@50Hz */ 1496 { DRM_BASE_MODE(74250, 1920, 2448, 1497 2492, 2640, 1080, 1084, 1094, 1125, 0, 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1499 DRM_MODE_FLAG_INTERLACE), 1500 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1501 /* 10. vic:21 - 720(1440)x576i@50Hz */ 1502 { DRM_BASE_MODE(13500, 720, 732, 1503 795, 864, 576, 580, 586, 625, 0, 1504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1505 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1506 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1507 /* 11. vic:31 - 1920x1080@50Hz */ 1508 { DRM_BASE_MODE(148500, 1920, 2448, 1509 2492, 2640, 1080, 1084, 1089, 1125, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1512 /* 12. vic:32 - 1920x1080@24Hz */ 1513 { DRM_BASE_MODE(74250, 1920, 2558, 1514 2602, 2750, 1080, 1084, 1089, 1125, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1517 /* 13. vic:33 - 1920x1080@25Hz */ 1518 { DRM_BASE_MODE(74250, 1920, 2448, 1519 2492, 2640, 1080, 1084, 1089, 1125, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1522 /* 14. vic:34 - 1920x1080@30Hz */ 1523 { DRM_BASE_MODE(74250, 1920, 2008, 1524 2052, 2200, 1080, 1084, 1089, 1125, 0, 1525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1526 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1527 /* 15. vic:39 - 1920x1080i@50Hz */ 1528 { DRM_BASE_MODE(72000, 1920, 1952, 1529 2120, 2304, 1080, 1126, 1136, 1250, 0, 1530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 1531 DRM_MODE_FLAG_INTERLACE), 1532 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1533 /* 16. vic:60 - 1280x720@24Hz */ 1534 { DRM_BASE_MODE(59400, 1280, 3040, 1535 3080, 3300, 720, 725, 730, 750, 0, 1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1537 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1538 /* 17. vic:61 - 1280x720@25Hz */ 1539 { DRM_BASE_MODE(74250, 1280, 3700, 1540 3740, 3960, 720, 725, 730, 750, 0, 1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1542 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1543 /* 18. vic:62 - 1280x720@30Hz */ 1544 { DRM_BASE_MODE(74250, 1280, 3040, 1545 3080, 3300, 720, 725, 730, 750, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 19. vic:93 - 3840x2160p@24Hz 16:9 */ 1549 { DRM_BASE_MODE(297000, 3840, 5116, 1550 5204, 5500, 2160, 2168, 2178, 2250, 0, 1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1552 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1553 /* 20. vic:94 - 3840x2160p@25Hz 16:9 */ 1554 { DRM_BASE_MODE(297000, 3840, 4896, 1555 4984, 5280, 2160, 2168, 2178, 2250, 0, 1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1557 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1558 /* 21. vic:95 - 3840x2160p@30Hz 16:9 */ 1559 { DRM_BASE_MODE(297000, 3840, 4016, 1560 4104, 4400, 2160, 2168, 2178, 2250, 0, 1561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1562 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1563 /* 22. vic:96 - 3840x2160p@50Hz 16:9 */ 1564 { DRM_BASE_MODE(594000, 3840, 4896, 1565 4984, 5280, 2160, 2168, 2178, 2250, 0, 1566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1567 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1568 /* 23. vic:97 - 3840x2160p@60Hz 16:9 */ 1569 { DRM_BASE_MODE(594000, 3840, 4016, 1570 4104, 4400, 2160, 2168, 2178, 2250, 0, 1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1572 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1573 /* 24. vic:98 - 4096x2160p@24Hz 256:135 */ 1574 { DRM_BASE_MODE(297000, 4096, 5116, 1575 5204, 5500, 2160, 2168, 2178, 2250, 0, 1576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1577 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1578 /* 25. vic:99 - 4096x2160p@25Hz 256:135 */ 1579 { DRM_BASE_MODE(297000, 4096, 5064, 1580 5152, 5280, 2160, 2168, 2178, 2250, 0, 1581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1582 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1583 /* 26. vic:100 - 4096x2160p@30Hz 256:135 */ 1584 { DRM_BASE_MODE(297000, 4096, 4184, 1585 4272, 4400, 2160, 2168, 2178, 2250, 0, 1586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1587 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1588 /* 27. vic:101 - 4096x2160p@50Hz 256:135 */ 1589 { DRM_BASE_MODE(594000, 4096, 5064, 1590 5152, 5280, 2160, 2168, 2178, 2250, 0, 1591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1592 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1593 /* 28. vic:102 - 4096x2160p@60Hz 256:135 */ 1594 { DRM_BASE_MODE(594000, 4096, 4184, 1595 4272, 4400, 2160, 2168, 2178, 2250, 0, 1596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1597 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1598 /* 29. vic:118 - 3840x2160@120Hz 16:9 */ 1599 { DRM_BASE_MODE(1188000, 3840, 4016, 1600 4104, 4400, 2160, 2168, 2178, 2250, 0, 1601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1602 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1603 /* 30. vic:196 - 7680x4320@30Hz 16:9 */ 1604 { DRM_BASE_MODE(1188000, 7680, 8232, 1605 8408, 9000, 4320, 4336, 4356, 4400, 0, 1606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1607 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1608 /* 31. vic:198 - 7680x4320@50Hz 16:9 */ 1609 { DRM_BASE_MODE(2376000, 7680, 10032, 1610 10208, 10800, 4320, 4336, 4356, 4400, 0, 1611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1612 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1613 /* 32. vic:199 - 7680x4320@60Hz 16:9 */ 1614 { DRM_BASE_MODE(2376000, 7680, 8232, 1615 8408, 9000, 4320, 4336, 4356, 4400, 0, 1616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1617 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1618 }; 1619 1620 struct minimode { 1621 short w; 1622 short h; 1623 short r; 1624 short rb; 1625 }; 1626 1627 static const struct minimode est3_modes[] = { 1628 /* byte 6 */ 1629 { 640, 350, 85, 0 }, 1630 { 640, 400, 85, 0 }, 1631 { 720, 400, 85, 0 }, 1632 { 640, 480, 85, 0 }, 1633 { 848, 480, 60, 0 }, 1634 { 800, 600, 85, 0 }, 1635 { 1024, 768, 85, 0 }, 1636 { 1152, 864, 75, 0 }, 1637 /* byte 7 */ 1638 { 1280, 768, 60, 1 }, 1639 { 1280, 768, 60, 0 }, 1640 { 1280, 768, 75, 0 }, 1641 { 1280, 768, 85, 0 }, 1642 { 1280, 960, 60, 0 }, 1643 { 1280, 960, 85, 0 }, 1644 { 1280, 1024, 60, 0 }, 1645 { 1280, 1024, 85, 0 }, 1646 /* byte 8 */ 1647 { 1360, 768, 60, 0 }, 1648 { 1440, 900, 60, 1 }, 1649 { 1440, 900, 60, 0 }, 1650 { 1440, 900, 75, 0 }, 1651 { 1440, 900, 85, 0 }, 1652 { 1400, 1050, 60, 1 }, 1653 { 1400, 1050, 60, 0 }, 1654 { 1400, 1050, 75, 0 }, 1655 /* byte 9 */ 1656 { 1400, 1050, 85, 0 }, 1657 { 1680, 1050, 60, 1 }, 1658 { 1680, 1050, 60, 0 }, 1659 { 1680, 1050, 75, 0 }, 1660 { 1680, 1050, 85, 0 }, 1661 { 1600, 1200, 60, 0 }, 1662 { 1600, 1200, 65, 0 }, 1663 { 1600, 1200, 70, 0 }, 1664 /* byte 10 */ 1665 { 1600, 1200, 75, 0 }, 1666 { 1600, 1200, 85, 0 }, 1667 { 1792, 1344, 60, 0 }, 1668 { 1792, 1344, 75, 0 }, 1669 { 1856, 1392, 60, 0 }, 1670 { 1856, 1392, 75, 0 }, 1671 { 1920, 1200, 60, 1 }, 1672 { 1920, 1200, 60, 0 }, 1673 /* byte 11 */ 1674 { 1920, 1200, 75, 0 }, 1675 { 1920, 1200, 85, 0 }, 1676 { 1920, 1440, 60, 0 }, 1677 { 1920, 1440, 75, 0 }, 1678 }; 1679 1680 static const struct minimode extra_modes[] = { 1681 { 1024, 576, 60, 0 }, 1682 { 1366, 768, 60, 0 }, 1683 { 1600, 900, 60, 0 }, 1684 { 1680, 945, 60, 0 }, 1685 { 1920, 1080, 60, 0 }, 1686 { 2048, 1152, 60, 0 }, 1687 { 2048, 1536, 60, 0 }, 1688 }; 1689 1690 static const struct drm_display_mode *cea_mode_for_vic(u8 vic) 1691 { 1692 if (!vic) 1693 return NULL; 1694 else if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 1695 return &edid_cea_modes_1[vic - 1]; 1696 else if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 1697 return &edid_cea_modes_193[vic - 193]; 1698 1699 return NULL; 1700 } 1701 1702 static u8 cea_num_vics(void) 1703 { 1704 return 193 + ARRAY_SIZE(edid_cea_modes_193); 1705 } 1706 1707 static u8 cea_next_vic(u8 vic) 1708 { 1709 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 1710 vic = 193; 1711 1712 return vic; 1713 } 1714 1715 int edid_check_info(struct edid1_info *edid_info) 1716 { 1717 if ((edid_info == NULL) || (edid_info->version == 0)) 1718 return -1; 1719 1720 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1721 return -1; 1722 1723 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1724 return -1; 1725 1726 return 0; 1727 } 1728 1729 int edid_check_checksum(u8 *edid_block) 1730 { 1731 u8 checksum = 0; 1732 int i; 1733 1734 for (i = 0; i < 128; i++) 1735 checksum += edid_block[i]; 1736 1737 return (checksum == 0) ? 0 : -EINVAL; 1738 } 1739 1740 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1741 unsigned int *hmax, unsigned int *vmin, 1742 unsigned int *vmax) 1743 { 1744 int i; 1745 struct edid_monitor_descriptor *monitor; 1746 1747 *hmin = *hmax = *vmin = *vmax = 0; 1748 if (edid_check_info(edid)) 1749 return -1; 1750 1751 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1752 monitor = &edid->monitor_details.descriptor[i]; 1753 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1754 *hmin = monitor->data.range_data.horizontal_min; 1755 *hmax = monitor->data.range_data.horizontal_max; 1756 *vmin = monitor->data.range_data.vertical_min; 1757 *vmax = monitor->data.range_data.vertical_max; 1758 return 0; 1759 } 1760 } 1761 return -1; 1762 } 1763 1764 /* Set all parts of a timing entry to the same value */ 1765 static void set_entry(struct timing_entry *entry, u32 value) 1766 { 1767 entry->min = value; 1768 entry->typ = value; 1769 entry->max = value; 1770 } 1771 1772 /** 1773 * decode_timing() - Decoding an 18-byte detailed timing record 1774 * 1775 * @buf: Pointer to EDID detailed timing record 1776 * @timing: Place to put timing 1777 */ 1778 static void decode_timing(u8 *buf, struct display_timing *timing) 1779 { 1780 uint x_mm, y_mm; 1781 unsigned int ha, hbl, hso, hspw, hborder; 1782 unsigned int va, vbl, vso, vspw, vborder; 1783 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1784 1785 /* Edid contains pixel clock in terms of 10KHz */ 1786 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1787 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1788 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1789 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1790 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1791 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1792 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1793 hborder = buf[15]; 1794 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1795 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1796 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1797 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1798 vborder = buf[16]; 1799 1800 set_entry(&timing->hactive, ha); 1801 set_entry(&timing->hfront_porch, hso); 1802 set_entry(&timing->hback_porch, hbl - hso - hspw); 1803 set_entry(&timing->hsync_len, hspw); 1804 1805 set_entry(&timing->vactive, va); 1806 set_entry(&timing->vfront_porch, vso); 1807 set_entry(&timing->vback_porch, vbl - vso - vspw); 1808 set_entry(&timing->vsync_len, vspw); 1809 1810 timing->flags = 0; 1811 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1812 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1813 else 1814 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1815 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1816 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1817 else 1818 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1819 1820 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1821 timing->flags = DISPLAY_FLAGS_INTERLACED; 1822 1823 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1824 " %04x %04x %04x %04x hborder %x\n" 1825 " %04x %04x %04x %04x vborder %x\n", 1826 timing->pixelclock.typ, 1827 x_mm, y_mm, 1828 ha, ha + hso, ha + hso + hspw, 1829 ha + hbl, hborder, 1830 va, va + vso, va + vso + vspw, 1831 va + vbl, vborder); 1832 } 1833 1834 /** 1835 * decode_mode() - Decoding an 18-byte detailed timing record 1836 * 1837 * @buf: Pointer to EDID detailed timing record 1838 * @timing: Place to put timing 1839 */ 1840 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1841 { 1842 uint x_mm, y_mm; 1843 unsigned int ha, hbl, hso, hspw, hborder; 1844 unsigned int va, vbl, vso, vspw, vborder; 1845 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1846 1847 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1848 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1849 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1850 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1851 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1852 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1853 hborder = buf[15]; 1854 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1855 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1856 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1857 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1858 vborder = buf[16]; 1859 1860 /* Edid contains pixel clock in terms of 10KHz */ 1861 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1862 mode->hdisplay = ha; 1863 mode->hsync_start = ha + hso; 1864 mode->hsync_end = ha + hso + hspw; 1865 mode->htotal = ha + hbl; 1866 mode->vdisplay = va; 1867 mode->vsync_start = va + vso; 1868 mode->vsync_end = va + vso + vspw; 1869 mode->vtotal = va + vbl; 1870 1871 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1872 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1873 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1874 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1875 1876 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1877 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1878 1879 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1880 " %04d %04d %04d %04d hborder %d\n" 1881 " %04d %04d %04d %04d vborder %d\n", 1882 mode->clock, 1883 x_mm, y_mm, mode->flags, 1884 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1885 mode->htotal, hborder, 1886 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1887 mode->vtotal, vborder); 1888 } 1889 1890 /** 1891 * edid_vendor - match a string against EDID's obfuscated vendor field 1892 * @edid: EDID to match 1893 * @vendor: vendor string 1894 * 1895 * Returns true if @vendor is in @edid, false otherwise 1896 */ 1897 static bool edid_vendor(struct edid *edid, char *vendor) 1898 { 1899 char edid_vendor[3]; 1900 1901 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1902 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1903 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1904 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1905 1906 return !strncmp(edid_vendor, vendor, 3); 1907 } 1908 1909 /** 1910 * Check if HDMI vendor specific data block is present in CEA block 1911 * @param info CEA extension block 1912 * @return true if block is found 1913 */ 1914 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1915 { 1916 u8 end, i = 0; 1917 1918 /* check for end of data block */ 1919 end = info->dtd_offset; 1920 if (end == 0) 1921 end = sizeof(info->data); 1922 if (end < 4 || end > sizeof(info->data)) 1923 return false; 1924 end -= 4; 1925 1926 while (i < end) { 1927 /* Look for vendor specific data block of appropriate size */ 1928 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1929 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1930 u8 *db = &info->data[i + 1]; 1931 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1932 1933 if (oui == HDMI_IEEE_OUI) 1934 return true; 1935 } 1936 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1937 } 1938 1939 return false; 1940 } 1941 1942 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1943 { 1944 int refresh = 0; 1945 unsigned int calc_val; 1946 1947 if (mode->vrefresh > 0) { 1948 refresh = mode->vrefresh; 1949 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1950 int vtotal; 1951 1952 vtotal = mode->vtotal; 1953 /* work out vrefresh the value will be x1000 */ 1954 calc_val = (mode->clock * 1000); 1955 calc_val /= mode->htotal; 1956 refresh = (calc_val + vtotal / 2) / vtotal; 1957 1958 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1959 refresh *= 2; 1960 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1961 refresh /= 2; 1962 if (mode->vscan > 1) 1963 refresh /= mode->vscan; 1964 } 1965 return refresh; 1966 } 1967 1968 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1969 int *panel_bits_per_colourp) 1970 { 1971 struct edid1_info *edid = (struct edid1_info *)buf; 1972 bool timing_done; 1973 int i; 1974 1975 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1976 debug("%s: Invalid buffer\n", __func__); 1977 return -EINVAL; 1978 } 1979 1980 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1981 debug("%s: No preferred timing\n", __func__); 1982 return -ENOENT; 1983 } 1984 1985 /* Look for detailed timing */ 1986 timing_done = false; 1987 for (i = 0; i < 4; i++) { 1988 struct edid_monitor_descriptor *desc; 1989 1990 desc = &edid->monitor_details.descriptor[i]; 1991 if (desc->zero_flag_1 != 0) { 1992 decode_mode((u8 *)desc, mode); 1993 timing_done = true; 1994 break; 1995 } 1996 } 1997 if (!timing_done) 1998 return -EINVAL; 1999 2000 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 2001 debug("%s: Not a digital display\n", __func__); 2002 return -ENOSYS; 2003 } 2004 if (edid->version != 1 || edid->revision < 4) { 2005 debug("%s: EDID version %d.%d does not have required info\n", 2006 __func__, edid->version, edid->revision); 2007 *panel_bits_per_colourp = -1; 2008 } else { 2009 *panel_bits_per_colourp = 2010 ((edid->video_input_definition & 0x70) >> 3) + 4; 2011 } 2012 2013 return 0; 2014 } 2015 2016 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 2017 int *panel_bits_per_colourp) 2018 { 2019 struct edid1_info *edid = (struct edid1_info *)buf; 2020 bool timing_done; 2021 int i; 2022 2023 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 2024 debug("%s: Invalid buffer\n", __func__); 2025 return -EINVAL; 2026 } 2027 2028 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 2029 debug("%s: No preferred timing\n", __func__); 2030 return -ENOENT; 2031 } 2032 2033 /* Look for detailed timing */ 2034 timing_done = false; 2035 for (i = 0; i < 4; i++) { 2036 struct edid_monitor_descriptor *desc; 2037 2038 desc = &edid->monitor_details.descriptor[i]; 2039 if (desc->zero_flag_1 != 0) { 2040 decode_timing((u8 *)desc, timing); 2041 timing_done = true; 2042 break; 2043 } 2044 } 2045 if (!timing_done) 2046 return -EINVAL; 2047 2048 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 2049 debug("%s: Not a digital display\n", __func__); 2050 return -ENOSYS; 2051 } 2052 if (edid->version != 1 || edid->revision < 4) { 2053 debug("%s: EDID version %d.%d does not have required info\n", 2054 __func__, edid->version, edid->revision); 2055 *panel_bits_per_colourp = -1; 2056 } else { 2057 *panel_bits_per_colourp = 2058 ((edid->video_input_definition & 0x70) >> 3) + 4; 2059 } 2060 2061 timing->hdmi_monitor = false; 2062 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 2063 struct edid_cea861_info *info = 2064 (struct edid_cea861_info *)(buf + sizeof(*edid)); 2065 2066 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 2067 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 2068 } 2069 2070 return 0; 2071 } 2072 2073 /** 2074 * Snip the tailing whitespace/return of a string. 2075 * 2076 * @param string The string to be snipped 2077 * @return the snipped string 2078 */ 2079 static char *snip(char *string) 2080 { 2081 char *s; 2082 2083 /* 2084 * This is always a 13 character buffer 2085 * and it's not always terminated. 2086 */ 2087 string[12] = '\0'; 2088 s = &string[strlen(string) - 1]; 2089 2090 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 2091 *s == '\0')) 2092 *(s--) = '\0'; 2093 2094 return string; 2095 } 2096 2097 /** 2098 * Print an EDID monitor descriptor block 2099 * 2100 * @param monitor The EDID monitor descriptor block 2101 * @have_timing Modifies to 1 if the desciptor contains timing info 2102 */ 2103 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 2104 unsigned int *have_timing) 2105 { 2106 unsigned char *bytes = (unsigned char *)monitor; 2107 struct edid_detailed_timing *timing = 2108 (struct edid_detailed_timing *)monitor; 2109 2110 if (bytes[0] == 0 && bytes[1] == 0) { 2111 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 2112 printf("Monitor serial number: %s\n", 2113 snip(monitor->data.string)); 2114 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 2115 printf("Monitor ID: %s\n", 2116 snip(monitor->data.string)); 2117 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 2118 printf("Monitor name: %s\n", 2119 snip(monitor->data.string)); 2120 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 2121 printf("Monitor range limits, horizontal sync: " 2122 "%d-%d kHz, vertical refresh: " 2123 "%d-%d Hz, max pixel clock: " 2124 "%d MHz\n", 2125 monitor->data.range_data.horizontal_min, 2126 monitor->data.range_data.horizontal_max, 2127 monitor->data.range_data.vertical_min, 2128 monitor->data.range_data.vertical_max, 2129 monitor->data.range_data.pixel_clock_max * 10); 2130 } else { 2131 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 2132 u32 h_total, v_total, vfreq; 2133 2134 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 2135 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 2136 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 2137 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 2138 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 2139 2140 h_total = h_active + h_blanking; 2141 v_total = v_active + v_blanking; 2142 if (v_total > 0 && h_total > 0) 2143 vfreq = pixclock / (v_total * h_total); 2144 else 2145 vfreq = 1; /* Error case */ 2146 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 2147 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 2148 *have_timing = 1; 2149 } 2150 } 2151 2152 /** 2153 * Get the manufacturer name from an EDID info. 2154 * 2155 * @param edid_info The EDID info to be printed 2156 * @param name Returns the string of the manufacturer name 2157 */ 2158 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 2159 { 2160 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 2161 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 2162 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 2163 name[3] = '\0'; 2164 } 2165 2166 void edid_print_info(struct edid1_info *edid_info) 2167 { 2168 int i; 2169 char manufacturer[4]; 2170 unsigned int have_timing = 0; 2171 u32 serial_number; 2172 2173 if (edid_check_info(edid_info)) { 2174 printf("Not a valid EDID\n"); 2175 return; 2176 } 2177 2178 printf("EDID version: %d.%d\n", 2179 edid_info->version, edid_info->revision); 2180 2181 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 2182 2183 edid_get_manufacturer_name(edid_info, manufacturer); 2184 printf("Manufacturer: %s\n", manufacturer); 2185 2186 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 2187 if (serial_number != 0xffffffff) { 2188 if (strcmp(manufacturer, "MAG") == 0) 2189 serial_number -= 0x7000000; 2190 if (strcmp(manufacturer, "OQI") == 0) 2191 serial_number -= 456150000; 2192 if (strcmp(manufacturer, "VSC") == 0) 2193 serial_number -= 640000000; 2194 } 2195 printf("Serial number: %08x\n", serial_number); 2196 printf("Manufactured in week: %d year: %d\n", 2197 edid_info->week, edid_info->year + 1990); 2198 2199 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 2200 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 2201 "digital signal, " : "analog signal, ", 2202 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 2203 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 2204 ", blank to black" : "", 2205 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 2206 ", separate sync" : "", 2207 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 2208 ", composite sync" : "", 2209 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 2210 ", sync on green" : "", 2211 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 2212 ", serration v" : ""); 2213 2214 printf("Monitor is %s\n", 2215 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 2216 2217 printf("Maximum visible display size: %d cm x %d cm\n", 2218 edid_info->max_size_horizontal, 2219 edid_info->max_size_vertical); 2220 2221 printf("Power management features: %s%s, %s%s, %s%s\n", 2222 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 2223 "" : "no ", "active off", 2224 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 2225 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 2226 2227 printf("Estabilished timings:\n"); 2228 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 2229 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 2230 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 2231 printf("\t720x400\t\t88 Hz (XGA2)\n"); 2232 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 2233 printf("\t640x480\t\t60 Hz (VGA)\n"); 2234 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 2235 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 2236 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 2237 printf("\t640x480\t\t72 Hz (VESA)\n"); 2238 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 2239 printf("\t640x480\t\t75 Hz (VESA)\n"); 2240 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 2241 printf("\t800x600\t\t56 Hz (VESA)\n"); 2242 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 2243 printf("\t800x600\t\t60 Hz (VESA)\n"); 2244 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 2245 printf("\t800x600\t\t72 Hz (VESA)\n"); 2246 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 2247 printf("\t800x600\t\t75 Hz (VESA)\n"); 2248 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 2249 printf("\t832x624\t\t75 Hz (Mac II)\n"); 2250 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 2251 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 2252 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 2253 printf("\t1024x768\t60 Hz (VESA)\n"); 2254 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 2255 printf("\t1024x768\t70 Hz (VESA)\n"); 2256 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 2257 printf("\t1024x768\t75 Hz (VESA)\n"); 2258 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 2259 printf("\t1280x1024\t75 (VESA)\n"); 2260 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 2261 printf("\t1152x870\t75 (Mac II)\n"); 2262 2263 /* Standard timings. */ 2264 printf("Standard timings:\n"); 2265 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 2266 unsigned int aspect = 10000; 2267 unsigned int x, y; 2268 unsigned char xres, vfreq; 2269 2270 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 2271 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 2272 if ((xres != vfreq) || 2273 ((xres != 0) && (xres != 1)) || 2274 ((vfreq != 0) && (vfreq != 1))) { 2275 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 2276 i)) { 2277 case ASPECT_625: 2278 aspect = 6250; 2279 break; 2280 case ASPECT_75: 2281 aspect = 7500; 2282 break; 2283 case ASPECT_8: 2284 aspect = 8000; 2285 break; 2286 case ASPECT_5625: 2287 aspect = 5625; 2288 break; 2289 } 2290 x = (xres + 31) * 8; 2291 y = x * aspect / 10000; 2292 printf("\t%dx%d%c\t%d Hz\n", x, y, 2293 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 2294 have_timing = 1; 2295 } 2296 } 2297 2298 /* Detailed timing information. */ 2299 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 2300 i++) { 2301 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 2302 &have_timing); 2303 } 2304 2305 if (!have_timing) 2306 printf("\tNone\n"); 2307 } 2308 2309 /** 2310 * drm_mode_create - create a new display mode 2311 * 2312 * Create a new, cleared drm_display_mode. 2313 * 2314 * Returns: 2315 * Pointer to new mode on success, NULL on error. 2316 */ 2317 static struct drm_display_mode *drm_mode_create(void) 2318 { 2319 struct drm_display_mode *nmode; 2320 2321 nmode = malloc(sizeof(struct drm_display_mode)); 2322 memset(nmode, 0, sizeof(struct drm_display_mode)); 2323 if (!nmode) 2324 return NULL; 2325 2326 return nmode; 2327 } 2328 2329 /** 2330 * drm_mode_destroy - remove a mode 2331 * @mode: mode to remove 2332 * 2333 */ 2334 static void drm_mode_destroy(struct drm_display_mode *mode) 2335 { 2336 if (!mode) 2337 return; 2338 2339 kfree(mode); 2340 } 2341 2342 /** 2343 * drm_cvt_mode -create a modeline based on the CVT algorithm 2344 * @hdisplay: hdisplay size 2345 * @vdisplay: vdisplay size 2346 * @vrefresh: vrefresh rate 2347 * @reduced: whether to use reduced blanking 2348 * @interlaced: whether to compute an interlaced mode 2349 * @margins: whether to add margins (borders) 2350 * 2351 * This function is called to generate the modeline based on CVT algorithm 2352 * according to the hdisplay, vdisplay, vrefresh. 2353 * It is based from the VESA(TM) Coordinated Video Timing Generator by 2354 * Graham Loveridge April 9, 2003 available at 2355 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 2356 * 2357 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 2358 * What I have done is to translate it by using integer calculation. 2359 * 2360 * Returns: 2361 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 2362 * The display mode object is allocated with drm_mode_create(). Returns NULL 2363 * when no mode could be allocated. 2364 */ 2365 static 2366 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 2367 bool reduced, bool interlaced, 2368 bool margins) 2369 { 2370 #define HV_FACTOR 1000 2371 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 2372 #define CVT_MARGIN_PERCENTAGE 18 2373 /* 2) character cell horizontal granularity (pixels) - default 8 */ 2374 #define CVT_H_GRANULARITY 8 2375 /* 3) Minimum vertical porch (lines) - default 3 */ 2376 #define CVT_MIN_V_PORCH 3 2377 /* 4) Minimum number of vertical back porch lines - default 6 */ 2378 #define CVT_MIN_V_BPORCH 6 2379 /* Pixel Clock step (kHz) */ 2380 #define CVT_CLOCK_STEP 250 2381 struct drm_display_mode *drm_mode; 2382 unsigned int vfieldrate, hperiod; 2383 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 2384 int interlace; 2385 2386 /* allocate the drm_display_mode structure. If failure, we will 2387 * return directly 2388 */ 2389 drm_mode = drm_mode_create(); 2390 if (!drm_mode) 2391 return NULL; 2392 2393 /* the CVT default refresh rate is 60Hz */ 2394 if (!vrefresh) 2395 vrefresh = 60; 2396 2397 /* the required field fresh rate */ 2398 if (interlaced) 2399 vfieldrate = vrefresh * 2; 2400 else 2401 vfieldrate = vrefresh; 2402 2403 /* horizontal pixels */ 2404 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 2405 2406 /* determine the left&right borders */ 2407 hmargin = 0; 2408 if (margins) { 2409 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2410 hmargin -= hmargin % CVT_H_GRANULARITY; 2411 } 2412 /* find the total active pixels */ 2413 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 2414 2415 /* find the number of lines per field */ 2416 if (interlaced) 2417 vdisplay_rnd = vdisplay / 2; 2418 else 2419 vdisplay_rnd = vdisplay; 2420 2421 /* find the top & bottom borders */ 2422 vmargin = 0; 2423 if (margins) 2424 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2425 2426 drm_mode->vdisplay = vdisplay + 2 * vmargin; 2427 2428 /* Interlaced */ 2429 if (interlaced) 2430 interlace = 1; 2431 else 2432 interlace = 0; 2433 2434 /* Determine VSync Width from aspect ratio */ 2435 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 2436 vsync = 4; 2437 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 2438 vsync = 5; 2439 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 2440 vsync = 6; 2441 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 2442 vsync = 7; 2443 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 2444 vsync = 7; 2445 else /* custom */ 2446 vsync = 10; 2447 2448 if (!reduced) { 2449 /* simplify the GTF calculation */ 2450 /* 4) Minimum time of vertical sync + back porch interval 2451 * default 550.0 2452 */ 2453 int tmp1, tmp2; 2454 #define CVT_MIN_VSYNC_BP 550 2455 /* 3) Nominal HSync width (% of line period) - default 8 */ 2456 #define CVT_HSYNC_PERCENTAGE 8 2457 unsigned int hblank_percentage; 2458 int vsyncandback_porch, hblank; 2459 2460 /* estimated the horizontal period */ 2461 tmp1 = HV_FACTOR * 1000000 - 2462 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2463 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2464 interlace; 2465 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2466 2467 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2468 /* 9. Find number of lines in sync + backporch */ 2469 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2470 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2471 else 2472 vsyncandback_porch = tmp1; 2473 /* 10. Find number of lines in back porch 2474 * vback_porch = vsyncandback_porch - vsync; 2475 */ 2476 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2477 vsyncandback_porch + CVT_MIN_V_PORCH; 2478 /* 5) Definition of Horizontal blanking time limitation */ 2479 /* Gradient (%/kHz) - default 600 */ 2480 #define CVT_M_FACTOR 600 2481 /* Offset (%) - default 40 */ 2482 #define CVT_C_FACTOR 40 2483 /* Blanking time scaling factor - default 128 */ 2484 #define CVT_K_FACTOR 128 2485 /* Scaling factor weighting - default 20 */ 2486 #define CVT_J_FACTOR 20 2487 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2488 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2489 CVT_J_FACTOR) 2490 /* 12. Find ideal blanking duty cycle from formula */ 2491 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2492 hperiod / 1000; 2493 /* 13. Blanking time */ 2494 if (hblank_percentage < 20 * HV_FACTOR) 2495 hblank_percentage = 20 * HV_FACTOR; 2496 hblank = drm_mode->hdisplay * hblank_percentage / 2497 (100 * HV_FACTOR - hblank_percentage); 2498 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2499 /* 14. find the total pixels per line */ 2500 drm_mode->htotal = drm_mode->hdisplay + hblank; 2501 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2502 drm_mode->hsync_start = drm_mode->hsync_end - 2503 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2504 drm_mode->hsync_start += CVT_H_GRANULARITY - 2505 drm_mode->hsync_start % CVT_H_GRANULARITY; 2506 /* fill the Vsync values */ 2507 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2508 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2509 } else { 2510 /* Reduced blanking */ 2511 /* Minimum vertical blanking interval time - default 460 */ 2512 #define CVT_RB_MIN_VBLANK 460 2513 /* Fixed number of clocks for horizontal sync */ 2514 #define CVT_RB_H_SYNC 32 2515 /* Fixed number of clocks for horizontal blanking */ 2516 #define CVT_RB_H_BLANK 160 2517 /* Fixed number of lines for vertical front porch - default 3*/ 2518 #define CVT_RB_VFPORCH 3 2519 int vbilines; 2520 int tmp1, tmp2; 2521 /* 8. Estimate Horizontal period. */ 2522 tmp1 = HV_FACTOR * 1000000 - 2523 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2524 tmp2 = vdisplay_rnd + 2 * vmargin; 2525 hperiod = tmp1 / (tmp2 * vfieldrate); 2526 /* 9. Find number of lines in vertical blanking */ 2527 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2528 /* 10. Check if vertical blanking is sufficient */ 2529 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2530 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2531 /* 11. Find total number of lines in vertical field */ 2532 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2533 /* 12. Find total number of pixels in a line */ 2534 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2535 /* Fill in HSync values */ 2536 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2537 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2538 /* Fill in VSync values */ 2539 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2540 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2541 } 2542 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2543 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2544 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2545 /* 18/16. Find actual vertical frame frequency */ 2546 /* ignore - just set the mode flag for interlaced */ 2547 if (interlaced) { 2548 drm_mode->vtotal *= 2; 2549 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2550 } 2551 2552 if (reduced) 2553 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2554 DRM_MODE_FLAG_NVSYNC); 2555 else 2556 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2557 DRM_MODE_FLAG_NHSYNC); 2558 2559 return drm_mode; 2560 } 2561 2562 static int 2563 cea_db_payload_len(const u8 *db) 2564 { 2565 return db[0] & 0x1f; 2566 } 2567 2568 static int 2569 cea_db_extended_tag(const u8 *db) 2570 { 2571 return db[1]; 2572 } 2573 2574 static int 2575 cea_db_tag(const u8 *db) 2576 { 2577 return db[0] >> 5; 2578 } 2579 2580 #define for_each_cea_db(cea, i, start, end) \ 2581 for ((i) = (start); (i) < (end) && (i) + \ 2582 cea_db_payload_len(&(cea)[(i)]) < \ 2583 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2584 2585 static int 2586 cea_revision(const u8 *cea) 2587 { 2588 return cea[1]; 2589 } 2590 2591 static int 2592 cea_db_offsets(const u8 *cea, int *start, int *end) 2593 { 2594 /* Data block offset in CEA extension block */ 2595 *start = 4; 2596 *end = cea[2]; 2597 if (*end == 0) 2598 *end = 127; 2599 if (*end < 4 || *end > 127) 2600 return -ERANGE; 2601 2602 /* 2603 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2604 */ 2605 if (*end != 4) { 2606 int i; 2607 2608 i = *start; 2609 while (i < (*end) && 2610 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2611 i += cea_db_payload_len(&(cea)[i]) + 1; 2612 2613 if (cea_db_payload_len(&(cea)[i]) && 2614 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2615 (*end)++; 2616 } 2617 2618 return 0; 2619 } 2620 2621 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2622 { 2623 int hdmi_id; 2624 2625 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2626 return false; 2627 2628 if (cea_db_payload_len(db) < 5) 2629 return false; 2630 2631 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2632 2633 return hdmi_id == HDMI_IEEE_OUI; 2634 } 2635 2636 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2637 { 2638 unsigned int oui; 2639 2640 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2641 return false; 2642 2643 if (cea_db_payload_len(db) < 7) 2644 return false; 2645 2646 oui = db[3] << 16 | db[2] << 8 | db[1]; 2647 2648 return oui == HDMI_FORUM_IEEE_OUI; 2649 } 2650 2651 static bool cea_db_is_y420cmdb(const u8 *db) 2652 { 2653 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2654 return false; 2655 2656 if (!cea_db_payload_len(db)) 2657 return false; 2658 2659 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2660 return false; 2661 2662 return true; 2663 } 2664 2665 static bool cea_db_is_y420vdb(const u8 *db) 2666 { 2667 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2668 return false; 2669 2670 if (!cea_db_payload_len(db)) 2671 return false; 2672 2673 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2674 return false; 2675 2676 return true; 2677 } 2678 2679 static bool drm_valid_hdmi_vic(u8 vic) 2680 { 2681 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2682 } 2683 2684 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2685 const struct drm_display_mode *mode) 2686 { 2687 struct drm_display_mode *mode_buf = data->mode_buf; 2688 2689 if (data->modes >= MODE_LEN) 2690 return; 2691 mode_buf[(data->modes)++] = *mode; 2692 } 2693 2694 static bool drm_valid_cea_vic(u8 vic) 2695 { 2696 return cea_mode_for_vic(vic) ? true : false; 2697 } 2698 2699 static u8 svd_to_vic(u8 svd) 2700 { 2701 /* 0-6 bit vic, 7th bit native mode indicator */ 2702 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2703 return svd & 127; 2704 2705 return svd; 2706 } 2707 2708 static struct drm_display_mode * 2709 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2710 u8 video_index) 2711 { 2712 struct drm_display_mode *newmode; 2713 u8 vic; 2714 2715 if (!video_db || video_index >= video_len) 2716 return NULL; 2717 2718 /* CEA modes are numbered 1..127 */ 2719 vic = svd_to_vic(video_db[video_index]); 2720 if (!drm_valid_cea_vic(vic)) 2721 return NULL; 2722 2723 newmode = drm_mode_create(); 2724 if (!newmode) 2725 return NULL; 2726 2727 *newmode = *cea_mode_for_vic(vic); 2728 newmode->vrefresh = 0; 2729 2730 return newmode; 2731 } 2732 2733 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2734 { 2735 unsigned long *p = map + BIT_WORD(start); 2736 const unsigned int size = start + len; 2737 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2738 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2739 2740 while (len - bits_to_set >= 0) { 2741 *p |= mask_to_set; 2742 len -= bits_to_set; 2743 bits_to_set = BITS_PER_LONG; 2744 mask_to_set = ~0UL; 2745 p++; 2746 } 2747 if (len) { 2748 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2749 *p |= mask_to_set; 2750 } 2751 } 2752 2753 static void 2754 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2755 { 2756 u8 vic = svd_to_vic(svd); 2757 2758 if (!drm_valid_cea_vic(vic)) 2759 return; 2760 2761 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2762 } 2763 2764 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2765 { 2766 int i, modes = 0; 2767 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2768 2769 for (i = 0; i < len; i++) { 2770 struct drm_display_mode *mode; 2771 2772 mode = drm_display_mode_from_vic_index(db, len, i); 2773 if (mode) { 2774 /* 2775 * YCBCR420 capability block contains a bitmap which 2776 * gives the index of CEA modes from CEA VDB, which 2777 * can support YCBCR 420 sampling output also (apart 2778 * from RGB/YCBCR444 etc). 2779 * For example, if the bit 0 in bitmap is set, 2780 * first mode in VDB can support YCBCR420 output too. 2781 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2782 */ 2783 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2784 drm_add_cmdb_modes(db[i], hdmi); 2785 drm_add_hdmi_modes(data, mode); 2786 drm_mode_destroy(mode); 2787 modes++; 2788 } 2789 } 2790 2791 return modes; 2792 } 2793 2794 /* 2795 * do_y420vdb_modes - Parse YCBCR 420 only modes 2796 * @data: the structure that save parsed hdmi edid data 2797 * @svds: start of the data block of CEA YCBCR 420 VDB 2798 * @svds_len: length of the CEA YCBCR 420 VDB 2799 * @hdmi: runtime information about the connected HDMI sink 2800 * 2801 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2802 * which contains modes which can be supported in YCBCR 420 2803 * output format only. 2804 */ 2805 static int 2806 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2807 { 2808 int modes = 0, i; 2809 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2810 2811 for (i = 0; i < svds_len; i++) { 2812 u8 vic = svd_to_vic(svds[i]); 2813 2814 if (!drm_valid_cea_vic(vic)) 2815 continue; 2816 2817 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2818 drm_add_hdmi_modes(data, cea_mode_for_vic(vic)); 2819 modes++; 2820 } 2821 2822 return modes; 2823 } 2824 2825 struct stereo_mandatory_mode { 2826 int width, height, vrefresh; 2827 unsigned int flags; 2828 }; 2829 2830 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2831 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2832 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2833 { 1920, 1080, 50, 2834 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2835 { 1920, 1080, 60, 2836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2837 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2838 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2839 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2840 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2841 }; 2842 2843 static bool 2844 stereo_match_mandatory(const struct drm_display_mode *mode, 2845 const struct stereo_mandatory_mode *stereo_mode) 2846 { 2847 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2848 2849 return mode->hdisplay == stereo_mode->width && 2850 mode->vdisplay == stereo_mode->height && 2851 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2852 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2853 } 2854 2855 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2856 { 2857 const struct drm_display_mode *mode; 2858 int num = data->modes, modes = 0, i, k; 2859 2860 for (k = 0; k < num; k++) { 2861 mode = &data->mode_buf[k]; 2862 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2863 const struct stereo_mandatory_mode *mandatory; 2864 struct drm_display_mode *new_mode; 2865 2866 if (!stereo_match_mandatory(mode, 2867 &stereo_mandatory_modes[i])) 2868 continue; 2869 2870 mandatory = &stereo_mandatory_modes[i]; 2871 new_mode = drm_mode_create(); 2872 if (!new_mode) 2873 continue; 2874 2875 *new_mode = *mode; 2876 new_mode->flags |= mandatory->flags; 2877 drm_add_hdmi_modes(data, new_mode); 2878 drm_mode_destroy(new_mode); 2879 modes++; 2880 } 2881 } 2882 2883 return modes; 2884 } 2885 2886 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2887 const u8 *video_db, u8 video_len, u8 video_index) 2888 { 2889 struct drm_display_mode *newmode; 2890 int modes = 0; 2891 2892 if (structure & (1 << 0)) { 2893 newmode = drm_display_mode_from_vic_index(video_db, 2894 video_len, 2895 video_index); 2896 if (newmode) { 2897 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2898 drm_add_hdmi_modes(data, newmode); 2899 modes++; 2900 drm_mode_destroy(newmode); 2901 } 2902 } 2903 if (structure & (1 << 6)) { 2904 newmode = drm_display_mode_from_vic_index(video_db, 2905 video_len, 2906 video_index); 2907 if (newmode) { 2908 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2909 drm_add_hdmi_modes(data, newmode); 2910 modes++; 2911 drm_mode_destroy(newmode); 2912 } 2913 } 2914 if (structure & (1 << 8)) { 2915 newmode = drm_display_mode_from_vic_index(video_db, 2916 video_len, 2917 video_index); 2918 if (newmode) { 2919 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2920 drm_add_hdmi_modes(data, newmode); 2921 modes++; 2922 drm_mode_destroy(newmode); 2923 } 2924 } 2925 2926 return modes; 2927 } 2928 2929 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2930 { 2931 if (!drm_valid_hdmi_vic(vic)) { 2932 debug("Unknown HDMI VIC: %d\n", vic); 2933 return 0; 2934 } 2935 2936 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2937 2938 return 1; 2939 } 2940 2941 /* 2942 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2943 * @db: start of the CEA vendor specific block 2944 * @len: length of the CEA block payload, ie. one can access up to db[len] 2945 * 2946 * Parses the HDMI VSDB looking for modes to add to @data. This function 2947 * also adds the stereo 3d modes when applicable. 2948 */ 2949 static int 2950 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2951 struct hdmi_edid_data *data) 2952 { 2953 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2954 u8 vic_len, hdmi_3d_len = 0; 2955 u16 mask; 2956 u16 structure_all; 2957 2958 if (len < 8) 2959 goto out; 2960 2961 /* no HDMI_Video_Present */ 2962 if (!(db[8] & (1 << 5))) 2963 goto out; 2964 2965 /* Latency_Fields_Present */ 2966 if (db[8] & (1 << 7)) 2967 offset += 2; 2968 2969 /* I_Latency_Fields_Present */ 2970 if (db[8] & (1 << 6)) 2971 offset += 2; 2972 2973 /* the declared length is not long enough for the 2 first bytes 2974 * of additional video format capabilities 2975 */ 2976 if (len < (8 + offset + 2)) 2977 goto out; 2978 2979 /* 3D_Present */ 2980 offset++; 2981 if (db[8 + offset] & (1 << 7)) { 2982 modes += add_hdmi_mandatory_stereo_modes(data); 2983 2984 /* 3D_Multi_present */ 2985 multi_present = (db[8 + offset] & 0x60) >> 5; 2986 } 2987 2988 offset++; 2989 vic_len = db[8 + offset] >> 5; 2990 hdmi_3d_len = db[8 + offset] & 0x1f; 2991 2992 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2993 u8 vic; 2994 2995 vic = db[9 + offset + i]; 2996 modes += add_hdmi_mode(data, vic); 2997 } 2998 2999 offset += 1 + vic_len; 3000 3001 if (multi_present == 1) 3002 multi_len = 2; 3003 else if (multi_present == 2) 3004 multi_len = 4; 3005 else 3006 multi_len = 0; 3007 3008 if (len < (8 + offset + hdmi_3d_len - 1)) 3009 goto out; 3010 3011 if (hdmi_3d_len < multi_len) 3012 goto out; 3013 3014 if (multi_present == 1 || multi_present == 2) { 3015 /* 3D_Structure_ALL */ 3016 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3017 3018 /* check if 3D_MASK is present */ 3019 if (multi_present == 2) 3020 mask = (db[10 + offset] << 8) | db[11 + offset]; 3021 else 3022 mask = 0xffff; 3023 3024 for (i = 0; i < 16; i++) { 3025 if (mask & (1 << i)) 3026 modes += add_3d_struct_modes(data, 3027 structure_all, 3028 video_db, 3029 video_len, i); 3030 } 3031 } 3032 3033 offset += multi_len; 3034 3035 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3036 int vic_index; 3037 struct drm_display_mode *newmode = NULL; 3038 unsigned int newflag = 0; 3039 bool detail_present; 3040 3041 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3042 3043 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3044 break; 3045 3046 /* 2D_VIC_order_X */ 3047 vic_index = db[8 + offset + i] >> 4; 3048 3049 /* 3D_Structure_X */ 3050 switch (db[8 + offset + i] & 0x0f) { 3051 case 0: 3052 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3053 break; 3054 case 6: 3055 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3056 break; 3057 case 8: 3058 /* 3D_Detail_X */ 3059 if ((db[9 + offset + i] >> 4) == 1) 3060 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3061 break; 3062 } 3063 3064 if (newflag != 0) { 3065 newmode = drm_display_mode_from_vic_index( 3066 video_db, 3067 video_len, 3068 vic_index); 3069 3070 if (newmode) { 3071 newmode->flags |= newflag; 3072 drm_add_hdmi_modes(data, newmode); 3073 modes++; 3074 drm_mode_destroy(newmode); 3075 } 3076 } 3077 3078 if (detail_present) 3079 i++; 3080 } 3081 3082 out: 3083 return modes; 3084 } 3085 3086 /** 3087 * edid_get_quirks - return quirk flags for a given EDID 3088 * @edid: EDID to process 3089 * 3090 * This tells subsequent routines what fixes they need to apply. 3091 */ 3092 static u32 edid_get_quirks(struct edid *edid) 3093 { 3094 struct edid_quirk *quirk; 3095 int i; 3096 3097 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 3098 quirk = &edid_quirk_list[i]; 3099 3100 if (edid_vendor(edid, quirk->vendor) && 3101 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 3102 return quirk->quirks; 3103 } 3104 3105 return 0; 3106 } 3107 3108 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 3109 const u8 *db) 3110 { 3111 struct drm_display_info *info = &data->display_info; 3112 struct drm_hdmi_info *hdmi = &info->hdmi; 3113 u8 map_len = cea_db_payload_len(db) - 1; 3114 u8 count; 3115 u64 map = 0; 3116 3117 if (map_len == 0) { 3118 /* All CEA modes support ycbcr420 sampling also.*/ 3119 hdmi->y420_cmdb_map = U64_MAX; 3120 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3121 return; 3122 } 3123 3124 /* 3125 * This map indicates which of the existing CEA block modes 3126 * from VDB can support YCBCR420 output too. So if bit=0 is 3127 * set, first mode from VDB can support YCBCR420 output too. 3128 * We will parse and keep this map, before parsing VDB itself 3129 * to avoid going through the same block again and again. 3130 * 3131 * Spec is not clear about max possible size of this block. 3132 * Clamping max bitmap block size at 8 bytes. Every byte can 3133 * address 8 CEA modes, in this way this map can address 3134 * 8*8 = first 64 SVDs. 3135 */ 3136 if (map_len > 8) 3137 map_len = 8; 3138 3139 for (count = 0; count < map_len; count++) 3140 map |= (u64)db[2 + count] << (8 * count); 3141 3142 if (map) 3143 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3144 3145 hdmi->y420_cmdb_map = map; 3146 } 3147 3148 static 3149 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 3150 { 3151 switch (max_frl_rate) { 3152 case 1: 3153 *max_lanes = 3; 3154 *max_rate_per_lane = 3; 3155 break; 3156 case 2: 3157 *max_lanes = 3; 3158 *max_rate_per_lane = 6; 3159 break; 3160 case 3: 3161 *max_lanes = 4; 3162 *max_rate_per_lane = 6; 3163 break; 3164 case 4: 3165 *max_lanes = 4; 3166 *max_rate_per_lane = 8; 3167 break; 3168 case 5: 3169 *max_lanes = 4; 3170 *max_rate_per_lane = 10; 3171 break; 3172 case 6: 3173 *max_lanes = 4; 3174 *max_rate_per_lane = 12; 3175 break; 3176 case 0: 3177 default: 3178 *max_lanes = 0; 3179 *max_rate_per_lane = 0; 3180 } 3181 } 3182 3183 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 3184 const u8 *db) 3185 { 3186 u8 dc_mask; 3187 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 3188 3189 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 3190 hdmi->y420_dc_modes |= dc_mask; 3191 } 3192 3193 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 3194 const u8 *hf_vsdb) 3195 { 3196 struct drm_display_info *display = &data->display_info; 3197 struct drm_hdmi_info *hdmi = &display->hdmi; 3198 3199 if (hf_vsdb[6] & 0x80) { 3200 hdmi->scdc.supported = true; 3201 if (hf_vsdb[6] & 0x40) 3202 hdmi->scdc.read_request = true; 3203 } 3204 3205 /* 3206 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 3207 * And as per the spec, three factors confirm this: 3208 * * Availability of a HF-VSDB block in EDID (check) 3209 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 3210 * * SCDC support available (let's check) 3211 * Lets check it out. 3212 */ 3213 3214 if (hf_vsdb[5]) { 3215 /* max clock is 5000 KHz times block value */ 3216 u32 max_tmds_clock = hf_vsdb[5] * 5000; 3217 struct drm_scdc *scdc = &hdmi->scdc; 3218 3219 if (max_tmds_clock > 340000) { 3220 display->max_tmds_clock = max_tmds_clock; 3221 debug("HF-VSDB: max TMDS clock %d kHz\n", 3222 display->max_tmds_clock); 3223 } 3224 3225 if (scdc->supported) { 3226 scdc->scrambling.supported = true; 3227 3228 /* Few sinks support scrambling for cloks < 340M */ 3229 if ((hf_vsdb[6] & 0x8)) 3230 scdc->scrambling.low_rates = true; 3231 } 3232 } 3233 3234 if (hf_vsdb[7]) { 3235 u8 max_frl_rate; 3236 u8 dsc_max_frl_rate; 3237 u8 dsc_max_slices; 3238 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 3239 3240 debug("hdmi_21 sink detected. parsing edid\n"); 3241 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 3242 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 3243 &hdmi->max_frl_rate_per_lane); 3244 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 3245 3246 if (hdmi_dsc->v_1p2) { 3247 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 3248 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 3249 3250 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 3251 hdmi_dsc->bpc_supported = 16; 3252 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 3253 hdmi_dsc->bpc_supported = 12; 3254 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 3255 hdmi_dsc->bpc_supported = 10; 3256 else 3257 hdmi_dsc->bpc_supported = 0; 3258 3259 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 3260 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 3261 &hdmi_dsc->max_frl_rate_per_lane); 3262 hdmi_dsc->total_chunk_kbytes = 3263 hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 3264 3265 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 3266 switch (dsc_max_slices) { 3267 case 1: 3268 hdmi_dsc->max_slices = 1; 3269 hdmi_dsc->clk_per_slice = 340; 3270 break; 3271 case 2: 3272 hdmi_dsc->max_slices = 2; 3273 hdmi_dsc->clk_per_slice = 340; 3274 break; 3275 case 3: 3276 hdmi_dsc->max_slices = 4; 3277 hdmi_dsc->clk_per_slice = 340; 3278 break; 3279 case 4: 3280 hdmi_dsc->max_slices = 8; 3281 hdmi_dsc->clk_per_slice = 340; 3282 break; 3283 case 5: 3284 hdmi_dsc->max_slices = 8; 3285 hdmi_dsc->clk_per_slice = 400; 3286 break; 3287 case 6: 3288 hdmi_dsc->max_slices = 12; 3289 hdmi_dsc->clk_per_slice = 400; 3290 break; 3291 case 7: 3292 hdmi_dsc->max_slices = 16; 3293 hdmi_dsc->clk_per_slice = 400; 3294 break; 3295 case 0: 3296 default: 3297 hdmi_dsc->max_slices = 0; 3298 hdmi_dsc->clk_per_slice = 0; 3299 } 3300 } 3301 } 3302 3303 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 3304 } 3305 3306 /** 3307 * drm_default_rgb_quant_range - default RGB quantization range 3308 * @mode: display mode 3309 * 3310 * Determine the default RGB quantization range for the mode, 3311 * as specified in CEA-861. 3312 * 3313 * Return: The default RGB quantization range for the mode 3314 */ 3315 enum hdmi_quantization_range 3316 drm_default_rgb_quant_range(struct drm_display_mode *mode) 3317 { 3318 /* All CEA modes other than VIC 1 use limited quantization range. */ 3319 return drm_match_cea_mode(mode) > 1 ? 3320 HDMI_QUANTIZATION_RANGE_LIMITED : 3321 HDMI_QUANTIZATION_RANGE_FULL; 3322 } 3323 3324 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 3325 const u8 *hdmi) 3326 { 3327 struct drm_display_info *info = &data->display_info; 3328 unsigned int dc_bpc = 0; 3329 3330 /* HDMI supports at least 8 bpc */ 3331 info->bpc = 8; 3332 3333 if (cea_db_payload_len(hdmi) < 6) 3334 return; 3335 3336 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3337 dc_bpc = 10; 3338 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3339 debug("HDMI sink does deep color 30.\n"); 3340 } 3341 3342 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3343 dc_bpc = 12; 3344 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3345 debug("HDMI sink does deep color 36.\n"); 3346 } 3347 3348 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3349 dc_bpc = 16; 3350 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3351 debug("HDMI sink does deep color 48.\n"); 3352 } 3353 3354 if (dc_bpc == 0) { 3355 debug("No deep color support on this HDMI sink.\n"); 3356 return; 3357 } 3358 3359 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 3360 info->bpc = dc_bpc; 3361 3362 /* YCRCB444 is optional according to spec. */ 3363 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3364 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 3365 debug("HDMI sink does YCRCB444 in deep color.\n"); 3366 } 3367 3368 /* 3369 * Spec says that if any deep color mode is supported at all, 3370 * then deep color 36 bit must be supported. 3371 */ 3372 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 3373 debug("HDMI sink should do DC_36, but does not!\n"); 3374 } 3375 3376 /* 3377 * Search EDID for CEA extension block. 3378 */ 3379 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 3380 { 3381 u8 *edid_ext = NULL; 3382 int i; 3383 3384 /* No EDID or EDID extensions */ 3385 if (!edid || !edid->extensions) 3386 return NULL; 3387 3388 /* Find CEA extension */ 3389 for (i = 0; i < edid->extensions; i++) { 3390 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 3391 if (edid_ext[0] == ext_id) 3392 break; 3393 } 3394 3395 if (i == edid->extensions) 3396 return NULL; 3397 3398 return edid_ext; 3399 } 3400 3401 static u8 *drm_find_cea_extension(struct edid *edid) 3402 { 3403 return drm_find_edid_extension(edid, 0x02); 3404 } 3405 3406 #define AUDIO_BLOCK 0x01 3407 #define VIDEO_BLOCK 0x02 3408 #define VENDOR_BLOCK 0x03 3409 #define SPEAKER_BLOCK 0x04 3410 #define EDID_BASIC_AUDIO BIT(6) 3411 3412 /** 3413 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3414 * @edid: monitor EDID information 3415 * 3416 * Parse the CEA extension according to CEA-861-B. 3417 * 3418 * Return: True if the monitor is HDMI, false if not or unknown. 3419 */ 3420 bool drm_detect_hdmi_monitor(struct edid *edid) 3421 { 3422 u8 *edid_ext; 3423 int i; 3424 int start_offset, end_offset; 3425 3426 edid_ext = drm_find_cea_extension(edid); 3427 if (!edid_ext) 3428 return false; 3429 3430 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3431 return false; 3432 3433 /* 3434 * Because HDMI identifier is in Vendor Specific Block, 3435 * search it from all data blocks of CEA extension. 3436 */ 3437 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3438 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3439 return true; 3440 } 3441 3442 return false; 3443 } 3444 3445 /** 3446 * drm_detect_monitor_audio - check monitor audio capability 3447 * @edid: EDID block to scan 3448 * 3449 * Monitor should have CEA extension block. 3450 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3451 * audio' only. If there is any audio extension block and supported 3452 * audio format, assume at least 'basic audio' support, even if 'basic 3453 * audio' is not defined in EDID. 3454 * 3455 * Return: True if the monitor supports audio, false otherwise. 3456 */ 3457 bool drm_detect_monitor_audio(struct edid *edid) 3458 { 3459 u8 *edid_ext; 3460 int i, j; 3461 bool has_audio = false; 3462 int start_offset, end_offset; 3463 3464 edid_ext = drm_find_cea_extension(edid); 3465 if (!edid_ext) 3466 goto end; 3467 3468 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3469 3470 if (has_audio) { 3471 printf("Monitor has basic audio support\n"); 3472 goto end; 3473 } 3474 3475 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3476 goto end; 3477 3478 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3479 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3480 has_audio = true; 3481 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 3482 j += 3) 3483 debug("CEA audio format %d\n", 3484 (edid_ext[i + j] >> 3) & 0xf); 3485 goto end; 3486 } 3487 } 3488 end: 3489 return has_audio; 3490 } 3491 3492 static void 3493 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 3494 { 3495 struct drm_display_info *info = &data->display_info; 3496 u8 len = cea_db_payload_len(db); 3497 3498 if (len >= 6) 3499 info->dvi_dual = db[6] & 1; 3500 if (len >= 7) 3501 info->max_tmds_clock = db[7] * 5000; 3502 3503 drm_parse_hdmi_deep_color_info(data, db); 3504 } 3505 3506 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 3507 struct edid *edid) 3508 { 3509 struct drm_display_info *info = &data->display_info; 3510 const u8 *edid_ext; 3511 int i, start, end; 3512 3513 edid_ext = drm_find_cea_extension(edid); 3514 if (!edid_ext) 3515 return; 3516 3517 info->cea_rev = edid_ext[1]; 3518 3519 /* The existence of a CEA block should imply RGB support */ 3520 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3521 if (edid_ext[3] & EDID_CEA_YCRCB444) 3522 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3523 if (edid_ext[3] & EDID_CEA_YCRCB422) 3524 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3525 3526 if (cea_db_offsets(edid_ext, &start, &end)) 3527 return; 3528 3529 for_each_cea_db(edid_ext, i, start, end) { 3530 const u8 *db = &edid_ext[i]; 3531 3532 if (cea_db_is_hdmi_vsdb(db)) 3533 drm_parse_hdmi_vsdb_video(data, db); 3534 if (cea_db_is_hdmi_forum_vsdb(db)) 3535 drm_parse_hdmi_forum_vsdb(data, db); 3536 if (cea_db_is_y420cmdb(db)) 3537 drm_parse_y420cmdb_bitmap(data, db); 3538 } 3539 } 3540 3541 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 3542 { 3543 struct drm_display_info *info = &data->display_info; 3544 3545 info->width_mm = edid->width_cm * 10; 3546 info->height_mm = edid->height_cm * 10; 3547 3548 /* driver figures it out in this case */ 3549 info->bpc = 0; 3550 info->color_formats = 0; 3551 info->cea_rev = 0; 3552 info->max_tmds_clock = 0; 3553 info->dvi_dual = false; 3554 info->edid_hdmi_dc_modes = 0; 3555 3556 memset(&info->hdmi, 0, sizeof(info->hdmi)); 3557 3558 if (edid->revision < 3) 3559 return; 3560 3561 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3562 return; 3563 3564 drm_parse_cea_ext(data, edid); 3565 3566 /* 3567 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3568 * 3569 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3570 * tells us to assume 8 bpc color depth if the EDID doesn't have 3571 * extensions which tell otherwise. 3572 */ 3573 if ((info->bpc == 0) && (edid->revision < 4) && 3574 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3575 info->bpc = 8; 3576 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3577 } 3578 3579 /* Only defined for 1.4 with digital displays */ 3580 if (edid->revision < 4) 3581 return; 3582 3583 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3584 case DRM_EDID_DIGITAL_DEPTH_6: 3585 info->bpc = 6; 3586 break; 3587 case DRM_EDID_DIGITAL_DEPTH_8: 3588 info->bpc = 8; 3589 break; 3590 case DRM_EDID_DIGITAL_DEPTH_10: 3591 info->bpc = 10; 3592 break; 3593 case DRM_EDID_DIGITAL_DEPTH_12: 3594 info->bpc = 12; 3595 break; 3596 case DRM_EDID_DIGITAL_DEPTH_14: 3597 info->bpc = 14; 3598 break; 3599 case DRM_EDID_DIGITAL_DEPTH_16: 3600 info->bpc = 16; 3601 break; 3602 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3603 default: 3604 info->bpc = 0; 3605 break; 3606 } 3607 3608 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3609 info->bpc); 3610 3611 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3612 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3613 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3614 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3615 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3616 } 3617 3618 static 3619 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3620 { 3621 const u8 *cea = drm_find_cea_extension(edid); 3622 const u8 *db, *hdmi = NULL, *video = NULL; 3623 u8 dbl, hdmi_len, video_len = 0; 3624 int modes = 0; 3625 3626 if (cea && cea_revision(cea) >= 3) { 3627 int i, start, end; 3628 3629 if (cea_db_offsets(cea, &start, &end)) 3630 return 0; 3631 3632 for_each_cea_db(cea, i, start, end) { 3633 db = &cea[i]; 3634 dbl = cea_db_payload_len(db); 3635 3636 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3637 video = db + 1; 3638 video_len = dbl; 3639 modes += do_cea_modes(data, video, dbl); 3640 } else if (cea_db_is_hdmi_vsdb(db)) { 3641 hdmi = db; 3642 hdmi_len = dbl; 3643 } else if (cea_db_is_y420vdb(db)) { 3644 const u8 *vdb420 = &db[2]; 3645 3646 /* Add 4:2:0(only) modes present in EDID */ 3647 modes += do_y420vdb_modes(data, vdb420, 3648 dbl - 1); 3649 } 3650 } 3651 } 3652 3653 /* 3654 * We parse the HDMI VSDB after having added the cea modes as we will 3655 * be patching their flags when the sink supports stereo 3D. 3656 */ 3657 if (hdmi) 3658 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3659 video_len, data); 3660 3661 return modes; 3662 } 3663 3664 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3665 3666 static void 3667 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3668 { 3669 int i, n = 0; 3670 u8 d = ext[0x02]; 3671 u8 *det_base = ext + d; 3672 3673 if (d < 4 || d > 127) 3674 return; 3675 3676 n = (127 - d) / 18; 3677 for (i = 0; i < n; i++) 3678 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3679 } 3680 3681 static void 3682 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3683 { 3684 unsigned int i, n = min((int)ext[0x02], 6); 3685 u8 *det_base = ext + 5; 3686 3687 if (ext[0x01] != 1) 3688 return; /* unknown version */ 3689 3690 for (i = 0; i < n; i++) 3691 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3692 } 3693 3694 static void 3695 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3696 { 3697 int i; 3698 struct edid *edid = (struct edid *)raw_edid; 3699 3700 if (!edid) 3701 return; 3702 3703 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3704 cb(&edid->detailed_timings[i], closure); 3705 3706 for (i = 1; i <= raw_edid[0x7e]; i++) { 3707 u8 *ext = raw_edid + (i * EDID_SIZE); 3708 3709 switch (*ext) { 3710 case CEA_EXT: 3711 cea_for_each_detailed_block(ext, cb, closure); 3712 break; 3713 case VTB_EXT: 3714 vtb_for_each_detailed_block(ext, cb, closure); 3715 break; 3716 default: 3717 break; 3718 } 3719 } 3720 } 3721 3722 /* 3723 * EDID is delightfully ambiguous about how interlaced modes are to be 3724 * encoded. Our internal representation is of frame height, but some 3725 * HDTV detailed timings are encoded as field height. 3726 * 3727 * The format list here is from CEA, in frame size. Technically we 3728 * should be checking refresh rate too. Whatever. 3729 */ 3730 static void 3731 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3732 struct detailed_pixel_timing *pt) 3733 { 3734 int i; 3735 3736 static const struct { 3737 int w, h; 3738 } cea_interlaced[] = { 3739 { 1920, 1080 }, 3740 { 720, 480 }, 3741 { 1440, 480 }, 3742 { 2880, 480 }, 3743 { 720, 576 }, 3744 { 1440, 576 }, 3745 { 2880, 576 }, 3746 }; 3747 3748 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3749 return; 3750 3751 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3752 if ((mode->hdisplay == cea_interlaced[i].w) && 3753 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3754 mode->vdisplay *= 2; 3755 mode->vsync_start *= 2; 3756 mode->vsync_end *= 2; 3757 mode->vtotal *= 2; 3758 mode->vtotal |= 1; 3759 } 3760 } 3761 3762 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3763 } 3764 3765 /** 3766 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3767 * @edid: EDID block 3768 * @timing: EDID detailed timing info 3769 * @quirks: quirks to apply 3770 * 3771 * An EDID detailed timing block contains enough info for us to create and 3772 * return a new struct drm_display_mode. 3773 */ 3774 static 3775 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3776 struct detailed_timing *timing, 3777 u32 quirks) 3778 { 3779 struct drm_display_mode *mode; 3780 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3781 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3782 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3783 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3784 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3785 unsigned hsync_offset = 3786 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3787 pt->hsync_offset_lo; 3788 unsigned hsync_pulse_width = 3789 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3790 pt->hsync_pulse_width_lo; 3791 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3792 2 | pt->vsync_offset_pulse_width_lo >> 4; 3793 unsigned vsync_pulse_width = 3794 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3795 (pt->vsync_offset_pulse_width_lo & 0xf); 3796 3797 /* ignore tiny modes */ 3798 if (hactive < 64 || vactive < 64) 3799 return NULL; 3800 3801 if (pt->misc & DRM_EDID_PT_STEREO) { 3802 debug("stereo mode not supported\n"); 3803 return NULL; 3804 } 3805 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3806 debug("composite sync not supported\n"); 3807 3808 /* it is incorrect if hsync/vsync width is zero */ 3809 if (!hsync_pulse_width || !vsync_pulse_width) { 3810 debug("Incorrect Detailed timing. "); 3811 debug("Wrong Hsync/Vsync pulse width\n"); 3812 return NULL; 3813 } 3814 3815 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3816 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3817 if (!mode) 3818 return NULL; 3819 3820 goto set_refresh; 3821 } 3822 3823 mode = drm_mode_create(); 3824 if (!mode) 3825 return NULL; 3826 3827 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3828 timing->pixel_clock = cpu_to_le16(1088); 3829 3830 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3831 3832 mode->hdisplay = hactive; 3833 mode->hsync_start = mode->hdisplay + hsync_offset; 3834 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3835 mode->htotal = mode->hdisplay + hblank; 3836 3837 mode->vdisplay = vactive; 3838 mode->vsync_start = mode->vdisplay + vsync_offset; 3839 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3840 mode->vtotal = mode->vdisplay + vblank; 3841 3842 /* Some EDIDs have bogus h/vtotal values */ 3843 if (mode->hsync_end > mode->htotal) 3844 mode->htotal = mode->hsync_end + 1; 3845 if (mode->vsync_end > mode->vtotal) 3846 mode->vtotal = mode->vsync_end + 1; 3847 3848 drm_mode_do_interlace_quirk(mode, pt); 3849 3850 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3851 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3852 DRM_EDID_PT_VSYNC_POSITIVE; 3853 3854 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3855 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3856 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3857 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3858 3859 set_refresh: 3860 3861 mode->type = DRM_MODE_TYPE_DRIVER; 3862 mode->vrefresh = drm_get_vrefresh(mode); 3863 3864 return mode; 3865 } 3866 3867 /* 3868 * Calculate the alternate clock for the CEA mode 3869 * (60Hz vs. 59.94Hz etc.) 3870 */ 3871 static unsigned int 3872 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3873 { 3874 unsigned int clock = cea_mode->clock; 3875 3876 if (cea_mode->vrefresh % 6 != 0) 3877 return clock; 3878 3879 /* 3880 * edid_cea_modes contains the 59.94Hz 3881 * variant for 240 and 480 line modes, 3882 * and the 60Hz variant otherwise. 3883 */ 3884 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3885 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3886 else 3887 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3888 3889 return clock; 3890 } 3891 3892 /** 3893 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3894 * @mode1: first mode 3895 * @mode2: second mode 3896 * 3897 * Check to see if @mode1 and @mode2 are equivalent, but 3898 * don't check the pixel clocks nor the stereo layout. 3899 * 3900 * Returns: 3901 * True if the modes are equal, false otherwise. 3902 */ 3903 3904 static 3905 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3906 const struct drm_display_mode *mode2) 3907 { 3908 unsigned int flags_mask = 3909 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3910 3911 if (mode1->hdisplay == mode2->hdisplay && 3912 mode1->hsync_start == mode2->hsync_start && 3913 mode1->hsync_end == mode2->hsync_end && 3914 mode1->htotal == mode2->htotal && 3915 mode1->vdisplay == mode2->vdisplay && 3916 mode1->vsync_start == mode2->vsync_start && 3917 mode1->vsync_end == mode2->vsync_end && 3918 mode1->vtotal == mode2->vtotal && 3919 mode1->vscan == mode2->vscan && 3920 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3921 return true; 3922 3923 return false; 3924 } 3925 3926 /** 3927 * drm_mode_equal_no_clocks - test modes for equality 3928 * @mode1: first mode 3929 * @mode2: second mode 3930 * 3931 * Check to see if @mode1 and @mode2 are equivalent, but 3932 * don't check the pixel clocks. 3933 * 3934 * Returns: 3935 * True if the modes are equal, false otherwise. 3936 */ 3937 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3938 const struct drm_display_mode *mode2) 3939 { 3940 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3941 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3942 return false; 3943 3944 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3945 } 3946 3947 static 3948 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3949 unsigned int clock_tolerance) 3950 { 3951 u8 vic; 3952 3953 if (!to_match->clock) 3954 return 0; 3955 3956 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3957 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 3958 unsigned int clock1, clock2; 3959 3960 /* Check both 60Hz and 59.94Hz */ 3961 clock1 = cea_mode->clock; 3962 clock2 = cea_mode_alternate_clock(cea_mode); 3963 3964 if (abs(to_match->clock - clock1) > clock_tolerance && 3965 abs(to_match->clock - clock2) > clock_tolerance) 3966 continue; 3967 3968 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3969 return vic; 3970 } 3971 3972 return 0; 3973 } 3974 3975 static unsigned int 3976 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3977 { 3978 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3979 return hdmi_mode->clock; 3980 3981 return cea_mode_alternate_clock(hdmi_mode); 3982 } 3983 3984 static 3985 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3986 unsigned int clock_tolerance) 3987 { 3988 u8 vic; 3989 3990 if (!to_match->clock) 3991 return 0; 3992 3993 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3994 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3995 unsigned int clock1, clock2; 3996 3997 /* Make sure to also match alternate clocks */ 3998 clock1 = hdmi_mode->clock; 3999 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4000 4001 if (abs(to_match->clock - clock1) > clock_tolerance && 4002 abs(to_match->clock - clock2) > clock_tolerance) 4003 continue; 4004 4005 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 4006 return vic; 4007 } 4008 4009 return 0; 4010 } 4011 4012 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4013 { 4014 const struct drm_display_mode *cea_mode; 4015 int clock1, clock2, clock; 4016 u8 vic; 4017 const char *type; 4018 4019 /* 4020 * allow 5kHz clock difference either way to account for 4021 * the 10kHz clock resolution limit of detailed timings. 4022 */ 4023 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4024 if (drm_valid_cea_vic(vic)) { 4025 type = "CEA"; 4026 cea_mode = cea_mode_for_vic(vic); 4027 clock1 = cea_mode->clock; 4028 clock2 = cea_mode_alternate_clock(cea_mode); 4029 } else { 4030 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4031 if (drm_valid_hdmi_vic(vic)) { 4032 type = "HDMI"; 4033 cea_mode = &edid_4k_modes[vic]; 4034 clock1 = cea_mode->clock; 4035 clock2 = hdmi_mode_alternate_clock(cea_mode); 4036 } else { 4037 return; 4038 } 4039 } 4040 4041 /* pick whichever is closest */ 4042 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4043 clock = clock1; 4044 else 4045 clock = clock2; 4046 4047 if (mode->clock == clock) 4048 return; 4049 4050 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4051 type, vic, mode->clock, clock); 4052 mode->clock = clock; 4053 } 4054 4055 static void 4056 do_detailed_mode(struct detailed_timing *timing, void *c) 4057 { 4058 struct detailed_mode_closure *closure = c; 4059 struct drm_display_mode *newmode; 4060 4061 if (timing->pixel_clock) { 4062 newmode = drm_mode_detailed( 4063 closure->edid, timing, 4064 closure->quirks); 4065 if (!newmode) 4066 return; 4067 4068 if (closure->preferred) 4069 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4070 4071 /* 4072 * Detailed modes are limited to 10kHz pixel clock resolution, 4073 * so fix up anything that looks like CEA/HDMI mode, 4074 * but the clock is just slightly off. 4075 */ 4076 fixup_detailed_cea_mode_clock(newmode); 4077 drm_add_hdmi_modes(closure->data, newmode); 4078 drm_mode_destroy(newmode); 4079 closure->modes++; 4080 closure->preferred = 0; 4081 } 4082 } 4083 4084 /* 4085 * add_detailed_modes - Add modes from detailed timings 4086 * @data: attached data 4087 * @edid: EDID block to scan 4088 * @quirks: quirks to apply 4089 */ 4090 static int 4091 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 4092 u32 quirks) 4093 { 4094 struct detailed_mode_closure closure = { 4095 .data = data, 4096 .edid = edid, 4097 .preferred = 1, 4098 .quirks = quirks, 4099 }; 4100 4101 if (closure.preferred && !version_greater(edid, 1, 3)) 4102 closure.preferred = 4103 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 4104 4105 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 4106 4107 return closure.modes; 4108 } 4109 4110 static int drm_cvt_modes(struct hdmi_edid_data *data, 4111 struct detailed_timing *timing) 4112 { 4113 int i, j, modes = 0; 4114 struct drm_display_mode *newmode; 4115 struct cvt_timing *cvt; 4116 const int rates[] = { 60, 85, 75, 60, 50 }; 4117 const u8 empty[3] = { 0, 0, 0 }; 4118 4119 for (i = 0; i < 4; i++) { 4120 int uninitialized_var(width), height; 4121 4122 cvt = &timing->data.other_data.data.cvt[i]; 4123 4124 if (!memcmp(cvt->code, empty, 3)) 4125 continue; 4126 4127 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4128 switch (cvt->code[1] & 0x0c) { 4129 case 0x00: 4130 width = height * 4 / 3; 4131 break; 4132 case 0x04: 4133 width = height * 16 / 9; 4134 break; 4135 case 0x08: 4136 width = height * 16 / 10; 4137 break; 4138 case 0x0c: 4139 width = height * 15 / 9; 4140 break; 4141 } 4142 4143 for (j = 1; j < 5; j++) { 4144 if (cvt->code[2] & (1 << j)) { 4145 newmode = drm_cvt_mode(width, height, 4146 rates[j], j == 0, 4147 false, false); 4148 if (newmode) { 4149 drm_add_hdmi_modes(data, newmode); 4150 modes++; 4151 drm_mode_destroy(newmode); 4152 } 4153 } 4154 } 4155 } 4156 4157 return modes; 4158 } 4159 4160 static void 4161 do_cvt_mode(struct detailed_timing *timing, void *c) 4162 { 4163 struct detailed_mode_closure *closure = c; 4164 struct detailed_non_pixel *data = &timing->data.other_data; 4165 4166 if (data->type == EDID_DETAIL_CVT_3BYTE) 4167 closure->modes += drm_cvt_modes(closure->data, timing); 4168 } 4169 4170 static int 4171 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 4172 { 4173 struct detailed_mode_closure closure = { 4174 .data = data, 4175 .edid = edid, 4176 }; 4177 4178 if (version_greater(edid, 1, 2)) 4179 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 4180 4181 /* XXX should also look for CVT codes in VTB blocks */ 4182 4183 return closure.modes; 4184 } 4185 4186 static void 4187 find_gtf2(struct detailed_timing *t, void *data) 4188 { 4189 u8 *r = (u8 *)t; 4190 4191 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 4192 *(u8 **)data = r; 4193 } 4194 4195 /* Secondary GTF curve kicks in above some break frequency */ 4196 static int 4197 drm_gtf2_hbreak(struct edid *edid) 4198 { 4199 u8 *r = NULL; 4200 4201 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4202 return r ? (r[12] * 2) : 0; 4203 } 4204 4205 static int 4206 drm_gtf2_2c(struct edid *edid) 4207 { 4208 u8 *r = NULL; 4209 4210 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4211 return r ? r[13] : 0; 4212 } 4213 4214 static int 4215 drm_gtf2_m(struct edid *edid) 4216 { 4217 u8 *r = NULL; 4218 4219 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4220 return r ? (r[15] << 8) + r[14] : 0; 4221 } 4222 4223 static int 4224 drm_gtf2_k(struct edid *edid) 4225 { 4226 u8 *r = NULL; 4227 4228 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4229 return r ? r[16] : 0; 4230 } 4231 4232 static int 4233 drm_gtf2_2j(struct edid *edid) 4234 { 4235 u8 *r = NULL; 4236 4237 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4238 return r ? r[17] : 0; 4239 } 4240 4241 /** 4242 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 4243 * @edid: EDID block to scan 4244 */ 4245 static int standard_timing_level(struct edid *edid) 4246 { 4247 if (edid->revision >= 2) { 4248 if (edid->revision >= 4 && 4249 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 4250 return LEVEL_CVT; 4251 if (drm_gtf2_hbreak(edid)) 4252 return LEVEL_GTF2; 4253 return LEVEL_GTF; 4254 } 4255 return LEVEL_DMT; 4256 } 4257 4258 /* 4259 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 4260 * monitors fill with ascii space (0x20) instead. 4261 */ 4262 static int 4263 bad_std_timing(u8 a, u8 b) 4264 { 4265 return (a == 0x00 && b == 0x00) || 4266 (a == 0x01 && b == 0x01) || 4267 (a == 0x20 && b == 0x20); 4268 } 4269 4270 static void 4271 is_rb(struct detailed_timing *t, void *data) 4272 { 4273 u8 *r = (u8 *)t; 4274 4275 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 4276 if (r[15] & 0x10) 4277 *(bool *)data = true; 4278 } 4279 4280 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 4281 static bool 4282 drm_monitor_supports_rb(struct edid *edid) 4283 { 4284 if (edid->revision >= 4) { 4285 bool ret = false; 4286 4287 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 4288 return ret; 4289 } 4290 4291 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 4292 } 4293 4294 static bool 4295 mode_is_rb(const struct drm_display_mode *mode) 4296 { 4297 return (mode->htotal - mode->hdisplay == 160) && 4298 (mode->hsync_end - mode->hdisplay == 80) && 4299 (mode->hsync_end - mode->hsync_start == 32) && 4300 (mode->vsync_start - mode->vdisplay == 3); 4301 } 4302 4303 /* 4304 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 4305 * @hsize: Mode width 4306 * @vsize: Mode height 4307 * @fresh: Mode refresh rate 4308 * @rb: Mode reduced-blanking-ness 4309 * 4310 * Walk the DMT mode list looking for a match for the given parameters. 4311 * 4312 * Return: A newly allocated copy of the mode, or NULL if not found. 4313 */ 4314 static struct drm_display_mode *drm_mode_find_dmt( 4315 int hsize, int vsize, int fresh, 4316 bool rb) 4317 { 4318 int i; 4319 struct drm_display_mode *newmode; 4320 4321 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4322 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4323 4324 if (hsize != ptr->hdisplay) 4325 continue; 4326 if (vsize != ptr->vdisplay) 4327 continue; 4328 if (fresh != drm_get_vrefresh(ptr)) 4329 continue; 4330 if (rb != mode_is_rb(ptr)) 4331 continue; 4332 4333 newmode = drm_mode_create(); 4334 *newmode = *ptr; 4335 return newmode; 4336 } 4337 4338 return NULL; 4339 } 4340 4341 static struct drm_display_mode * 4342 drm_gtf_mode_complex(int hdisplay, int vdisplay, 4343 int vrefresh, bool interlaced, int margins, 4344 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 4345 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 4346 #define GTF_MARGIN_PERCENTAGE 18 4347 /* 2) character cell horizontal granularity (pixels) - default 8 */ 4348 #define GTF_CELL_GRAN 8 4349 /* 3) Minimum vertical porch (lines) - default 3 */ 4350 #define GTF_MIN_V_PORCH 1 4351 /* width of vsync in lines */ 4352 #define V_SYNC_RQD 3 4353 /* width of hsync as % of total line */ 4354 #define H_SYNC_PERCENT 8 4355 /* min time of vsync + back porch (microsec) */ 4356 #define MIN_VSYNC_PLUS_BP 550 4357 /* C' and M' are part of the Blanking Duty Cycle computation */ 4358 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 4359 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 4360 struct drm_display_mode *drm_mode; 4361 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 4362 int top_margin, bottom_margin; 4363 int interlace; 4364 unsigned int hfreq_est; 4365 int vsync_plus_bp; 4366 unsigned int vtotal_lines; 4367 int left_margin, right_margin; 4368 unsigned int total_active_pixels, ideal_duty_cycle; 4369 unsigned int hblank, total_pixels, pixel_freq; 4370 int hsync, hfront_porch, vodd_front_porch_lines; 4371 unsigned int tmp1, tmp2; 4372 4373 drm_mode = drm_mode_create(); 4374 if (!drm_mode) 4375 return NULL; 4376 4377 /* 1. In order to give correct results, the number of horizontal 4378 * pixels requested is first processed to ensure that it is divisible 4379 * by the character size, by rounding it to the nearest character 4380 * cell boundary: 4381 */ 4382 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4383 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 4384 4385 /* 2. If interlace is requested, the number of vertical lines assumed 4386 * by the calculation must be halved, as the computation calculates 4387 * the number of vertical lines per field. 4388 */ 4389 if (interlaced) 4390 vdisplay_rnd = vdisplay / 2; 4391 else 4392 vdisplay_rnd = vdisplay; 4393 4394 /* 3. Find the frame rate required: */ 4395 if (interlaced) 4396 vfieldrate_rqd = vrefresh * 2; 4397 else 4398 vfieldrate_rqd = vrefresh; 4399 4400 /* 4. Find number of lines in Top margin: */ 4401 top_margin = 0; 4402 if (margins) 4403 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4404 1000; 4405 /* 5. Find number of lines in bottom margin: */ 4406 bottom_margin = top_margin; 4407 4408 /* 6. If interlace is required, then set variable interlace: */ 4409 if (interlaced) 4410 interlace = 1; 4411 else 4412 interlace = 0; 4413 4414 /* 7. Estimate the Horizontal frequency */ 4415 { 4416 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 4417 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 4418 2 + interlace; 4419 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 4420 } 4421 4422 /* 8. Find the number of lines in V sync + back porch */ 4423 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 4424 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 4425 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 4426 /* 9. Find the number of lines in V back porch alone: 4427 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 4428 */ 4429 /* 10. Find the total number of lines in Vertical field period: */ 4430 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 4431 vsync_plus_bp + GTF_MIN_V_PORCH; 4432 /* 11. Estimate the Vertical field frequency: 4433 * vfieldrate_est = hfreq_est / vtotal_lines; 4434 */ 4435 4436 /* 12. Find the actual horizontal period: 4437 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 4438 */ 4439 /* 13. Find the actual Vertical field frequency: 4440 * vfield_rate = hfreq_est / vtotal_lines; 4441 */ 4442 /* 14. Find the Vertical frame frequency: 4443 * if (interlaced) 4444 * vframe_rate = vfield_rate / 2; 4445 * else 4446 * vframe_rate = vfield_rate; 4447 */ 4448 /* 15. Find number of pixels in left margin: */ 4449 if (margins) 4450 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4451 1000; 4452 else 4453 left_margin = 0; 4454 4455 /* 16.Find number of pixels in right margin: */ 4456 right_margin = left_margin; 4457 /* 17.Find total number of active pixels in image and left and right */ 4458 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 4459 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 4460 ideal_duty_cycle = GTF_C_PRIME * 1000 - 4461 (GTF_M_PRIME * 1000000 / hfreq_est); 4462 /* 19.Find the number of pixels in the blanking time to the nearest 4463 * double character cell: 4464 */ 4465 hblank = total_active_pixels * ideal_duty_cycle / 4466 (100000 - ideal_duty_cycle); 4467 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 4468 hblank = hblank * 2 * GTF_CELL_GRAN; 4469 /* 20.Find total number of pixels: */ 4470 total_pixels = total_active_pixels + hblank; 4471 /* 21.Find pixel clock frequency: */ 4472 pixel_freq = total_pixels * hfreq_est / 1000; 4473 /* Stage 1 computations are now complete; I should really pass 4474 * the results to another function and do the Stage 2 computations, 4475 * but I only need a few more values so I'll just append the 4476 * computations here for now 4477 */ 4478 4479 /* 17. Find the number of pixels in the horizontal sync period: */ 4480 hsync = H_SYNC_PERCENT * total_pixels / 100; 4481 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4482 hsync = hsync * GTF_CELL_GRAN; 4483 /* 18. Find the number of pixels in horizontal front porch period */ 4484 hfront_porch = hblank / 2 - hsync; 4485 /* 36. Find the number of lines in the odd front porch period: */ 4486 vodd_front_porch_lines = GTF_MIN_V_PORCH; 4487 4488 /* finally, pack the results in the mode struct */ 4489 drm_mode->hdisplay = hdisplay_rnd; 4490 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 4491 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 4492 drm_mode->htotal = total_pixels; 4493 drm_mode->vdisplay = vdisplay_rnd; 4494 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 4495 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 4496 drm_mode->vtotal = vtotal_lines; 4497 4498 drm_mode->clock = pixel_freq; 4499 4500 if (interlaced) { 4501 drm_mode->vtotal *= 2; 4502 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 4503 } 4504 4505 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 4506 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 4507 else 4508 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 4509 4510 return drm_mode; 4511 } 4512 4513 /** 4514 * drm_gtf_mode - create the mode based on the GTF algorithm 4515 * @hdisplay: hdisplay size 4516 * @vdisplay: vdisplay size 4517 * @vrefresh: vrefresh rate. 4518 * @interlaced: whether to compute an interlaced mode 4519 * @margins: desired margin (borders) size 4520 * 4521 * return the mode based on GTF algorithm 4522 * 4523 * This function is to create the mode based on the GTF algorithm. 4524 * Generalized Timing Formula is derived from: 4525 * GTF Spreadsheet by Andy Morrish (1/5/97) 4526 * available at http://www.vesa.org 4527 * 4528 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 4529 * What I have done is to translate it by using integer calculation. 4530 * I also refer to the function of fb_get_mode in the file of 4531 * drivers/video/fbmon.c 4532 * 4533 * Standard GTF parameters: 4534 * M = 600 4535 * C = 40 4536 * K = 128 4537 * J = 20 4538 * 4539 * Returns: 4540 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 4541 * The display mode object is allocated with drm_mode_create(). Returns NULL 4542 * when no mode could be allocated. 4543 */ 4544 static struct drm_display_mode * 4545 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 4546 bool interlaced, int margins) 4547 { 4548 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 4549 interlaced, margins, 4550 600, 40 * 2, 128, 20 * 2); 4551 } 4552 4553 /** drm_mode_hsync - get the hsync of a mode 4554 * @mode: mode 4555 * 4556 * Returns: 4557 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 4558 * value first if it is not yet set. 4559 */ 4560 static int drm_mode_hsync(const struct drm_display_mode *mode) 4561 { 4562 unsigned int calc_val; 4563 4564 if (mode->htotal < 0) 4565 return 0; 4566 4567 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 4568 calc_val += 500; /* round to 1000Hz */ 4569 calc_val /= 1000; /* truncate to kHz */ 4570 4571 return calc_val; 4572 } 4573 4574 /** 4575 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 4576 * @data: the structure that save parsed hdmi edid data 4577 * @edid: EDID block to scan 4578 * @t: standard timing params 4579 * 4580 * Take the standard timing params (in this case width, aspect, and refresh) 4581 * and convert them into a real mode using CVT/GTF/DMT. 4582 */ 4583 static struct drm_display_mode * 4584 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4585 struct std_timing *t) 4586 { 4587 struct drm_display_mode *mode = NULL; 4588 int i, hsize, vsize; 4589 int vrefresh_rate; 4590 int num = data->modes; 4591 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4592 >> EDID_TIMING_ASPECT_SHIFT; 4593 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4594 >> EDID_TIMING_VFREQ_SHIFT; 4595 int timing_level = standard_timing_level(edid); 4596 4597 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4598 return NULL; 4599 4600 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4601 hsize = t->hsize * 8 + 248; 4602 /* vrefresh_rate = vfreq + 60 */ 4603 vrefresh_rate = vfreq + 60; 4604 /* the vdisplay is calculated based on the aspect ratio */ 4605 if (aspect_ratio == 0) { 4606 if (edid->revision < 3) 4607 vsize = hsize; 4608 else 4609 vsize = (hsize * 10) / 16; 4610 } else if (aspect_ratio == 1) { 4611 vsize = (hsize * 3) / 4; 4612 } else if (aspect_ratio == 2) { 4613 vsize = (hsize * 4) / 5; 4614 } else { 4615 vsize = (hsize * 9) / 16; 4616 } 4617 4618 /* HDTV hack, part 1 */ 4619 if (vrefresh_rate == 60 && 4620 ((hsize == 1360 && vsize == 765) || 4621 (hsize == 1368 && vsize == 769))) { 4622 hsize = 1366; 4623 vsize = 768; 4624 } 4625 4626 /* 4627 * If we already has a mode for this size and refresh 4628 * rate (because it came from detailed or CVT info), use that 4629 * instead. This way we don't have to guess at interlace or 4630 * reduced blanking. 4631 */ 4632 for (i = 0; i < num; i++) 4633 if (data->mode_buf[i].hdisplay == hsize && 4634 data->mode_buf[i].vdisplay == vsize && 4635 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4636 return NULL; 4637 4638 /* HDTV hack, part 2 */ 4639 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4640 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4641 false); 4642 mode->hdisplay = 1366; 4643 mode->hsync_start = mode->hsync_start - 1; 4644 mode->hsync_end = mode->hsync_end - 1; 4645 return mode; 4646 } 4647 4648 /* check whether it can be found in default mode table */ 4649 if (drm_monitor_supports_rb(edid)) { 4650 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4651 true); 4652 if (mode) 4653 return mode; 4654 } 4655 4656 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4657 if (mode) 4658 return mode; 4659 4660 /* okay, generate it */ 4661 switch (timing_level) { 4662 case LEVEL_DMT: 4663 break; 4664 case LEVEL_GTF: 4665 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4666 break; 4667 case LEVEL_GTF2: 4668 /* 4669 * This is potentially wrong if there's ever a monitor with 4670 * more than one ranges section, each claiming a different 4671 * secondary GTF curve. Please don't do that. 4672 */ 4673 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4674 if (!mode) 4675 return NULL; 4676 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4677 drm_mode_destroy(mode); 4678 mode = drm_gtf_mode_complex(hsize, vsize, 4679 vrefresh_rate, 0, 0, 4680 drm_gtf2_m(edid), 4681 drm_gtf2_2c(edid), 4682 drm_gtf2_k(edid), 4683 drm_gtf2_2j(edid)); 4684 } 4685 break; 4686 case LEVEL_CVT: 4687 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4688 false); 4689 break; 4690 } 4691 4692 return mode; 4693 } 4694 4695 static void 4696 do_standard_modes(struct detailed_timing *timing, void *c) 4697 { 4698 struct detailed_mode_closure *closure = c; 4699 struct detailed_non_pixel *data = &timing->data.other_data; 4700 struct edid *edid = closure->edid; 4701 4702 if (data->type == EDID_DETAIL_STD_MODES) { 4703 int i; 4704 4705 for (i = 0; i < 6; i++) { 4706 struct std_timing *std; 4707 struct drm_display_mode *newmode; 4708 4709 std = &data->data.timings[i]; 4710 newmode = drm_mode_std(closure->data, edid, std); 4711 if (newmode) { 4712 drm_add_hdmi_modes(closure->data, newmode); 4713 closure->modes++; 4714 drm_mode_destroy(newmode); 4715 } 4716 } 4717 } 4718 } 4719 4720 /** 4721 * add_standard_modes - get std. modes from EDID and add them 4722 * @data: data to add mode(s) to 4723 * @edid: EDID block to scan 4724 * 4725 * Standard modes can be calculated using the appropriate standard (DMT, 4726 * GTF or CVT. Grab them from @edid and add them to the list. 4727 */ 4728 static int 4729 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4730 { 4731 int i, modes = 0; 4732 struct detailed_mode_closure closure = { 4733 .data = data, 4734 .edid = edid, 4735 }; 4736 4737 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4738 struct drm_display_mode *newmode; 4739 4740 newmode = drm_mode_std(data, edid, 4741 &edid->standard_timings[i]); 4742 if (newmode) { 4743 drm_add_hdmi_modes(data, newmode); 4744 modes++; 4745 drm_mode_destroy(newmode); 4746 } 4747 } 4748 4749 if (version_greater(edid, 1, 0)) 4750 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4751 &closure); 4752 4753 /* XXX should also look for standard codes in VTB blocks */ 4754 4755 return modes + closure.modes; 4756 } 4757 4758 static int 4759 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4760 { 4761 int i, j, m, modes = 0; 4762 struct drm_display_mode *mode; 4763 u8 *est = ((u8 *)timing) + 6; 4764 4765 for (i = 0; i < 6; i++) { 4766 for (j = 7; j >= 0; j--) { 4767 m = (i * 8) + (7 - j); 4768 if (m >= ARRAY_SIZE(est3_modes)) 4769 break; 4770 if (est[i] & (1 << j)) { 4771 mode = drm_mode_find_dmt( 4772 est3_modes[m].w, 4773 est3_modes[m].h, 4774 est3_modes[m].r, 4775 est3_modes[m].rb); 4776 if (mode) { 4777 drm_add_hdmi_modes(data, mode); 4778 modes++; 4779 drm_mode_destroy(mode); 4780 } 4781 } 4782 } 4783 } 4784 4785 return modes; 4786 } 4787 4788 static void 4789 do_established_modes(struct detailed_timing *timing, void *c) 4790 { 4791 struct detailed_mode_closure *closure = c; 4792 struct detailed_non_pixel *data = &timing->data.other_data; 4793 4794 if (data->type == EDID_DETAIL_EST_TIMINGS) 4795 closure->modes += drm_est3_modes(closure->data, timing); 4796 } 4797 4798 /** 4799 * add_established_modes - get est. modes from EDID and add them 4800 * @data: data to add mode(s) to 4801 * @edid: EDID block to scan 4802 * 4803 * Each EDID block contains a bitmap of the supported "established modes" list 4804 * (defined above). Tease them out and add them to the modes list. 4805 */ 4806 static int 4807 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4808 { 4809 unsigned long est_bits = edid->established_timings.t1 | 4810 (edid->established_timings.t2 << 8) | 4811 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4812 int i, modes = 0; 4813 struct detailed_mode_closure closure = { 4814 .data = data, 4815 .edid = edid, 4816 }; 4817 4818 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4819 if (est_bits & (1 << i)) { 4820 struct drm_display_mode *newmode = drm_mode_create(); 4821 *newmode = edid_est_modes[i]; 4822 if (newmode) { 4823 drm_add_hdmi_modes(data, newmode); 4824 modes++; 4825 drm_mode_destroy(newmode); 4826 } 4827 } 4828 } 4829 4830 if (version_greater(edid, 1, 0)) 4831 drm_for_each_detailed_block((u8 *)edid, 4832 do_established_modes, &closure); 4833 4834 return modes + closure.modes; 4835 } 4836 4837 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4838 { 4839 u8 vic; 4840 4841 if (!to_match->clock) 4842 return 0; 4843 4844 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4845 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4846 unsigned int clock1, clock2; 4847 4848 /* Make sure to also match alternate clocks */ 4849 clock1 = hdmi_mode->clock; 4850 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4851 4852 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4853 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4854 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4855 return vic; 4856 } 4857 return 0; 4858 } 4859 4860 static int 4861 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4862 { 4863 struct drm_display_mode *mode; 4864 int i, num, modes = 0; 4865 4866 /* Don't add CEA modes if the CEA extension block is missing */ 4867 if (!drm_find_cea_extension(edid)) 4868 return 0; 4869 4870 /* 4871 * Go through all probed modes and create a new mode 4872 * with the alternate clock for certain CEA modes. 4873 */ 4874 num = data->modes; 4875 4876 for (i = 0; i < num; i++) { 4877 const struct drm_display_mode *cea_mode = NULL; 4878 struct drm_display_mode *newmode; 4879 u8 vic; 4880 unsigned int clock1, clock2; 4881 4882 mode = &data->mode_buf[i]; 4883 vic = drm_match_cea_mode(mode); 4884 4885 if (drm_valid_cea_vic(vic)) { 4886 cea_mode = cea_mode_for_vic(vic); 4887 clock2 = cea_mode_alternate_clock(cea_mode); 4888 } else { 4889 vic = drm_match_hdmi_mode(mode); 4890 if (drm_valid_hdmi_vic(vic)) { 4891 cea_mode = &edid_4k_modes[vic]; 4892 clock2 = hdmi_mode_alternate_clock(cea_mode); 4893 } 4894 } 4895 4896 if (!cea_mode) 4897 continue; 4898 4899 clock1 = cea_mode->clock; 4900 4901 if (clock1 == clock2) 4902 continue; 4903 4904 if (mode->clock != clock1 && mode->clock != clock2) 4905 continue; 4906 4907 newmode = drm_mode_create(); 4908 *newmode = *cea_mode; 4909 if (!newmode) 4910 continue; 4911 4912 /* Carry over the stereo flags */ 4913 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4914 4915 /* 4916 * The current mode could be either variant. Make 4917 * sure to pick the "other" clock for the new mode. 4918 */ 4919 if (mode->clock != clock1) 4920 newmode->clock = clock1; 4921 else 4922 newmode->clock = clock2; 4923 4924 drm_add_hdmi_modes(data, newmode); 4925 modes++; 4926 drm_mode_destroy(newmode); 4927 } 4928 4929 return modes; 4930 } 4931 4932 static u8 *drm_find_displayid_extension(struct edid *edid) 4933 { 4934 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4935 } 4936 4937 static int validate_displayid(u8 *displayid, int length, int idx) 4938 { 4939 int i; 4940 u8 csum = 0; 4941 struct displayid_hdr *base; 4942 4943 base = (struct displayid_hdr *)&displayid[idx]; 4944 4945 debug("base revision 0x%x, length %d, %d %d\n", 4946 base->rev, base->bytes, base->prod_id, base->ext_count); 4947 4948 if (base->bytes + 5 > length - idx) 4949 return -EINVAL; 4950 for (i = idx; i <= base->bytes + 5; i++) 4951 csum += displayid[i]; 4952 if (csum) { 4953 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4954 return -EINVAL; 4955 } 4956 return 0; 4957 } 4958 4959 static struct 4960 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4961 *timings) 4962 { 4963 struct drm_display_mode *mode; 4964 unsigned pixel_clock = (timings->pixel_clock[0] | 4965 (timings->pixel_clock[1] << 8) | 4966 (timings->pixel_clock[2] << 16)); 4967 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4968 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4969 unsigned hsync = (timings->hsync[0] | 4970 (timings->hsync[1] & 0x7f) << 8) + 1; 4971 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4972 unsigned vactive = (timings->vactive[0] | 4973 timings->vactive[1] << 8) + 1; 4974 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4975 unsigned vsync = (timings->vsync[0] | 4976 (timings->vsync[1] & 0x7f) << 8) + 1; 4977 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4978 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4979 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4980 4981 mode = drm_mode_create(); 4982 if (!mode) 4983 return NULL; 4984 4985 mode->clock = pixel_clock * 10; 4986 mode->hdisplay = hactive; 4987 mode->hsync_start = mode->hdisplay + hsync; 4988 mode->hsync_end = mode->hsync_start + hsync_width; 4989 mode->htotal = mode->hdisplay + hblank; 4990 4991 mode->vdisplay = vactive; 4992 mode->vsync_start = mode->vdisplay + vsync; 4993 mode->vsync_end = mode->vsync_start + vsync_width; 4994 mode->vtotal = mode->vdisplay + vblank; 4995 4996 mode->flags = 0; 4997 mode->flags |= 4998 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4999 mode->flags |= 5000 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5001 mode->type = DRM_MODE_TYPE_DRIVER; 5002 5003 if (timings->flags & 0x80) 5004 mode->type |= DRM_MODE_TYPE_PREFERRED; 5005 mode->vrefresh = drm_get_vrefresh(mode); 5006 5007 return mode; 5008 } 5009 5010 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 5011 struct displayid_block *block) 5012 { 5013 struct displayid_detailed_timing_block *det; 5014 int i; 5015 int num_timings; 5016 struct drm_display_mode *newmode; 5017 int num_modes = 0; 5018 5019 det = (struct displayid_detailed_timing_block *)block; 5020 /* blocks must be multiple of 20 bytes length */ 5021 if (block->num_bytes % 20) 5022 return 0; 5023 5024 num_timings = block->num_bytes / 20; 5025 for (i = 0; i < num_timings; i++) { 5026 struct displayid_detailed_timings_1 *timings = 5027 &det->timings[i]; 5028 5029 newmode = drm_displayid_detailed(timings); 5030 if (!newmode) 5031 continue; 5032 5033 drm_add_hdmi_modes(data, newmode); 5034 num_modes++; 5035 drm_mode_destroy(newmode); 5036 } 5037 return num_modes; 5038 } 5039 5040 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 5041 struct edid *edid) 5042 { 5043 u8 *displayid; 5044 int ret; 5045 int idx = 1; 5046 int length = EDID_SIZE; 5047 struct displayid_block *block; 5048 int num_modes = 0; 5049 5050 displayid = drm_find_displayid_extension(edid); 5051 if (!displayid) 5052 return 0; 5053 5054 ret = validate_displayid(displayid, length, idx); 5055 if (ret) 5056 return 0; 5057 5058 idx += sizeof(struct displayid_hdr); 5059 while (block = (struct displayid_block *)&displayid[idx], 5060 idx + sizeof(struct displayid_block) <= length && 5061 idx + sizeof(struct displayid_block) + block->num_bytes <= 5062 length && block->num_bytes > 0) { 5063 idx += block->num_bytes + sizeof(struct displayid_block); 5064 switch (block->tag) { 5065 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5066 num_modes += 5067 add_displayid_detailed_1_modes(data, block); 5068 break; 5069 } 5070 } 5071 return num_modes; 5072 } 5073 5074 static bool 5075 mode_in_hsync_range(const struct drm_display_mode *mode, 5076 struct edid *edid, u8 *t) 5077 { 5078 int hsync, hmin, hmax; 5079 5080 hmin = t[7]; 5081 if (edid->revision >= 4) 5082 hmin += ((t[4] & 0x04) ? 255 : 0); 5083 hmax = t[8]; 5084 if (edid->revision >= 4) 5085 hmax += ((t[4] & 0x08) ? 255 : 0); 5086 hsync = drm_mode_hsync(mode); 5087 5088 return (hsync <= hmax && hsync >= hmin); 5089 } 5090 5091 static bool 5092 mode_in_vsync_range(const struct drm_display_mode *mode, 5093 struct edid *edid, u8 *t) 5094 { 5095 int vsync, vmin, vmax; 5096 5097 vmin = t[5]; 5098 if (edid->revision >= 4) 5099 vmin += ((t[4] & 0x01) ? 255 : 0); 5100 vmax = t[6]; 5101 if (edid->revision >= 4) 5102 vmax += ((t[4] & 0x02) ? 255 : 0); 5103 vsync = drm_get_vrefresh(mode); 5104 5105 return (vsync <= vmax && vsync >= vmin); 5106 } 5107 5108 static u32 5109 range_pixel_clock(struct edid *edid, u8 *t) 5110 { 5111 /* unspecified */ 5112 if (t[9] == 0 || t[9] == 255) 5113 return 0; 5114 5115 /* 1.4 with CVT support gives us real precision, yay */ 5116 if (edid->revision >= 4 && t[10] == 0x04) 5117 return (t[9] * 10000) - ((t[12] >> 2) * 250); 5118 5119 /* 1.3 is pathetic, so fuzz up a bit */ 5120 return t[9] * 10000 + 5001; 5121 } 5122 5123 static bool 5124 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 5125 struct detailed_timing *timing) 5126 { 5127 u32 max_clock; 5128 u8 *t = (u8 *)timing; 5129 5130 if (!mode_in_hsync_range(mode, edid, t)) 5131 return false; 5132 5133 if (!mode_in_vsync_range(mode, edid, t)) 5134 return false; 5135 5136 max_clock = range_pixel_clock(edid, t); 5137 if (max_clock) 5138 if (mode->clock > max_clock) 5139 return false; 5140 5141 /* 1.4 max horizontal check */ 5142 if (edid->revision >= 4 && t[10] == 0x04) 5143 if (t[13] && mode->hdisplay > 8 * 5144 (t[13] + (256 * (t[12] & 0x3)))) 5145 return false; 5146 5147 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 5148 return false; 5149 5150 return true; 5151 } 5152 5153 static bool valid_inferred_mode(struct hdmi_edid_data *data, 5154 const struct drm_display_mode *mode) 5155 { 5156 const struct drm_display_mode *m; 5157 bool ok = false; 5158 int i; 5159 5160 for (i = 0; i < data->modes; i++) { 5161 m = &data->mode_buf[i]; 5162 if (mode->hdisplay == m->hdisplay && 5163 mode->vdisplay == m->vdisplay && 5164 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 5165 return false; /* duplicated */ 5166 if (mode->hdisplay <= m->hdisplay && 5167 mode->vdisplay <= m->vdisplay) 5168 ok = true; 5169 } 5170 return ok; 5171 } 5172 5173 static int 5174 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5175 struct detailed_timing *timing) 5176 { 5177 int i, modes = 0; 5178 5179 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 5180 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 5181 valid_inferred_mode(data, drm_dmt_modes + i)) { 5182 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 5183 modes++; 5184 } 5185 } 5186 5187 return modes; 5188 } 5189 5190 /* fix up 1366x768 mode from 1368x768; 5191 * GFT/CVT can't express 1366 width which isn't dividable by 8 5192 */ 5193 static void fixup_mode_1366x768(struct drm_display_mode *mode) 5194 { 5195 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 5196 mode->hdisplay = 1366; 5197 mode->hsync_start--; 5198 mode->hsync_end--; 5199 } 5200 } 5201 5202 static int 5203 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5204 struct detailed_timing *timing) 5205 { 5206 int i, modes = 0; 5207 struct drm_display_mode *newmode; 5208 5209 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5210 const struct minimode *m = &extra_modes[i]; 5211 5212 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 5213 if (!newmode) 5214 return modes; 5215 5216 fixup_mode_1366x768(newmode); 5217 if (!mode_in_range(newmode, edid, timing) || 5218 !valid_inferred_mode(data, newmode)) { 5219 drm_mode_destroy(newmode); 5220 continue; 5221 } 5222 5223 drm_add_hdmi_modes(data, newmode); 5224 modes++; 5225 drm_mode_destroy(newmode); 5226 } 5227 5228 return modes; 5229 } 5230 5231 static int 5232 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5233 struct detailed_timing *timing) 5234 { 5235 int i, modes = 0; 5236 struct drm_display_mode *newmode; 5237 bool rb = drm_monitor_supports_rb(edid); 5238 5239 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5240 const struct minimode *m = &extra_modes[i]; 5241 5242 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 5243 if (!newmode) 5244 return modes; 5245 5246 fixup_mode_1366x768(newmode); 5247 if (!mode_in_range(newmode, edid, timing) || 5248 !valid_inferred_mode(data, newmode)) { 5249 drm_mode_destroy(newmode); 5250 continue; 5251 } 5252 5253 drm_add_hdmi_modes(data, newmode); 5254 modes++; 5255 drm_mode_destroy(newmode); 5256 } 5257 5258 return modes; 5259 } 5260 5261 static void 5262 do_inferred_modes(struct detailed_timing *timing, void *c) 5263 { 5264 struct detailed_mode_closure *closure = c; 5265 struct detailed_non_pixel *data = &timing->data.other_data; 5266 struct detailed_data_monitor_range *range = &data->data.range; 5267 5268 if (data->type != EDID_DETAIL_MONITOR_RANGE) 5269 return; 5270 5271 closure->modes += drm_dmt_modes_for_range(closure->data, 5272 closure->edid, 5273 timing); 5274 5275 if (!version_greater(closure->edid, 1, 1)) 5276 return; /* GTF not defined yet */ 5277 5278 switch (range->flags) { 5279 case 0x02: /* secondary gtf, XXX could do more */ 5280 case 0x00: /* default gtf */ 5281 closure->modes += drm_gtf_modes_for_range(closure->data, 5282 closure->edid, 5283 timing); 5284 break; 5285 case 0x04: /* cvt, only in 1.4+ */ 5286 if (!version_greater(closure->edid, 1, 3)) 5287 break; 5288 5289 closure->modes += drm_cvt_modes_for_range(closure->data, 5290 closure->edid, 5291 timing); 5292 break; 5293 case 0x01: /* just the ranges, no formula */ 5294 default: 5295 break; 5296 } 5297 } 5298 5299 static int 5300 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 5301 { 5302 struct detailed_mode_closure closure = { 5303 .data = data, 5304 .edid = edid, 5305 }; 5306 5307 if (version_greater(edid, 1, 0)) 5308 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 5309 &closure); 5310 5311 return closure.modes; 5312 } 5313 5314 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 5315 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 5316 5317 /** 5318 * edid_fixup_preferred - set preferred modes based on quirk list 5319 * @data: the structure that save parsed hdmi edid data 5320 * @quirks: quirks list 5321 * 5322 * Walk the mode list, clearing the preferred status 5323 * on existing modes and setting it anew for the right mode ala @quirks. 5324 */ 5325 static void edid_fixup_preferred(struct hdmi_edid_data *data, 5326 u32 quirks) 5327 { 5328 struct drm_display_mode *cur_mode, *preferred_mode; 5329 int i, target_refresh = 0; 5330 int num = data->modes; 5331 int cur_vrefresh, preferred_vrefresh; 5332 5333 if (!num) 5334 return; 5335 5336 preferred_mode = data->preferred_mode; 5337 5338 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 5339 target_refresh = 60; 5340 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 5341 target_refresh = 75; 5342 5343 for (i = 0; i < num; i++) { 5344 cur_mode = &data->mode_buf[i]; 5345 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 5346 5347 if (cur_mode == preferred_mode) 5348 continue; 5349 5350 /* Largest mode is preferred */ 5351 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 5352 preferred_mode = cur_mode; 5353 5354 cur_vrefresh = cur_mode->vrefresh ? 5355 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 5356 preferred_vrefresh = preferred_mode->vrefresh ? 5357 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 5358 /* At a given size, try to get closest to target refresh */ 5359 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 5360 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 5361 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 5362 preferred_mode = cur_mode; 5363 } 5364 } 5365 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 5366 data->preferred_mode = preferred_mode; 5367 } 5368 5369 static const u8 edid_header[] = { 5370 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 5371 }; 5372 5373 /** 5374 * drm_edid_header_is_valid - sanity check the header of the base EDID block 5375 * @raw_edid: pointer to raw base EDID block 5376 * 5377 * Sanity check the header of the base EDID block. 5378 * 5379 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 5380 */ 5381 static int drm_edid_header_is_valid(const u8 *raw_edid) 5382 { 5383 int i, score = 0; 5384 5385 for (i = 0; i < sizeof(edid_header); i++) 5386 if (raw_edid[i] == edid_header[i]) 5387 score++; 5388 5389 return score; 5390 } 5391 5392 static int drm_edid_block_checksum(const u8 *raw_edid) 5393 { 5394 int i; 5395 u8 csum = 0; 5396 5397 for (i = 0; i < EDID_SIZE; i++) 5398 csum += raw_edid[i]; 5399 5400 return csum; 5401 } 5402 5403 static bool drm_edid_is_zero(const u8 *in_edid, int length) 5404 { 5405 if (memchr_inv(in_edid, 0, length)) 5406 return false; 5407 5408 return true; 5409 } 5410 5411 /** 5412 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 5413 * @raw_edid: pointer to raw EDID block 5414 * @block: type of block to validate (0 for base, extension otherwise) 5415 * @print_bad_edid: if true, dump bad EDID blocks to the console 5416 * @edid_corrupt: if true, the header or checksum is invalid 5417 * 5418 * Validate a base or extension EDID block and optionally dump bad blocks to 5419 * the console. 5420 * 5421 * Return: True if the block is valid, false otherwise. 5422 */ 5423 static 5424 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 5425 bool *edid_corrupt) 5426 { 5427 u8 csum; 5428 int edid_fixup = 6; 5429 struct edid *edid = (struct edid *)raw_edid; 5430 5431 if ((!raw_edid)) 5432 return false; 5433 5434 if (block == 0) { 5435 int score = drm_edid_header_is_valid(raw_edid); 5436 5437 if (score == 8) { 5438 if (edid_corrupt) 5439 *edid_corrupt = false; 5440 } else if (score >= edid_fixup) { 5441 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 5442 * The corrupt flag needs to be set here otherwise, the 5443 * fix-up code here will correct the problem, the 5444 * checksum is correct and the test fails 5445 */ 5446 if (edid_corrupt) 5447 *edid_corrupt = true; 5448 debug("Fixing header, your hardware may be failing\n"); 5449 memcpy(raw_edid, edid_header, sizeof(edid_header)); 5450 } else { 5451 if (edid_corrupt) 5452 *edid_corrupt = true; 5453 goto bad; 5454 } 5455 } 5456 5457 csum = drm_edid_block_checksum(raw_edid); 5458 if (csum) { 5459 if (print_bad_edid) { 5460 debug("EDID checksum is invalid, remainder is %d\n", 5461 csum); 5462 } 5463 5464 if (edid_corrupt) 5465 *edid_corrupt = true; 5466 5467 /* allow CEA to slide through, switches mangle this */ 5468 if (raw_edid[0] != 0x02) 5469 goto bad; 5470 } 5471 5472 /* per-block-type checks */ 5473 switch (raw_edid[0]) { 5474 case 0: /* base */ 5475 if (edid->version != 1) { 5476 debug("EDID has major version %d, instead of 1\n", 5477 edid->version); 5478 goto bad; 5479 } 5480 5481 if (edid->revision > 4) 5482 debug("minor > 4, assuming backward compatibility\n"); 5483 break; 5484 5485 default: 5486 break; 5487 } 5488 5489 return true; 5490 5491 bad: 5492 if (print_bad_edid) { 5493 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 5494 debug("EDID block is all zeroes\n"); 5495 } else { 5496 debug("Raw EDID:\n"); 5497 print_hex_dump("", DUMP_PREFIX_NONE, 16, 1, 5498 raw_edid, EDID_SIZE, false); 5499 } 5500 } 5501 return false; 5502 } 5503 5504 /** 5505 * drm_edid_is_valid - sanity check EDID data 5506 * @edid: EDID data 5507 * 5508 * Sanity-check an entire EDID record (including extensions) 5509 * 5510 * Return: True if the EDID data is valid, false otherwise. 5511 */ 5512 static bool drm_edid_is_valid(struct edid *edid) 5513 { 5514 int i; 5515 u8 *raw = (u8 *)edid; 5516 5517 if (!edid) 5518 return false; 5519 5520 for (i = 0; i <= edid->extensions; i++) 5521 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 5522 return false; 5523 5524 return true; 5525 } 5526 5527 /** 5528 * drm_add_edid_modes - add modes from EDID data, if available 5529 * @data: data we're probing 5530 * @edid: EDID data 5531 * 5532 * Add the specified modes to the data's mode list. 5533 * 5534 * Return: The number of modes added or 0 if we couldn't find any. 5535 */ 5536 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 5537 { 5538 int num_modes = 0; 5539 u32 quirks; 5540 struct edid *edid = (struct edid *)raw_edid; 5541 5542 if (!edid) { 5543 debug("no edid\n"); 5544 return 0; 5545 } 5546 5547 if (!drm_edid_is_valid(edid)) { 5548 debug("EDID invalid\n"); 5549 return 0; 5550 } 5551 5552 if (!data->mode_buf) { 5553 debug("mode buff is null\n"); 5554 return 0; 5555 } 5556 5557 quirks = edid_get_quirks(edid); 5558 /* 5559 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5560 * To avoid multiple parsing of same block, lets parse that map 5561 * from sink info, before parsing CEA modes. 5562 */ 5563 drm_add_display_info(data, edid); 5564 5565 /* 5566 * EDID spec says modes should be preferred in this order: 5567 * - preferred detailed mode 5568 * - other detailed modes from base block 5569 * - detailed modes from extension blocks 5570 * - CVT 3-byte code modes 5571 * - standard timing codes 5572 * - established timing codes 5573 * - modes inferred from GTF or CVT range information 5574 * 5575 * We get this pretty much right. 5576 * 5577 * XXX order for additional mode types in extension blocks? 5578 */ 5579 num_modes += add_detailed_modes(data, edid, quirks); 5580 num_modes += add_cvt_modes(data, edid); 5581 num_modes += add_standard_modes(data, edid); 5582 num_modes += add_established_modes(data, edid); 5583 num_modes += add_cea_modes(data, edid); 5584 num_modes += add_alternate_cea_modes(data, edid); 5585 num_modes += add_displayid_detailed_modes(data, edid); 5586 5587 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5588 num_modes += add_inferred_modes(data, edid); 5589 5590 if (num_modes > 0) 5591 data->preferred_mode = &data->mode_buf[0]; 5592 5593 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5594 edid_fixup_preferred(data, quirks); 5595 5596 if (quirks & EDID_QUIRK_FORCE_6BPC) 5597 data->display_info.bpc = 6; 5598 5599 if (quirks & EDID_QUIRK_FORCE_8BPC) 5600 data->display_info.bpc = 8; 5601 5602 if (quirks & EDID_QUIRK_FORCE_10BPC) 5603 data->display_info.bpc = 10; 5604 5605 if (quirks & EDID_QUIRK_FORCE_12BPC) 5606 data->display_info.bpc = 12; 5607 5608 return num_modes; 5609 } 5610 5611 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5612 { 5613 u8 vic; 5614 5615 if (!to_match->clock) { 5616 printf("can't find to match\n"); 5617 return 0; 5618 } 5619 5620 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 5621 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 5622 unsigned int clock1, clock2; 5623 5624 /* Check both 60Hz and 59.94Hz */ 5625 clock1 = cea_mode->clock; 5626 clock2 = cea_mode_alternate_clock(cea_mode); 5627 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5628 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5629 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5630 return vic; 5631 } 5632 5633 return 0; 5634 } 5635 5636 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5637 { 5638 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 5639 5640 if (mode) 5641 return mode->picture_aspect_ratio; 5642 5643 return HDMI_PICTURE_ASPECT_NONE; 5644 } 5645 5646 int 5647 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5648 struct drm_display_mode *mode, 5649 bool is_hdmi2_sink) 5650 { 5651 int err; 5652 5653 if (!frame || !mode) 5654 return -EINVAL; 5655 5656 err = hdmi_avi_infoframe_init(frame); 5657 if (err < 0) 5658 return err; 5659 5660 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5661 frame->pixel_repeat = 1; 5662 5663 frame->video_code = drm_match_cea_mode(mode); 5664 5665 /* 5666 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5667 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5668 * have to make sure we dont break HDMI 1.4 sinks. 5669 */ 5670 if (!is_hdmi2_sink && frame->video_code > 64) 5671 frame->video_code = 0; 5672 5673 /* 5674 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5675 * we should send its VIC in vendor infoframes, else send the 5676 * VIC in AVI infoframes. Lets check if this mode is present in 5677 * HDMI 1.4b 4K modes 5678 */ 5679 if (frame->video_code) { 5680 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5681 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5682 5683 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5684 frame->video_code = 0; 5685 } 5686 5687 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5688 5689 /* 5690 * Populate picture aspect ratio from either 5691 * user input (if specified) or from the CEA mode list. 5692 */ 5693 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5694 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5695 frame->picture_aspect = mode->picture_aspect_ratio; 5696 else if (frame->video_code > 0) 5697 frame->picture_aspect = drm_get_cea_aspect_ratio( 5698 frame->video_code); 5699 5700 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5701 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5702 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5703 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5704 5705 return 0; 5706 } 5707 5708 /** 5709 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5710 * @frame: HDMI vendor infoframe 5711 * 5712 * Returns 0 on success or a negative error code on failure. 5713 */ 5714 int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5715 { 5716 memset(frame, 0, sizeof(*frame)); 5717 5718 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5719 frame->version = 1; 5720 5721 frame->oui = HDMI_IEEE_OUI; 5722 5723 /* 5724 * 0 is a valid value for s3d_struct, so we use a special "not set" 5725 * value 5726 */ 5727 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5728 5729 return 0; 5730 } 5731 5732 /** 5733 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5734 * quantization range information 5735 * @frame: HDMI AVI infoframe 5736 * @rgb_quant_range: RGB quantization range (Q) 5737 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 5738 */ 5739 void 5740 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5741 struct drm_display_mode *mode, 5742 enum hdmi_quantization_range rgb_quant_range, 5743 bool rgb_quant_range_selectable) 5744 { 5745 /* 5746 * CEA-861: 5747 * "A Source shall not send a non-zero Q value that does not correspond 5748 * to the default RGB Quantization Range for the transmitted Picture 5749 * unless the Sink indicates support for the Q bit in a Video 5750 * Capabilities Data Block." 5751 * 5752 * HDMI 2.0 recommends sending non-zero Q when it does match the 5753 * default RGB quantization range for the mode, even when QS=0. 5754 */ 5755 if (rgb_quant_range_selectable || 5756 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5757 frame->quantization_range = rgb_quant_range; 5758 else 5759 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5760 5761 /* 5762 * CEA-861-F: 5763 * "When transmitting any RGB colorimetry, the Source should set the 5764 * YQ-field to match the RGB Quantization Range being transmitted 5765 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5766 * set YQ=1) and the Sink shall ignore the YQ-field." 5767 */ 5768 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5769 frame->ycc_quantization_range = 5770 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5771 else 5772 frame->ycc_quantization_range = 5773 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5774 } 5775 5776 static enum hdmi_3d_structure 5777 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5778 { 5779 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5780 5781 switch (layout) { 5782 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5783 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5784 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5785 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5786 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5787 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5788 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5789 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5790 case DRM_MODE_FLAG_3D_L_DEPTH: 5791 return HDMI_3D_STRUCTURE_L_DEPTH; 5792 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5793 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5794 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5795 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5796 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5797 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5798 default: 5799 return HDMI_3D_STRUCTURE_INVALID; 5800 } 5801 } 5802 5803 int 5804 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5805 struct drm_display_mode *mode) 5806 { 5807 int err; 5808 u32 s3d_flags; 5809 u8 vic; 5810 5811 if (!frame || !mode) 5812 return -EINVAL; 5813 5814 vic = drm_match_hdmi_mode(mode); 5815 5816 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5817 5818 if (!vic && !s3d_flags) 5819 return -EINVAL; 5820 5821 if (vic && s3d_flags) 5822 return -EINVAL; 5823 5824 err = hdmi_vendor_infoframe_init(frame); 5825 if (err < 0) 5826 return err; 5827 5828 if (vic) 5829 frame->vic = vic; 5830 else 5831 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5832 5833 return 0; 5834 } 5835 5836 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5837 { 5838 u8 csum = 0; 5839 size_t i; 5840 5841 /* compute checksum */ 5842 for (i = 0; i < size; i++) 5843 csum += ptr[i]; 5844 5845 return 256 - csum; 5846 } 5847 5848 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5849 { 5850 u8 *ptr = buffer; 5851 5852 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5853 } 5854 5855 /** 5856 * hdmi_avi_infoframe_init() - initialize an HDMI AVI infoframe 5857 * @frame: HDMI AVI infoframe 5858 * 5859 * Returns 0 on success or a negative error code on failure. 5860 */ 5861 int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5862 { 5863 memset(frame, 0, sizeof(*frame)); 5864 5865 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5866 frame->version = 2; 5867 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5868 5869 return 0; 5870 } 5871 EXPORT_SYMBOL(hdmi_avi_infoframe_init); 5872 5873 /** 5874 * hdmi_avi_infoframe_pack() - write HDMI AVI infoframe to binary buffer 5875 * @frame: HDMI AVI infoframe 5876 * @buffer: destination buffer 5877 * @size: size of buffer 5878 * 5879 * Packs the information contained in the @frame structure into a binary 5880 * representation that can be written into the corresponding controller 5881 * registers. Also computes the checksum as required by section 5.3.5 of 5882 * the HDMI 1.4 specification. 5883 * 5884 * Returns the number of bytes packed into the binary buffer or a negative 5885 * error code on failure. 5886 */ 5887 ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, 5888 size_t size) 5889 { 5890 u8 *ptr = buffer; 5891 size_t length; 5892 5893 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5894 5895 if (size < length) 5896 return -ENOSPC; 5897 5898 memset(buffer, 0, size); 5899 5900 ptr[0] = frame->type; 5901 ptr[1] = frame->version; 5902 ptr[2] = frame->length; 5903 ptr[3] = 0; /* checksum */ 5904 5905 /* start infoframe payload */ 5906 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5907 5908 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 5909 5910 /* 5911 * Data byte 1, bit 4 has to be set if we provide the active format 5912 * aspect ratio 5913 */ 5914 if (frame->active_aspect & 0xf) 5915 ptr[0] |= BIT(4); 5916 5917 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 5918 if (frame->top_bar || frame->bottom_bar) 5919 ptr[0] |= BIT(3); 5920 5921 if (frame->left_bar || frame->right_bar) 5922 ptr[0] |= BIT(2); 5923 5924 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 5925 ((frame->picture_aspect & 0x3) << 4) | 5926 (frame->active_aspect & 0xf); 5927 5928 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 5929 ((frame->quantization_range & 0x3) << 2) | 5930 (frame->nups & 0x3); 5931 5932 if (frame->itc) 5933 ptr[2] |= BIT(7); 5934 5935 ptr[3] = frame->video_code & 0x7f; 5936 5937 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 5938 ((frame->content_type & 0x3) << 4) | 5939 (frame->pixel_repeat & 0xf); 5940 5941 ptr[5] = frame->top_bar & 0xff; 5942 ptr[6] = (frame->top_bar >> 8) & 0xff; 5943 ptr[7] = frame->bottom_bar & 0xff; 5944 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 5945 ptr[9] = frame->left_bar & 0xff; 5946 ptr[10] = (frame->left_bar >> 8) & 0xff; 5947 ptr[11] = frame->right_bar & 0xff; 5948 ptr[12] = (frame->right_bar >> 8) & 0xff; 5949 5950 hdmi_infoframe_set_checksum(buffer, length); 5951 5952 return length; 5953 } 5954 EXPORT_SYMBOL(hdmi_avi_infoframe_pack); 5955 5956 static int hdmi_avi_infoframe_check_only(const struct hdmi_avi_infoframe *frame) 5957 { 5958 if (frame->type != HDMI_INFOFRAME_TYPE_AVI || 5959 frame->version != 2 || 5960 frame->length != HDMI_AVI_INFOFRAME_SIZE) 5961 return -EINVAL; 5962 5963 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5964 return -EINVAL; 5965 5966 return 0; 5967 } 5968 5969 /** 5970 * hdmi_avi_infoframe_check() - check a HDMI AVI infoframe 5971 * @frame: HDMI AVI infoframe 5972 * 5973 * Validates that the infoframe is consistent and updates derived fields 5974 * (eg. length) based on other fields. 5975 * 5976 * Returns 0 on success or a negative error code on failure. 5977 */ 5978 int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame) 5979 { 5980 return hdmi_avi_infoframe_check_only(frame); 5981 } 5982 EXPORT_SYMBOL(hdmi_avi_infoframe_check); 5983 5984 /** 5985 * hdmi_avi_infoframe_pack_only() - write HDMI AVI infoframe to binary buffer 5986 * @frame: HDMI AVI infoframe 5987 * @buffer: destination buffer 5988 * @size: size of buffer 5989 * 5990 * Packs the information contained in the @frame structure into a binary 5991 * representation that can be written into the corresponding controller 5992 * registers. Also computes the checksum as required by section 5.3.5 of 5993 * the HDMI 1.4 specification. 5994 * 5995 * Returns the number of bytes packed into the binary buffer or a negative 5996 * error code on failure. 5997 */ 5998 ssize_t hdmi_avi_infoframe_pack_only(const struct hdmi_avi_infoframe *frame, 5999 void *buffer, size_t size) 6000 { 6001 u8 *ptr = buffer; 6002 size_t length; 6003 int ret; 6004 6005 ret = hdmi_avi_infoframe_check_only(frame); 6006 if (ret) 6007 return ret; 6008 6009 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6010 6011 if (size < length) 6012 return -ENOSPC; 6013 6014 memset(buffer, 0, size); 6015 6016 ptr[0] = frame->type; 6017 ptr[1] = frame->version; 6018 ptr[2] = frame->length; 6019 ptr[3] = 0; /* checksum */ 6020 6021 /* start infoframe payload */ 6022 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6023 6024 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 6025 6026 /* 6027 * Data byte 1, bit 4 has to be set if we provide the active format 6028 * aspect ratio 6029 */ 6030 if (frame->active_aspect & 0xf) 6031 ptr[0] |= BIT(4); 6032 6033 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 6034 if (frame->top_bar || frame->bottom_bar) 6035 ptr[0] |= BIT(3); 6036 6037 if (frame->left_bar || frame->right_bar) 6038 ptr[0] |= BIT(2); 6039 6040 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 6041 ((frame->picture_aspect & 0x3) << 4) | 6042 (frame->active_aspect & 0xf); 6043 6044 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 6045 ((frame->quantization_range & 0x3) << 2) | 6046 (frame->nups & 0x3); 6047 6048 if (frame->itc) 6049 ptr[2] |= BIT(7); 6050 6051 ptr[3] = frame->video_code & 0xff; 6052 6053 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 6054 ((frame->content_type & 0x3) << 4) | 6055 (frame->pixel_repeat & 0xf); 6056 6057 ptr[5] = frame->top_bar & 0xff; 6058 ptr[6] = (frame->top_bar >> 8) & 0xff; 6059 ptr[7] = frame->bottom_bar & 0xff; 6060 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 6061 ptr[9] = frame->left_bar & 0xff; 6062 ptr[10] = (frame->left_bar >> 8) & 0xff; 6063 ptr[11] = frame->right_bar & 0xff; 6064 ptr[12] = (frame->right_bar >> 8) & 0xff; 6065 6066 hdmi_infoframe_set_checksum(buffer, length); 6067 6068 return length; 6069 } 6070 EXPORT_SYMBOL(hdmi_avi_infoframe_pack_only); 6071 6072 /** 6073 * hdmi_spd_infoframe_init() - initialize an HDMI SPD infoframe 6074 * @frame: HDMI SPD infoframe 6075 * @vendor: vendor string 6076 * @product: product string 6077 * 6078 * Returns 0 on success or a negative error code on failure. 6079 */ 6080 int hdmi_spd_infoframe_init(struct hdmi_spd_infoframe *frame, 6081 const char *vendor, const char *product) 6082 { 6083 memset(frame, 0, sizeof(*frame)); 6084 6085 frame->type = HDMI_INFOFRAME_TYPE_SPD; 6086 frame->version = 1; 6087 frame->length = HDMI_SPD_INFOFRAME_SIZE; 6088 6089 strncpy(frame->vendor, vendor, sizeof(frame->vendor)); 6090 strncpy(frame->product, product, sizeof(frame->product)); 6091 6092 return 0; 6093 } 6094 EXPORT_SYMBOL(hdmi_spd_infoframe_init); 6095 6096 /** 6097 * hdmi_spd_infoframe_pack() - write HDMI SPD infoframe to binary buffer 6098 * @frame: HDMI SPD infoframe 6099 * @buffer: destination buffer 6100 * @size: size of buffer 6101 * 6102 * Packs the information contained in the @frame structure into a binary 6103 * representation that can be written into the corresponding controller 6104 * registers. Also computes the checksum as required by section 5.3.5 of 6105 * the HDMI 1.4 specification. 6106 * 6107 * Returns the number of bytes packed into the binary buffer or a negative 6108 * error code on failure. 6109 */ 6110 ssize_t hdmi_spd_infoframe_pack(struct hdmi_spd_infoframe *frame, void *buffer, 6111 size_t size) 6112 { 6113 u8 *ptr = buffer; 6114 size_t length; 6115 6116 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6117 6118 if (size < length) 6119 return -ENOSPC; 6120 6121 memset(buffer, 0, size); 6122 6123 ptr[0] = frame->type; 6124 ptr[1] = frame->version; 6125 ptr[2] = frame->length; 6126 ptr[3] = 0; /* checksum */ 6127 6128 /* start infoframe payload */ 6129 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6130 6131 memcpy(ptr, frame->vendor, sizeof(frame->vendor)); 6132 memcpy(ptr + 8, frame->product, sizeof(frame->product)); 6133 6134 ptr[24] = frame->sdi; 6135 6136 hdmi_infoframe_set_checksum(buffer, length); 6137 6138 return length; 6139 } 6140 EXPORT_SYMBOL(hdmi_spd_infoframe_pack); 6141 6142 /** 6143 * hdmi_audio_infoframe_init() - initialize an HDMI audio infoframe 6144 * @frame: HDMI audio infoframe 6145 * 6146 * Returns 0 on success or a negative error code on failure. 6147 */ 6148 int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame) 6149 { 6150 memset(frame, 0, sizeof(*frame)); 6151 6152 frame->type = HDMI_INFOFRAME_TYPE_AUDIO; 6153 frame->version = 1; 6154 frame->length = HDMI_AUDIO_INFOFRAME_SIZE; 6155 6156 return 0; 6157 } 6158 6159 /** 6160 * hdmi_audio_infoframe_pack() - write HDMI audio infoframe to binary buffer 6161 * @frame: HDMI audio infoframe 6162 * @buffer: destination buffer 6163 * @size: size of buffer 6164 * 6165 * Packs the information contained in the @frame structure into a binary 6166 * representation that can be written into the corresponding controller 6167 * registers. Also computes the checksum as required by section 5.3.5 of 6168 * the HDMI 1.4 specification. 6169 * 6170 * Returns the number of bytes packed into the binary buffer or a negative 6171 * error code on failure. 6172 */ 6173 ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame, 6174 void *buffer, size_t size) 6175 { 6176 unsigned char channels; 6177 char *ptr = buffer; 6178 size_t length; 6179 6180 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6181 6182 if (size < length) 6183 return -ENOSPC; 6184 6185 memset(buffer, 0, size); 6186 6187 if (frame->channels >= 2) 6188 channels = frame->channels - 1; 6189 else 6190 channels = 0; 6191 6192 ptr[0] = frame->type; 6193 ptr[1] = frame->version; 6194 ptr[2] = frame->length; 6195 ptr[3] = 0; /* checksum */ 6196 6197 /* start infoframe payload */ 6198 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6199 6200 ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7); 6201 ptr[1] = ((frame->sample_frequency & 0x7) << 2) | 6202 (frame->sample_size & 0x3); 6203 ptr[2] = frame->coding_type_ext & 0x1f; 6204 ptr[3] = frame->channel_allocation; 6205 ptr[4] = (frame->level_shift_value & 0xf) << 3; 6206 6207 if (frame->downmix_inhibit) 6208 ptr[4] |= BIT(7); 6209 6210 hdmi_infoframe_set_checksum(buffer, length); 6211 6212 return length; 6213 } 6214 6215 /** 6216 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 6217 * @frame: HDMI infoframe 6218 * @buffer: destination buffer 6219 * @size: size of buffer 6220 * 6221 * Packs the information contained in the @frame structure into a binary 6222 * representation that can be written into the corresponding controller 6223 * registers. Also computes the checksum as required by section 5.3.5 of 6224 * the HDMI 1.4 specification. 6225 * 6226 * Returns the number of bytes packed into the binary buffer or a negative 6227 * error code on failure. 6228 */ 6229 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 6230 void *buffer, size_t size) 6231 { 6232 char *ptr = buffer; 6233 size_t length; 6234 6235 /* empty info frame */ 6236 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 6237 return -EINVAL; 6238 6239 /* only one of those can be supplied */ 6240 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 6241 return -EINVAL; 6242 6243 /* for side by side (half) we also need to provide 3D_Ext_Data */ 6244 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6245 frame->length = 6; 6246 else 6247 frame->length = 5; 6248 6249 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6250 6251 if (size < length) 6252 return -ENOSPC; 6253 6254 memset(buffer, 0, size); 6255 6256 ptr[0] = frame->type; 6257 ptr[1] = frame->version; 6258 ptr[2] = frame->length; 6259 ptr[3] = 0; /* checksum */ 6260 6261 /* HDMI OUI */ 6262 ptr[4] = 0x03; 6263 ptr[5] = 0x0c; 6264 ptr[6] = 0x00; 6265 6266 if (frame->vic) { 6267 ptr[7] = 0x1 << 5; /* video format */ 6268 ptr[8] = frame->vic; 6269 } else { 6270 ptr[7] = 0x2 << 5; /* video format */ 6271 ptr[8] = (frame->s3d_struct & 0xf) << 4; 6272 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6273 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 6274 } 6275 6276 hdmi_infoframe_set_checksum(buffer, length); 6277 6278 return length; 6279 } 6280 6281 /** 6282 * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and 6283 * mastering infoframe 6284 * @frame: HDMI DRM infoframe 6285 * 6286 * Returns 0 on success or a negative error code on failure. 6287 */ 6288 int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame) 6289 { 6290 memset(frame, 0, sizeof(*frame)); 6291 6292 frame->type = HDMI_INFOFRAME_TYPE_DRM; 6293 frame->version = 1; 6294 6295 return 0; 6296 } 6297 6298 /** 6299 * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer 6300 * @frame: HDMI DRM infoframe 6301 * @buffer: destination buffer 6302 * @size: size of buffer 6303 * 6304 * Packs the information contained in the @frame structure into a binary 6305 * representation that can be written into the corresponding controller 6306 * registers. Also computes the checksum as required by section 5.3.5 of 6307 * the HDMI 1.4 specification. 6308 * 6309 * Returns the number of bytes packed into the binary buffer or a negative 6310 * error code on failure. 6311 */ 6312 ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer, 6313 size_t size) 6314 { 6315 u8 *ptr = buffer; 6316 size_t length; 6317 6318 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6319 6320 if (size < length) 6321 return -ENOSPC; 6322 6323 memset(buffer, 0, size); 6324 6325 ptr[0] = frame->type; 6326 ptr[1] = frame->version; 6327 ptr[2] = frame->length; 6328 ptr[3] = 0; /* checksum */ 6329 6330 /* start infoframe payload */ 6331 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6332 6333 ptr[0] = frame->eotf; 6334 ptr[1] = frame->metadata_type; 6335 6336 ptr[2] = frame->display_primaries_x[0] & 0xff; 6337 ptr[3] = frame->display_primaries_x[0] >> 8; 6338 6339 ptr[4] = frame->display_primaries_x[1] & 0xff; 6340 ptr[5] = frame->display_primaries_x[1] >> 8; 6341 6342 ptr[6] = frame->display_primaries_x[2] & 0xff; 6343 ptr[7] = frame->display_primaries_x[2] >> 8; 6344 6345 ptr[9] = frame->display_primaries_y[0] & 0xff; 6346 ptr[10] = frame->display_primaries_y[0] >> 8; 6347 6348 ptr[11] = frame->display_primaries_y[1] & 0xff; 6349 ptr[12] = frame->display_primaries_y[1] >> 8; 6350 6351 ptr[13] = frame->display_primaries_y[2] & 0xff; 6352 ptr[14] = frame->display_primaries_y[2] >> 8; 6353 6354 ptr[15] = frame->white_point_x & 0xff; 6355 ptr[16] = frame->white_point_x >> 8; 6356 6357 ptr[17] = frame->white_point_y & 0xff; 6358 ptr[18] = frame->white_point_y >> 8; 6359 6360 ptr[19] = frame->max_mastering_display_luminance & 0xff; 6361 ptr[20] = frame->max_mastering_display_luminance >> 8; 6362 6363 ptr[21] = frame->min_mastering_display_luminance & 0xff; 6364 ptr[22] = frame->min_mastering_display_luminance >> 8; 6365 6366 ptr[23] = frame->max_cll & 0xff; 6367 ptr[24] = frame->max_cll >> 8; 6368 6369 ptr[25] = frame->max_fall & 0xff; 6370 ptr[26] = frame->max_fall >> 8; 6371 6372 hdmi_infoframe_set_checksum(buffer, length); 6373 6374 return length; 6375 } 6376 6377 /* 6378 * hdmi_vendor_any_infoframe_pack() - write a vendor infoframe to binary buffer 6379 */ 6380 static ssize_t 6381 hdmi_vendor_any_infoframe_pack(union hdmi_vendor_any_infoframe *frame, 6382 void *buffer, size_t size) 6383 { 6384 /* we only know about HDMI vendor infoframes */ 6385 if (frame->any.oui != HDMI_IEEE_OUI) 6386 return -EINVAL; 6387 6388 return hdmi_vendor_infoframe_pack(&frame->hdmi, buffer, size); 6389 } 6390 6391 /** 6392 * hdmi_infoframe_pack() - write a HDMI infoframe to binary buffer 6393 * @frame: HDMI infoframe 6394 * @buffer: destination buffer 6395 * @size: size of buffer 6396 * 6397 * Packs the information contained in the @frame structure into a binary 6398 * representation that can be written into the corresponding controller 6399 * registers. Also computes the checksum as required by section 5.3.5 of 6400 * the HDMI 1.4 specification. 6401 * 6402 * Returns the number of bytes packed into the binary buffer or a negative 6403 * error code on failure. 6404 */ 6405 ssize_t 6406 hdmi_infoframe_pack(union hdmi_infoframe *frame, void *buffer, size_t size) 6407 { 6408 ssize_t length; 6409 6410 switch (frame->any.type) { 6411 case HDMI_INFOFRAME_TYPE_AVI: 6412 length = hdmi_avi_infoframe_pack(&frame->avi, buffer, size); 6413 break; 6414 case HDMI_INFOFRAME_TYPE_DRM: 6415 length = hdmi_drm_infoframe_pack(&frame->drm, buffer, size); 6416 break; 6417 case HDMI_INFOFRAME_TYPE_SPD: 6418 length = hdmi_spd_infoframe_pack(&frame->spd, buffer, size); 6419 break; 6420 case HDMI_INFOFRAME_TYPE_AUDIO: 6421 length = hdmi_audio_infoframe_pack(&frame->audio, buffer, size); 6422 break; 6423 case HDMI_INFOFRAME_TYPE_VENDOR: 6424 length = hdmi_vendor_any_infoframe_pack(&frame->vendor, 6425 buffer, size); 6426 break; 6427 default: 6428 printf("Bad infoframe type %d\n", frame->any.type); 6429 length = -EINVAL; 6430 } 6431 6432 return length; 6433 } 6434 6435 /** 6436 * hdmi_avi_infoframe_unpack() - unpack binary buffer to a HDMI AVI infoframe 6437 * @buffer: source buffer 6438 * @frame: HDMI AVI infoframe 6439 * 6440 * Unpacks the information contained in binary @buffer into a structured 6441 * @frame of the HDMI Auxiliary Video (AVI) information frame. 6442 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6443 * specification. 6444 * 6445 * Returns 0 on success or a negative error code on failure. 6446 */ 6447 static int hdmi_avi_infoframe_unpack(struct hdmi_avi_infoframe *frame, 6448 void *buffer) 6449 { 6450 u8 *ptr = buffer; 6451 int ret; 6452 6453 if (ptr[0] != HDMI_INFOFRAME_TYPE_AVI || 6454 ptr[1] != 2 || 6455 ptr[2] != HDMI_AVI_INFOFRAME_SIZE) 6456 return -EINVAL; 6457 6458 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AVI)) != 0) 6459 return -EINVAL; 6460 6461 ret = hdmi_avi_infoframe_init(frame); 6462 if (ret) 6463 return ret; 6464 6465 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6466 6467 frame->colorspace = (ptr[0] >> 5) & 0x3; 6468 if (ptr[0] & 0x10) 6469 frame->active_aspect = ptr[1] & 0xf; 6470 if (ptr[0] & 0x8) { 6471 frame->top_bar = (ptr[5] << 8) + ptr[6]; 6472 frame->bottom_bar = (ptr[7] << 8) + ptr[8]; 6473 } 6474 if (ptr[0] & 0x4) { 6475 frame->left_bar = (ptr[9] << 8) + ptr[10]; 6476 frame->right_bar = (ptr[11] << 8) + ptr[12]; 6477 } 6478 frame->scan_mode = ptr[0] & 0x3; 6479 6480 frame->colorimetry = (ptr[1] >> 6) & 0x3; 6481 frame->picture_aspect = (ptr[1] >> 4) & 0x3; 6482 frame->active_aspect = ptr[1] & 0xf; 6483 6484 frame->itc = ptr[2] & 0x80 ? true : false; 6485 frame->extended_colorimetry = (ptr[2] >> 4) & 0x7; 6486 frame->quantization_range = (ptr[2] >> 2) & 0x3; 6487 frame->nups = ptr[2] & 0x3; 6488 6489 frame->video_code = ptr[3] & 0x7f; 6490 frame->ycc_quantization_range = (ptr[4] >> 6) & 0x3; 6491 frame->content_type = (ptr[4] >> 4) & 0x3; 6492 6493 frame->pixel_repeat = ptr[4] & 0xf; 6494 6495 return 0; 6496 } 6497 6498 /** 6499 * hdmi_spd_infoframe_unpack() - unpack binary buffer to a HDMI SPD infoframe 6500 * @buffer: source buffer 6501 * @frame: HDMI SPD infoframe 6502 * 6503 * Unpacks the information contained in binary @buffer into a structured 6504 * @frame of the HDMI Source Product Description (SPD) information frame. 6505 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6506 * specification. 6507 * 6508 * Returns 0 on success or a negative error code on failure. 6509 */ 6510 static int hdmi_spd_infoframe_unpack(struct hdmi_spd_infoframe *frame, 6511 void *buffer) 6512 { 6513 char *ptr = buffer; 6514 int ret; 6515 6516 if (ptr[0] != HDMI_INFOFRAME_TYPE_SPD || 6517 ptr[1] != 1 || 6518 ptr[2] != HDMI_SPD_INFOFRAME_SIZE) { 6519 return -EINVAL; 6520 } 6521 6522 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(SPD)) != 0) 6523 return -EINVAL; 6524 6525 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6526 6527 ret = hdmi_spd_infoframe_init(frame, ptr, ptr + 8); 6528 if (ret) 6529 return ret; 6530 6531 frame->sdi = ptr[24]; 6532 6533 return 0; 6534 } 6535 6536 /** 6537 * hdmi_audio_infoframe_unpack() - unpack binary buffer to a HDMI AUDIO infoframe 6538 * @buffer: source buffer 6539 * @frame: HDMI Audio infoframe 6540 * 6541 * Unpacks the information contained in binary @buffer into a structured 6542 * @frame of the HDMI Audio information frame. 6543 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6544 * specification. 6545 * 6546 * Returns 0 on success or a negative error code on failure. 6547 */ 6548 static int hdmi_audio_infoframe_unpack(struct hdmi_audio_infoframe *frame, 6549 void *buffer) 6550 { 6551 u8 *ptr = buffer; 6552 int ret; 6553 6554 if (ptr[0] != HDMI_INFOFRAME_TYPE_AUDIO || 6555 ptr[1] != 1 || 6556 ptr[2] != HDMI_AUDIO_INFOFRAME_SIZE) { 6557 return -EINVAL; 6558 } 6559 6560 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AUDIO)) != 0) 6561 return -EINVAL; 6562 6563 ret = hdmi_audio_infoframe_init(frame); 6564 if (ret) 6565 return ret; 6566 6567 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6568 6569 frame->channels = ptr[0] & 0x7; 6570 frame->coding_type = (ptr[0] >> 4) & 0xf; 6571 frame->sample_size = ptr[1] & 0x3; 6572 frame->sample_frequency = (ptr[1] >> 2) & 0x7; 6573 frame->coding_type_ext = ptr[2] & 0x1f; 6574 frame->channel_allocation = ptr[3]; 6575 frame->level_shift_value = (ptr[4] >> 3) & 0xf; 6576 frame->downmix_inhibit = ptr[4] & 0x80 ? true : false; 6577 6578 return 0; 6579 } 6580 6581 /** 6582 * hdmi_vendor_infoframe_unpack() - unpack binary buffer to a HDMI vendor infoframe 6583 * @buffer: source buffer 6584 * @frame: HDMI Vendor infoframe 6585 * 6586 * Unpacks the information contained in binary @buffer into a structured 6587 * @frame of the HDMI Vendor information frame. 6588 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6589 * specification. 6590 * 6591 * Returns 0 on success or a negative error code on failure. 6592 */ 6593 static int 6594 hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame, 6595 void *buffer) 6596 { 6597 u8 *ptr = buffer; 6598 size_t length; 6599 int ret; 6600 u8 hdmi_video_format; 6601 struct hdmi_vendor_infoframe *hvf = &frame->hdmi; 6602 6603 if (ptr[0] != HDMI_INFOFRAME_TYPE_VENDOR || 6604 ptr[1] != 1 || 6605 (ptr[2] != 4 && ptr[2] != 5 && ptr[2] != 6)) 6606 return -EINVAL; 6607 6608 length = ptr[2]; 6609 6610 if (hdmi_infoframe_checksum(buffer, 6611 HDMI_INFOFRAME_HEADER_SIZE + length) != 0) 6612 return -EINVAL; 6613 6614 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6615 6616 /* HDMI OUI */ 6617 if (ptr[0] != 0x03 || 6618 ptr[1] != 0x0c || 6619 ptr[2] != 0x00) 6620 return -EINVAL; 6621 6622 hdmi_video_format = ptr[3] >> 5; 6623 6624 if (hdmi_video_format > 0x2) 6625 return -EINVAL; 6626 6627 ret = hdmi_vendor_infoframe_init(hvf); 6628 if (ret) 6629 return ret; 6630 6631 hvf->length = length; 6632 6633 if (hdmi_video_format == 0x2) { 6634 if (length != 5 && length != 6) 6635 return -EINVAL; 6636 hvf->s3d_struct = ptr[4] >> 4; 6637 if (hvf->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) { 6638 if (length != 6) 6639 return -EINVAL; 6640 hvf->s3d_ext_data = ptr[5] >> 4; 6641 } 6642 } else if (hdmi_video_format == 0x1) { 6643 if (length != 5) 6644 return -EINVAL; 6645 hvf->vic = ptr[4]; 6646 } else { 6647 if (length != 4) 6648 return -EINVAL; 6649 } 6650 6651 return 0; 6652 } 6653 6654 /** 6655 * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe 6656 * @buffer: source buffer 6657 * @frame: HDMI infoframe 6658 * 6659 * Unpacks the information contained in binary buffer @buffer into a structured 6660 * @frame of a HDMI infoframe. 6661 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6662 * specification. 6663 * 6664 * Returns 0 on success or a negative error code on failure. 6665 */ 6666 int hdmi_infoframe_unpack(union hdmi_infoframe *frame, void *buffer) 6667 { 6668 int ret; 6669 u8 *ptr = buffer; 6670 6671 switch (ptr[0]) { 6672 case HDMI_INFOFRAME_TYPE_AVI: 6673 ret = hdmi_avi_infoframe_unpack(&frame->avi, buffer); 6674 break; 6675 case HDMI_INFOFRAME_TYPE_SPD: 6676 ret = hdmi_spd_infoframe_unpack(&frame->spd, buffer); 6677 break; 6678 case HDMI_INFOFRAME_TYPE_AUDIO: 6679 ret = hdmi_audio_infoframe_unpack(&frame->audio, buffer); 6680 break; 6681 case HDMI_INFOFRAME_TYPE_VENDOR: 6682 ret = hdmi_vendor_any_infoframe_unpack(&frame->vendor, buffer); 6683 break; 6684 default: 6685 ret = -EINVAL; 6686 break; 6687 } 6688 6689 return ret; 6690 } 6691 6692 bool drm_mode_equal(const struct base_drm_display_mode *mode1, 6693 const struct drm_display_mode *mode2) 6694 { 6695 if (mode1->clock == mode2->clock && 6696 mode1->hdisplay == mode2->hdisplay && 6697 mode1->hsync_start == mode2->hsync_start && 6698 mode1->hsync_end == mode2->hsync_end && 6699 mode1->htotal == mode2->htotal && 6700 mode1->vdisplay == mode2->vdisplay && 6701 mode1->vsync_start == mode2->vsync_start && 6702 mode1->vsync_end == mode2->vsync_end && 6703 mode1->vtotal == mode2->vtotal && 6704 mode1->flags == mode2->flags) 6705 return true; 6706 6707 return false; 6708 } 6709 6710 /** 6711 * drm_mode_sort - sort mode list 6712 * @edid_data: modes structures to sort 6713 * 6714 * Sort @edid_data by favorability, moving good modes to the head of the list. 6715 */ 6716 void drm_mode_sort(struct hdmi_edid_data *edid_data) 6717 { 6718 struct drm_display_mode *a, *b; 6719 struct drm_display_mode c; 6720 int diff, i, j; 6721 6722 for (i = 0; i < (edid_data->modes - 1); i++) { 6723 a = &edid_data->mode_buf[i]; 6724 for (j = i + 1; j < edid_data->modes; j++) { 6725 b = &edid_data->mode_buf[j]; 6726 diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) - 6727 ((a->type & DRM_MODE_TYPE_PREFERRED) != 0); 6728 if (diff) { 6729 if (diff > 0) { 6730 c = *a; 6731 *a = *b; 6732 *b = c; 6733 } 6734 continue; 6735 } 6736 6737 diff = b->hdisplay * b->vdisplay 6738 - a->hdisplay * a->vdisplay; 6739 if (diff) { 6740 if (diff > 0) { 6741 c = *a; 6742 *a = *b; 6743 *b = c; 6744 } 6745 continue; 6746 } 6747 6748 diff = b->vrefresh - a->vrefresh; 6749 if (diff) { 6750 if (diff > 0) { 6751 c = *a; 6752 *a = *b; 6753 *b = c; 6754 } 6755 continue; 6756 } 6757 6758 diff = b->clock - a->clock; 6759 if (diff > 0) { 6760 c = *a; 6761 *a = *b; 6762 *b = c; 6763 } 6764 } 6765 } 6766 edid_data->preferred_mode = &edid_data->mode_buf[0]; 6767 } 6768 6769 /** 6770 * drm_mode_prune_invalid - remove invalid modes from mode list 6771 * @edid_data: structure store mode list 6772 * Returns: 6773 * Number of valid modes. 6774 */ 6775 int drm_mode_prune_invalid(struct hdmi_edid_data *edid_data) 6776 { 6777 int i, j; 6778 int num = edid_data->modes; 6779 int len = sizeof(struct drm_display_mode); 6780 struct drm_display_mode *mode_buf = edid_data->mode_buf; 6781 6782 for (i = 0; i < num; i++) { 6783 if (mode_buf[i].invalid) { 6784 /* If mode is invalid, delete it. */ 6785 for (j = i; j < num - 1; j++) 6786 memcpy(&mode_buf[j], &mode_buf[j + 1], len); 6787 6788 num--; 6789 i--; 6790 } 6791 } 6792 /* Clear redundant modes of mode_buf. */ 6793 memset(&mode_buf[num], 0, len * (edid_data->modes - num)); 6794 6795 edid_data->modes = num; 6796 return num; 6797 } 6798 6799 /** 6800 * drm_rk_filter_whitelist - mark modes out of white list from mode list 6801 * @edid_data: structure store mode list 6802 */ 6803 void drm_rk_filter_whitelist(struct hdmi_edid_data *edid_data) 6804 { 6805 int i, j, white_len; 6806 6807 if (sizeof(resolution_white)) { 6808 white_len = sizeof(resolution_white) / 6809 sizeof(resolution_white[0]); 6810 for (i = 0; i < edid_data->modes; i++) { 6811 for (j = 0; j < white_len; j++) { 6812 if (drm_mode_equal(&resolution_white[j], 6813 &edid_data->mode_buf[i])) 6814 break; 6815 } 6816 6817 if (j == white_len) 6818 edid_data->mode_buf[i].invalid = true; 6819 } 6820 } 6821 } 6822 6823 void drm_rk_select_mode(struct hdmi_edid_data *edid_data, 6824 struct base_screen_info *screen_info) 6825 { 6826 int i; 6827 const struct base_drm_display_mode *base_mode; 6828 6829 if (!screen_info) { 6830 /* define init resolution here */ 6831 } else { 6832 base_mode = &screen_info->mode; 6833 for (i = 0; i < edid_data->modes; i++) { 6834 if (drm_mode_equal(base_mode, 6835 &edid_data->mode_buf[i])) { 6836 edid_data->preferred_mode = 6837 &edid_data->mode_buf[i]; 6838 break; 6839 } 6840 } 6841 } 6842 } 6843 6844 /** 6845 * drm_do_probe_ddc_edid() - get EDID information via I2C 6846 * @adap: ddc adapter 6847 * @buf: EDID data buffer to be filled 6848 * @block: 128 byte EDID block to start fetching from 6849 * @len: EDID data buffer length to fetch 6850 * 6851 * Try to fetch EDID information by calling I2C driver functions. 6852 * 6853 * Return: 0 on success or -1 on failure. 6854 */ 6855 static int 6856 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 6857 size_t len) 6858 { 6859 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 6860 unsigned char segment = block >> 1; 6861 unsigned char xfers = segment ? 3 : 2; 6862 int ret, retries = 5; 6863 6864 do { 6865 struct i2c_msg msgs[] = { 6866 { 6867 .addr = DDC_SEGMENT_ADDR, 6868 .flags = 0, 6869 .len = 1, 6870 .buf = &segment, 6871 }, { 6872 .addr = DDC_ADDR, 6873 .flags = 0, 6874 .len = 1, 6875 .buf = &start, 6876 }, { 6877 .addr = DDC_ADDR, 6878 .flags = I2C_M_RD, 6879 .len = len, 6880 .buf = buf, 6881 } 6882 }; 6883 6884 if (adap->ops) { 6885 ret = adap->ops->xfer(adap->i2c_bus, &msgs[3 - xfers], 6886 xfers); 6887 if (!ret) 6888 ret = xfers; 6889 } else { 6890 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 6891 } 6892 } while (ret != xfers && --retries); 6893 6894 /* All msg transfer successfully. */ 6895 return ret == xfers ? 0 : -1; 6896 } 6897 6898 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid) 6899 { 6900 int i, j, block_num, block = 0; 6901 bool edid_corrupt; 6902 #ifdef DEBUG 6903 u8 *buff; 6904 #endif 6905 6906 /* base block fetch */ 6907 for (i = 0; i < 4; i++) { 6908 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 6909 goto err; 6910 if (drm_edid_block_valid(edid, 0, true, 6911 &edid_corrupt)) 6912 break; 6913 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 6914 printf("edid base block is 0, get edid failed\n"); 6915 goto err; 6916 } 6917 } 6918 6919 if (i == 4) 6920 goto err; 6921 6922 block++; 6923 /* get the number of extensions */ 6924 block_num = edid[0x7e]; 6925 6926 for (j = 1; j <= block_num; j++) { 6927 for (i = 0; i < 4; i++) { 6928 if (drm_do_probe_ddc_edid(adap, &edid[0x80 * j], j, 6929 HDMI_EDID_BLOCK_SIZE)) 6930 goto err; 6931 if (drm_edid_block_valid(&edid[0x80 * j], j, 6932 true, NULL)) 6933 break; 6934 } 6935 6936 if (i == 4) 6937 goto err; 6938 block++; 6939 } 6940 6941 #ifdef DEBUG 6942 printf("RAW EDID:\n"); 6943 for (i = 0; i < block_num + 1; i++) { 6944 buff = &edid[0x80 * i]; 6945 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 6946 if (j % 16 == 0) 6947 printf("\n"); 6948 printf("0x%02x, ", buff[j]); 6949 } 6950 printf("\n"); 6951 } 6952 #endif 6953 6954 return 0; 6955 6956 err: 6957 printf("can't get edid block:%d\n", block); 6958 /* clear all read edid block, include invalid block */ 6959 memset(edid, 0, HDMI_EDID_BLOCK_SIZE * (block + 1)); 6960 return -EFAULT; 6961 } 6962 6963 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 6964 void *buffer, size_t size) 6965 { 6966 struct i2c_msg msgs[2] = { 6967 { 6968 .addr = addr, 6969 .flags = 0, 6970 .len = 1, 6971 .buf = &offset, 6972 }, { 6973 .addr = addr, 6974 .flags = I2C_M_RD, 6975 .len = size, 6976 .buf = buffer, 6977 } 6978 }; 6979 6980 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 6981 } 6982 6983 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 6984 const void *buffer, size_t size) 6985 { 6986 struct i2c_msg msg = { 6987 .addr = addr, 6988 .flags = 0, 6989 .len = 1 + size, 6990 .buf = NULL, 6991 }; 6992 void *data; 6993 int err; 6994 6995 data = malloc(1 + size); 6996 if (!data) 6997 return -ENOMEM; 6998 6999 msg.buf = data; 7000 7001 memcpy(data, &offset, sizeof(offset)); 7002 memcpy(data + 1, buffer, size); 7003 7004 err = adap->ddc_xfer(adap, &msg, 1); 7005 7006 free(data); 7007 7008 return err; 7009 } 7010 7011 /** 7012 * drm_scdc_readb - read a single byte from SCDC 7013 * @adap: ddc adapter 7014 * @offset: offset of register to read 7015 * @value: return location for the register value 7016 * 7017 * Reads a single byte from SCDC. This is a convenience wrapper around the 7018 * drm_scdc_read() function. 7019 * 7020 * Returns: 7021 * 0 on success or a negative error code on failure. 7022 */ 7023 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 7024 u8 *value) 7025 { 7026 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 7027 sizeof(*value)); 7028 } 7029 7030 /** 7031 * drm_scdc_writeb - write a single byte to SCDC 7032 * @adap: ddc adapter 7033 * @offset: offset of register to read 7034 * @value: return location for the register value 7035 * 7036 * Writes a single byte to SCDC. This is a convenience wrapper around the 7037 * drm_scdc_write() function. 7038 * 7039 * Returns: 7040 * 0 on success or a negative error code on failure. 7041 */ 7042 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 7043 u8 value) 7044 { 7045 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 7046 sizeof(value)); 7047 } 7048 7049