1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <malloc.h> 22 #include <linux/compat.h> 23 #include <linux/ctype.h> 24 #include <linux/fb.h> 25 #include <linux/hdmi.h> 26 #include <linux/string.h> 27 28 #define EDID_EST_TIMINGS 16 29 #define EDID_STD_TIMINGS 8 30 #define EDID_DETAILED_TIMINGS 4 31 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 32 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 33 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 34 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 35 #define version_greater(edid, maj, min) \ 36 (((edid)->version > (maj)) || \ 37 ((edid)->version == (maj) && (edid)->revision > (min))) 38 39 /* 40 * EDID blocks out in the wild have a variety of bugs, try to collect 41 * them here (note that userspace may work around broken monitors first, 42 * but fixes should make their way here so that the kernel "just works" 43 * on as many displays as possible). 44 */ 45 46 /* First detailed mode wrong, use largest 60Hz mode */ 47 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 48 /* Reported 135MHz pixel clock is too high, needs adjustment */ 49 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 50 /* Prefer the largest mode at 75 Hz */ 51 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 52 /* Detail timing is in cm not mm */ 53 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 54 /* Detailed timing descriptors have bogus size values, so just take the 55 * maximum size and use that. 56 */ 57 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 58 /* Monitor forgot to set the first detailed is preferred bit. */ 59 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 60 /* use +hsync +vsync for detailed mode */ 61 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 62 /* Force reduced-blanking timings for detailed modes */ 63 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 64 /* Force 8bpc */ 65 #define EDID_QUIRK_FORCE_8BPC BIT(8) 66 /* Force 12bpc */ 67 #define EDID_QUIRK_FORCE_12BPC BIT(9) 68 /* Force 6bpc */ 69 #define EDID_QUIRK_FORCE_6BPC BIT(10) 70 /* Force 10bpc */ 71 #define EDID_QUIRK_FORCE_10BPC BIT(11) 72 73 struct detailed_mode_closure { 74 struct edid *edid; 75 struct hdmi_edid_data *data; 76 bool preferred; 77 u32 quirks; 78 int modes; 79 }; 80 81 #define LEVEL_DMT 0 82 #define LEVEL_GTF 1 83 #define LEVEL_GTF2 2 84 #define LEVEL_CVT 3 85 86 static struct edid_quirk { 87 char vendor[4]; 88 int product_id; 89 u32 quirks; 90 } edid_quirk_list[] = { 91 /* Acer AL1706 */ 92 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 93 /* Acer F51 */ 94 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 95 /* Unknown Acer */ 96 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 97 98 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 99 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 100 101 /* Belinea 10 15 55 */ 102 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 103 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 104 105 /* Envision Peripherals, Inc. EN-7100e */ 106 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 107 /* Envision EN2028 */ 108 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 109 110 /* Funai Electronics PM36B */ 111 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 112 EDID_QUIRK_DETAILED_IN_CM }, 113 114 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 115 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 116 117 /* LG Philips LCD LP154W01-A5 */ 118 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 119 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 121 /* Philips 107p5 CRT */ 122 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 123 124 /* Proview AY765C */ 125 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 126 127 /* Samsung SyncMaster 205BW. Note: irony */ 128 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 129 /* Samsung SyncMaster 22[5-6]BW */ 130 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 131 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 132 133 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 134 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 135 136 /* ViewSonic VA2026w */ 137 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 138 139 /* Medion MD 30217 PG */ 140 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 141 142 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 143 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 144 145 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 146 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 147 }; 148 149 /* 150 * Probably taken from CEA-861 spec. 151 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 152 * 153 * Index using the VIC. 154 */ 155 static const struct drm_display_mode edid_cea_modes[] = { 156 /* 0 - dummy, VICs start at 1 */ 157 { }, 158 /* 1 - 640x480@60Hz */ 159 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 160 752, 800, 480, 490, 492, 525, 0, 161 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 162 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 163 /* 2 - 720x480@60Hz */ 164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 165 798, 858, 480, 489, 495, 525, 0, 166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 167 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 168 /* 3 - 720x480@60Hz */ 169 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 170 798, 858, 480, 489, 495, 525, 0, 171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 172 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 173 /* 4 - 1280x720@60Hz */ 174 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 175 1430, 1650, 720, 725, 730, 750, 0, 176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 177 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 178 /* 5 - 1920x1080i@60Hz */ 179 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 180 2052, 2200, 1080, 1084, 1094, 1125, 0, 181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 182 DRM_MODE_FLAG_INTERLACE), 183 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 184 /* 6 - 720(1440)x480i@60Hz */ 185 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 186 801, 858, 480, 488, 494, 525, 0, 187 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 188 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 189 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 190 /* 7 - 720(1440)x480i@60Hz */ 191 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 192 801, 858, 480, 488, 494, 525, 0, 193 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 194 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 195 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 196 /* 8 - 720(1440)x240@60Hz */ 197 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 198 801, 858, 240, 244, 247, 262, 0, 199 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 200 DRM_MODE_FLAG_DBLCLK), 201 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 202 /* 9 - 720(1440)x240@60Hz */ 203 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 204 801, 858, 240, 244, 247, 262, 0, 205 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 206 DRM_MODE_FLAG_DBLCLK), 207 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 208 /* 10 - 2880x480i@60Hz */ 209 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 210 3204, 3432, 480, 488, 494, 525, 0, 211 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 212 DRM_MODE_FLAG_INTERLACE), 213 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 214 /* 11 - 2880x480i@60Hz */ 215 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 216 3204, 3432, 480, 488, 494, 525, 0, 217 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 218 DRM_MODE_FLAG_INTERLACE), 219 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 220 /* 12 - 2880x240@60Hz */ 221 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 222 3204, 3432, 240, 244, 247, 262, 0, 223 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 224 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 225 /* 13 - 2880x240@60Hz */ 226 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 227 3204, 3432, 240, 244, 247, 262, 0, 228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 229 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 230 /* 14 - 1440x480@60Hz */ 231 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 232 1596, 1716, 480, 489, 495, 525, 0, 233 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 234 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 235 /* 15 - 1440x480@60Hz */ 236 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 237 1596, 1716, 480, 489, 495, 525, 0, 238 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 239 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 240 /* 16 - 1920x1080@60Hz */ 241 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 242 2052, 2200, 1080, 1084, 1089, 1125, 0, 243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 244 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 245 /* 17 - 720x576@50Hz */ 246 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 247 796, 864, 576, 581, 586, 625, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 249 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 250 /* 18 - 720x576@50Hz */ 251 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 252 796, 864, 576, 581, 586, 625, 0, 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 254 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 255 /* 19 - 1280x720@50Hz */ 256 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 257 1760, 1980, 720, 725, 730, 750, 0, 258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 259 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 260 /* 20 - 1920x1080i@50Hz */ 261 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 262 2492, 2640, 1080, 1084, 1094, 1125, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 264 DRM_MODE_FLAG_INTERLACE), 265 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 266 /* 21 - 720(1440)x576i@50Hz */ 267 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 268 795, 864, 576, 580, 586, 625, 0, 269 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 270 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 271 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 272 /* 22 - 720(1440)x576i@50Hz */ 273 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 274 795, 864, 576, 580, 586, 625, 0, 275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 276 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 277 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 278 /* 23 - 720(1440)x288@50Hz */ 279 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 280 795, 864, 288, 290, 293, 312, 0, 281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 282 DRM_MODE_FLAG_DBLCLK), 283 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 284 /* 24 - 720(1440)x288@50Hz */ 285 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 286 795, 864, 288, 290, 293, 312, 0, 287 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 288 DRM_MODE_FLAG_DBLCLK), 289 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 290 /* 25 - 2880x576i@50Hz */ 291 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 292 3180, 3456, 576, 580, 586, 625, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 294 DRM_MODE_FLAG_INTERLACE), 295 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 296 /* 26 - 2880x576i@50Hz */ 297 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 298 3180, 3456, 576, 580, 586, 625, 0, 299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 300 DRM_MODE_FLAG_INTERLACE), 301 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 302 /* 27 - 2880x288@50Hz */ 303 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 304 3180, 3456, 288, 290, 293, 312, 0, 305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 306 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 307 /* 28 - 2880x288@50Hz */ 308 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 309 3180, 3456, 288, 290, 293, 312, 0, 310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 311 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 312 /* 29 - 1440x576@50Hz */ 313 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 314 1592, 1728, 576, 581, 586, 625, 0, 315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 316 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 317 /* 30 - 1440x576@50Hz */ 318 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 319 1592, 1728, 576, 581, 586, 625, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 321 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 322 /* 31 - 1920x1080@50Hz */ 323 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 324 2492, 2640, 1080, 1084, 1089, 1125, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 326 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 327 /* 32 - 1920x1080@24Hz */ 328 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 329 2602, 2750, 1080, 1084, 1089, 1125, 0, 330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 331 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 332 /* 33 - 1920x1080@25Hz */ 333 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 334 2492, 2640, 1080, 1084, 1089, 1125, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 336 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 337 /* 34 - 1920x1080@30Hz */ 338 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 339 2052, 2200, 1080, 1084, 1089, 1125, 0, 340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 341 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 342 /* 35 - 2880x480@60Hz */ 343 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 344 3192, 3432, 480, 489, 495, 525, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 346 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 347 /* 36 - 2880x480@60Hz */ 348 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 349 3192, 3432, 480, 489, 495, 525, 0, 350 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 351 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 352 /* 37 - 2880x576@50Hz */ 353 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 354 3184, 3456, 576, 581, 586, 625, 0, 355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 356 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 357 /* 38 - 2880x576@50Hz */ 358 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 359 3184, 3456, 576, 581, 586, 625, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 361 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 362 /* 39 - 1920x1080i@50Hz */ 363 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 364 2120, 2304, 1080, 1126, 1136, 1250, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 366 DRM_MODE_FLAG_INTERLACE), 367 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 368 /* 40 - 1920x1080i@100Hz */ 369 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 370 2492, 2640, 1080, 1084, 1094, 1125, 0, 371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 372 DRM_MODE_FLAG_INTERLACE), 373 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 374 /* 41 - 1280x720@100Hz */ 375 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 376 1760, 1980, 720, 725, 730, 750, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 378 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 379 /* 42 - 720x576@100Hz */ 380 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 381 796, 864, 576, 581, 586, 625, 0, 382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 383 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 384 /* 43 - 720x576@100Hz */ 385 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 386 796, 864, 576, 581, 586, 625, 0, 387 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 388 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 389 /* 44 - 720(1440)x576i@100Hz */ 390 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 391 795, 864, 576, 580, 586, 625, 0, 392 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 393 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 394 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 395 /* 45 - 720(1440)x576i@100Hz */ 396 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 397 795, 864, 576, 580, 586, 625, 0, 398 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 399 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 400 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 401 /* 46 - 1920x1080i@120Hz */ 402 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 403 2052, 2200, 1080, 1084, 1094, 1125, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 405 DRM_MODE_FLAG_INTERLACE), 406 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 407 /* 47 - 1280x720@120Hz */ 408 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 409 1430, 1650, 720, 725, 730, 750, 0, 410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 411 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 412 /* 48 - 720x480@120Hz */ 413 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 414 798, 858, 480, 489, 495, 525, 0, 415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 416 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 417 /* 49 - 720x480@120Hz */ 418 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 419 798, 858, 480, 489, 495, 525, 0, 420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 421 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 422 /* 50 - 720(1440)x480i@120Hz */ 423 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 424 801, 858, 480, 488, 494, 525, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 426 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 427 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 428 /* 51 - 720(1440)x480i@120Hz */ 429 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 430 801, 858, 480, 488, 494, 525, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 432 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 433 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 434 /* 52 - 720x576@200Hz */ 435 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 436 796, 864, 576, 581, 586, 625, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 438 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 439 /* 53 - 720x576@200Hz */ 440 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 441 796, 864, 576, 581, 586, 625, 0, 442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 443 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 444 /* 54 - 720(1440)x576i@200Hz */ 445 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 446 795, 864, 576, 580, 586, 625, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 448 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 449 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 450 /* 55 - 720(1440)x576i@200Hz */ 451 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 452 795, 864, 576, 580, 586, 625, 0, 453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 454 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 455 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 456 /* 56 - 720x480@240Hz */ 457 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 458 798, 858, 480, 489, 495, 525, 0, 459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 460 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 461 /* 57 - 720x480@240Hz */ 462 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 463 798, 858, 480, 489, 495, 525, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 465 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 466 /* 58 - 720(1440)x480i@240 */ 467 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 468 801, 858, 480, 488, 494, 525, 0, 469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 470 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 471 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 472 /* 59 - 720(1440)x480i@240 */ 473 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 474 801, 858, 480, 488, 494, 525, 0, 475 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 476 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 477 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 478 /* 60 - 1280x720@24Hz */ 479 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 480 3080, 3300, 720, 725, 730, 750, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 482 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 483 /* 61 - 1280x720@25Hz */ 484 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 485 3740, 3960, 720, 725, 730, 750, 0, 486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 487 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 488 /* 62 - 1280x720@30Hz */ 489 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 490 3080, 3300, 720, 725, 730, 750, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 492 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 493 /* 63 - 1920x1080@120Hz */ 494 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 495 2052, 2200, 1080, 1084, 1089, 1125, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 497 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 498 /* 64 - 1920x1080@100Hz */ 499 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 500 2492, 2640, 1080, 1084, 1089, 1125, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 502 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 503 /* 65 - 1280x720@24Hz */ 504 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 505 3080, 3300, 720, 725, 730, 750, 0, 506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 507 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 508 /* 66 - 1280x720@25Hz */ 509 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 510 3740, 3960, 720, 725, 730, 750, 0, 511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 512 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 513 /* 67 - 1280x720@30Hz */ 514 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 515 3080, 3300, 720, 725, 730, 750, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 517 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 518 /* 68 - 1280x720@50Hz */ 519 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 520 1760, 1980, 720, 725, 730, 750, 0, 521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 522 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 523 /* 69 - 1280x720@60Hz */ 524 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 525 1430, 1650, 720, 725, 730, 750, 0, 526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 527 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 528 /* 70 - 1280x720@100Hz */ 529 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 530 1760, 1980, 720, 725, 730, 750, 0, 531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 532 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 533 /* 71 - 1280x720@120Hz */ 534 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 535 1430, 1650, 720, 725, 730, 750, 0, 536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 537 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 538 /* 72 - 1920x1080@24Hz */ 539 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 540 2602, 2750, 1080, 1084, 1089, 1125, 0, 541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 542 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 543 /* 73 - 1920x1080@25Hz */ 544 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 545 2492, 2640, 1080, 1084, 1089, 1125, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 547 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 548 /* 74 - 1920x1080@30Hz */ 549 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 550 2052, 2200, 1080, 1084, 1089, 1125, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 552 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 553 /* 75 - 1920x1080@50Hz */ 554 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 555 2492, 2640, 1080, 1084, 1089, 1125, 0, 556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 557 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 558 /* 76 - 1920x1080@60Hz */ 559 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 560 2052, 2200, 1080, 1084, 1089, 1125, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 562 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 563 /* 77 - 1920x1080@100Hz */ 564 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 565 2492, 2640, 1080, 1084, 1089, 1125, 0, 566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 567 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 568 /* 78 - 1920x1080@120Hz */ 569 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 570 2052, 2200, 1080, 1084, 1089, 1125, 0, 571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 572 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 573 /* 79 - 1680x720@24Hz */ 574 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 575 3080, 3300, 720, 725, 730, 750, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 577 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 578 /* 80 - 1680x720@25Hz */ 579 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 580 2948, 3168, 720, 725, 730, 750, 0, 581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 582 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 583 /* 81 - 1680x720@30Hz */ 584 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 585 2420, 2640, 720, 725, 730, 750, 0, 586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 587 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 588 /* 82 - 1680x720@50Hz */ 589 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 590 1980, 2200, 720, 725, 730, 750, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 592 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 593 /* 83 - 1680x720@60Hz */ 594 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 595 1980, 2200, 720, 725, 730, 750, 0, 596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 597 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 598 /* 84 - 1680x720@100Hz */ 599 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 600 1780, 2000, 720, 725, 730, 825, 0, 601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 602 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 603 /* 85 - 1680x720@120Hz */ 604 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 605 1780, 2000, 720, 725, 730, 825, 0, 606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 607 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 608 /* 86 - 2560x1080@24Hz */ 609 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 610 3602, 3750, 1080, 1084, 1089, 1100, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 612 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 613 /* 87 - 2560x1080@25Hz */ 614 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 615 3052, 3200, 1080, 1084, 1089, 1125, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 617 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 618 /* 88 - 2560x1080@30Hz */ 619 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 620 3372, 3520, 1080, 1084, 1089, 1125, 0, 621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 622 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 623 /* 89 - 2560x1080@50Hz */ 624 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 625 3152, 3300, 1080, 1084, 1089, 1125, 0, 626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 627 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 628 /* 90 - 2560x1080@60Hz */ 629 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 630 2852, 3000, 1080, 1084, 1089, 1100, 0, 631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 632 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 633 /* 91 - 2560x1080@100Hz */ 634 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 635 2822, 2970, 1080, 1084, 1089, 1250, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 637 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 638 /* 92 - 2560x1080@120Hz */ 639 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 640 3152, 3300, 1080, 1084, 1089, 1250, 0, 641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 642 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 643 /* 93 - 3840x2160p@24Hz 16:9 */ 644 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 645 5204, 5500, 2160, 2168, 2178, 2250, 0, 646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 647 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 648 /* 94 - 3840x2160p@25Hz 16:9 */ 649 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 650 4984, 5280, 2160, 2168, 2178, 2250, 0, 651 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 652 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 653 /* 95 - 3840x2160p@30Hz 16:9 */ 654 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 655 4104, 4400, 2160, 2168, 2178, 2250, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 657 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 658 /* 96 - 3840x2160p@50Hz 16:9 */ 659 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 660 4984, 5280, 2160, 2168, 2178, 2250, 0, 661 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 662 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 663 /* 97 - 3840x2160p@60Hz 16:9 */ 664 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 665 4104, 4400, 2160, 2168, 2178, 2250, 0, 666 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 667 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 668 /* 98 - 4096x2160p@24Hz 256:135 */ 669 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 670 5204, 5500, 2160, 2168, 2178, 2250, 0, 671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 672 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 673 /* 99 - 4096x2160p@25Hz 256:135 */ 674 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 675 5152, 5280, 2160, 2168, 2178, 2250, 0, 676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 677 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 678 /* 100 - 4096x2160p@30Hz 256:135 */ 679 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 680 4272, 4400, 2160, 2168, 2178, 2250, 0, 681 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 682 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 683 /* 101 - 4096x2160p@50Hz 256:135 */ 684 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 685 5152, 5280, 2160, 2168, 2178, 2250, 0, 686 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 687 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 688 /* 102 - 4096x2160p@60Hz 256:135 */ 689 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 690 4272, 4400, 2160, 2168, 2178, 2250, 0, 691 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 692 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 693 /* 103 - 3840x2160p@24Hz 64:27 */ 694 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 695 5204, 5500, 2160, 2168, 2178, 2250, 0, 696 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 697 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 698 /* 104 - 3840x2160p@25Hz 64:27 */ 699 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 700 4104, 4400, 2160, 2168, 2178, 2250, 0, 701 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 702 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 703 /* 105 - 3840x2160p@30Hz 64:27 */ 704 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 705 4104, 4400, 2160, 2168, 2178, 2250, 0, 706 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 707 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 708 /* 106 - 3840x2160p@50Hz 64:27 */ 709 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 710 4984, 5280, 2160, 2168, 2178, 2250, 0, 711 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 712 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 713 /* 107 - 3840x2160p@60Hz 64:27 */ 714 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 715 4104, 4400, 2160, 2168, 2178, 2250, 0, 716 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 717 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 718 }; 719 720 /* 721 * HDMI 1.4 4k modes. Index using the VIC. 722 */ 723 static const struct drm_display_mode edid_4k_modes[] = { 724 /* 0 - dummy, VICs start at 1 */ 725 { }, 726 /* 1 - 3840x2160@30Hz */ 727 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 728 3840, 4016, 4104, 4400, 729 2160, 2168, 2178, 2250, 0, 730 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 731 .vrefresh = 30, }, 732 /* 2 - 3840x2160@25Hz */ 733 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 734 3840, 4896, 4984, 5280, 735 2160, 2168, 2178, 2250, 0, 736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 737 .vrefresh = 25, }, 738 /* 3 - 3840x2160@24Hz */ 739 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 740 3840, 5116, 5204, 5500, 741 2160, 2168, 2178, 2250, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 743 .vrefresh = 24, }, 744 /* 4 - 4096x2160@24Hz (SMPTE) */ 745 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 746 4096, 5116, 5204, 5500, 747 2160, 2168, 2178, 2250, 0, 748 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 749 .vrefresh = 24, }, 750 }; 751 752 /* 753 * Autogenerated from the DMT spec. 754 * This table is copied from xfree86/modes/xf86EdidModes.c. 755 */ 756 static const struct drm_display_mode drm_dmt_modes[] = { 757 /* 0x01 - 640x350@85Hz */ 758 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 759 736, 832, 350, 382, 385, 445, 0, 760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 761 /* 0x02 - 640x400@85Hz */ 762 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 763 736, 832, 400, 401, 404, 445, 0, 764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 765 /* 0x03 - 720x400@85Hz */ 766 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 767 828, 936, 400, 401, 404, 446, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 769 /* 0x04 - 640x480@60Hz */ 770 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 771 752, 800, 480, 490, 492, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 773 /* 0x05 - 640x480@72Hz */ 774 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 775 704, 832, 480, 489, 492, 520, 0, 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 777 /* 0x06 - 640x480@75Hz */ 778 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 779 720, 840, 480, 481, 484, 500, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 781 /* 0x07 - 640x480@85Hz */ 782 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 783 752, 832, 480, 481, 484, 509, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 785 /* 0x08 - 800x600@56Hz */ 786 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 787 896, 1024, 600, 601, 603, 625, 0, 788 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 789 /* 0x09 - 800x600@60Hz */ 790 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 791 968, 1056, 600, 601, 605, 628, 0, 792 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 793 /* 0x0a - 800x600@72Hz */ 794 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 795 976, 1040, 600, 637, 643, 666, 0, 796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 797 /* 0x0b - 800x600@75Hz */ 798 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 799 896, 1056, 600, 601, 604, 625, 0, 800 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 801 /* 0x0c - 800x600@85Hz */ 802 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 803 896, 1048, 600, 601, 604, 631, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 805 /* 0x0d - 800x600@120Hz RB */ 806 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 807 880, 960, 600, 603, 607, 636, 0, 808 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 809 /* 0x0e - 848x480@60Hz */ 810 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 811 976, 1088, 480, 486, 494, 517, 0, 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 813 /* 0x0f - 1024x768@43Hz, interlace */ 814 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 815 1208, 1264, 768, 768, 772, 817, 0, 816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 817 DRM_MODE_FLAG_INTERLACE) }, 818 /* 0x10 - 1024x768@60Hz */ 819 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 820 1184, 1344, 768, 771, 777, 806, 0, 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 822 /* 0x11 - 1024x768@70Hz */ 823 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 824 1184, 1328, 768, 771, 777, 806, 0, 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 826 /* 0x12 - 1024x768@75Hz */ 827 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 828 1136, 1312, 768, 769, 772, 800, 0, 829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 830 /* 0x13 - 1024x768@85Hz */ 831 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 832 1168, 1376, 768, 769, 772, 808, 0, 833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 834 /* 0x14 - 1024x768@120Hz RB */ 835 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 836 1104, 1184, 768, 771, 775, 813, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 838 /* 0x15 - 1152x864@75Hz */ 839 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 840 1344, 1600, 864, 865, 868, 900, 0, 841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 842 /* 0x55 - 1280x720@60Hz */ 843 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 844 1430, 1650, 720, 725, 730, 750, 0, 845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 846 /* 0x16 - 1280x768@60Hz RB */ 847 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 848 1360, 1440, 768, 771, 778, 790, 0, 849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 850 /* 0x17 - 1280x768@60Hz */ 851 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 852 1472, 1664, 768, 771, 778, 798, 0, 853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 854 /* 0x18 - 1280x768@75Hz */ 855 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 856 1488, 1696, 768, 771, 778, 805, 0, 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 858 /* 0x19 - 1280x768@85Hz */ 859 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 860 1496, 1712, 768, 771, 778, 809, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 862 /* 0x1a - 1280x768@120Hz RB */ 863 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 864 1360, 1440, 768, 771, 778, 813, 0, 865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 866 /* 0x1b - 1280x800@60Hz RB */ 867 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 868 1360, 1440, 800, 803, 809, 823, 0, 869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 870 /* 0x1c - 1280x800@60Hz */ 871 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 872 1480, 1680, 800, 803, 809, 831, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 874 /* 0x1d - 1280x800@75Hz */ 875 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 876 1488, 1696, 800, 803, 809, 838, 0, 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 878 /* 0x1e - 1280x800@85Hz */ 879 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 880 1496, 1712, 800, 803, 809, 843, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 882 /* 0x1f - 1280x800@120Hz RB */ 883 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 884 1360, 1440, 800, 803, 809, 847, 0, 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 886 /* 0x20 - 1280x960@60Hz */ 887 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 888 1488, 1800, 960, 961, 964, 1000, 0, 889 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 890 /* 0x21 - 1280x960@85Hz */ 891 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 892 1504, 1728, 960, 961, 964, 1011, 0, 893 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 894 /* 0x22 - 1280x960@120Hz RB */ 895 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 896 1360, 1440, 960, 963, 967, 1017, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 898 /* 0x23 - 1280x1024@60Hz */ 899 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 900 1440, 1688, 1024, 1025, 1028, 1066, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 902 /* 0x24 - 1280x1024@75Hz */ 903 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 904 1440, 1688, 1024, 1025, 1028, 1066, 0, 905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 906 /* 0x25 - 1280x1024@85Hz */ 907 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 908 1504, 1728, 1024, 1025, 1028, 1072, 0, 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 910 /* 0x26 - 1280x1024@120Hz RB */ 911 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 912 1360, 1440, 1024, 1027, 1034, 1084, 0, 913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 914 /* 0x27 - 1360x768@60Hz */ 915 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 916 1536, 1792, 768, 771, 777, 795, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 918 /* 0x28 - 1360x768@120Hz RB */ 919 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 920 1440, 1520, 768, 771, 776, 813, 0, 921 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 922 /* 0x51 - 1366x768@60Hz */ 923 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 924 1579, 1792, 768, 771, 774, 798, 0, 925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 926 /* 0x56 - 1366x768@60Hz */ 927 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 928 1436, 1500, 768, 769, 772, 800, 0, 929 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 930 /* 0x29 - 1400x1050@60Hz RB */ 931 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 932 1480, 1560, 1050, 1053, 1057, 1080, 0, 933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 934 /* 0x2a - 1400x1050@60Hz */ 935 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 936 1632, 1864, 1050, 1053, 1057, 1089, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 938 /* 0x2b - 1400x1050@75Hz */ 939 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 940 1648, 1896, 1050, 1053, 1057, 1099, 0, 941 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 942 /* 0x2c - 1400x1050@85Hz */ 943 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 944 1656, 1912, 1050, 1053, 1057, 1105, 0, 945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 946 /* 0x2d - 1400x1050@120Hz RB */ 947 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 948 1480, 1560, 1050, 1053, 1057, 1112, 0, 949 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 950 /* 0x2e - 1440x900@60Hz RB */ 951 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 952 1520, 1600, 900, 903, 909, 926, 0, 953 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 954 /* 0x2f - 1440x900@60Hz */ 955 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 956 1672, 1904, 900, 903, 909, 934, 0, 957 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 958 /* 0x30 - 1440x900@75Hz */ 959 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 960 1688, 1936, 900, 903, 909, 942, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 962 /* 0x31 - 1440x900@85Hz */ 963 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 964 1696, 1952, 900, 903, 909, 948, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 966 /* 0x32 - 1440x900@120Hz RB */ 967 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 968 1520, 1600, 900, 903, 909, 953, 0, 969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 970 /* 0x53 - 1600x900@60Hz */ 971 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 972 1704, 1800, 900, 901, 904, 1000, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 974 /* 0x33 - 1600x1200@60Hz */ 975 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 976 1856, 2160, 1200, 1201, 1204, 1250, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 978 /* 0x34 - 1600x1200@65Hz */ 979 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 980 1856, 2160, 1200, 1201, 1204, 1250, 0, 981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 982 /* 0x35 - 1600x1200@70Hz */ 983 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 984 1856, 2160, 1200, 1201, 1204, 1250, 0, 985 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 986 /* 0x36 - 1600x1200@75Hz */ 987 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 988 1856, 2160, 1200, 1201, 1204, 1250, 0, 989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 990 /* 0x37 - 1600x1200@85Hz */ 991 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 992 1856, 2160, 1200, 1201, 1204, 1250, 0, 993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 994 /* 0x38 - 1600x1200@120Hz RB */ 995 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 996 1680, 1760, 1200, 1203, 1207, 1271, 0, 997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 998 /* 0x39 - 1680x1050@60Hz RB */ 999 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1000 1760, 1840, 1050, 1053, 1059, 1080, 0, 1001 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1002 /* 0x3a - 1680x1050@60Hz */ 1003 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1004 1960, 2240, 1050, 1053, 1059, 1089, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1006 /* 0x3b - 1680x1050@75Hz */ 1007 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1008 1976, 2272, 1050, 1053, 1059, 1099, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1010 /* 0x3c - 1680x1050@85Hz */ 1011 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1012 1984, 2288, 1050, 1053, 1059, 1105, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1014 /* 0x3d - 1680x1050@120Hz RB */ 1015 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1016 1760, 1840, 1050, 1053, 1059, 1112, 0, 1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1018 /* 0x3e - 1792x1344@60Hz */ 1019 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1020 2120, 2448, 1344, 1345, 1348, 1394, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1022 /* 0x3f - 1792x1344@75Hz */ 1023 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1024 2104, 2456, 1344, 1345, 1348, 1417, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1026 /* 0x40 - 1792x1344@120Hz RB */ 1027 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1028 1872, 1952, 1344, 1347, 1351, 1423, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1030 /* 0x41 - 1856x1392@60Hz */ 1031 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1032 2176, 2528, 1392, 1393, 1396, 1439, 0, 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1034 /* 0x42 - 1856x1392@75Hz */ 1035 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1036 2208, 2560, 1392, 1393, 1396, 1500, 0, 1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1038 /* 0x43 - 1856x1392@120Hz RB */ 1039 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1040 1936, 2016, 1392, 1395, 1399, 1474, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1042 /* 0x52 - 1920x1080@60Hz */ 1043 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1044 2052, 2200, 1080, 1084, 1089, 1125, 0, 1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1046 /* 0x44 - 1920x1200@60Hz RB */ 1047 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1048 2000, 2080, 1200, 1203, 1209, 1235, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1050 /* 0x45 - 1920x1200@60Hz */ 1051 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1052 2256, 2592, 1200, 1203, 1209, 1245, 0, 1053 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1054 /* 0x46 - 1920x1200@75Hz */ 1055 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1056 2264, 2608, 1200, 1203, 1209, 1255, 0, 1057 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1058 /* 0x47 - 1920x1200@85Hz */ 1059 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1060 2272, 2624, 1200, 1203, 1209, 1262, 0, 1061 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1062 /* 0x48 - 1920x1200@120Hz RB */ 1063 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1064 2000, 2080, 1200, 1203, 1209, 1271, 0, 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1066 /* 0x49 - 1920x1440@60Hz */ 1067 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1068 2256, 2600, 1440, 1441, 1444, 1500, 0, 1069 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1070 /* 0x4a - 1920x1440@75Hz */ 1071 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1072 2288, 2640, 1440, 1441, 1444, 1500, 0, 1073 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1074 /* 0x4b - 1920x1440@120Hz RB */ 1075 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1076 2000, 2080, 1440, 1443, 1447, 1525, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1078 /* 0x54 - 2048x1152@60Hz */ 1079 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1080 2154, 2250, 1152, 1153, 1156, 1200, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1082 /* 0x4c - 2560x1600@60Hz RB */ 1083 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1084 2640, 2720, 1600, 1603, 1609, 1646, 0, 1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1086 /* 0x4d - 2560x1600@60Hz */ 1087 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1088 3032, 3504, 1600, 1603, 1609, 1658, 0, 1089 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1090 /* 0x4e - 2560x1600@75Hz */ 1091 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1092 3048, 3536, 1600, 1603, 1609, 1672, 0, 1093 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1094 /* 0x4f - 2560x1600@85Hz */ 1095 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1096 3048, 3536, 1600, 1603, 1609, 1682, 0, 1097 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1098 /* 0x50 - 2560x1600@120Hz RB */ 1099 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1100 2640, 2720, 1600, 1603, 1609, 1694, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1102 /* 0x57 - 4096x2160@60Hz RB */ 1103 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1104 4136, 4176, 2160, 2208, 2216, 2222, 0, 1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1106 /* 0x58 - 4096x2160@59.94Hz RB */ 1107 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1108 4136, 4176, 2160, 2208, 2216, 2222, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1110 }; 1111 1112 /* 1113 * These more or less come from the DMT spec. The 720x400 modes are 1114 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1115 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1116 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1117 * mode. 1118 * 1119 * The DMT modes have been fact-checked; the rest are mild guesses. 1120 */ 1121 static const struct drm_display_mode edid_est_modes[] = { 1122 /* 800x600@60Hz */ 1123 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1124 968, 1056, 600, 601, 605, 628, 0, 1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1126 /* 800x600@56Hz */ 1127 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1128 896, 1024, 600, 601, 603, 625, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1130 /* 640x480@75Hz */ 1131 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1132 720, 840, 480, 481, 484, 500, 0, 1133 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1134 /* 640x480@72Hz */ 1135 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1136 704, 832, 480, 489, 492, 520, 0, 1137 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1138 /* 640x480@67Hz */ 1139 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1140 768, 864, 480, 483, 486, 525, 0, 1141 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1142 /* 640x480@60Hz */ 1143 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1144 752, 800, 480, 490, 492, 525, 0, 1145 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1146 /* 720x400@88Hz */ 1147 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1148 846, 900, 400, 421, 423, 449, 0, 1149 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1150 /* 720x400@70Hz */ 1151 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1152 846, 900, 400, 412, 414, 449, 0, 1153 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1154 /* 1280x1024@75Hz */ 1155 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1156 1440, 1688, 1024, 1025, 1028, 1066, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1158 /* 1024x768@75Hz */ 1159 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1160 1136, 1312, 768, 769, 772, 800, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1162 /* 1024x768@70Hz */ 1163 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1164 1184, 1328, 768, 771, 777, 806, 0, 1165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1166 /* 1024x768@60Hz */ 1167 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1168 1184, 1344, 768, 771, 777, 806, 0, 1169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1170 /* 1024x768@43Hz */ 1171 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1172 1208, 1264, 768, 768, 776, 817, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1174 DRM_MODE_FLAG_INTERLACE) }, 1175 /* 832x624@75Hz */ 1176 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1177 928, 1152, 624, 625, 628, 667, 0, 1178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1179 /* 800x600@75Hz */ 1180 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1181 896, 1056, 600, 601, 604, 625, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1183 /* 800x600@72Hz */ 1184 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1185 976, 1040, 600, 637, 643, 666, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1187 /* 1152x864@75Hz */ 1188 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1189 1344, 1600, 864, 865, 868, 900, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1191 }; 1192 1193 struct minimode { 1194 short w; 1195 short h; 1196 short r; 1197 short rb; 1198 }; 1199 1200 static const struct minimode est3_modes[] = { 1201 /* byte 6 */ 1202 { 640, 350, 85, 0 }, 1203 { 640, 400, 85, 0 }, 1204 { 720, 400, 85, 0 }, 1205 { 640, 480, 85, 0 }, 1206 { 848, 480, 60, 0 }, 1207 { 800, 600, 85, 0 }, 1208 { 1024, 768, 85, 0 }, 1209 { 1152, 864, 75, 0 }, 1210 /* byte 7 */ 1211 { 1280, 768, 60, 1 }, 1212 { 1280, 768, 60, 0 }, 1213 { 1280, 768, 75, 0 }, 1214 { 1280, 768, 85, 0 }, 1215 { 1280, 960, 60, 0 }, 1216 { 1280, 960, 85, 0 }, 1217 { 1280, 1024, 60, 0 }, 1218 { 1280, 1024, 85, 0 }, 1219 /* byte 8 */ 1220 { 1360, 768, 60, 0 }, 1221 { 1440, 900, 60, 1 }, 1222 { 1440, 900, 60, 0 }, 1223 { 1440, 900, 75, 0 }, 1224 { 1440, 900, 85, 0 }, 1225 { 1400, 1050, 60, 1 }, 1226 { 1400, 1050, 60, 0 }, 1227 { 1400, 1050, 75, 0 }, 1228 /* byte 9 */ 1229 { 1400, 1050, 85, 0 }, 1230 { 1680, 1050, 60, 1 }, 1231 { 1680, 1050, 60, 0 }, 1232 { 1680, 1050, 75, 0 }, 1233 { 1680, 1050, 85, 0 }, 1234 { 1600, 1200, 60, 0 }, 1235 { 1600, 1200, 65, 0 }, 1236 { 1600, 1200, 70, 0 }, 1237 /* byte 10 */ 1238 { 1600, 1200, 75, 0 }, 1239 { 1600, 1200, 85, 0 }, 1240 { 1792, 1344, 60, 0 }, 1241 { 1792, 1344, 75, 0 }, 1242 { 1856, 1392, 60, 0 }, 1243 { 1856, 1392, 75, 0 }, 1244 { 1920, 1200, 60, 1 }, 1245 { 1920, 1200, 60, 0 }, 1246 /* byte 11 */ 1247 { 1920, 1200, 75, 0 }, 1248 { 1920, 1200, 85, 0 }, 1249 { 1920, 1440, 60, 0 }, 1250 { 1920, 1440, 75, 0 }, 1251 }; 1252 1253 static const struct minimode extra_modes[] = { 1254 { 1024, 576, 60, 0 }, 1255 { 1366, 768, 60, 0 }, 1256 { 1600, 900, 60, 0 }, 1257 { 1680, 945, 60, 0 }, 1258 { 1920, 1080, 60, 0 }, 1259 { 2048, 1152, 60, 0 }, 1260 { 2048, 1536, 60, 0 }, 1261 }; 1262 1263 int edid_check_info(struct edid1_info *edid_info) 1264 { 1265 if ((edid_info == NULL) || (edid_info->version == 0)) 1266 return -1; 1267 1268 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1269 return -1; 1270 1271 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1272 return -1; 1273 1274 return 0; 1275 } 1276 1277 int edid_check_checksum(u8 *edid_block) 1278 { 1279 u8 checksum = 0; 1280 int i; 1281 1282 for (i = 0; i < 128; i++) 1283 checksum += edid_block[i]; 1284 1285 return (checksum == 0) ? 0 : -EINVAL; 1286 } 1287 1288 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1289 unsigned int *hmax, unsigned int *vmin, 1290 unsigned int *vmax) 1291 { 1292 int i; 1293 struct edid_monitor_descriptor *monitor; 1294 1295 *hmin = *hmax = *vmin = *vmax = 0; 1296 if (edid_check_info(edid)) 1297 return -1; 1298 1299 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1300 monitor = &edid->monitor_details.descriptor[i]; 1301 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1302 *hmin = monitor->data.range_data.horizontal_min; 1303 *hmax = monitor->data.range_data.horizontal_max; 1304 *vmin = monitor->data.range_data.vertical_min; 1305 *vmax = monitor->data.range_data.vertical_max; 1306 return 0; 1307 } 1308 } 1309 return -1; 1310 } 1311 1312 /* Set all parts of a timing entry to the same value */ 1313 static void set_entry(struct timing_entry *entry, u32 value) 1314 { 1315 entry->min = value; 1316 entry->typ = value; 1317 entry->max = value; 1318 } 1319 1320 /** 1321 * decode_timing() - Decoding an 18-byte detailed timing record 1322 * 1323 * @buf: Pointer to EDID detailed timing record 1324 * @timing: Place to put timing 1325 */ 1326 static void decode_timing(u8 *buf, struct display_timing *timing) 1327 { 1328 uint x_mm, y_mm; 1329 unsigned int ha, hbl, hso, hspw, hborder; 1330 unsigned int va, vbl, vso, vspw, vborder; 1331 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1332 1333 /* Edid contains pixel clock in terms of 10KHz */ 1334 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1335 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1336 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1337 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1338 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1339 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1340 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1341 hborder = buf[15]; 1342 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1343 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1344 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1345 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1346 vborder = buf[16]; 1347 1348 set_entry(&timing->hactive, ha); 1349 set_entry(&timing->hfront_porch, hso); 1350 set_entry(&timing->hback_porch, hbl - hso - hspw); 1351 set_entry(&timing->hsync_len, hspw); 1352 1353 set_entry(&timing->vactive, va); 1354 set_entry(&timing->vfront_porch, vso); 1355 set_entry(&timing->vback_porch, vbl - vso - vspw); 1356 set_entry(&timing->vsync_len, vspw); 1357 1358 timing->flags = 0; 1359 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1360 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1361 else 1362 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1363 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1364 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1365 else 1366 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1367 1368 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1369 timing->flags = DISPLAY_FLAGS_INTERLACED; 1370 1371 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1372 " %04x %04x %04x %04x hborder %x\n" 1373 " %04x %04x %04x %04x vborder %x\n", 1374 timing->pixelclock.typ, 1375 x_mm, y_mm, 1376 ha, ha + hso, ha + hso + hspw, 1377 ha + hbl, hborder, 1378 va, va + vso, va + vso + vspw, 1379 va + vbl, vborder); 1380 } 1381 1382 /** 1383 * decode_mode() - Decoding an 18-byte detailed timing record 1384 * 1385 * @buf: Pointer to EDID detailed timing record 1386 * @timing: Place to put timing 1387 */ 1388 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1389 { 1390 uint x_mm, y_mm; 1391 unsigned int ha, hbl, hso, hspw, hborder; 1392 unsigned int va, vbl, vso, vspw, vborder; 1393 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1394 1395 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1396 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1397 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1398 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1399 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1400 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1401 hborder = buf[15]; 1402 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1403 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1404 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1405 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1406 vborder = buf[16]; 1407 1408 /* Edid contains pixel clock in terms of 10KHz */ 1409 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1410 mode->hdisplay = ha; 1411 mode->hsync_start = ha + hso; 1412 mode->hsync_end = ha + hso + hspw; 1413 mode->htotal = ha + hbl; 1414 mode->vdisplay = va; 1415 mode->vsync_start = va + vso; 1416 mode->vsync_end = va + vso + vspw; 1417 mode->vtotal = va + vbl; 1418 1419 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1420 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1421 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1422 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1423 1424 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1425 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1426 1427 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1428 " %04d %04d %04d %04d hborder %d\n" 1429 " %04d %04d %04d %04d vborder %d\n", 1430 mode->clock, 1431 x_mm, y_mm, mode->flags, 1432 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1433 mode->htotal, hborder, 1434 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1435 mode->vtotal, vborder); 1436 } 1437 1438 /** 1439 * edid_vendor - match a string against EDID's obfuscated vendor field 1440 * @edid: EDID to match 1441 * @vendor: vendor string 1442 * 1443 * Returns true if @vendor is in @edid, false otherwise 1444 */ 1445 static bool edid_vendor(struct edid *edid, char *vendor) 1446 { 1447 char edid_vendor[3]; 1448 1449 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1450 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1451 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1452 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1453 1454 return !strncmp(edid_vendor, vendor, 3); 1455 } 1456 1457 /** 1458 * Check if HDMI vendor specific data block is present in CEA block 1459 * @param info CEA extension block 1460 * @return true if block is found 1461 */ 1462 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1463 { 1464 u8 end, i = 0; 1465 1466 /* check for end of data block */ 1467 end = info->dtd_offset; 1468 if (end == 0) 1469 end = sizeof(info->data); 1470 if (end < 4 || end > sizeof(info->data)) 1471 return false; 1472 end -= 4; 1473 1474 while (i < end) { 1475 /* Look for vendor specific data block of appropriate size */ 1476 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1477 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1478 u8 *db = &info->data[i + 1]; 1479 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1480 1481 if (oui == HDMI_IEEE_OUI) 1482 return true; 1483 } 1484 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1485 } 1486 1487 return false; 1488 } 1489 1490 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1491 { 1492 int refresh = 0; 1493 unsigned int calc_val; 1494 1495 if (mode->vrefresh > 0) { 1496 refresh = mode->vrefresh; 1497 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1498 int vtotal; 1499 1500 vtotal = mode->vtotal; 1501 /* work out vrefresh the value will be x1000 */ 1502 calc_val = (mode->clock * 1000); 1503 calc_val /= mode->htotal; 1504 refresh = (calc_val + vtotal / 2) / vtotal; 1505 1506 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1507 refresh *= 2; 1508 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1509 refresh /= 2; 1510 if (mode->vscan > 1) 1511 refresh /= mode->vscan; 1512 } 1513 return refresh; 1514 } 1515 1516 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1517 int *panel_bits_per_colourp) 1518 { 1519 struct edid1_info *edid = (struct edid1_info *)buf; 1520 bool timing_done; 1521 int i; 1522 1523 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1524 debug("%s: Invalid buffer\n", __func__); 1525 return -EINVAL; 1526 } 1527 1528 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1529 debug("%s: No preferred timing\n", __func__); 1530 return -ENOENT; 1531 } 1532 1533 /* Look for detailed timing */ 1534 timing_done = false; 1535 for (i = 0; i < 4; i++) { 1536 struct edid_monitor_descriptor *desc; 1537 1538 desc = &edid->monitor_details.descriptor[i]; 1539 if (desc->zero_flag_1 != 0) { 1540 decode_mode((u8 *)desc, mode); 1541 timing_done = true; 1542 break; 1543 } 1544 } 1545 if (!timing_done) 1546 return -EINVAL; 1547 1548 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1549 debug("%s: Not a digital display\n", __func__); 1550 return -ENOSYS; 1551 } 1552 if (edid->version != 1 || edid->revision < 4) { 1553 debug("%s: EDID version %d.%d does not have required info\n", 1554 __func__, edid->version, edid->revision); 1555 *panel_bits_per_colourp = -1; 1556 } else { 1557 *panel_bits_per_colourp = 1558 ((edid->video_input_definition & 0x70) >> 3) + 4; 1559 } 1560 1561 return 0; 1562 } 1563 1564 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 1565 int *panel_bits_per_colourp) 1566 { 1567 struct edid1_info *edid = (struct edid1_info *)buf; 1568 bool timing_done; 1569 int i; 1570 1571 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1572 debug("%s: Invalid buffer\n", __func__); 1573 return -EINVAL; 1574 } 1575 1576 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1577 debug("%s: No preferred timing\n", __func__); 1578 return -ENOENT; 1579 } 1580 1581 /* Look for detailed timing */ 1582 timing_done = false; 1583 for (i = 0; i < 4; i++) { 1584 struct edid_monitor_descriptor *desc; 1585 1586 desc = &edid->monitor_details.descriptor[i]; 1587 if (desc->zero_flag_1 != 0) { 1588 decode_timing((u8 *)desc, timing); 1589 timing_done = true; 1590 break; 1591 } 1592 } 1593 if (!timing_done) 1594 return -EINVAL; 1595 1596 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1597 debug("%s: Not a digital display\n", __func__); 1598 return -ENOSYS; 1599 } 1600 if (edid->version != 1 || edid->revision < 4) { 1601 debug("%s: EDID version %d.%d does not have required info\n", 1602 __func__, edid->version, edid->revision); 1603 *panel_bits_per_colourp = -1; 1604 } else { 1605 *panel_bits_per_colourp = 1606 ((edid->video_input_definition & 0x70) >> 3) + 4; 1607 } 1608 1609 timing->hdmi_monitor = false; 1610 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 1611 struct edid_cea861_info *info = 1612 (struct edid_cea861_info *)(buf + sizeof(*edid)); 1613 1614 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 1615 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 1616 } 1617 1618 return 0; 1619 } 1620 1621 /** 1622 * Snip the tailing whitespace/return of a string. 1623 * 1624 * @param string The string to be snipped 1625 * @return the snipped string 1626 */ 1627 static char *snip(char *string) 1628 { 1629 char *s; 1630 1631 /* 1632 * This is always a 13 character buffer 1633 * and it's not always terminated. 1634 */ 1635 string[12] = '\0'; 1636 s = &string[strlen(string) - 1]; 1637 1638 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 1639 *s == '\0')) 1640 *(s--) = '\0'; 1641 1642 return string; 1643 } 1644 1645 /** 1646 * Print an EDID monitor descriptor block 1647 * 1648 * @param monitor The EDID monitor descriptor block 1649 * @have_timing Modifies to 1 if the desciptor contains timing info 1650 */ 1651 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 1652 unsigned int *have_timing) 1653 { 1654 unsigned char *bytes = (unsigned char *)monitor; 1655 struct edid_detailed_timing *timing = 1656 (struct edid_detailed_timing *)monitor; 1657 1658 if (bytes[0] == 0 && bytes[1] == 0) { 1659 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 1660 printf("Monitor serial number: %s\n", 1661 snip(monitor->data.string)); 1662 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 1663 printf("Monitor ID: %s\n", 1664 snip(monitor->data.string)); 1665 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 1666 printf("Monitor name: %s\n", 1667 snip(monitor->data.string)); 1668 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 1669 printf("Monitor range limits, horizontal sync: " 1670 "%d-%d kHz, vertical refresh: " 1671 "%d-%d Hz, max pixel clock: " 1672 "%d MHz\n", 1673 monitor->data.range_data.horizontal_min, 1674 monitor->data.range_data.horizontal_max, 1675 monitor->data.range_data.vertical_min, 1676 monitor->data.range_data.vertical_max, 1677 monitor->data.range_data.pixel_clock_max * 10); 1678 } else { 1679 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 1680 u32 h_total, v_total, vfreq; 1681 1682 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 1683 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 1684 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 1685 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 1686 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 1687 1688 h_total = h_active + h_blanking; 1689 v_total = v_active + v_blanking; 1690 if (v_total > 0 && h_total > 0) 1691 vfreq = pixclock / (v_total * h_total); 1692 else 1693 vfreq = 1; /* Error case */ 1694 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 1695 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 1696 *have_timing = 1; 1697 } 1698 } 1699 1700 /** 1701 * Get the manufacturer name from an EDID info. 1702 * 1703 * @param edid_info The EDID info to be printed 1704 * @param name Returns the string of the manufacturer name 1705 */ 1706 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 1707 { 1708 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 1709 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 1710 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 1711 name[3] = '\0'; 1712 } 1713 1714 void edid_print_info(struct edid1_info *edid_info) 1715 { 1716 int i; 1717 char manufacturer[4]; 1718 unsigned int have_timing = 0; 1719 u32 serial_number; 1720 1721 if (edid_check_info(edid_info)) { 1722 printf("Not a valid EDID\n"); 1723 return; 1724 } 1725 1726 printf("EDID version: %d.%d\n", 1727 edid_info->version, edid_info->revision); 1728 1729 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 1730 1731 edid_get_manufacturer_name(edid_info, manufacturer); 1732 printf("Manufacturer: %s\n", manufacturer); 1733 1734 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 1735 if (serial_number != 0xffffffff) { 1736 if (strcmp(manufacturer, "MAG") == 0) 1737 serial_number -= 0x7000000; 1738 if (strcmp(manufacturer, "OQI") == 0) 1739 serial_number -= 456150000; 1740 if (strcmp(manufacturer, "VSC") == 0) 1741 serial_number -= 640000000; 1742 } 1743 printf("Serial number: %08x\n", serial_number); 1744 printf("Manufactured in week: %d year: %d\n", 1745 edid_info->week, edid_info->year + 1990); 1746 1747 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 1748 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 1749 "digital signal, " : "analog signal, ", 1750 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 1751 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 1752 ", blank to black" : "", 1753 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 1754 ", separate sync" : "", 1755 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 1756 ", composite sync" : "", 1757 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 1758 ", sync on green" : "", 1759 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 1760 ", serration v" : ""); 1761 1762 printf("Monitor is %s\n", 1763 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 1764 1765 printf("Maximum visible display size: %d cm x %d cm\n", 1766 edid_info->max_size_horizontal, 1767 edid_info->max_size_vertical); 1768 1769 printf("Power management features: %s%s, %s%s, %s%s\n", 1770 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 1771 "" : "no ", "active off", 1772 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 1773 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 1774 1775 printf("Estabilished timings:\n"); 1776 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 1777 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 1778 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 1779 printf("\t720x400\t\t88 Hz (XGA2)\n"); 1780 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 1781 printf("\t640x480\t\t60 Hz (VGA)\n"); 1782 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 1783 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 1784 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 1785 printf("\t640x480\t\t72 Hz (VESA)\n"); 1786 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 1787 printf("\t640x480\t\t75 Hz (VESA)\n"); 1788 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 1789 printf("\t800x600\t\t56 Hz (VESA)\n"); 1790 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 1791 printf("\t800x600\t\t60 Hz (VESA)\n"); 1792 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 1793 printf("\t800x600\t\t72 Hz (VESA)\n"); 1794 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 1795 printf("\t800x600\t\t75 Hz (VESA)\n"); 1796 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 1797 printf("\t832x624\t\t75 Hz (Mac II)\n"); 1798 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 1799 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 1800 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 1801 printf("\t1024x768\t60 Hz (VESA)\n"); 1802 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 1803 printf("\t1024x768\t70 Hz (VESA)\n"); 1804 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 1805 printf("\t1024x768\t75 Hz (VESA)\n"); 1806 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 1807 printf("\t1280x1024\t75 (VESA)\n"); 1808 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 1809 printf("\t1152x870\t75 (Mac II)\n"); 1810 1811 /* Standard timings. */ 1812 printf("Standard timings:\n"); 1813 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 1814 unsigned int aspect = 10000; 1815 unsigned int x, y; 1816 unsigned char xres, vfreq; 1817 1818 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 1819 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 1820 if ((xres != vfreq) || 1821 ((xres != 0) && (xres != 1)) || 1822 ((vfreq != 0) && (vfreq != 1))) { 1823 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 1824 i)) { 1825 case ASPECT_625: 1826 aspect = 6250; 1827 break; 1828 case ASPECT_75: 1829 aspect = 7500; 1830 break; 1831 case ASPECT_8: 1832 aspect = 8000; 1833 break; 1834 case ASPECT_5625: 1835 aspect = 5625; 1836 break; 1837 } 1838 x = (xres + 31) * 8; 1839 y = x * aspect / 10000; 1840 printf("\t%dx%d%c\t%d Hz\n", x, y, 1841 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 1842 have_timing = 1; 1843 } 1844 } 1845 1846 /* Detailed timing information. */ 1847 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 1848 i++) { 1849 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 1850 &have_timing); 1851 } 1852 1853 if (!have_timing) 1854 printf("\tNone\n"); 1855 } 1856 1857 /** 1858 * drm_mode_create - create a new display mode 1859 * 1860 * Create a new, cleared drm_display_mode. 1861 * 1862 * Returns: 1863 * Pointer to new mode on success, NULL on error. 1864 */ 1865 static struct drm_display_mode *drm_mode_create(void) 1866 { 1867 struct drm_display_mode *nmode; 1868 1869 nmode = malloc(sizeof(struct drm_display_mode)); 1870 memset(nmode, 0, sizeof(struct drm_display_mode)); 1871 if (!nmode) 1872 return NULL; 1873 1874 return nmode; 1875 } 1876 1877 /** 1878 * drm_mode_destroy - remove a mode 1879 * @mode: mode to remove 1880 * 1881 */ 1882 static void drm_mode_destroy(struct drm_display_mode *mode) 1883 { 1884 if (!mode) 1885 return; 1886 1887 kfree(mode); 1888 } 1889 1890 /** 1891 * drm_cvt_mode -create a modeline based on the CVT algorithm 1892 * @hdisplay: hdisplay size 1893 * @vdisplay: vdisplay size 1894 * @vrefresh: vrefresh rate 1895 * @reduced: whether to use reduced blanking 1896 * @interlaced: whether to compute an interlaced mode 1897 * @margins: whether to add margins (borders) 1898 * 1899 * This function is called to generate the modeline based on CVT algorithm 1900 * according to the hdisplay, vdisplay, vrefresh. 1901 * It is based from the VESA(TM) Coordinated Video Timing Generator by 1902 * Graham Loveridge April 9, 2003 available at 1903 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 1904 * 1905 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 1906 * What I have done is to translate it by using integer calculation. 1907 * 1908 * Returns: 1909 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 1910 * The display mode object is allocated with drm_mode_create(). Returns NULL 1911 * when no mode could be allocated. 1912 */ 1913 static 1914 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 1915 bool reduced, bool interlaced, 1916 bool margins) 1917 { 1918 #define HV_FACTOR 1000 1919 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 1920 #define CVT_MARGIN_PERCENTAGE 18 1921 /* 2) character cell horizontal granularity (pixels) - default 8 */ 1922 #define CVT_H_GRANULARITY 8 1923 /* 3) Minimum vertical porch (lines) - default 3 */ 1924 #define CVT_MIN_V_PORCH 3 1925 /* 4) Minimum number of vertical back porch lines - default 6 */ 1926 #define CVT_MIN_V_BPORCH 6 1927 /* Pixel Clock step (kHz) */ 1928 #define CVT_CLOCK_STEP 250 1929 struct drm_display_mode *drm_mode; 1930 unsigned int vfieldrate, hperiod; 1931 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 1932 int interlace; 1933 1934 /* allocate the drm_display_mode structure. If failure, we will 1935 * return directly 1936 */ 1937 drm_mode = drm_mode_create(); 1938 if (!drm_mode) 1939 return NULL; 1940 1941 /* the CVT default refresh rate is 60Hz */ 1942 if (!vrefresh) 1943 vrefresh = 60; 1944 1945 /* the required field fresh rate */ 1946 if (interlaced) 1947 vfieldrate = vrefresh * 2; 1948 else 1949 vfieldrate = vrefresh; 1950 1951 /* horizontal pixels */ 1952 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 1953 1954 /* determine the left&right borders */ 1955 hmargin = 0; 1956 if (margins) { 1957 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1958 hmargin -= hmargin % CVT_H_GRANULARITY; 1959 } 1960 /* find the total active pixels */ 1961 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 1962 1963 /* find the number of lines per field */ 1964 if (interlaced) 1965 vdisplay_rnd = vdisplay / 2; 1966 else 1967 vdisplay_rnd = vdisplay; 1968 1969 /* find the top & bottom borders */ 1970 vmargin = 0; 1971 if (margins) 1972 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1973 1974 drm_mode->vdisplay = vdisplay + 2 * vmargin; 1975 1976 /* Interlaced */ 1977 if (interlaced) 1978 interlace = 1; 1979 else 1980 interlace = 0; 1981 1982 /* Determine VSync Width from aspect ratio */ 1983 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 1984 vsync = 4; 1985 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 1986 vsync = 5; 1987 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 1988 vsync = 6; 1989 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 1990 vsync = 7; 1991 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 1992 vsync = 7; 1993 else /* custom */ 1994 vsync = 10; 1995 1996 if (!reduced) { 1997 /* simplify the GTF calculation */ 1998 /* 4) Minimum time of vertical sync + back porch interval 1999 * default 550.0 2000 */ 2001 int tmp1, tmp2; 2002 #define CVT_MIN_VSYNC_BP 550 2003 /* 3) Nominal HSync width (% of line period) - default 8 */ 2004 #define CVT_HSYNC_PERCENTAGE 8 2005 unsigned int hblank_percentage; 2006 int vsyncandback_porch, hblank; 2007 2008 /* estimated the horizontal period */ 2009 tmp1 = HV_FACTOR * 1000000 - 2010 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2011 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2012 interlace; 2013 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2014 2015 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2016 /* 9. Find number of lines in sync + backporch */ 2017 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2018 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2019 else 2020 vsyncandback_porch = tmp1; 2021 /* 10. Find number of lines in back porch 2022 * vback_porch = vsyncandback_porch - vsync; 2023 */ 2024 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2025 vsyncandback_porch + CVT_MIN_V_PORCH; 2026 /* 5) Definition of Horizontal blanking time limitation */ 2027 /* Gradient (%/kHz) - default 600 */ 2028 #define CVT_M_FACTOR 600 2029 /* Offset (%) - default 40 */ 2030 #define CVT_C_FACTOR 40 2031 /* Blanking time scaling factor - default 128 */ 2032 #define CVT_K_FACTOR 128 2033 /* Scaling factor weighting - default 20 */ 2034 #define CVT_J_FACTOR 20 2035 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2036 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2037 CVT_J_FACTOR) 2038 /* 12. Find ideal blanking duty cycle from formula */ 2039 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2040 hperiod / 1000; 2041 /* 13. Blanking time */ 2042 if (hblank_percentage < 20 * HV_FACTOR) 2043 hblank_percentage = 20 * HV_FACTOR; 2044 hblank = drm_mode->hdisplay * hblank_percentage / 2045 (100 * HV_FACTOR - hblank_percentage); 2046 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2047 /* 14. find the total pixels per line */ 2048 drm_mode->htotal = drm_mode->hdisplay + hblank; 2049 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2050 drm_mode->hsync_start = drm_mode->hsync_end - 2051 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2052 drm_mode->hsync_start += CVT_H_GRANULARITY - 2053 drm_mode->hsync_start % CVT_H_GRANULARITY; 2054 /* fill the Vsync values */ 2055 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2056 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2057 } else { 2058 /* Reduced blanking */ 2059 /* Minimum vertical blanking interval time - default 460 */ 2060 #define CVT_RB_MIN_VBLANK 460 2061 /* Fixed number of clocks for horizontal sync */ 2062 #define CVT_RB_H_SYNC 32 2063 /* Fixed number of clocks for horizontal blanking */ 2064 #define CVT_RB_H_BLANK 160 2065 /* Fixed number of lines for vertical front porch - default 3*/ 2066 #define CVT_RB_VFPORCH 3 2067 int vbilines; 2068 int tmp1, tmp2; 2069 /* 8. Estimate Horizontal period. */ 2070 tmp1 = HV_FACTOR * 1000000 - 2071 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2072 tmp2 = vdisplay_rnd + 2 * vmargin; 2073 hperiod = tmp1 / (tmp2 * vfieldrate); 2074 /* 9. Find number of lines in vertical blanking */ 2075 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2076 /* 10. Check if vertical blanking is sufficient */ 2077 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2078 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2079 /* 11. Find total number of lines in vertical field */ 2080 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2081 /* 12. Find total number of pixels in a line */ 2082 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2083 /* Fill in HSync values */ 2084 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2085 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2086 /* Fill in VSync values */ 2087 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2088 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2089 } 2090 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2091 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2092 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2093 /* 18/16. Find actual vertical frame frequency */ 2094 /* ignore - just set the mode flag for interlaced */ 2095 if (interlaced) { 2096 drm_mode->vtotal *= 2; 2097 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2098 } 2099 2100 if (reduced) 2101 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2102 DRM_MODE_FLAG_NVSYNC); 2103 else 2104 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2105 DRM_MODE_FLAG_NHSYNC); 2106 2107 return drm_mode; 2108 } 2109 2110 static int 2111 cea_db_payload_len(const u8 *db) 2112 { 2113 return db[0] & 0x1f; 2114 } 2115 2116 static int 2117 cea_db_extended_tag(const u8 *db) 2118 { 2119 return db[1]; 2120 } 2121 2122 static int 2123 cea_db_tag(const u8 *db) 2124 { 2125 return db[0] >> 5; 2126 } 2127 2128 #define for_each_cea_db(cea, i, start, end) \ 2129 for ((i) = (start); (i) < (end) && (i) + \ 2130 cea_db_payload_len(&(cea)[(i)]) < \ 2131 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2132 2133 static int 2134 cea_revision(const u8 *cea) 2135 { 2136 return cea[1]; 2137 } 2138 2139 static int 2140 cea_db_offsets(const u8 *cea, int *start, int *end) 2141 { 2142 /* Data block offset in CEA extension block */ 2143 *start = 4; 2144 *end = cea[2]; 2145 if (*end == 0) 2146 *end = 127; 2147 if (*end < 4 || *end > 127) 2148 return -ERANGE; 2149 2150 /* 2151 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2152 */ 2153 if (*end != 4) { 2154 int i; 2155 2156 i = *start; 2157 while (i < (*end) && 2158 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2159 i += cea_db_payload_len(&(cea)[i]) + 1; 2160 2161 if (cea_db_payload_len(&(cea)[i]) && 2162 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2163 (*end)++; 2164 } 2165 2166 return 0; 2167 } 2168 2169 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2170 { 2171 int hdmi_id; 2172 2173 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2174 return false; 2175 2176 if (cea_db_payload_len(db) < 5) 2177 return false; 2178 2179 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2180 2181 return hdmi_id == HDMI_IEEE_OUI; 2182 } 2183 2184 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2185 { 2186 unsigned int oui; 2187 2188 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2189 return false; 2190 2191 if (cea_db_payload_len(db) < 7) 2192 return false; 2193 2194 oui = db[3] << 16 | db[2] << 8 | db[1]; 2195 2196 return oui == HDMI_FORUM_IEEE_OUI; 2197 } 2198 2199 static bool cea_db_is_y420cmdb(const u8 *db) 2200 { 2201 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2202 return false; 2203 2204 if (!cea_db_payload_len(db)) 2205 return false; 2206 2207 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2208 return false; 2209 2210 return true; 2211 } 2212 2213 static bool cea_db_is_y420vdb(const u8 *db) 2214 { 2215 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2216 return false; 2217 2218 if (!cea_db_payload_len(db)) 2219 return false; 2220 2221 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2222 return false; 2223 2224 return true; 2225 } 2226 2227 static bool drm_valid_hdmi_vic(u8 vic) 2228 { 2229 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2230 } 2231 2232 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2233 const struct drm_display_mode *mode) 2234 { 2235 struct drm_display_mode *mode_buf = data->mode_buf; 2236 2237 if (data->modes >= MODE_LEN) 2238 return; 2239 mode_buf[(data->modes)++] = *mode; 2240 } 2241 2242 static bool drm_valid_cea_vic(u8 vic) 2243 { 2244 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2245 } 2246 2247 static u8 svd_to_vic(u8 svd) 2248 { 2249 /* 0-6 bit vic, 7th bit native mode indicator */ 2250 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2251 return svd & 127; 2252 2253 return svd; 2254 } 2255 2256 static struct drm_display_mode * 2257 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2258 u8 video_index) 2259 { 2260 struct drm_display_mode *newmode; 2261 u8 vic; 2262 2263 if (!video_db || video_index >= video_len) 2264 return NULL; 2265 2266 /* CEA modes are numbered 1..127 */ 2267 vic = svd_to_vic(video_db[video_index]); 2268 if (!drm_valid_cea_vic(vic)) 2269 return NULL; 2270 2271 newmode = drm_mode_create(); 2272 if (!newmode) 2273 return NULL; 2274 2275 *newmode = edid_cea_modes[vic]; 2276 newmode->vrefresh = 0; 2277 2278 return newmode; 2279 } 2280 2281 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2282 { 2283 unsigned long *p = map + BIT_WORD(start); 2284 const unsigned int size = start + len; 2285 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2286 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2287 2288 while (len - bits_to_set >= 0) { 2289 *p |= mask_to_set; 2290 len -= bits_to_set; 2291 bits_to_set = BITS_PER_LONG; 2292 mask_to_set = ~0UL; 2293 p++; 2294 } 2295 if (len) { 2296 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2297 *p |= mask_to_set; 2298 } 2299 } 2300 2301 static void 2302 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2303 { 2304 u8 vic = svd_to_vic(svd); 2305 2306 if (!drm_valid_cea_vic(vic)) 2307 return; 2308 2309 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2310 } 2311 2312 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2313 { 2314 int i, modes = 0; 2315 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2316 2317 for (i = 0; i < len; i++) { 2318 struct drm_display_mode *mode; 2319 2320 mode = drm_display_mode_from_vic_index(db, len, i); 2321 if (mode) { 2322 /* 2323 * YCBCR420 capability block contains a bitmap which 2324 * gives the index of CEA modes from CEA VDB, which 2325 * can support YCBCR 420 sampling output also (apart 2326 * from RGB/YCBCR444 etc). 2327 * For example, if the bit 0 in bitmap is set, 2328 * first mode in VDB can support YCBCR420 output too. 2329 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2330 */ 2331 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2332 drm_add_cmdb_modes(db[i], hdmi); 2333 drm_add_hdmi_modes(data, mode); 2334 drm_mode_destroy(mode); 2335 modes++; 2336 } 2337 } 2338 2339 return modes; 2340 } 2341 2342 /* 2343 * do_y420vdb_modes - Parse YCBCR 420 only modes 2344 * @data: the structure that save parsed hdmi edid data 2345 * @svds: start of the data block of CEA YCBCR 420 VDB 2346 * @svds_len: length of the CEA YCBCR 420 VDB 2347 * @hdmi: runtime information about the connected HDMI sink 2348 * 2349 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2350 * which contains modes which can be supported in YCBCR 420 2351 * output format only. 2352 */ 2353 static int 2354 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2355 { 2356 int modes = 0, i; 2357 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2358 2359 for (i = 0; i < svds_len; i++) { 2360 u8 vic = svd_to_vic(svds[i]); 2361 2362 if (!drm_valid_cea_vic(vic)) 2363 continue; 2364 2365 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2366 drm_add_hdmi_modes(data, &edid_cea_modes[vic]); 2367 modes++; 2368 } 2369 2370 return modes; 2371 } 2372 2373 struct stereo_mandatory_mode { 2374 int width, height, vrefresh; 2375 unsigned int flags; 2376 }; 2377 2378 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2379 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2380 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2381 { 1920, 1080, 50, 2382 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2383 { 1920, 1080, 60, 2384 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2385 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2386 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2387 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2388 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2389 }; 2390 2391 static bool 2392 stereo_match_mandatory(const struct drm_display_mode *mode, 2393 const struct stereo_mandatory_mode *stereo_mode) 2394 { 2395 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2396 2397 return mode->hdisplay == stereo_mode->width && 2398 mode->vdisplay == stereo_mode->height && 2399 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2400 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2401 } 2402 2403 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2404 { 2405 const struct drm_display_mode *mode; 2406 int num = data->modes, modes = 0, i, k; 2407 2408 for (k = 0; k < num; k++) { 2409 mode = &data->mode_buf[k]; 2410 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2411 const struct stereo_mandatory_mode *mandatory; 2412 struct drm_display_mode *new_mode; 2413 2414 if (!stereo_match_mandatory(mode, 2415 &stereo_mandatory_modes[i])) 2416 continue; 2417 2418 mandatory = &stereo_mandatory_modes[i]; 2419 new_mode = drm_mode_create(); 2420 if (!new_mode) 2421 continue; 2422 2423 *new_mode = *mode; 2424 new_mode->flags |= mandatory->flags; 2425 drm_add_hdmi_modes(data, new_mode); 2426 drm_mode_destroy(new_mode); 2427 modes++; 2428 } 2429 } 2430 2431 return modes; 2432 } 2433 2434 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2435 const u8 *video_db, u8 video_len, u8 video_index) 2436 { 2437 struct drm_display_mode *newmode; 2438 int modes = 0; 2439 2440 if (structure & (1 << 0)) { 2441 newmode = drm_display_mode_from_vic_index(video_db, 2442 video_len, 2443 video_index); 2444 if (newmode) { 2445 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2446 drm_add_hdmi_modes(data, newmode); 2447 modes++; 2448 drm_mode_destroy(newmode); 2449 } 2450 } 2451 if (structure & (1 << 6)) { 2452 newmode = drm_display_mode_from_vic_index(video_db, 2453 video_len, 2454 video_index); 2455 if (newmode) { 2456 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2457 drm_add_hdmi_modes(data, newmode); 2458 modes++; 2459 drm_mode_destroy(newmode); 2460 } 2461 } 2462 if (structure & (1 << 8)) { 2463 newmode = drm_display_mode_from_vic_index(video_db, 2464 video_len, 2465 video_index); 2466 if (newmode) { 2467 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2468 drm_add_hdmi_modes(data, newmode); 2469 modes++; 2470 drm_mode_destroy(newmode); 2471 } 2472 } 2473 2474 return modes; 2475 } 2476 2477 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2478 { 2479 if (!drm_valid_hdmi_vic(vic)) { 2480 debug("Unknown HDMI VIC: %d\n", vic); 2481 return 0; 2482 } 2483 2484 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2485 2486 return 1; 2487 } 2488 2489 /* 2490 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2491 * @db: start of the CEA vendor specific block 2492 * @len: length of the CEA block payload, ie. one can access up to db[len] 2493 * 2494 * Parses the HDMI VSDB looking for modes to add to @data. This function 2495 * also adds the stereo 3d modes when applicable. 2496 */ 2497 static int 2498 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2499 struct hdmi_edid_data *data) 2500 { 2501 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2502 u8 vic_len, hdmi_3d_len = 0; 2503 u16 mask; 2504 u16 structure_all; 2505 2506 if (len < 8) 2507 goto out; 2508 2509 /* no HDMI_Video_Present */ 2510 if (!(db[8] & (1 << 5))) 2511 goto out; 2512 2513 /* Latency_Fields_Present */ 2514 if (db[8] & (1 << 7)) 2515 offset += 2; 2516 2517 /* I_Latency_Fields_Present */ 2518 if (db[8] & (1 << 6)) 2519 offset += 2; 2520 2521 /* the declared length is not long enough for the 2 first bytes 2522 * of additional video format capabilities 2523 */ 2524 if (len < (8 + offset + 2)) 2525 goto out; 2526 2527 /* 3D_Present */ 2528 offset++; 2529 if (db[8 + offset] & (1 << 7)) { 2530 modes += add_hdmi_mandatory_stereo_modes(data); 2531 2532 /* 3D_Multi_present */ 2533 multi_present = (db[8 + offset] & 0x60) >> 5; 2534 } 2535 2536 offset++; 2537 vic_len = db[8 + offset] >> 5; 2538 hdmi_3d_len = db[8 + offset] & 0x1f; 2539 2540 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2541 u8 vic; 2542 2543 vic = db[9 + offset + i]; 2544 modes += add_hdmi_mode(data, vic); 2545 } 2546 2547 offset += 1 + vic_len; 2548 2549 if (multi_present == 1) 2550 multi_len = 2; 2551 else if (multi_present == 2) 2552 multi_len = 4; 2553 else 2554 multi_len = 0; 2555 2556 if (len < (8 + offset + hdmi_3d_len - 1)) 2557 goto out; 2558 2559 if (hdmi_3d_len < multi_len) 2560 goto out; 2561 2562 if (multi_present == 1 || multi_present == 2) { 2563 /* 3D_Structure_ALL */ 2564 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2565 2566 /* check if 3D_MASK is present */ 2567 if (multi_present == 2) 2568 mask = (db[10 + offset] << 8) | db[11 + offset]; 2569 else 2570 mask = 0xffff; 2571 2572 for (i = 0; i < 16; i++) { 2573 if (mask & (1 << i)) 2574 modes += add_3d_struct_modes(data, 2575 structure_all, 2576 video_db, 2577 video_len, i); 2578 } 2579 } 2580 2581 offset += multi_len; 2582 2583 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2584 int vic_index; 2585 struct drm_display_mode *newmode = NULL; 2586 unsigned int newflag = 0; 2587 bool detail_present; 2588 2589 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2590 2591 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2592 break; 2593 2594 /* 2D_VIC_order_X */ 2595 vic_index = db[8 + offset + i] >> 4; 2596 2597 /* 3D_Structure_X */ 2598 switch (db[8 + offset + i] & 0x0f) { 2599 case 0: 2600 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2601 break; 2602 case 6: 2603 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2604 break; 2605 case 8: 2606 /* 3D_Detail_X */ 2607 if ((db[9 + offset + i] >> 4) == 1) 2608 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2609 break; 2610 } 2611 2612 if (newflag != 0) { 2613 newmode = drm_display_mode_from_vic_index( 2614 video_db, 2615 video_len, 2616 vic_index); 2617 2618 if (newmode) { 2619 newmode->flags |= newflag; 2620 drm_add_hdmi_modes(data, newmode); 2621 modes++; 2622 drm_mode_destroy(newmode); 2623 } 2624 } 2625 2626 if (detail_present) 2627 i++; 2628 } 2629 2630 out: 2631 return modes; 2632 } 2633 2634 /** 2635 * edid_get_quirks - return quirk flags for a given EDID 2636 * @edid: EDID to process 2637 * 2638 * This tells subsequent routines what fixes they need to apply. 2639 */ 2640 static u32 edid_get_quirks(struct edid *edid) 2641 { 2642 struct edid_quirk *quirk; 2643 int i; 2644 2645 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2646 quirk = &edid_quirk_list[i]; 2647 2648 if (edid_vendor(edid, quirk->vendor) && 2649 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2650 return quirk->quirks; 2651 } 2652 2653 return 0; 2654 } 2655 2656 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 2657 const u8 *db) 2658 { 2659 struct drm_display_info *info = &data->display_info; 2660 struct drm_hdmi_info *hdmi = &info->hdmi; 2661 u8 map_len = cea_db_payload_len(db) - 1; 2662 u8 count; 2663 u64 map = 0; 2664 2665 if (map_len == 0) { 2666 /* All CEA modes support ycbcr420 sampling also.*/ 2667 hdmi->y420_cmdb_map = U64_MAX; 2668 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2669 return; 2670 } 2671 2672 /* 2673 * This map indicates which of the existing CEA block modes 2674 * from VDB can support YCBCR420 output too. So if bit=0 is 2675 * set, first mode from VDB can support YCBCR420 output too. 2676 * We will parse and keep this map, before parsing VDB itself 2677 * to avoid going through the same block again and again. 2678 * 2679 * Spec is not clear about max possible size of this block. 2680 * Clamping max bitmap block size at 8 bytes. Every byte can 2681 * address 8 CEA modes, in this way this map can address 2682 * 8*8 = first 64 SVDs. 2683 */ 2684 if (map_len > 8) 2685 map_len = 8; 2686 2687 for (count = 0; count < map_len; count++) 2688 map |= (u64)db[2 + count] << (8 * count); 2689 2690 if (map) 2691 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2692 2693 hdmi->y420_cmdb_map = map; 2694 } 2695 2696 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 2697 const u8 *db) 2698 { 2699 u8 dc_mask; 2700 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2701 2702 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 2703 hdmi->y420_dc_modes |= dc_mask; 2704 } 2705 2706 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 2707 const u8 *hf_vsdb) 2708 { 2709 struct drm_display_info *display = &data->display_info; 2710 struct drm_hdmi_info *hdmi = &display->hdmi; 2711 2712 if (hf_vsdb[6] & 0x80) { 2713 hdmi->scdc.supported = true; 2714 if (hf_vsdb[6] & 0x40) 2715 hdmi->scdc.read_request = true; 2716 } 2717 2718 /* 2719 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 2720 * And as per the spec, three factors confirm this: 2721 * * Availability of a HF-VSDB block in EDID (check) 2722 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 2723 * * SCDC support available (let's check) 2724 * Lets check it out. 2725 */ 2726 2727 if (hf_vsdb[5]) { 2728 /* max clock is 5000 KHz times block value */ 2729 u32 max_tmds_clock = hf_vsdb[5] * 5000; 2730 struct drm_scdc *scdc = &hdmi->scdc; 2731 2732 if (max_tmds_clock > 340000) { 2733 display->max_tmds_clock = max_tmds_clock; 2734 debug("HF-VSDB: max TMDS clock %d kHz\n", 2735 display->max_tmds_clock); 2736 } 2737 2738 if (scdc->supported) { 2739 scdc->scrambling.supported = true; 2740 2741 /* Few sinks support scrambling for cloks < 340M */ 2742 if ((hf_vsdb[6] & 0x8)) 2743 scdc->scrambling.low_rates = true; 2744 } 2745 } 2746 2747 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 2748 } 2749 2750 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 2751 const u8 *hdmi) 2752 { 2753 struct drm_display_info *info = &data->display_info; 2754 unsigned int dc_bpc = 0; 2755 2756 /* HDMI supports at least 8 bpc */ 2757 info->bpc = 8; 2758 2759 if (cea_db_payload_len(hdmi) < 6) 2760 return; 2761 2762 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 2763 dc_bpc = 10; 2764 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 2765 debug("HDMI sink does deep color 30.\n"); 2766 } 2767 2768 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 2769 dc_bpc = 12; 2770 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 2771 debug("HDMI sink does deep color 36.\n"); 2772 } 2773 2774 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 2775 dc_bpc = 16; 2776 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 2777 debug("HDMI sink does deep color 48.\n"); 2778 } 2779 2780 if (dc_bpc == 0) { 2781 debug("No deep color support on this HDMI sink.\n"); 2782 return; 2783 } 2784 2785 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 2786 info->bpc = dc_bpc; 2787 2788 /* YCRCB444 is optional according to spec. */ 2789 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 2790 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 2791 debug("HDMI sink does YCRCB444 in deep color.\n"); 2792 } 2793 2794 /* 2795 * Spec says that if any deep color mode is supported at all, 2796 * then deep color 36 bit must be supported. 2797 */ 2798 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 2799 debug("HDMI sink should do DC_36, but does not!\n"); 2800 } 2801 2802 /* 2803 * Search EDID for CEA extension block. 2804 */ 2805 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2806 { 2807 u8 *edid_ext = NULL; 2808 int i; 2809 2810 /* No EDID or EDID extensions */ 2811 if (!edid || !edid->extensions) 2812 return NULL; 2813 2814 /* Find CEA extension */ 2815 for (i = 0; i < edid->extensions; i++) { 2816 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 2817 if (edid_ext[0] == ext_id) 2818 break; 2819 } 2820 2821 if (i == edid->extensions) 2822 return NULL; 2823 2824 return edid_ext; 2825 } 2826 2827 static u8 *drm_find_cea_extension(struct edid *edid) 2828 { 2829 return drm_find_edid_extension(edid, 0x02); 2830 } 2831 2832 #define AUDIO_BLOCK 0x01 2833 #define VIDEO_BLOCK 0x02 2834 #define VENDOR_BLOCK 0x03 2835 #define SPEAKER_BLOCK 0x04 2836 #define EDID_BASIC_AUDIO BIT(6) 2837 2838 /** 2839 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 2840 * @edid: monitor EDID information 2841 * 2842 * Parse the CEA extension according to CEA-861-B. 2843 * 2844 * Return: True if the monitor is HDMI, false if not or unknown. 2845 */ 2846 bool drm_detect_hdmi_monitor(struct edid *edid) 2847 { 2848 u8 *edid_ext; 2849 int i; 2850 int start_offset, end_offset; 2851 2852 edid_ext = drm_find_cea_extension(edid); 2853 if (!edid_ext) 2854 return false; 2855 2856 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2857 return false; 2858 2859 /* 2860 * Because HDMI identifier is in Vendor Specific Block, 2861 * search it from all data blocks of CEA extension. 2862 */ 2863 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2864 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 2865 return true; 2866 } 2867 2868 return false; 2869 } 2870 2871 /** 2872 * drm_detect_monitor_audio - check monitor audio capability 2873 * @edid: EDID block to scan 2874 * 2875 * Monitor should have CEA extension block. 2876 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 2877 * audio' only. If there is any audio extension block and supported 2878 * audio format, assume at least 'basic audio' support, even if 'basic 2879 * audio' is not defined in EDID. 2880 * 2881 * Return: True if the monitor supports audio, false otherwise. 2882 */ 2883 bool drm_detect_monitor_audio(struct edid *edid) 2884 { 2885 u8 *edid_ext; 2886 int i, j; 2887 bool has_audio = false; 2888 int start_offset, end_offset; 2889 2890 edid_ext = drm_find_cea_extension(edid); 2891 if (!edid_ext) 2892 goto end; 2893 2894 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 2895 2896 if (has_audio) { 2897 printf("Monitor has basic audio support\n"); 2898 goto end; 2899 } 2900 2901 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2902 goto end; 2903 2904 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2905 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 2906 has_audio = true; 2907 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 2908 j += 3) 2909 debug("CEA audio format %d\n", 2910 (edid_ext[i + j] >> 3) & 0xf); 2911 goto end; 2912 } 2913 } 2914 end: 2915 return has_audio; 2916 } 2917 2918 static void 2919 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 2920 { 2921 struct drm_display_info *info = &data->display_info; 2922 u8 len = cea_db_payload_len(db); 2923 2924 if (len >= 6) 2925 info->dvi_dual = db[6] & 1; 2926 if (len >= 7) 2927 info->max_tmds_clock = db[7] * 5000; 2928 2929 drm_parse_hdmi_deep_color_info(data, db); 2930 } 2931 2932 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 2933 struct edid *edid) 2934 { 2935 struct drm_display_info *info = &data->display_info; 2936 const u8 *edid_ext; 2937 int i, start, end; 2938 2939 edid_ext = drm_find_cea_extension(edid); 2940 if (!edid_ext) 2941 return; 2942 2943 info->cea_rev = edid_ext[1]; 2944 2945 /* The existence of a CEA block should imply RGB support */ 2946 info->color_formats = DRM_COLOR_FORMAT_RGB444; 2947 if (edid_ext[3] & EDID_CEA_YCRCB444) 2948 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 2949 if (edid_ext[3] & EDID_CEA_YCRCB422) 2950 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 2951 2952 if (cea_db_offsets(edid_ext, &start, &end)) 2953 return; 2954 2955 for_each_cea_db(edid_ext, i, start, end) { 2956 const u8 *db = &edid_ext[i]; 2957 2958 if (cea_db_is_hdmi_vsdb(db)) 2959 drm_parse_hdmi_vsdb_video(data, db); 2960 if (cea_db_is_hdmi_forum_vsdb(db)) 2961 drm_parse_hdmi_forum_vsdb(data, db); 2962 if (cea_db_is_y420cmdb(db)) 2963 drm_parse_y420cmdb_bitmap(data, db); 2964 } 2965 } 2966 2967 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 2968 { 2969 struct drm_display_info *info = &data->display_info; 2970 2971 info->width_mm = edid->width_cm * 10; 2972 info->height_mm = edid->height_cm * 10; 2973 2974 /* driver figures it out in this case */ 2975 info->bpc = 0; 2976 info->color_formats = 0; 2977 info->cea_rev = 0; 2978 info->max_tmds_clock = 0; 2979 info->dvi_dual = false; 2980 info->edid_hdmi_dc_modes = 0; 2981 2982 memset(&info->hdmi, 0, sizeof(info->hdmi)); 2983 2984 if (edid->revision < 3) 2985 return; 2986 2987 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 2988 return; 2989 2990 drm_parse_cea_ext(data, edid); 2991 2992 /* 2993 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 2994 * 2995 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 2996 * tells us to assume 8 bpc color depth if the EDID doesn't have 2997 * extensions which tell otherwise. 2998 */ 2999 if ((info->bpc == 0) && (edid->revision < 4) && 3000 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3001 info->bpc = 8; 3002 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3003 } 3004 3005 /* Only defined for 1.4 with digital displays */ 3006 if (edid->revision < 4) 3007 return; 3008 3009 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3010 case DRM_EDID_DIGITAL_DEPTH_6: 3011 info->bpc = 6; 3012 break; 3013 case DRM_EDID_DIGITAL_DEPTH_8: 3014 info->bpc = 8; 3015 break; 3016 case DRM_EDID_DIGITAL_DEPTH_10: 3017 info->bpc = 10; 3018 break; 3019 case DRM_EDID_DIGITAL_DEPTH_12: 3020 info->bpc = 12; 3021 break; 3022 case DRM_EDID_DIGITAL_DEPTH_14: 3023 info->bpc = 14; 3024 break; 3025 case DRM_EDID_DIGITAL_DEPTH_16: 3026 info->bpc = 16; 3027 break; 3028 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3029 default: 3030 info->bpc = 0; 3031 break; 3032 } 3033 3034 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3035 info->bpc); 3036 3037 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3038 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3039 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3040 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3041 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3042 } 3043 3044 static 3045 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3046 { 3047 const u8 *cea = drm_find_cea_extension(edid); 3048 const u8 *db, *hdmi = NULL, *video = NULL; 3049 u8 dbl, hdmi_len, video_len = 0; 3050 int modes = 0; 3051 3052 if (cea && cea_revision(cea) >= 3) { 3053 int i, start, end; 3054 3055 if (cea_db_offsets(cea, &start, &end)) 3056 return 0; 3057 3058 for_each_cea_db(cea, i, start, end) { 3059 db = &cea[i]; 3060 dbl = cea_db_payload_len(db); 3061 3062 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3063 video = db + 1; 3064 video_len = dbl; 3065 modes += do_cea_modes(data, video, dbl); 3066 } else if (cea_db_is_hdmi_vsdb(db)) { 3067 hdmi = db; 3068 hdmi_len = dbl; 3069 } else if (cea_db_is_y420vdb(db)) { 3070 const u8 *vdb420 = &db[2]; 3071 3072 /* Add 4:2:0(only) modes present in EDID */ 3073 modes += do_y420vdb_modes(data, vdb420, 3074 dbl - 1); 3075 } 3076 } 3077 } 3078 3079 /* 3080 * We parse the HDMI VSDB after having added the cea modes as we will 3081 * be patching their flags when the sink supports stereo 3D. 3082 */ 3083 if (hdmi) 3084 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3085 video_len, data); 3086 3087 return modes; 3088 } 3089 3090 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3091 3092 static void 3093 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3094 { 3095 int i, n = 0; 3096 u8 d = ext[0x02]; 3097 u8 *det_base = ext + d; 3098 3099 n = (127 - d) / 18; 3100 for (i = 0; i < n; i++) 3101 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3102 } 3103 3104 static void 3105 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3106 { 3107 unsigned int i, n = min((int)ext[0x02], 6); 3108 u8 *det_base = ext + 5; 3109 3110 if (ext[0x01] != 1) 3111 return; /* unknown version */ 3112 3113 for (i = 0; i < n; i++) 3114 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3115 } 3116 3117 static void 3118 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3119 { 3120 int i; 3121 struct edid *edid = (struct edid *)raw_edid; 3122 3123 if (!edid) 3124 return; 3125 3126 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3127 cb(&edid->detailed_timings[i], closure); 3128 3129 for (i = 1; i <= raw_edid[0x7e]; i++) { 3130 u8 *ext = raw_edid + (i * EDID_SIZE); 3131 3132 switch (*ext) { 3133 case CEA_EXT: 3134 cea_for_each_detailed_block(ext, cb, closure); 3135 break; 3136 case VTB_EXT: 3137 vtb_for_each_detailed_block(ext, cb, closure); 3138 break; 3139 default: 3140 break; 3141 } 3142 } 3143 } 3144 3145 /* 3146 * EDID is delightfully ambiguous about how interlaced modes are to be 3147 * encoded. Our internal representation is of frame height, but some 3148 * HDTV detailed timings are encoded as field height. 3149 * 3150 * The format list here is from CEA, in frame size. Technically we 3151 * should be checking refresh rate too. Whatever. 3152 */ 3153 static void 3154 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3155 struct detailed_pixel_timing *pt) 3156 { 3157 int i; 3158 3159 static const struct { 3160 int w, h; 3161 } cea_interlaced[] = { 3162 { 1920, 1080 }, 3163 { 720, 480 }, 3164 { 1440, 480 }, 3165 { 2880, 480 }, 3166 { 720, 576 }, 3167 { 1440, 576 }, 3168 { 2880, 576 }, 3169 }; 3170 3171 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3172 return; 3173 3174 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3175 if ((mode->hdisplay == cea_interlaced[i].w) && 3176 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3177 mode->vdisplay *= 2; 3178 mode->vsync_start *= 2; 3179 mode->vsync_end *= 2; 3180 mode->vtotal *= 2; 3181 mode->vtotal |= 1; 3182 } 3183 } 3184 3185 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3186 } 3187 3188 /** 3189 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3190 * @edid: EDID block 3191 * @timing: EDID detailed timing info 3192 * @quirks: quirks to apply 3193 * 3194 * An EDID detailed timing block contains enough info for us to create and 3195 * return a new struct drm_display_mode. 3196 */ 3197 static 3198 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3199 struct detailed_timing *timing, 3200 u32 quirks) 3201 { 3202 struct drm_display_mode *mode; 3203 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3204 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3205 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3206 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3207 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3208 unsigned hsync_offset = 3209 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3210 pt->hsync_offset_lo; 3211 unsigned hsync_pulse_width = 3212 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3213 pt->hsync_pulse_width_lo; 3214 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3215 2 | pt->vsync_offset_pulse_width_lo >> 4; 3216 unsigned vsync_pulse_width = 3217 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3218 (pt->vsync_offset_pulse_width_lo & 0xf); 3219 3220 /* ignore tiny modes */ 3221 if (hactive < 64 || vactive < 64) 3222 return NULL; 3223 3224 if (pt->misc & DRM_EDID_PT_STEREO) { 3225 debug("stereo mode not supported\n"); 3226 return NULL; 3227 } 3228 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3229 debug("composite sync not supported\n"); 3230 3231 /* it is incorrect if hsync/vsync width is zero */ 3232 if (!hsync_pulse_width || !vsync_pulse_width) { 3233 debug("Incorrect Detailed timing. "); 3234 debug("Wrong Hsync/Vsync pulse width\n"); 3235 return NULL; 3236 } 3237 3238 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3239 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3240 if (!mode) 3241 return NULL; 3242 3243 goto set_refresh; 3244 } 3245 3246 mode = drm_mode_create(); 3247 if (!mode) 3248 return NULL; 3249 3250 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3251 timing->pixel_clock = cpu_to_le16(1088); 3252 3253 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3254 3255 mode->hdisplay = hactive; 3256 mode->hsync_start = mode->hdisplay + hsync_offset; 3257 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3258 mode->htotal = mode->hdisplay + hblank; 3259 3260 mode->vdisplay = vactive; 3261 mode->vsync_start = mode->vdisplay + vsync_offset; 3262 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3263 mode->vtotal = mode->vdisplay + vblank; 3264 3265 /* Some EDIDs have bogus h/vtotal values */ 3266 if (mode->hsync_end > mode->htotal) 3267 mode->htotal = mode->hsync_end + 1; 3268 if (mode->vsync_end > mode->vtotal) 3269 mode->vtotal = mode->vsync_end + 1; 3270 3271 drm_mode_do_interlace_quirk(mode, pt); 3272 3273 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3274 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3275 DRM_EDID_PT_VSYNC_POSITIVE; 3276 3277 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3278 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3279 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3280 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3281 3282 set_refresh: 3283 3284 mode->type = DRM_MODE_TYPE_DRIVER; 3285 mode->vrefresh = drm_get_vrefresh(mode); 3286 3287 return mode; 3288 } 3289 3290 /* 3291 * Calculate the alternate clock for the CEA mode 3292 * (60Hz vs. 59.94Hz etc.) 3293 */ 3294 static unsigned int 3295 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3296 { 3297 unsigned int clock = cea_mode->clock; 3298 3299 if (cea_mode->vrefresh % 6 != 0) 3300 return clock; 3301 3302 /* 3303 * edid_cea_modes contains the 59.94Hz 3304 * variant for 240 and 480 line modes, 3305 * and the 60Hz variant otherwise. 3306 */ 3307 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3308 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3309 else 3310 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3311 3312 return clock; 3313 } 3314 3315 /** 3316 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3317 * @mode1: first mode 3318 * @mode2: second mode 3319 * 3320 * Check to see if @mode1 and @mode2 are equivalent, but 3321 * don't check the pixel clocks nor the stereo layout. 3322 * 3323 * Returns: 3324 * True if the modes are equal, false otherwise. 3325 */ 3326 3327 static 3328 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3329 const struct drm_display_mode *mode2) 3330 { 3331 unsigned int flags_mask = 3332 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3333 3334 if (mode1->hdisplay == mode2->hdisplay && 3335 mode1->hsync_start == mode2->hsync_start && 3336 mode1->hsync_end == mode2->hsync_end && 3337 mode1->htotal == mode2->htotal && 3338 mode1->vdisplay == mode2->vdisplay && 3339 mode1->vsync_start == mode2->vsync_start && 3340 mode1->vsync_end == mode2->vsync_end && 3341 mode1->vtotal == mode2->vtotal && 3342 mode1->vscan == mode2->vscan && 3343 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3344 return true; 3345 3346 return false; 3347 } 3348 3349 /** 3350 * drm_mode_equal_no_clocks - test modes for equality 3351 * @mode1: first mode 3352 * @mode2: second mode 3353 * 3354 * Check to see if @mode1 and @mode2 are equivalent, but 3355 * don't check the pixel clocks. 3356 * 3357 * Returns: 3358 * True if the modes are equal, false otherwise. 3359 */ 3360 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3361 const struct drm_display_mode *mode2) 3362 { 3363 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3364 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3365 return false; 3366 3367 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3368 } 3369 3370 static 3371 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3372 unsigned int clock_tolerance) 3373 { 3374 u8 vic; 3375 3376 if (!to_match->clock) 3377 return 0; 3378 3379 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3380 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 3381 unsigned int clock1, clock2; 3382 3383 /* Check both 60Hz and 59.94Hz */ 3384 clock1 = cea_mode->clock; 3385 clock2 = cea_mode_alternate_clock(cea_mode); 3386 3387 if (abs(to_match->clock - clock1) > clock_tolerance && 3388 abs(to_match->clock - clock2) > clock_tolerance) 3389 continue; 3390 3391 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3392 return vic; 3393 } 3394 3395 return 0; 3396 } 3397 3398 static unsigned int 3399 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3400 { 3401 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3402 return hdmi_mode->clock; 3403 3404 return cea_mode_alternate_clock(hdmi_mode); 3405 } 3406 3407 static 3408 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3409 unsigned int clock_tolerance) 3410 { 3411 u8 vic; 3412 3413 if (!to_match->clock) 3414 return 0; 3415 3416 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3417 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3418 unsigned int clock1, clock2; 3419 3420 /* Make sure to also match alternate clocks */ 3421 clock1 = hdmi_mode->clock; 3422 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3423 3424 if (abs(to_match->clock - clock1) > clock_tolerance && 3425 abs(to_match->clock - clock2) > clock_tolerance) 3426 continue; 3427 3428 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3429 return vic; 3430 } 3431 3432 return 0; 3433 } 3434 3435 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3436 { 3437 const struct drm_display_mode *cea_mode; 3438 int clock1, clock2, clock; 3439 u8 vic; 3440 const char *type; 3441 3442 /* 3443 * allow 5kHz clock difference either way to account for 3444 * the 10kHz clock resolution limit of detailed timings. 3445 */ 3446 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3447 if (drm_valid_cea_vic(vic)) { 3448 type = "CEA"; 3449 cea_mode = &edid_cea_modes[vic]; 3450 clock1 = cea_mode->clock; 3451 clock2 = cea_mode_alternate_clock(cea_mode); 3452 } else { 3453 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3454 if (drm_valid_hdmi_vic(vic)) { 3455 type = "HDMI"; 3456 cea_mode = &edid_4k_modes[vic]; 3457 clock1 = cea_mode->clock; 3458 clock2 = hdmi_mode_alternate_clock(cea_mode); 3459 } else { 3460 return; 3461 } 3462 } 3463 3464 /* pick whichever is closest */ 3465 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3466 clock = clock1; 3467 else 3468 clock = clock2; 3469 3470 if (mode->clock == clock) 3471 return; 3472 3473 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3474 type, vic, mode->clock, clock); 3475 mode->clock = clock; 3476 } 3477 3478 static void 3479 do_detailed_mode(struct detailed_timing *timing, void *c) 3480 { 3481 struct detailed_mode_closure *closure = c; 3482 struct drm_display_mode *newmode; 3483 3484 if (timing->pixel_clock) { 3485 newmode = drm_mode_detailed( 3486 closure->edid, timing, 3487 closure->quirks); 3488 if (!newmode) 3489 return; 3490 3491 if (closure->preferred) 3492 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3493 3494 /* 3495 * Detailed modes are limited to 10kHz pixel clock resolution, 3496 * so fix up anything that looks like CEA/HDMI mode, 3497 * but the clock is just slightly off. 3498 */ 3499 fixup_detailed_cea_mode_clock(newmode); 3500 drm_add_hdmi_modes(closure->data, newmode); 3501 drm_mode_destroy(newmode); 3502 closure->modes++; 3503 closure->preferred = 0; 3504 } 3505 } 3506 3507 /* 3508 * add_detailed_modes - Add modes from detailed timings 3509 * @data: attached data 3510 * @edid: EDID block to scan 3511 * @quirks: quirks to apply 3512 */ 3513 static int 3514 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 3515 u32 quirks) 3516 { 3517 struct detailed_mode_closure closure = { 3518 .data = data, 3519 .edid = edid, 3520 .preferred = 1, 3521 .quirks = quirks, 3522 }; 3523 3524 if (closure.preferred && !version_greater(edid, 1, 3)) 3525 closure.preferred = 3526 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3527 3528 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3529 3530 return closure.modes; 3531 } 3532 3533 static int drm_cvt_modes(struct hdmi_edid_data *data, 3534 struct detailed_timing *timing) 3535 { 3536 int i, j, modes = 0; 3537 struct drm_display_mode *newmode; 3538 struct cvt_timing *cvt; 3539 const int rates[] = { 60, 85, 75, 60, 50 }; 3540 const u8 empty[3] = { 0, 0, 0 }; 3541 3542 for (i = 0; i < 4; i++) { 3543 int uninitialized_var(width), height; 3544 3545 cvt = &timing->data.other_data.data.cvt[i]; 3546 3547 if (!memcmp(cvt->code, empty, 3)) 3548 continue; 3549 3550 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3551 switch (cvt->code[1] & 0x0c) { 3552 case 0x00: 3553 width = height * 4 / 3; 3554 break; 3555 case 0x04: 3556 width = height * 16 / 9; 3557 break; 3558 case 0x08: 3559 width = height * 16 / 10; 3560 break; 3561 case 0x0c: 3562 width = height * 15 / 9; 3563 break; 3564 } 3565 3566 for (j = 1; j < 5; j++) { 3567 if (cvt->code[2] & (1 << j)) { 3568 newmode = drm_cvt_mode(width, height, 3569 rates[j], j == 0, 3570 false, false); 3571 if (newmode) { 3572 drm_add_hdmi_modes(data, newmode); 3573 modes++; 3574 drm_mode_destroy(newmode); 3575 } 3576 } 3577 } 3578 } 3579 3580 return modes; 3581 } 3582 3583 static void 3584 do_cvt_mode(struct detailed_timing *timing, void *c) 3585 { 3586 struct detailed_mode_closure *closure = c; 3587 struct detailed_non_pixel *data = &timing->data.other_data; 3588 3589 if (data->type == EDID_DETAIL_CVT_3BYTE) 3590 closure->modes += drm_cvt_modes(closure->data, timing); 3591 } 3592 3593 static int 3594 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 3595 { 3596 struct detailed_mode_closure closure = { 3597 .data = data, 3598 .edid = edid, 3599 }; 3600 3601 if (version_greater(edid, 1, 2)) 3602 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3603 3604 /* XXX should also look for CVT codes in VTB blocks */ 3605 3606 return closure.modes; 3607 } 3608 3609 static void 3610 find_gtf2(struct detailed_timing *t, void *data) 3611 { 3612 u8 *r = (u8 *)t; 3613 3614 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 3615 *(u8 **)data = r; 3616 } 3617 3618 /* Secondary GTF curve kicks in above some break frequency */ 3619 static int 3620 drm_gtf2_hbreak(struct edid *edid) 3621 { 3622 u8 *r = NULL; 3623 3624 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3625 return r ? (r[12] * 2) : 0; 3626 } 3627 3628 static int 3629 drm_gtf2_2c(struct edid *edid) 3630 { 3631 u8 *r = NULL; 3632 3633 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3634 return r ? r[13] : 0; 3635 } 3636 3637 static int 3638 drm_gtf2_m(struct edid *edid) 3639 { 3640 u8 *r = NULL; 3641 3642 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3643 return r ? (r[15] << 8) + r[14] : 0; 3644 } 3645 3646 static int 3647 drm_gtf2_k(struct edid *edid) 3648 { 3649 u8 *r = NULL; 3650 3651 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3652 return r ? r[16] : 0; 3653 } 3654 3655 static int 3656 drm_gtf2_2j(struct edid *edid) 3657 { 3658 u8 *r = NULL; 3659 3660 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3661 return r ? r[17] : 0; 3662 } 3663 3664 /** 3665 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 3666 * @edid: EDID block to scan 3667 */ 3668 static int standard_timing_level(struct edid *edid) 3669 { 3670 if (edid->revision >= 2) { 3671 if (edid->revision >= 4 && 3672 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 3673 return LEVEL_CVT; 3674 if (drm_gtf2_hbreak(edid)) 3675 return LEVEL_GTF2; 3676 return LEVEL_GTF; 3677 } 3678 return LEVEL_DMT; 3679 } 3680 3681 /* 3682 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3683 * monitors fill with ascii space (0x20) instead. 3684 */ 3685 static int 3686 bad_std_timing(u8 a, u8 b) 3687 { 3688 return (a == 0x00 && b == 0x00) || 3689 (a == 0x01 && b == 0x01) || 3690 (a == 0x20 && b == 0x20); 3691 } 3692 3693 static void 3694 is_rb(struct detailed_timing *t, void *data) 3695 { 3696 u8 *r = (u8 *)t; 3697 3698 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 3699 if (r[15] & 0x10) 3700 *(bool *)data = true; 3701 } 3702 3703 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3704 static bool 3705 drm_monitor_supports_rb(struct edid *edid) 3706 { 3707 if (edid->revision >= 4) { 3708 bool ret = false; 3709 3710 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 3711 return ret; 3712 } 3713 3714 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3715 } 3716 3717 static bool 3718 mode_is_rb(const struct drm_display_mode *mode) 3719 { 3720 return (mode->htotal - mode->hdisplay == 160) && 3721 (mode->hsync_end - mode->hdisplay == 80) && 3722 (mode->hsync_end - mode->hsync_start == 32) && 3723 (mode->vsync_start - mode->vdisplay == 3); 3724 } 3725 3726 /* 3727 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3728 * @hsize: Mode width 3729 * @vsize: Mode height 3730 * @fresh: Mode refresh rate 3731 * @rb: Mode reduced-blanking-ness 3732 * 3733 * Walk the DMT mode list looking for a match for the given parameters. 3734 * 3735 * Return: A newly allocated copy of the mode, or NULL if not found. 3736 */ 3737 static struct drm_display_mode *drm_mode_find_dmt( 3738 int hsize, int vsize, int fresh, 3739 bool rb) 3740 { 3741 int i; 3742 struct drm_display_mode *newmode; 3743 3744 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3745 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3746 3747 if (hsize != ptr->hdisplay) 3748 continue; 3749 if (vsize != ptr->vdisplay) 3750 continue; 3751 if (fresh != drm_get_vrefresh(ptr)) 3752 continue; 3753 if (rb != mode_is_rb(ptr)) 3754 continue; 3755 3756 newmode = drm_mode_create(); 3757 *newmode = *ptr; 3758 return newmode; 3759 } 3760 3761 return NULL; 3762 } 3763 3764 static struct drm_display_mode * 3765 drm_gtf_mode_complex(int hdisplay, int vdisplay, 3766 int vrefresh, bool interlaced, int margins, 3767 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 3768 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 3769 #define GTF_MARGIN_PERCENTAGE 18 3770 /* 2) character cell horizontal granularity (pixels) - default 8 */ 3771 #define GTF_CELL_GRAN 8 3772 /* 3) Minimum vertical porch (lines) - default 3 */ 3773 #define GTF_MIN_V_PORCH 1 3774 /* width of vsync in lines */ 3775 #define V_SYNC_RQD 3 3776 /* width of hsync as % of total line */ 3777 #define H_SYNC_PERCENT 8 3778 /* min time of vsync + back porch (microsec) */ 3779 #define MIN_VSYNC_PLUS_BP 550 3780 /* C' and M' are part of the Blanking Duty Cycle computation */ 3781 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 3782 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 3783 struct drm_display_mode *drm_mode; 3784 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 3785 int top_margin, bottom_margin; 3786 int interlace; 3787 unsigned int hfreq_est; 3788 int vsync_plus_bp; 3789 unsigned int vtotal_lines; 3790 int left_margin, right_margin; 3791 unsigned int total_active_pixels, ideal_duty_cycle; 3792 unsigned int hblank, total_pixels, pixel_freq; 3793 int hsync, hfront_porch, vodd_front_porch_lines; 3794 unsigned int tmp1, tmp2; 3795 3796 drm_mode = drm_mode_create(); 3797 if (!drm_mode) 3798 return NULL; 3799 3800 /* 1. In order to give correct results, the number of horizontal 3801 * pixels requested is first processed to ensure that it is divisible 3802 * by the character size, by rounding it to the nearest character 3803 * cell boundary: 3804 */ 3805 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3806 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 3807 3808 /* 2. If interlace is requested, the number of vertical lines assumed 3809 * by the calculation must be halved, as the computation calculates 3810 * the number of vertical lines per field. 3811 */ 3812 if (interlaced) 3813 vdisplay_rnd = vdisplay / 2; 3814 else 3815 vdisplay_rnd = vdisplay; 3816 3817 /* 3. Find the frame rate required: */ 3818 if (interlaced) 3819 vfieldrate_rqd = vrefresh * 2; 3820 else 3821 vfieldrate_rqd = vrefresh; 3822 3823 /* 4. Find number of lines in Top margin: */ 3824 top_margin = 0; 3825 if (margins) 3826 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3827 1000; 3828 /* 5. Find number of lines in bottom margin: */ 3829 bottom_margin = top_margin; 3830 3831 /* 6. If interlace is required, then set variable interlace: */ 3832 if (interlaced) 3833 interlace = 1; 3834 else 3835 interlace = 0; 3836 3837 /* 7. Estimate the Horizontal frequency */ 3838 { 3839 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 3840 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 3841 2 + interlace; 3842 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 3843 } 3844 3845 /* 8. Find the number of lines in V sync + back porch */ 3846 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 3847 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 3848 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 3849 /* 9. Find the number of lines in V back porch alone: 3850 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 3851 */ 3852 /* 10. Find the total number of lines in Vertical field period: */ 3853 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 3854 vsync_plus_bp + GTF_MIN_V_PORCH; 3855 /* 11. Estimate the Vertical field frequency: 3856 * vfieldrate_est = hfreq_est / vtotal_lines; 3857 */ 3858 3859 /* 12. Find the actual horizontal period: 3860 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 3861 */ 3862 /* 13. Find the actual Vertical field frequency: 3863 * vfield_rate = hfreq_est / vtotal_lines; 3864 */ 3865 /* 14. Find the Vertical frame frequency: 3866 * if (interlaced) 3867 * vframe_rate = vfield_rate / 2; 3868 * else 3869 * vframe_rate = vfield_rate; 3870 */ 3871 /* 15. Find number of pixels in left margin: */ 3872 if (margins) 3873 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3874 1000; 3875 else 3876 left_margin = 0; 3877 3878 /* 16.Find number of pixels in right margin: */ 3879 right_margin = left_margin; 3880 /* 17.Find total number of active pixels in image and left and right */ 3881 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 3882 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 3883 ideal_duty_cycle = GTF_C_PRIME * 1000 - 3884 (GTF_M_PRIME * 1000000 / hfreq_est); 3885 /* 19.Find the number of pixels in the blanking time to the nearest 3886 * double character cell: 3887 */ 3888 hblank = total_active_pixels * ideal_duty_cycle / 3889 (100000 - ideal_duty_cycle); 3890 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 3891 hblank = hblank * 2 * GTF_CELL_GRAN; 3892 /* 20.Find total number of pixels: */ 3893 total_pixels = total_active_pixels + hblank; 3894 /* 21.Find pixel clock frequency: */ 3895 pixel_freq = total_pixels * hfreq_est / 1000; 3896 /* Stage 1 computations are now complete; I should really pass 3897 * the results to another function and do the Stage 2 computations, 3898 * but I only need a few more values so I'll just append the 3899 * computations here for now 3900 */ 3901 3902 /* 17. Find the number of pixels in the horizontal sync period: */ 3903 hsync = H_SYNC_PERCENT * total_pixels / 100; 3904 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3905 hsync = hsync * GTF_CELL_GRAN; 3906 /* 18. Find the number of pixels in horizontal front porch period */ 3907 hfront_porch = hblank / 2 - hsync; 3908 /* 36. Find the number of lines in the odd front porch period: */ 3909 vodd_front_porch_lines = GTF_MIN_V_PORCH; 3910 3911 /* finally, pack the results in the mode struct */ 3912 drm_mode->hdisplay = hdisplay_rnd; 3913 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 3914 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 3915 drm_mode->htotal = total_pixels; 3916 drm_mode->vdisplay = vdisplay_rnd; 3917 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 3918 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 3919 drm_mode->vtotal = vtotal_lines; 3920 3921 drm_mode->clock = pixel_freq; 3922 3923 if (interlaced) { 3924 drm_mode->vtotal *= 2; 3925 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 3926 } 3927 3928 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 3929 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 3930 else 3931 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 3932 3933 return drm_mode; 3934 } 3935 3936 /** 3937 * drm_gtf_mode - create the mode based on the GTF algorithm 3938 * @hdisplay: hdisplay size 3939 * @vdisplay: vdisplay size 3940 * @vrefresh: vrefresh rate. 3941 * @interlaced: whether to compute an interlaced mode 3942 * @margins: desired margin (borders) size 3943 * 3944 * return the mode based on GTF algorithm 3945 * 3946 * This function is to create the mode based on the GTF algorithm. 3947 * Generalized Timing Formula is derived from: 3948 * GTF Spreadsheet by Andy Morrish (1/5/97) 3949 * available at http://www.vesa.org 3950 * 3951 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 3952 * What I have done is to translate it by using integer calculation. 3953 * I also refer to the function of fb_get_mode in the file of 3954 * drivers/video/fbmon.c 3955 * 3956 * Standard GTF parameters: 3957 * M = 600 3958 * C = 40 3959 * K = 128 3960 * J = 20 3961 * 3962 * Returns: 3963 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 3964 * The display mode object is allocated with drm_mode_create(). Returns NULL 3965 * when no mode could be allocated. 3966 */ 3967 static struct drm_display_mode * 3968 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 3969 bool interlaced, int margins) 3970 { 3971 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 3972 interlaced, margins, 3973 600, 40 * 2, 128, 20 * 2); 3974 } 3975 3976 /** drm_mode_hsync - get the hsync of a mode 3977 * @mode: mode 3978 * 3979 * Returns: 3980 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 3981 * value first if it is not yet set. 3982 */ 3983 static int drm_mode_hsync(const struct drm_display_mode *mode) 3984 { 3985 unsigned int calc_val; 3986 3987 if (mode->htotal < 0) 3988 return 0; 3989 3990 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 3991 calc_val += 500; /* round to 1000Hz */ 3992 calc_val /= 1000; /* truncate to kHz */ 3993 3994 return calc_val; 3995 } 3996 3997 /** 3998 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 3999 * @data: the structure that save parsed hdmi edid data 4000 * @edid: EDID block to scan 4001 * @t: standard timing params 4002 * 4003 * Take the standard timing params (in this case width, aspect, and refresh) 4004 * and convert them into a real mode using CVT/GTF/DMT. 4005 */ 4006 static struct drm_display_mode * 4007 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4008 struct std_timing *t) 4009 { 4010 struct drm_display_mode *mode = NULL; 4011 int i, hsize, vsize; 4012 int vrefresh_rate; 4013 int num = data->modes; 4014 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4015 >> EDID_TIMING_ASPECT_SHIFT; 4016 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4017 >> EDID_TIMING_VFREQ_SHIFT; 4018 int timing_level = standard_timing_level(edid); 4019 4020 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4021 return NULL; 4022 4023 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4024 hsize = t->hsize * 8 + 248; 4025 /* vrefresh_rate = vfreq + 60 */ 4026 vrefresh_rate = vfreq + 60; 4027 /* the vdisplay is calculated based on the aspect ratio */ 4028 if (aspect_ratio == 0) { 4029 if (edid->revision < 3) 4030 vsize = hsize; 4031 else 4032 vsize = (hsize * 10) / 16; 4033 } else if (aspect_ratio == 1) { 4034 vsize = (hsize * 3) / 4; 4035 } else if (aspect_ratio == 2) { 4036 vsize = (hsize * 4) / 5; 4037 } else { 4038 vsize = (hsize * 9) / 16; 4039 } 4040 4041 /* HDTV hack, part 1 */ 4042 if (vrefresh_rate == 60 && 4043 ((hsize == 1360 && vsize == 765) || 4044 (hsize == 1368 && vsize == 769))) { 4045 hsize = 1366; 4046 vsize = 768; 4047 } 4048 4049 /* 4050 * If we already has a mode for this size and refresh 4051 * rate (because it came from detailed or CVT info), use that 4052 * instead. This way we don't have to guess at interlace or 4053 * reduced blanking. 4054 */ 4055 for (i = 0; i < num; i++) 4056 if (data->mode_buf[i].hdisplay == hsize && 4057 data->mode_buf[i].vdisplay == vsize && 4058 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4059 return NULL; 4060 4061 /* HDTV hack, part 2 */ 4062 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4063 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4064 false); 4065 mode->hdisplay = 1366; 4066 mode->hsync_start = mode->hsync_start - 1; 4067 mode->hsync_end = mode->hsync_end - 1; 4068 return mode; 4069 } 4070 4071 /* check whether it can be found in default mode table */ 4072 if (drm_monitor_supports_rb(edid)) { 4073 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4074 true); 4075 if (mode) 4076 return mode; 4077 } 4078 4079 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4080 if (mode) 4081 return mode; 4082 4083 /* okay, generate it */ 4084 switch (timing_level) { 4085 case LEVEL_DMT: 4086 break; 4087 case LEVEL_GTF: 4088 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4089 break; 4090 case LEVEL_GTF2: 4091 /* 4092 * This is potentially wrong if there's ever a monitor with 4093 * more than one ranges section, each claiming a different 4094 * secondary GTF curve. Please don't do that. 4095 */ 4096 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4097 if (!mode) 4098 return NULL; 4099 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4100 drm_mode_destroy(mode); 4101 mode = drm_gtf_mode_complex(hsize, vsize, 4102 vrefresh_rate, 0, 0, 4103 drm_gtf2_m(edid), 4104 drm_gtf2_2c(edid), 4105 drm_gtf2_k(edid), 4106 drm_gtf2_2j(edid)); 4107 } 4108 break; 4109 case LEVEL_CVT: 4110 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4111 false); 4112 break; 4113 } 4114 4115 return mode; 4116 } 4117 4118 static void 4119 do_standard_modes(struct detailed_timing *timing, void *c) 4120 { 4121 struct detailed_mode_closure *closure = c; 4122 struct detailed_non_pixel *data = &timing->data.other_data; 4123 struct edid *edid = closure->edid; 4124 4125 if (data->type == EDID_DETAIL_STD_MODES) { 4126 int i; 4127 4128 for (i = 0; i < 6; i++) { 4129 struct std_timing *std; 4130 struct drm_display_mode *newmode; 4131 4132 std = &data->data.timings[i]; 4133 newmode = drm_mode_std(closure->data, edid, std); 4134 if (newmode) { 4135 drm_add_hdmi_modes(closure->data, newmode); 4136 closure->modes++; 4137 drm_mode_destroy(newmode); 4138 } 4139 } 4140 } 4141 } 4142 4143 /** 4144 * add_standard_modes - get std. modes from EDID and add them 4145 * @data: data to add mode(s) to 4146 * @edid: EDID block to scan 4147 * 4148 * Standard modes can be calculated using the appropriate standard (DMT, 4149 * GTF or CVT. Grab them from @edid and add them to the list. 4150 */ 4151 static int 4152 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4153 { 4154 int i, modes = 0; 4155 struct detailed_mode_closure closure = { 4156 .data = data, 4157 .edid = edid, 4158 }; 4159 4160 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4161 struct drm_display_mode *newmode; 4162 4163 newmode = drm_mode_std(data, edid, 4164 &edid->standard_timings[i]); 4165 if (newmode) { 4166 drm_add_hdmi_modes(data, newmode); 4167 modes++; 4168 drm_mode_destroy(newmode); 4169 } 4170 } 4171 4172 if (version_greater(edid, 1, 0)) 4173 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4174 &closure); 4175 4176 /* XXX should also look for standard codes in VTB blocks */ 4177 4178 return modes + closure.modes; 4179 } 4180 4181 static int 4182 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4183 { 4184 int i, j, m, modes = 0; 4185 struct drm_display_mode *mode; 4186 u8 *est = ((u8 *)timing) + 6; 4187 4188 for (i = 0; i < 6; i++) { 4189 for (j = 7; j >= 0; j--) { 4190 m = (i * 8) + (7 - j); 4191 if (m >= ARRAY_SIZE(est3_modes)) 4192 break; 4193 if (est[i] & (1 << j)) { 4194 mode = drm_mode_find_dmt( 4195 est3_modes[m].w, 4196 est3_modes[m].h, 4197 est3_modes[m].r, 4198 est3_modes[m].rb); 4199 if (mode) { 4200 drm_add_hdmi_modes(data, mode); 4201 modes++; 4202 drm_mode_destroy(mode); 4203 } 4204 } 4205 } 4206 } 4207 4208 return modes; 4209 } 4210 4211 static void 4212 do_established_modes(struct detailed_timing *timing, void *c) 4213 { 4214 struct detailed_mode_closure *closure = c; 4215 struct detailed_non_pixel *data = &timing->data.other_data; 4216 4217 if (data->type == EDID_DETAIL_EST_TIMINGS) 4218 closure->modes += drm_est3_modes(closure->data, timing); 4219 } 4220 4221 /** 4222 * add_established_modes - get est. modes from EDID and add them 4223 * @data: data to add mode(s) to 4224 * @edid: EDID block to scan 4225 * 4226 * Each EDID block contains a bitmap of the supported "established modes" list 4227 * (defined above). Tease them out and add them to the modes list. 4228 */ 4229 static int 4230 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4231 { 4232 unsigned long est_bits = edid->established_timings.t1 | 4233 (edid->established_timings.t2 << 8) | 4234 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4235 int i, modes = 0; 4236 struct detailed_mode_closure closure = { 4237 .data = data, 4238 .edid = edid, 4239 }; 4240 4241 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4242 if (est_bits & (1 << i)) { 4243 struct drm_display_mode *newmode = drm_mode_create(); 4244 *newmode = edid_est_modes[i]; 4245 if (newmode) { 4246 drm_add_hdmi_modes(data, newmode); 4247 modes++; 4248 drm_mode_destroy(newmode); 4249 } 4250 } 4251 } 4252 4253 if (version_greater(edid, 1, 0)) 4254 drm_for_each_detailed_block((u8 *)edid, 4255 do_established_modes, &closure); 4256 4257 return modes + closure.modes; 4258 } 4259 4260 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4261 { 4262 u8 vic; 4263 4264 if (!to_match->clock) 4265 return 0; 4266 4267 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4268 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4269 unsigned int clock1, clock2; 4270 4271 /* Make sure to also match alternate clocks */ 4272 clock1 = hdmi_mode->clock; 4273 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4274 4275 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4276 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4277 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4278 return vic; 4279 } 4280 return 0; 4281 } 4282 4283 static int 4284 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4285 { 4286 struct drm_display_mode *mode; 4287 int i, num, modes = 0; 4288 4289 /* Don't add CEA modes if the CEA extension block is missing */ 4290 if (!drm_find_cea_extension(edid)) 4291 return 0; 4292 4293 /* 4294 * Go through all probed modes and create a new mode 4295 * with the alternate clock for certain CEA modes. 4296 */ 4297 num = data->modes; 4298 4299 for (i = 0; i < num; i++) { 4300 const struct drm_display_mode *cea_mode = NULL; 4301 struct drm_display_mode *newmode; 4302 u8 vic; 4303 unsigned int clock1, clock2; 4304 4305 mode = &data->mode_buf[i]; 4306 vic = drm_match_cea_mode(mode); 4307 4308 if (drm_valid_cea_vic(vic)) { 4309 cea_mode = &edid_cea_modes[vic]; 4310 clock2 = cea_mode_alternate_clock(cea_mode); 4311 } else { 4312 vic = drm_match_hdmi_mode(mode); 4313 if (drm_valid_hdmi_vic(vic)) { 4314 cea_mode = &edid_4k_modes[vic]; 4315 clock2 = hdmi_mode_alternate_clock(cea_mode); 4316 } 4317 } 4318 4319 if (!cea_mode) 4320 continue; 4321 4322 clock1 = cea_mode->clock; 4323 4324 if (clock1 == clock2) 4325 continue; 4326 4327 if (mode->clock != clock1 && mode->clock != clock2) 4328 continue; 4329 4330 newmode = drm_mode_create(); 4331 *newmode = *cea_mode; 4332 if (!newmode) 4333 continue; 4334 4335 /* Carry over the stereo flags */ 4336 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4337 4338 /* 4339 * The current mode could be either variant. Make 4340 * sure to pick the "other" clock for the new mode. 4341 */ 4342 if (mode->clock != clock1) 4343 newmode->clock = clock1; 4344 else 4345 newmode->clock = clock2; 4346 4347 drm_add_hdmi_modes(data, newmode); 4348 modes++; 4349 drm_mode_destroy(newmode); 4350 } 4351 4352 return modes; 4353 } 4354 4355 static u8 *drm_find_displayid_extension(struct edid *edid) 4356 { 4357 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4358 } 4359 4360 static int validate_displayid(u8 *displayid, int length, int idx) 4361 { 4362 int i; 4363 u8 csum = 0; 4364 struct displayid_hdr *base; 4365 4366 base = (struct displayid_hdr *)&displayid[idx]; 4367 4368 debug("base revision 0x%x, length %d, %d %d\n", 4369 base->rev, base->bytes, base->prod_id, base->ext_count); 4370 4371 if (base->bytes + 5 > length - idx) 4372 return -EINVAL; 4373 for (i = idx; i <= base->bytes + 5; i++) 4374 csum += displayid[i]; 4375 if (csum) { 4376 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4377 return -EINVAL; 4378 } 4379 return 0; 4380 } 4381 4382 static struct 4383 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4384 *timings) 4385 { 4386 struct drm_display_mode *mode; 4387 unsigned pixel_clock = (timings->pixel_clock[0] | 4388 (timings->pixel_clock[1] << 8) | 4389 (timings->pixel_clock[2] << 16)); 4390 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4391 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4392 unsigned hsync = (timings->hsync[0] | 4393 (timings->hsync[1] & 0x7f) << 8) + 1; 4394 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4395 unsigned vactive = (timings->vactive[0] | 4396 timings->vactive[1] << 8) + 1; 4397 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4398 unsigned vsync = (timings->vsync[0] | 4399 (timings->vsync[1] & 0x7f) << 8) + 1; 4400 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4401 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4402 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4403 4404 mode = drm_mode_create(); 4405 if (!mode) 4406 return NULL; 4407 4408 mode->clock = pixel_clock * 10; 4409 mode->hdisplay = hactive; 4410 mode->hsync_start = mode->hdisplay + hsync; 4411 mode->hsync_end = mode->hsync_start + hsync_width; 4412 mode->htotal = mode->hdisplay + hblank; 4413 4414 mode->vdisplay = vactive; 4415 mode->vsync_start = mode->vdisplay + vsync; 4416 mode->vsync_end = mode->vsync_start + vsync_width; 4417 mode->vtotal = mode->vdisplay + vblank; 4418 4419 mode->flags = 0; 4420 mode->flags |= 4421 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4422 mode->flags |= 4423 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4424 mode->type = DRM_MODE_TYPE_DRIVER; 4425 4426 if (timings->flags & 0x80) 4427 mode->type |= DRM_MODE_TYPE_PREFERRED; 4428 mode->vrefresh = drm_get_vrefresh(mode); 4429 4430 return mode; 4431 } 4432 4433 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 4434 struct displayid_block *block) 4435 { 4436 struct displayid_detailed_timing_block *det; 4437 int i; 4438 int num_timings; 4439 struct drm_display_mode *newmode; 4440 int num_modes = 0; 4441 4442 det = (struct displayid_detailed_timing_block *)block; 4443 /* blocks must be multiple of 20 bytes length */ 4444 if (block->num_bytes % 20) 4445 return 0; 4446 4447 num_timings = block->num_bytes / 20; 4448 for (i = 0; i < num_timings; i++) { 4449 struct displayid_detailed_timings_1 *timings = 4450 &det->timings[i]; 4451 4452 newmode = drm_displayid_detailed(timings); 4453 if (!newmode) 4454 continue; 4455 4456 drm_add_hdmi_modes(data, newmode); 4457 num_modes++; 4458 drm_mode_destroy(newmode); 4459 } 4460 return num_modes; 4461 } 4462 4463 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 4464 struct edid *edid) 4465 { 4466 u8 *displayid; 4467 int ret; 4468 int idx = 1; 4469 int length = EDID_SIZE; 4470 struct displayid_block *block; 4471 int num_modes = 0; 4472 4473 displayid = drm_find_displayid_extension(edid); 4474 if (!displayid) 4475 return 0; 4476 4477 ret = validate_displayid(displayid, length, idx); 4478 if (ret) 4479 return 0; 4480 4481 idx += sizeof(struct displayid_hdr); 4482 while (block = (struct displayid_block *)&displayid[idx], 4483 idx + sizeof(struct displayid_block) <= length && 4484 idx + sizeof(struct displayid_block) + block->num_bytes <= 4485 length && block->num_bytes > 0) { 4486 idx += block->num_bytes + sizeof(struct displayid_block); 4487 switch (block->tag) { 4488 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4489 num_modes += 4490 add_displayid_detailed_1_modes(data, block); 4491 break; 4492 } 4493 } 4494 return num_modes; 4495 } 4496 4497 static bool 4498 mode_in_hsync_range(const struct drm_display_mode *mode, 4499 struct edid *edid, u8 *t) 4500 { 4501 int hsync, hmin, hmax; 4502 4503 hmin = t[7]; 4504 if (edid->revision >= 4) 4505 hmin += ((t[4] & 0x04) ? 255 : 0); 4506 hmax = t[8]; 4507 if (edid->revision >= 4) 4508 hmax += ((t[4] & 0x08) ? 255 : 0); 4509 hsync = drm_mode_hsync(mode); 4510 4511 return (hsync <= hmax && hsync >= hmin); 4512 } 4513 4514 static bool 4515 mode_in_vsync_range(const struct drm_display_mode *mode, 4516 struct edid *edid, u8 *t) 4517 { 4518 int vsync, vmin, vmax; 4519 4520 vmin = t[5]; 4521 if (edid->revision >= 4) 4522 vmin += ((t[4] & 0x01) ? 255 : 0); 4523 vmax = t[6]; 4524 if (edid->revision >= 4) 4525 vmax += ((t[4] & 0x02) ? 255 : 0); 4526 vsync = drm_get_vrefresh(mode); 4527 4528 return (vsync <= vmax && vsync >= vmin); 4529 } 4530 4531 static u32 4532 range_pixel_clock(struct edid *edid, u8 *t) 4533 { 4534 /* unspecified */ 4535 if (t[9] == 0 || t[9] == 255) 4536 return 0; 4537 4538 /* 1.4 with CVT support gives us real precision, yay */ 4539 if (edid->revision >= 4 && t[10] == 0x04) 4540 return (t[9] * 10000) - ((t[12] >> 2) * 250); 4541 4542 /* 1.3 is pathetic, so fuzz up a bit */ 4543 return t[9] * 10000 + 5001; 4544 } 4545 4546 static bool 4547 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 4548 struct detailed_timing *timing) 4549 { 4550 u32 max_clock; 4551 u8 *t = (u8 *)timing; 4552 4553 if (!mode_in_hsync_range(mode, edid, t)) 4554 return false; 4555 4556 if (!mode_in_vsync_range(mode, edid, t)) 4557 return false; 4558 4559 max_clock = range_pixel_clock(edid, t); 4560 if (max_clock) 4561 if (mode->clock > max_clock) 4562 return false; 4563 4564 /* 1.4 max horizontal check */ 4565 if (edid->revision >= 4 && t[10] == 0x04) 4566 if (t[13] && mode->hdisplay > 8 * 4567 (t[13] + (256 * (t[12] & 0x3)))) 4568 return false; 4569 4570 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 4571 return false; 4572 4573 return true; 4574 } 4575 4576 static bool valid_inferred_mode(struct hdmi_edid_data *data, 4577 const struct drm_display_mode *mode) 4578 { 4579 const struct drm_display_mode *m; 4580 bool ok = false; 4581 int i; 4582 4583 for (i = 0; i < data->modes; i++) { 4584 m = &data->mode_buf[i]; 4585 if (mode->hdisplay == m->hdisplay && 4586 mode->vdisplay == m->vdisplay && 4587 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 4588 return false; /* duplicated */ 4589 if (mode->hdisplay <= m->hdisplay && 4590 mode->vdisplay <= m->vdisplay) 4591 ok = true; 4592 } 4593 return ok; 4594 } 4595 4596 static int 4597 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4598 struct detailed_timing *timing) 4599 { 4600 int i, modes = 0; 4601 4602 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4603 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 4604 valid_inferred_mode(data, drm_dmt_modes + i)) { 4605 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 4606 modes++; 4607 } 4608 } 4609 4610 return modes; 4611 } 4612 4613 /* fix up 1366x768 mode from 1368x768; 4614 * GFT/CVT can't express 1366 width which isn't dividable by 8 4615 */ 4616 static void fixup_mode_1366x768(struct drm_display_mode *mode) 4617 { 4618 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 4619 mode->hdisplay = 1366; 4620 mode->hsync_start--; 4621 mode->hsync_end--; 4622 } 4623 } 4624 4625 static int 4626 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4627 struct detailed_timing *timing) 4628 { 4629 int i, modes = 0; 4630 struct drm_display_mode *newmode; 4631 4632 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4633 const struct minimode *m = &extra_modes[i]; 4634 4635 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 4636 if (!newmode) 4637 return modes; 4638 4639 fixup_mode_1366x768(newmode); 4640 if (!mode_in_range(newmode, edid, timing) || 4641 !valid_inferred_mode(data, newmode)) { 4642 drm_mode_destroy(newmode); 4643 continue; 4644 } 4645 4646 drm_add_hdmi_modes(data, newmode); 4647 modes++; 4648 drm_mode_destroy(newmode); 4649 } 4650 4651 return modes; 4652 } 4653 4654 static int 4655 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4656 struct detailed_timing *timing) 4657 { 4658 int i, modes = 0; 4659 struct drm_display_mode *newmode; 4660 bool rb = drm_monitor_supports_rb(edid); 4661 4662 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4663 const struct minimode *m = &extra_modes[i]; 4664 4665 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 4666 if (!newmode) 4667 return modes; 4668 4669 fixup_mode_1366x768(newmode); 4670 if (!mode_in_range(newmode, edid, timing) || 4671 !valid_inferred_mode(data, newmode)) { 4672 drm_mode_destroy(newmode); 4673 continue; 4674 } 4675 4676 drm_add_hdmi_modes(data, newmode); 4677 modes++; 4678 drm_mode_destroy(newmode); 4679 } 4680 4681 return modes; 4682 } 4683 4684 static void 4685 do_inferred_modes(struct detailed_timing *timing, void *c) 4686 { 4687 struct detailed_mode_closure *closure = c; 4688 struct detailed_non_pixel *data = &timing->data.other_data; 4689 struct detailed_data_monitor_range *range = &data->data.range; 4690 4691 if (data->type != EDID_DETAIL_MONITOR_RANGE) 4692 return; 4693 4694 closure->modes += drm_dmt_modes_for_range(closure->data, 4695 closure->edid, 4696 timing); 4697 4698 if (!version_greater(closure->edid, 1, 1)) 4699 return; /* GTF not defined yet */ 4700 4701 switch (range->flags) { 4702 case 0x02: /* secondary gtf, XXX could do more */ 4703 case 0x00: /* default gtf */ 4704 closure->modes += drm_gtf_modes_for_range(closure->data, 4705 closure->edid, 4706 timing); 4707 break; 4708 case 0x04: /* cvt, only in 1.4+ */ 4709 if (!version_greater(closure->edid, 1, 3)) 4710 break; 4711 4712 closure->modes += drm_cvt_modes_for_range(closure->data, 4713 closure->edid, 4714 timing); 4715 break; 4716 case 0x01: /* just the ranges, no formula */ 4717 default: 4718 break; 4719 } 4720 } 4721 4722 static int 4723 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 4724 { 4725 struct detailed_mode_closure closure = { 4726 .data = data, 4727 .edid = edid, 4728 }; 4729 4730 if (version_greater(edid, 1, 0)) 4731 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 4732 &closure); 4733 4734 return closure.modes; 4735 } 4736 4737 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 4738 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 4739 4740 /** 4741 * edid_fixup_preferred - set preferred modes based on quirk list 4742 * @data: the structure that save parsed hdmi edid data 4743 * @quirks: quirks list 4744 * 4745 * Walk the mode list, clearing the preferred status 4746 * on existing modes and setting it anew for the right mode ala @quirks. 4747 */ 4748 static void edid_fixup_preferred(struct hdmi_edid_data *data, 4749 u32 quirks) 4750 { 4751 struct drm_display_mode *cur_mode, *preferred_mode; 4752 int i, target_refresh = 0; 4753 int num = data->modes; 4754 int cur_vrefresh, preferred_vrefresh; 4755 4756 if (!num) 4757 return; 4758 4759 preferred_mode = data->preferred_mode; 4760 4761 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 4762 target_refresh = 60; 4763 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 4764 target_refresh = 75; 4765 4766 for (i = 0; i < num; i++) { 4767 cur_mode = &data->mode_buf[i]; 4768 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 4769 4770 if (cur_mode == preferred_mode) 4771 continue; 4772 4773 /* Largest mode is preferred */ 4774 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 4775 preferred_mode = cur_mode; 4776 4777 cur_vrefresh = cur_mode->vrefresh ? 4778 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 4779 preferred_vrefresh = preferred_mode->vrefresh ? 4780 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 4781 /* At a given size, try to get closest to target refresh */ 4782 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 4783 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 4784 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 4785 preferred_mode = cur_mode; 4786 } 4787 } 4788 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 4789 data->preferred_mode = preferred_mode; 4790 } 4791 4792 static const u8 edid_header[] = { 4793 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 4794 }; 4795 4796 /** 4797 * drm_edid_header_is_valid - sanity check the header of the base EDID block 4798 * @raw_edid: pointer to raw base EDID block 4799 * 4800 * Sanity check the header of the base EDID block. 4801 * 4802 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 4803 */ 4804 static int drm_edid_header_is_valid(const u8 *raw_edid) 4805 { 4806 int i, score = 0; 4807 4808 for (i = 0; i < sizeof(edid_header); i++) 4809 if (raw_edid[i] == edid_header[i]) 4810 score++; 4811 4812 return score; 4813 } 4814 4815 static int drm_edid_block_checksum(const u8 *raw_edid) 4816 { 4817 int i; 4818 u8 csum = 0; 4819 4820 for (i = 0; i < EDID_SIZE; i++) 4821 csum += raw_edid[i]; 4822 4823 return csum; 4824 } 4825 4826 static bool drm_edid_is_zero(const u8 *in_edid, int length) 4827 { 4828 if (memchr_inv(in_edid, 0, length)) 4829 return false; 4830 4831 return true; 4832 } 4833 4834 /** 4835 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 4836 * @raw_edid: pointer to raw EDID block 4837 * @block: type of block to validate (0 for base, extension otherwise) 4838 * @print_bad_edid: if true, dump bad EDID blocks to the console 4839 * @edid_corrupt: if true, the header or checksum is invalid 4840 * 4841 * Validate a base or extension EDID block and optionally dump bad blocks to 4842 * the console. 4843 * 4844 * Return: True if the block is valid, false otherwise. 4845 */ 4846 static 4847 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 4848 bool *edid_corrupt) 4849 { 4850 u8 csum; 4851 int edid_fixup = 6; 4852 struct edid *edid = (struct edid *)raw_edid; 4853 4854 if ((!raw_edid)) 4855 return false; 4856 4857 if (block == 0) { 4858 int score = drm_edid_header_is_valid(raw_edid); 4859 4860 if (score == 8) { 4861 if (edid_corrupt) 4862 *edid_corrupt = false; 4863 } else if (score >= edid_fixup) { 4864 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 4865 * The corrupt flag needs to be set here otherwise, the 4866 * fix-up code here will correct the problem, the 4867 * checksum is correct and the test fails 4868 */ 4869 if (edid_corrupt) 4870 *edid_corrupt = true; 4871 debug("Fixing header, your hardware may be failing\n"); 4872 memcpy(raw_edid, edid_header, sizeof(edid_header)); 4873 } else { 4874 if (edid_corrupt) 4875 *edid_corrupt = true; 4876 goto bad; 4877 } 4878 } 4879 4880 csum = drm_edid_block_checksum(raw_edid); 4881 if (csum) { 4882 if (print_bad_edid) { 4883 debug("EDID checksum is invalid, remainder is %d\n", 4884 csum); 4885 } 4886 4887 if (edid_corrupt) 4888 *edid_corrupt = true; 4889 4890 /* allow CEA to slide through, switches mangle this */ 4891 if (raw_edid[0] != 0x02) 4892 goto bad; 4893 } 4894 4895 /* per-block-type checks */ 4896 switch (raw_edid[0]) { 4897 case 0: /* base */ 4898 if (edid->version != 1) { 4899 debug("EDID has major version %d, instead of 1\n", 4900 edid->version); 4901 goto bad; 4902 } 4903 4904 if (edid->revision > 4) 4905 debug("minor > 4, assuming backward compatibility\n"); 4906 break; 4907 4908 default: 4909 break; 4910 } 4911 4912 return true; 4913 4914 bad: 4915 if (print_bad_edid) { 4916 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 4917 debug("EDID block is all zeroes\n"); 4918 } else { 4919 debug("Raw EDID:\n"); 4920 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 4921 raw_edid, EDID_SIZE, false); 4922 } 4923 } 4924 return false; 4925 } 4926 4927 /** 4928 * drm_edid_is_valid - sanity check EDID data 4929 * @edid: EDID data 4930 * 4931 * Sanity-check an entire EDID record (including extensions) 4932 * 4933 * Return: True if the EDID data is valid, false otherwise. 4934 */ 4935 static bool drm_edid_is_valid(struct edid *edid) 4936 { 4937 int i; 4938 u8 *raw = (u8 *)edid; 4939 4940 if (!edid) 4941 return false; 4942 4943 for (i = 0; i <= edid->extensions; i++) 4944 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 4945 return false; 4946 4947 return true; 4948 } 4949 4950 /** 4951 * drm_add_edid_modes - add modes from EDID data, if available 4952 * @data: data we're probing 4953 * @edid: EDID data 4954 * 4955 * Add the specified modes to the data's mode list. 4956 * 4957 * Return: The number of modes added or 0 if we couldn't find any. 4958 */ 4959 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 4960 { 4961 int num_modes = 0; 4962 u32 quirks; 4963 struct edid *edid = (struct edid *)raw_edid; 4964 4965 if (!edid) { 4966 debug("no edid\n"); 4967 return 0; 4968 } 4969 4970 if (!drm_edid_is_valid(edid)) { 4971 debug("EDID invalid\n"); 4972 return 0; 4973 } 4974 4975 if (!data->mode_buf) { 4976 debug("mode buff is null\n"); 4977 return 0; 4978 } 4979 4980 quirks = edid_get_quirks(edid); 4981 /* 4982 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4983 * To avoid multiple parsing of same block, lets parse that map 4984 * from sink info, before parsing CEA modes. 4985 */ 4986 drm_add_display_info(data, edid); 4987 4988 /* 4989 * EDID spec says modes should be preferred in this order: 4990 * - preferred detailed mode 4991 * - other detailed modes from base block 4992 * - detailed modes from extension blocks 4993 * - CVT 3-byte code modes 4994 * - standard timing codes 4995 * - established timing codes 4996 * - modes inferred from GTF or CVT range information 4997 * 4998 * We get this pretty much right. 4999 * 5000 * XXX order for additional mode types in extension blocks? 5001 */ 5002 num_modes += add_detailed_modes(data, edid, quirks); 5003 num_modes += add_cvt_modes(data, edid); 5004 num_modes += add_standard_modes(data, edid); 5005 num_modes += add_established_modes(data, edid); 5006 num_modes += add_cea_modes(data, edid); 5007 num_modes += add_alternate_cea_modes(data, edid); 5008 num_modes += add_displayid_detailed_modes(data, edid); 5009 5010 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5011 num_modes += add_inferred_modes(data, edid); 5012 5013 if (num_modes > 0) 5014 data->preferred_mode = &data->mode_buf[0]; 5015 5016 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5017 edid_fixup_preferred(data, quirks); 5018 5019 if (quirks & EDID_QUIRK_FORCE_6BPC) 5020 data->display_info.bpc = 6; 5021 5022 if (quirks & EDID_QUIRK_FORCE_8BPC) 5023 data->display_info.bpc = 8; 5024 5025 if (quirks & EDID_QUIRK_FORCE_10BPC) 5026 data->display_info.bpc = 10; 5027 5028 if (quirks & EDID_QUIRK_FORCE_12BPC) 5029 data->display_info.bpc = 12; 5030 5031 return num_modes; 5032 } 5033 5034 static int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5035 { 5036 memset(frame, 0, sizeof(*frame)); 5037 5038 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5039 frame->version = 2; 5040 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5041 5042 return 0; 5043 } 5044 5045 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5046 { 5047 u8 vic; 5048 5049 if (!to_match->clock) { 5050 printf("can't find to match\n"); 5051 return 0; 5052 } 5053 5054 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 5055 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 5056 unsigned int clock1, clock2; 5057 5058 /* Check both 60Hz and 59.94Hz */ 5059 clock1 = cea_mode->clock; 5060 clock2 = cea_mode_alternate_clock(cea_mode); 5061 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5062 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5063 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5064 return vic; 5065 } 5066 5067 return 0; 5068 } 5069 5070 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5071 { 5072 return edid_cea_modes[video_code].picture_aspect_ratio; 5073 } 5074 5075 int 5076 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5077 struct drm_display_mode *mode, 5078 bool is_hdmi2_sink) 5079 { 5080 int err; 5081 5082 if (!frame || !mode) 5083 return -EINVAL; 5084 5085 err = hdmi_avi_infoframe_init(frame); 5086 if (err < 0) 5087 return err; 5088 5089 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5090 frame->pixel_repeat = 1; 5091 5092 frame->video_code = drm_match_cea_mode(mode); 5093 5094 /* 5095 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5096 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5097 * have to make sure we dont break HDMI 1.4 sinks. 5098 */ 5099 if (!is_hdmi2_sink && frame->video_code > 64) 5100 frame->video_code = 0; 5101 5102 /* 5103 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5104 * we should send its VIC in vendor infoframes, else send the 5105 * VIC in AVI infoframes. Lets check if this mode is present in 5106 * HDMI 1.4b 4K modes 5107 */ 5108 if (frame->video_code) { 5109 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5110 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5111 5112 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5113 frame->video_code = 0; 5114 } 5115 5116 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5117 5118 /* 5119 * Populate picture aspect ratio from either 5120 * user input (if specified) or from the CEA mode list. 5121 */ 5122 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5123 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5124 frame->picture_aspect = mode->picture_aspect_ratio; 5125 else if (frame->video_code > 0) 5126 frame->picture_aspect = drm_get_cea_aspect_ratio( 5127 frame->video_code); 5128 5129 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5130 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5131 5132 return 0; 5133 } 5134 5135 /** 5136 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5137 * @frame: HDMI vendor infoframe 5138 * 5139 * Returns 0 on success or a negative error code on failure. 5140 */ 5141 static int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5142 { 5143 memset(frame, 0, sizeof(*frame)); 5144 5145 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5146 frame->version = 1; 5147 5148 frame->oui = HDMI_IEEE_OUI; 5149 5150 /* 5151 * 0 is a valid value for s3d_struct, so we use a special "not set" 5152 * value 5153 */ 5154 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5155 5156 return 0; 5157 } 5158 5159 static enum hdmi_3d_structure 5160 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5161 { 5162 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5163 5164 switch (layout) { 5165 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5166 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5167 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5168 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5169 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5170 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5171 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5172 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5173 case DRM_MODE_FLAG_3D_L_DEPTH: 5174 return HDMI_3D_STRUCTURE_L_DEPTH; 5175 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5176 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5177 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5178 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5179 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5180 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5181 default: 5182 return HDMI_3D_STRUCTURE_INVALID; 5183 } 5184 } 5185 5186 int 5187 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5188 struct drm_display_mode *mode) 5189 { 5190 int err; 5191 u32 s3d_flags; 5192 u8 vic; 5193 5194 if (!frame || !mode) 5195 return -EINVAL; 5196 5197 vic = drm_match_hdmi_mode(mode); 5198 5199 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5200 5201 if (!vic && !s3d_flags) 5202 return -EINVAL; 5203 5204 if (vic && s3d_flags) 5205 return -EINVAL; 5206 5207 err = hdmi_vendor_infoframe_init(frame); 5208 if (err < 0) 5209 return err; 5210 5211 if (vic) 5212 frame->vic = vic; 5213 else 5214 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5215 5216 return 0; 5217 } 5218 5219 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5220 { 5221 u8 csum = 0; 5222 size_t i; 5223 5224 /* compute checksum */ 5225 for (i = 0; i < size; i++) 5226 csum += ptr[i]; 5227 5228 return 256 - csum; 5229 } 5230 5231 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5232 { 5233 u8 *ptr = buffer; 5234 5235 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5236 } 5237 5238 /** 5239 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 5240 * @frame: HDMI infoframe 5241 * @buffer: destination buffer 5242 * @size: size of buffer 5243 * 5244 * Packs the information contained in the @frame structure into a binary 5245 * representation that can be written into the corresponding controller 5246 * registers. Also computes the checksum as required by section 5.3.5 of 5247 * the HDMI 1.4 specification. 5248 * 5249 * Returns the number of bytes packed into the binary buffer or a negative 5250 * error code on failure. 5251 */ 5252 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 5253 void *buffer, size_t size) 5254 { 5255 u8 *ptr = buffer; 5256 size_t length; 5257 5258 /* empty info frame */ 5259 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 5260 return -EINVAL; 5261 5262 /* only one of those can be supplied */ 5263 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 5264 return -EINVAL; 5265 5266 /* for side by side (half) we also need to provide 3D_Ext_Data */ 5267 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5268 frame->length = 6; 5269 else 5270 frame->length = 5; 5271 5272 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5273 5274 if (size < length) 5275 return -ENOSPC; 5276 5277 memset(buffer, 0, size); 5278 5279 ptr[0] = frame->type; 5280 ptr[1] = frame->version; 5281 ptr[2] = frame->length; 5282 ptr[3] = 0; /* checksum */ 5283 5284 /* HDMI OUI */ 5285 ptr[4] = 0x03; 5286 ptr[5] = 0x0c; 5287 ptr[6] = 0x00; 5288 5289 if (frame->vic) { 5290 ptr[7] = 0x1 << 5; /* video format */ 5291 ptr[8] = frame->vic; 5292 } else { 5293 ptr[7] = 0x2 << 5; /* video format */ 5294 ptr[8] = (frame->s3d_struct & 0xf) << 4; 5295 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5296 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 5297 } 5298 5299 hdmi_infoframe_set_checksum(buffer, length); 5300 5301 return length; 5302 } 5303 5304 /** 5305 * drm_do_probe_ddc_edid() - get EDID information via I2C 5306 * @adap: ddc adapter 5307 * @buf: EDID data buffer to be filled 5308 * @block: 128 byte EDID block to start fetching from 5309 * @len: EDID data buffer length to fetch 5310 * 5311 * Try to fetch EDID information by calling I2C driver functions. 5312 * 5313 * Return: 0 on success or -1 on failure. 5314 */ 5315 static int 5316 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 5317 size_t len) 5318 { 5319 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 5320 unsigned char segment = block >> 1; 5321 unsigned char xfers = segment ? 3 : 2; 5322 int ret, retries = 5; 5323 5324 do { 5325 struct i2c_msg msgs[] = { 5326 { 5327 .addr = DDC_SEGMENT_ADDR, 5328 .flags = 0, 5329 .len = 1, 5330 .buf = &segment, 5331 }, { 5332 .addr = DDC_ADDR, 5333 .flags = 0, 5334 .len = 1, 5335 .buf = &start, 5336 }, { 5337 .addr = DDC_ADDR, 5338 .flags = I2C_M_RD, 5339 .len = len, 5340 .buf = buf, 5341 } 5342 }; 5343 5344 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 5345 5346 } while (ret != xfers && --retries); 5347 5348 /* All msg transfer successfully. */ 5349 return ret == xfers ? 0 : -1; 5350 } 5351 5352 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid) 5353 { 5354 int i, j, block_num, block = 0; 5355 bool edid_corrupt; 5356 #ifdef DEBUG 5357 u8 *buff; 5358 #endif 5359 5360 /* base block fetch */ 5361 for (i = 0; i < 4; i++) { 5362 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 5363 goto err; 5364 if (drm_edid_block_valid(edid, 0, true, 5365 &edid_corrupt)) 5366 break; 5367 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 5368 printf("edid base block is 0, get edid failed\n"); 5369 goto err; 5370 } 5371 } 5372 5373 if (i == 4) 5374 goto err; 5375 5376 block++; 5377 /* get the number of extensions */ 5378 block_num = edid[0x7e]; 5379 5380 for (j = 1; j <= block_num; j++) { 5381 for (i = 0; i < 4; i++) { 5382 if (drm_do_probe_ddc_edid(adap, &edid[0x80 * j], j, 5383 HDMI_EDID_BLOCK_SIZE)) 5384 goto err; 5385 if (drm_edid_block_valid(&edid[0x80 * j], j, 5386 true, NULL)) 5387 break; 5388 } 5389 5390 if (i == 4) 5391 goto err; 5392 block++; 5393 } 5394 5395 #ifdef DEBUG 5396 printf("RAW EDID:\n"); 5397 for (i = 0; i < block_num + 1; i++) { 5398 buff = &edid[0x80 * i]; 5399 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 5400 if (j % 16 == 0) 5401 printf("\n"); 5402 printf("0x%02x, ", buff[j]); 5403 } 5404 printf("\n"); 5405 } 5406 #endif 5407 5408 return 0; 5409 5410 err: 5411 printf("can't get edid block:%d\n", block); 5412 /* clear all read edid block, include invalid block */ 5413 memset(edid, 0, HDMI_EDID_BLOCK_SIZE * (block + 1)); 5414 return -EFAULT; 5415 } 5416 5417 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 5418 void *buffer, size_t size) 5419 { 5420 struct i2c_msg msgs[2] = { 5421 { 5422 .addr = addr, 5423 .flags = 0, 5424 .len = 1, 5425 .buf = &offset, 5426 }, { 5427 .addr = addr, 5428 .flags = I2C_M_RD, 5429 .len = size, 5430 .buf = buffer, 5431 } 5432 }; 5433 5434 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 5435 } 5436 5437 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 5438 const void *buffer, size_t size) 5439 { 5440 struct i2c_msg msg = { 5441 .addr = addr, 5442 .flags = 0, 5443 .len = 1 + size, 5444 .buf = NULL, 5445 }; 5446 void *data; 5447 int err; 5448 5449 data = malloc(1 + size); 5450 if (!data) 5451 return -ENOMEM; 5452 5453 msg.buf = data; 5454 5455 memcpy(data, &offset, sizeof(offset)); 5456 memcpy(data + 1, buffer, size); 5457 5458 err = adap->ddc_xfer(adap, &msg, 1); 5459 5460 free(data); 5461 5462 return err; 5463 } 5464 5465 /** 5466 * drm_scdc_readb - read a single byte from SCDC 5467 * @adap: ddc adapter 5468 * @offset: offset of register to read 5469 * @value: return location for the register value 5470 * 5471 * Reads a single byte from SCDC. This is a convenience wrapper around the 5472 * drm_scdc_read() function. 5473 * 5474 * Returns: 5475 * 0 on success or a negative error code on failure. 5476 */ 5477 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 5478 u8 *value) 5479 { 5480 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 5481 sizeof(*value)); 5482 } 5483 5484 /** 5485 * drm_scdc_writeb - write a single byte to SCDC 5486 * @adap: ddc adapter 5487 * @offset: offset of register to read 5488 * @value: return location for the register value 5489 * 5490 * Writes a single byte to SCDC. This is a convenience wrapper around the 5491 * drm_scdc_write() function. 5492 * 5493 * Returns: 5494 * 0 on success or a negative error code on failure. 5495 */ 5496 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 5497 u8 value) 5498 { 5499 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 5500 sizeof(value)); 5501 } 5502 5503