1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <hexdump.h> 22 #include <malloc.h> 23 #include <linux/compat.h> 24 #include <linux/ctype.h> 25 #include <linux/fb.h> 26 #include <linux/hdmi.h> 27 #include <linux/string.h> 28 29 #define EDID_EST_TIMINGS 16 30 #define EDID_STD_TIMINGS 8 31 #define EDID_DETAILED_TIMINGS 4 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 bool preferred; 78 u32 quirks; 79 int modes; 80 }; 81 82 #define LEVEL_DMT 0 83 #define LEVEL_GTF 1 84 #define LEVEL_GTF2 2 85 #define LEVEL_CVT 3 86 87 static struct edid_quirk { 88 char vendor[4]; 89 int product_id; 90 u32 quirks; 91 } edid_quirk_list[] = { 92 /* Acer AL1706 */ 93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Acer F51 */ 95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Unknown Acer */ 97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 98 99 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 100 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 116 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 146 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 147 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Probably taken from CEA-861 spec. 152 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 153 * 154 * Index using the VIC. 155 */ 156 /* 157 * From CEA/CTA-861 spec. 158 * Do not access directly, instead always use cea_mode_for_vic(). 159 */ 160 static const struct drm_display_mode edid_cea_modes_1[] = { 161 /* 1 - 640x480@60Hz */ 162 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 163 752, 800, 480, 490, 492, 525, 0, 164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 165 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 166 /* 2 - 720x480@60Hz */ 167 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 168 798, 858, 480, 489, 495, 525, 0, 169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 170 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 171 /* 3 - 720x480@60Hz */ 172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 173 798, 858, 480, 489, 495, 525, 0, 174 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 175 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 176 /* 4 - 1280x720@60Hz */ 177 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 178 1430, 1650, 720, 725, 730, 750, 0, 179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 180 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 181 /* 5 - 1920x1080i@60Hz */ 182 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 183 2052, 2200, 1080, 1084, 1094, 1125, 0, 184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 185 DRM_MODE_FLAG_INTERLACE), 186 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 187 /* 6 - 720(1440)x480i@60Hz */ 188 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 189 801, 858, 480, 488, 494, 525, 0, 190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 191 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 193 /* 7 - 720(1440)x480i@60Hz */ 194 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 195 801, 858, 480, 488, 494, 525, 0, 196 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 197 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 198 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 199 /* 8 - 720(1440)x240@60Hz */ 200 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 201 801, 858, 240, 244, 247, 262, 0, 202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 203 DRM_MODE_FLAG_DBLCLK), 204 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 205 /* 9 - 720(1440)x240@60Hz */ 206 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 207 801, 858, 240, 244, 247, 262, 0, 208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 209 DRM_MODE_FLAG_DBLCLK), 210 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 211 /* 10 - 2880x480i@60Hz */ 212 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 213 3204, 3432, 480, 488, 494, 525, 0, 214 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 215 DRM_MODE_FLAG_INTERLACE), 216 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 217 /* 11 - 2880x480i@60Hz */ 218 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 219 3204, 3432, 480, 488, 494, 525, 0, 220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 221 DRM_MODE_FLAG_INTERLACE), 222 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 223 /* 12 - 2880x240@60Hz */ 224 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 225 3204, 3432, 240, 244, 247, 262, 0, 226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 228 /* 13 - 2880x240@60Hz */ 229 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 230 3204, 3432, 240, 244, 247, 262, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 232 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 233 /* 14 - 1440x480@60Hz */ 234 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 235 1596, 1716, 480, 489, 495, 525, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 237 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 238 /* 15 - 1440x480@60Hz */ 239 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 240 1596, 1716, 480, 489, 495, 525, 0, 241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 242 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 243 /* 16 - 1920x1080@60Hz */ 244 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 245 2052, 2200, 1080, 1084, 1089, 1125, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 247 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 248 /* 17 - 720x576@50Hz */ 249 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 250 796, 864, 576, 581, 586, 625, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 252 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 253 /* 18 - 720x576@50Hz */ 254 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 255 796, 864, 576, 581, 586, 625, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 257 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 258 /* 19 - 1280x720@50Hz */ 259 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 260 1760, 1980, 720, 725, 730, 750, 0, 261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 262 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 263 /* 20 - 1920x1080i@50Hz */ 264 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 265 2492, 2640, 1080, 1084, 1094, 1125, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 267 DRM_MODE_FLAG_INTERLACE), 268 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 269 /* 21 - 720(1440)x576i@50Hz */ 270 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 271 795, 864, 576, 580, 586, 625, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 273 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 274 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 275 /* 22 - 720(1440)x576i@50Hz */ 276 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 277 795, 864, 576, 580, 586, 625, 0, 278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 279 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 280 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 281 /* 23 - 720(1440)x288@50Hz */ 282 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 283 795, 864, 288, 290, 293, 312, 0, 284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 285 DRM_MODE_FLAG_DBLCLK), 286 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 287 /* 24 - 720(1440)x288@50Hz */ 288 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 289 795, 864, 288, 290, 293, 312, 0, 290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 291 DRM_MODE_FLAG_DBLCLK), 292 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 293 /* 25 - 2880x576i@50Hz */ 294 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 295 3180, 3456, 576, 580, 586, 625, 0, 296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 297 DRM_MODE_FLAG_INTERLACE), 298 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 299 /* 26 - 2880x576i@50Hz */ 300 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 301 3180, 3456, 576, 580, 586, 625, 0, 302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 303 DRM_MODE_FLAG_INTERLACE), 304 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 305 /* 27 - 2880x288@50Hz */ 306 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 307 3180, 3456, 288, 290, 293, 312, 0, 308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 309 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 310 /* 28 - 2880x288@50Hz */ 311 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 312 3180, 3456, 288, 290, 293, 312, 0, 313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 314 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 315 /* 29 - 1440x576@50Hz */ 316 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 317 1592, 1728, 576, 581, 586, 625, 0, 318 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 319 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 320 /* 30 - 1440x576@50Hz */ 321 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 322 1592, 1728, 576, 581, 586, 625, 0, 323 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 324 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 325 /* 31 - 1920x1080@50Hz */ 326 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 327 2492, 2640, 1080, 1084, 1089, 1125, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 329 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 330 /* 32 - 1920x1080@24Hz */ 331 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 332 2602, 2750, 1080, 1084, 1089, 1125, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 334 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 335 /* 33 - 1920x1080@25Hz */ 336 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 337 2492, 2640, 1080, 1084, 1089, 1125, 0, 338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 339 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 340 /* 34 - 1920x1080@30Hz */ 341 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 342 2052, 2200, 1080, 1084, 1089, 1125, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 344 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 345 /* 35 - 2880x480@60Hz */ 346 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 347 3192, 3432, 480, 489, 495, 525, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 349 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 350 /* 36 - 2880x480@60Hz */ 351 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 352 3192, 3432, 480, 489, 495, 525, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 354 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 355 /* 37 - 2880x576@50Hz */ 356 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 357 3184, 3456, 576, 581, 586, 625, 0, 358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 359 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 360 /* 38 - 2880x576@50Hz */ 361 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 362 3184, 3456, 576, 581, 586, 625, 0, 363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 364 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 365 /* 39 - 1920x1080i@50Hz */ 366 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 367 2120, 2304, 1080, 1126, 1136, 1250, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 369 DRM_MODE_FLAG_INTERLACE), 370 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 371 /* 40 - 1920x1080i@100Hz */ 372 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 373 2492, 2640, 1080, 1084, 1094, 1125, 0, 374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 375 DRM_MODE_FLAG_INTERLACE), 376 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 377 /* 41 - 1280x720@100Hz */ 378 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 379 1760, 1980, 720, 725, 730, 750, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 381 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 382 /* 42 - 720x576@100Hz */ 383 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 384 796, 864, 576, 581, 586, 625, 0, 385 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 386 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 387 /* 43 - 720x576@100Hz */ 388 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 389 796, 864, 576, 581, 586, 625, 0, 390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 391 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 392 /* 44 - 720(1440)x576i@100Hz */ 393 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 394 795, 864, 576, 580, 586, 625, 0, 395 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 396 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 397 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 398 /* 45 - 720(1440)x576i@100Hz */ 399 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 400 795, 864, 576, 580, 586, 625, 0, 401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 402 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 403 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 404 /* 46 - 1920x1080i@120Hz */ 405 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 406 2052, 2200, 1080, 1084, 1094, 1125, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 408 DRM_MODE_FLAG_INTERLACE), 409 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 410 /* 47 - 1280x720@120Hz */ 411 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 412 1430, 1650, 720, 725, 730, 750, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 414 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 415 /* 48 - 720x480@120Hz */ 416 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 417 798, 858, 480, 489, 495, 525, 0, 418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 419 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 420 /* 49 - 720x480@120Hz */ 421 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 422 798, 858, 480, 489, 495, 525, 0, 423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 424 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 425 /* 50 - 720(1440)x480i@120Hz */ 426 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 427 801, 858, 480, 488, 494, 525, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 429 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 430 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 431 /* 51 - 720(1440)x480i@120Hz */ 432 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 433 801, 858, 480, 488, 494, 525, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 435 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 436 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 437 /* 52 - 720x576@200Hz */ 438 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 439 796, 864, 576, 581, 586, 625, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 441 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 442 /* 53 - 720x576@200Hz */ 443 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 444 796, 864, 576, 581, 586, 625, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 446 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 447 /* 54 - 720(1440)x576i@200Hz */ 448 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 449 795, 864, 576, 580, 586, 625, 0, 450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 451 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 452 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 453 /* 55 - 720(1440)x576i@200Hz */ 454 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 455 795, 864, 576, 580, 586, 625, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 457 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 458 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 459 /* 56 - 720x480@240Hz */ 460 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 461 798, 858, 480, 489, 495, 525, 0, 462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 463 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 464 /* 57 - 720x480@240Hz */ 465 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 466 798, 858, 480, 489, 495, 525, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 468 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 469 /* 58 - 720(1440)x480i@240 */ 470 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 471 801, 858, 480, 488, 494, 525, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 473 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 474 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 475 /* 59 - 720(1440)x480i@240 */ 476 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 477 801, 858, 480, 488, 494, 525, 0, 478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 479 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 480 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 481 /* 60 - 1280x720@24Hz */ 482 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 483 3080, 3300, 720, 725, 730, 750, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 485 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 486 /* 61 - 1280x720@25Hz */ 487 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 488 3740, 3960, 720, 725, 730, 750, 0, 489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 490 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 491 /* 62 - 1280x720@30Hz */ 492 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 493 3080, 3300, 720, 725, 730, 750, 0, 494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 495 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 496 /* 63 - 1920x1080@120Hz */ 497 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 498 2052, 2200, 1080, 1084, 1089, 1125, 0, 499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 500 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 501 /* 64 - 1920x1080@100Hz */ 502 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 503 2492, 2640, 1080, 1084, 1089, 1125, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 505 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 506 /* 65 - 1280x720@24Hz */ 507 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 508 3080, 3300, 720, 725, 730, 750, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 510 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 511 /* 66 - 1280x720@25Hz */ 512 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 513 3740, 3960, 720, 725, 730, 750, 0, 514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 515 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 516 /* 67 - 1280x720@30Hz */ 517 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 518 3080, 3300, 720, 725, 730, 750, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 520 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 521 /* 68 - 1280x720@50Hz */ 522 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 523 1760, 1980, 720, 725, 730, 750, 0, 524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 525 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 526 /* 69 - 1280x720@60Hz */ 527 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 528 1430, 1650, 720, 725, 730, 750, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 530 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 531 /* 70 - 1280x720@100Hz */ 532 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 533 1760, 1980, 720, 725, 730, 750, 0, 534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 535 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 536 /* 71 - 1280x720@120Hz */ 537 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 538 1430, 1650, 720, 725, 730, 750, 0, 539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 540 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 541 /* 72 - 1920x1080@24Hz */ 542 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 543 2602, 2750, 1080, 1084, 1089, 1125, 0, 544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 545 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 546 /* 73 - 1920x1080@25Hz */ 547 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 548 2492, 2640, 1080, 1084, 1089, 1125, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 550 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 551 /* 74 - 1920x1080@30Hz */ 552 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 553 2052, 2200, 1080, 1084, 1089, 1125, 0, 554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 555 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 556 /* 75 - 1920x1080@50Hz */ 557 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 558 2492, 2640, 1080, 1084, 1089, 1125, 0, 559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 560 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 561 /* 76 - 1920x1080@60Hz */ 562 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 563 2052, 2200, 1080, 1084, 1089, 1125, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 565 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 566 /* 77 - 1920x1080@100Hz */ 567 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 568 2492, 2640, 1080, 1084, 1089, 1125, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 570 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 571 /* 78 - 1920x1080@120Hz */ 572 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 573 2052, 2200, 1080, 1084, 1089, 1125, 0, 574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 575 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 576 /* 79 - 1680x720@24Hz */ 577 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 578 3080, 3300, 720, 725, 730, 750, 0, 579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 580 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 581 /* 80 - 1680x720@25Hz */ 582 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 583 2948, 3168, 720, 725, 730, 750, 0, 584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 585 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 586 /* 81 - 1680x720@30Hz */ 587 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 588 2420, 2640, 720, 725, 730, 750, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 590 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 591 /* 82 - 1680x720@50Hz */ 592 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 593 1980, 2200, 720, 725, 730, 750, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 595 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 596 /* 83 - 1680x720@60Hz */ 597 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 598 1980, 2200, 720, 725, 730, 750, 0, 599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 600 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 601 /* 84 - 1680x720@100Hz */ 602 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 603 1780, 2000, 720, 725, 730, 825, 0, 604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 605 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 606 /* 85 - 1680x720@120Hz */ 607 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 608 1780, 2000, 720, 725, 730, 825, 0, 609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 610 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 611 /* 86 - 2560x1080@24Hz */ 612 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 613 3602, 3750, 1080, 1084, 1089, 1100, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 615 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 616 /* 87 - 2560x1080@25Hz */ 617 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 618 3052, 3200, 1080, 1084, 1089, 1125, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 620 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 621 /* 88 - 2560x1080@30Hz */ 622 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 623 3372, 3520, 1080, 1084, 1089, 1125, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 625 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 626 /* 89 - 2560x1080@50Hz */ 627 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 628 3152, 3300, 1080, 1084, 1089, 1125, 0, 629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 630 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 631 /* 90 - 2560x1080@60Hz */ 632 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 633 2852, 3000, 1080, 1084, 1089, 1100, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 635 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 636 /* 91 - 2560x1080@100Hz */ 637 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 638 2822, 2970, 1080, 1084, 1089, 1250, 0, 639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 640 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 641 /* 92 - 2560x1080@120Hz */ 642 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 643 3152, 3300, 1080, 1084, 1089, 1250, 0, 644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 645 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 646 /* 93 - 3840x2160p@24Hz 16:9 */ 647 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 648 5204, 5500, 2160, 2168, 2178, 2250, 0, 649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 650 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 651 /* 94 - 3840x2160p@25Hz 16:9 */ 652 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 653 4984, 5280, 2160, 2168, 2178, 2250, 0, 654 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 655 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 656 /* 95 - 3840x2160p@30Hz 16:9 */ 657 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 658 4104, 4400, 2160, 2168, 2178, 2250, 0, 659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 660 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 661 /* 96 - 3840x2160p@50Hz 16:9 */ 662 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 663 4984, 5280, 2160, 2168, 2178, 2250, 0, 664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 665 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 666 /* 97 - 3840x2160p@60Hz 16:9 */ 667 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 668 4104, 4400, 2160, 2168, 2178, 2250, 0, 669 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 671 /* 98 - 4096x2160p@24Hz 256:135 */ 672 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 673 5204, 5500, 2160, 2168, 2178, 2250, 0, 674 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 675 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 676 /* 99 - 4096x2160p@25Hz 256:135 */ 677 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 678 5152, 5280, 2160, 2168, 2178, 2250, 0, 679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 680 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 681 /* 100 - 4096x2160p@30Hz 256:135 */ 682 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 683 4272, 4400, 2160, 2168, 2178, 2250, 0, 684 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 685 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 686 /* 101 - 4096x2160p@50Hz 256:135 */ 687 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 688 5152, 5280, 2160, 2168, 2178, 2250, 0, 689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 690 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 691 /* 102 - 4096x2160p@60Hz 256:135 */ 692 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 693 4272, 4400, 2160, 2168, 2178, 2250, 0, 694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 696 /* 103 - 3840x2160p@24Hz 64:27 */ 697 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 698 5204, 5500, 2160, 2168, 2178, 2250, 0, 699 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 700 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 701 /* 104 - 3840x2160p@25Hz 64:27 */ 702 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 703 4104, 4400, 2160, 2168, 2178, 2250, 0, 704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 705 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 706 /* 105 - 3840x2160p@30Hz 64:27 */ 707 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 708 4104, 4400, 2160, 2168, 2178, 2250, 0, 709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 710 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 711 /* 106 - 3840x2160p@50Hz 64:27 */ 712 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 713 4984, 5280, 2160, 2168, 2178, 2250, 0, 714 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 715 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 716 /* 107 - 3840x2160p@60Hz 64:27 */ 717 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 718 4104, 4400, 2160, 2168, 2178, 2250, 0, 719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 721 /* 108 - 1280x720@48Hz 16:9 */ 722 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 723 2280, 2500, 720, 725, 730, 750, 0, 724 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 725 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 726 /* 109 - 1280x720@48Hz 64:27 */ 727 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 728 2280, 2500, 720, 725, 730, 750, 0, 729 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 730 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 731 /* 110 - 1680x720@48Hz 64:27 */ 732 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 733 2530, 2750, 720, 725, 730, 750, 0, 734 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 735 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 736 /* 111 - 1920x1080@48Hz 16:9 */ 737 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 738 2602, 2750, 1080, 1084, 1089, 1125, 0, 739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 740 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 112 - 1920x1080@48Hz 64:27 */ 742 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 743 2602, 2750, 1080, 1084, 1089, 1125, 0, 744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 745 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 746 /* 113 - 2560x1080@48Hz 64:27 */ 747 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 748 3602, 3750, 1080, 1084, 1089, 1100, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 751 /* 114 - 3840x2160@48Hz 16:9 */ 752 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 753 5204, 5500, 2160, 2168, 2178, 2250, 0, 754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 755 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 115 - 4096x2160@48Hz 256:135 */ 757 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 758 5204, 5500, 2160, 2168, 2178, 2250, 0, 759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 760 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 761 /* 116 - 3840x2160@48Hz 64:27 */ 762 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 763 5204, 5500, 2160, 2168, 2178, 2250, 0, 764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 765 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 766 /* 117 - 3840x2160@100Hz 16:9 */ 767 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 768 4984, 5280, 2160, 2168, 2178, 2250, 0, 769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 770 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 771 /* 118 - 3840x2160@120Hz 16:9 */ 772 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 773 4104, 4400, 2160, 2168, 2178, 2250, 0, 774 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 775 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 119 - 3840x2160@100Hz 64:27 */ 777 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 778 4984, 5280, 2160, 2168, 2178, 2250, 0, 779 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 780 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 781 /* 120 - 3840x2160@120Hz 64:27 */ 782 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 783 4104, 4400, 2160, 2168, 2178, 2250, 0, 784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 785 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 786 /* 121 - 5120x2160@24Hz 64:27 */ 787 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 788 7204, 7500, 2160, 2168, 2178, 2200, 0, 789 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 790 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 791 /* 122 - 5120x2160@25Hz 64:27 */ 792 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 793 6904, 7200, 2160, 2168, 2178, 2200, 0, 794 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 795 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 796 /* 123 - 5120x2160@30Hz 64:27 */ 797 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 798 5872, 6000, 2160, 2168, 2178, 2200, 0, 799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 800 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 801 /* 124 - 5120x2160@48Hz 64:27 */ 802 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 803 5954, 6250, 2160, 2168, 2178, 2475, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 806 /* 125 - 5120x2160@50Hz 64:27 */ 807 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 808 6304, 6600, 2160, 2168, 2178, 2250, 0, 809 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 811 /* 126 - 5120x2160@60Hz 64:27 */ 812 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 813 5372, 5500, 2160, 2168, 2178, 2250, 0, 814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 815 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 816 /* 127 - 5120x2160@100Hz 64:27 */ 817 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 818 6304, 6600, 2160, 2168, 2178, 2250, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 821 }; 822 823 static const struct drm_display_mode edid_cea_modes_193[] = { 824 /* 193 - 5120x2160@120Hz 64:27 */ 825 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 826 5372, 5500, 2160, 2168, 2178, 2250, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 829 /* 194 - 7680x4320@24Hz 16:9 */ 830 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 831 10408, 11000, 4320, 4336, 4356, 4500, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 833 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 195 - 7680x4320@25Hz 16:9 */ 835 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 836 10208, 10800, 4320, 4336, 4356, 4400, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 838 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 196 - 7680x4320@30Hz 16:9 */ 840 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 841 8408, 9000, 4320, 4336, 4356, 4400, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 843 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 844 /* 197 - 7680x4320@48Hz 16:9 */ 845 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 846 10408, 11000, 4320, 4336, 4356, 4500, 0, 847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 848 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 198 - 7680x4320@50Hz 16:9 */ 850 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 851 10208, 10800, 4320, 4336, 4356, 4400, 0, 852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 854 /* 199 - 7680x4320@60Hz 16:9 */ 855 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 856 8408, 9000, 4320, 4336, 4356, 4400, 0, 857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 858 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 200 - 7680x4320@100Hz 16:9 */ 860 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 861 9968, 10560, 4320, 4336, 4356, 4500, 0, 862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 863 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 201 - 7680x4320@120Hz 16:9 */ 865 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 866 8208, 8800, 4320, 4336, 4356, 4500, 0, 867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 868 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 202 - 7680x4320@24Hz 64:27 */ 870 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 871 10408, 11000, 4320, 4336, 4356, 4500, 0, 872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 873 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 874 /* 203 - 7680x4320@25Hz 64:27 */ 875 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 876 10208, 10800, 4320, 4336, 4356, 4400, 0, 877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 878 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 879 /* 204 - 7680x4320@30Hz 64:27 */ 880 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 881 8408, 9000, 4320, 4336, 4356, 4400, 0, 882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 883 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 884 /* 205 - 7680x4320@48Hz 64:27 */ 885 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 886 10408, 11000, 4320, 4336, 4356, 4500, 0, 887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 888 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 889 /* 206 - 7680x4320@50Hz 64:27 */ 890 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 891 10208, 10800, 4320, 4336, 4356, 4400, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 893 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 894 /* 207 - 7680x4320@60Hz 64:27 */ 895 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 896 8408, 9000, 4320, 4336, 4356, 4400, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 899 /* 208 - 7680x4320@100Hz 64:27 */ 900 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 901 9968, 10560, 4320, 4336, 4356, 4500, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 904 /* 209 - 7680x4320@120Hz 64:27 */ 905 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 906 8208, 8800, 4320, 4336, 4356, 4500, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 909 /* 210 - 10240x4320@24Hz 64:27 */ 910 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 911 11908, 12500, 4320, 4336, 4356, 4950, 0, 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 913 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 914 /* 211 - 10240x4320@25Hz 64:27 */ 915 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 916 12908, 13500, 4320, 4336, 4356, 4400, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 919 /* 212 - 10240x4320@30Hz 64:27 */ 920 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 921 10704, 11000, 4320, 4336, 4356, 4500, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 923 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 924 /* 213 - 10240x4320@48Hz 64:27 */ 925 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 926 11908, 12500, 4320, 4336, 4356, 4950, 0, 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 928 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 929 /* 214 - 10240x4320@50Hz 64:27 */ 930 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 931 12908, 13500, 4320, 4336, 4356, 4400, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 933 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 934 /* 215 - 10240x4320@60Hz 64:27 */ 935 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 936 10704, 11000, 4320, 4336, 4356, 4500, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 939 /* 216 - 10240x4320@100Hz 64:27 */ 940 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 941 12608, 13200, 4320, 4336, 4356, 4500, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 944 /* 217 - 10240x4320@120Hz 64:27 */ 945 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 946 10704, 11000, 4320, 4336, 4356, 4500, 0, 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 949 /* 218 - 4096x2160@100Hz 256:135 */ 950 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 951 4984, 5280, 2160, 2168, 2178, 2250, 0, 952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 953 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 954 /* 219 - 4096x2160@120Hz 256:135 */ 955 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 956 4272, 4400, 2160, 2168, 2178, 2250, 0, 957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 958 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 959 }; 960 961 /* 962 * HDMI 1.4 4k modes. Index using the VIC. 963 */ 964 static const struct drm_display_mode edid_4k_modes[] = { 965 /* 0 - dummy, VICs start at 1 */ 966 { }, 967 /* 1 - 3840x2160@30Hz */ 968 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 969 3840, 4016, 4104, 4400, 970 2160, 2168, 2178, 2250, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 2 - 3840x2160@25Hz */ 974 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 975 3840, 4896, 4984, 5280, 976 2160, 2168, 2178, 2250, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 978 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 979 /* 3 - 3840x2160@24Hz */ 980 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 981 3840, 5116, 5204, 5500, 982 2160, 2168, 2178, 2250, 0, 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 984 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 4 - 4096x2160@24Hz (SMPTE) */ 986 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 987 4096, 5116, 5204, 5500, 988 2160, 2168, 2178, 2250, 0, 989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 990 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 991 }; 992 993 /* 994 * Autogenerated from the DMT spec. 995 * This table is copied from xfree86/modes/xf86EdidModes.c. 996 */ 997 static const struct drm_display_mode drm_dmt_modes[] = { 998 /* 0x01 - 640x350@85Hz */ 999 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1000 736, 832, 350, 382, 385, 445, 0, 1001 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1002 /* 0x02 - 640x400@85Hz */ 1003 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1004 736, 832, 400, 401, 404, 445, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1006 /* 0x03 - 720x400@85Hz */ 1007 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 1008 828, 936, 400, 401, 404, 446, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1010 /* 0x04 - 640x480@60Hz */ 1011 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1012 752, 800, 480, 490, 492, 525, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1014 /* 0x05 - 640x480@72Hz */ 1015 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1016 704, 832, 480, 489, 492, 520, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1018 /* 0x06 - 640x480@75Hz */ 1019 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1020 720, 840, 480, 481, 484, 500, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1022 /* 0x07 - 640x480@85Hz */ 1023 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 1024 752, 832, 480, 481, 484, 509, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1026 /* 0x08 - 800x600@56Hz */ 1027 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1028 896, 1024, 600, 601, 603, 625, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1030 /* 0x09 - 800x600@60Hz */ 1031 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1032 968, 1056, 600, 601, 605, 628, 0, 1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1034 /* 0x0a - 800x600@72Hz */ 1035 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1036 976, 1040, 600, 637, 643, 666, 0, 1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1038 /* 0x0b - 800x600@75Hz */ 1039 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1040 896, 1056, 600, 601, 604, 625, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1042 /* 0x0c - 800x600@85Hz */ 1043 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 1044 896, 1048, 600, 601, 604, 631, 0, 1045 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1046 /* 0x0d - 800x600@120Hz RB */ 1047 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 1048 880, 960, 600, 603, 607, 636, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1050 /* 0x0e - 848x480@60Hz */ 1051 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 1052 976, 1088, 480, 486, 494, 517, 0, 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1054 /* 0x0f - 1024x768@43Hz, interlace */ 1055 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1056 1208, 1264, 768, 768, 772, 817, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1058 DRM_MODE_FLAG_INTERLACE) }, 1059 /* 0x10 - 1024x768@60Hz */ 1060 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1061 1184, 1344, 768, 771, 777, 806, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1063 /* 0x11 - 1024x768@70Hz */ 1064 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1065 1184, 1328, 768, 771, 777, 806, 0, 1066 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1067 /* 0x12 - 1024x768@75Hz */ 1068 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1069 1136, 1312, 768, 769, 772, 800, 0, 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1071 /* 0x13 - 1024x768@85Hz */ 1072 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 1073 1168, 1376, 768, 769, 772, 808, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1075 /* 0x14 - 1024x768@120Hz RB */ 1076 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 1077 1104, 1184, 768, 771, 775, 813, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1079 /* 0x15 - 1152x864@75Hz */ 1080 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1081 1344, 1600, 864, 865, 868, 900, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1083 /* 0x55 - 1280x720@60Hz */ 1084 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1085 1430, 1650, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1087 /* 0x16 - 1280x768@60Hz RB */ 1088 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 1089 1360, 1440, 768, 771, 778, 790, 0, 1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1091 /* 0x17 - 1280x768@60Hz */ 1092 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 1093 1472, 1664, 768, 771, 778, 798, 0, 1094 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1095 /* 0x18 - 1280x768@75Hz */ 1096 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 1097 1488, 1696, 768, 771, 778, 805, 0, 1098 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1099 /* 0x19 - 1280x768@85Hz */ 1100 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 1101 1496, 1712, 768, 771, 778, 809, 0, 1102 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1103 /* 0x1a - 1280x768@120Hz RB */ 1104 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 1105 1360, 1440, 768, 771, 778, 813, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1107 /* 0x1b - 1280x800@60Hz RB */ 1108 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 1109 1360, 1440, 800, 803, 809, 823, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1111 /* 0x1c - 1280x800@60Hz */ 1112 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 1113 1480, 1680, 800, 803, 809, 831, 0, 1114 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1115 /* 0x1d - 1280x800@75Hz */ 1116 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 1117 1488, 1696, 800, 803, 809, 838, 0, 1118 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1119 /* 0x1e - 1280x800@85Hz */ 1120 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 1121 1496, 1712, 800, 803, 809, 843, 0, 1122 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1123 /* 0x1f - 1280x800@120Hz RB */ 1124 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 1125 1360, 1440, 800, 803, 809, 847, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1127 /* 0x20 - 1280x960@60Hz */ 1128 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 1129 1488, 1800, 960, 961, 964, 1000, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1131 /* 0x21 - 1280x960@85Hz */ 1132 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 1133 1504, 1728, 960, 961, 964, 1011, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1135 /* 0x22 - 1280x960@120Hz RB */ 1136 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 1137 1360, 1440, 960, 963, 967, 1017, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1139 /* 0x23 - 1280x1024@60Hz */ 1140 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 1141 1440, 1688, 1024, 1025, 1028, 1066, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1143 /* 0x24 - 1280x1024@75Hz */ 1144 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1145 1440, 1688, 1024, 1025, 1028, 1066, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1147 /* 0x25 - 1280x1024@85Hz */ 1148 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 1149 1504, 1728, 1024, 1025, 1028, 1072, 0, 1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1151 /* 0x26 - 1280x1024@120Hz RB */ 1152 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 1153 1360, 1440, 1024, 1027, 1034, 1084, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1155 /* 0x27 - 1360x768@60Hz */ 1156 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 1157 1536, 1792, 768, 771, 777, 795, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1159 /* 0x28 - 1360x768@120Hz RB */ 1160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 1161 1440, 1520, 768, 771, 776, 813, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1163 /* 0x51 - 1366x768@60Hz */ 1164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 1165 1579, 1792, 768, 771, 774, 798, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1167 /* 0x56 - 1366x768@60Hz */ 1168 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 1169 1436, 1500, 768, 769, 772, 800, 0, 1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1171 /* 0x29 - 1400x1050@60Hz RB */ 1172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 1173 1480, 1560, 1050, 1053, 1057, 1080, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1175 /* 0x2a - 1400x1050@60Hz */ 1176 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 1177 1632, 1864, 1050, 1053, 1057, 1089, 0, 1178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1179 /* 0x2b - 1400x1050@75Hz */ 1180 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 1181 1648, 1896, 1050, 1053, 1057, 1099, 0, 1182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1183 /* 0x2c - 1400x1050@85Hz */ 1184 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 1185 1656, 1912, 1050, 1053, 1057, 1105, 0, 1186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1187 /* 0x2d - 1400x1050@120Hz RB */ 1188 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 1189 1480, 1560, 1050, 1053, 1057, 1112, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1191 /* 0x2e - 1440x900@60Hz RB */ 1192 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 1193 1520, 1600, 900, 903, 909, 926, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1195 /* 0x2f - 1440x900@60Hz */ 1196 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 1197 1672, 1904, 900, 903, 909, 934, 0, 1198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1199 /* 0x30 - 1440x900@75Hz */ 1200 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 1201 1688, 1936, 900, 903, 909, 942, 0, 1202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1203 /* 0x31 - 1440x900@85Hz */ 1204 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 1205 1696, 1952, 900, 903, 909, 948, 0, 1206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1207 /* 0x32 - 1440x900@120Hz RB */ 1208 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 1209 1520, 1600, 900, 903, 909, 953, 0, 1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1211 /* 0x53 - 1600x900@60Hz */ 1212 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 1213 1704, 1800, 900, 901, 904, 1000, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1215 /* 0x33 - 1600x1200@60Hz */ 1216 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 1217 1856, 2160, 1200, 1201, 1204, 1250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1219 /* 0x34 - 1600x1200@65Hz */ 1220 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 1221 1856, 2160, 1200, 1201, 1204, 1250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1223 /* 0x35 - 1600x1200@70Hz */ 1224 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 1225 1856, 2160, 1200, 1201, 1204, 1250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1227 /* 0x36 - 1600x1200@75Hz */ 1228 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 1229 1856, 2160, 1200, 1201, 1204, 1250, 0, 1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1231 /* 0x37 - 1600x1200@85Hz */ 1232 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 1233 1856, 2160, 1200, 1201, 1204, 1250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1235 /* 0x38 - 1600x1200@120Hz RB */ 1236 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 1237 1680, 1760, 1200, 1203, 1207, 1271, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1239 /* 0x39 - 1680x1050@60Hz RB */ 1240 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1241 1760, 1840, 1050, 1053, 1059, 1080, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1243 /* 0x3a - 1680x1050@60Hz */ 1244 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1245 1960, 2240, 1050, 1053, 1059, 1089, 0, 1246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1247 /* 0x3b - 1680x1050@75Hz */ 1248 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1249 1976, 2272, 1050, 1053, 1059, 1099, 0, 1250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1251 /* 0x3c - 1680x1050@85Hz */ 1252 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1253 1984, 2288, 1050, 1053, 1059, 1105, 0, 1254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1255 /* 0x3d - 1680x1050@120Hz RB */ 1256 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1257 1760, 1840, 1050, 1053, 1059, 1112, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1259 /* 0x3e - 1792x1344@60Hz */ 1260 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1261 2120, 2448, 1344, 1345, 1348, 1394, 0, 1262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1263 /* 0x3f - 1792x1344@75Hz */ 1264 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1265 2104, 2456, 1344, 1345, 1348, 1417, 0, 1266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1267 /* 0x40 - 1792x1344@120Hz RB */ 1268 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1269 1872, 1952, 1344, 1347, 1351, 1423, 0, 1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1271 /* 0x41 - 1856x1392@60Hz */ 1272 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1273 2176, 2528, 1392, 1393, 1396, 1439, 0, 1274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1275 /* 0x42 - 1856x1392@75Hz */ 1276 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1277 2208, 2560, 1392, 1393, 1396, 1500, 0, 1278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1279 /* 0x43 - 1856x1392@120Hz RB */ 1280 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1281 1936, 2016, 1392, 1395, 1399, 1474, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1283 /* 0x52 - 1920x1080@60Hz */ 1284 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1285 2052, 2200, 1080, 1084, 1089, 1125, 0, 1286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1287 /* 0x44 - 1920x1200@60Hz RB */ 1288 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1289 2000, 2080, 1200, 1203, 1209, 1235, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1291 /* 0x45 - 1920x1200@60Hz */ 1292 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1293 2256, 2592, 1200, 1203, 1209, 1245, 0, 1294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1295 /* 0x46 - 1920x1200@75Hz */ 1296 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1297 2264, 2608, 1200, 1203, 1209, 1255, 0, 1298 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1299 /* 0x47 - 1920x1200@85Hz */ 1300 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1301 2272, 2624, 1200, 1203, 1209, 1262, 0, 1302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1303 /* 0x48 - 1920x1200@120Hz RB */ 1304 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1305 2000, 2080, 1200, 1203, 1209, 1271, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1307 /* 0x49 - 1920x1440@60Hz */ 1308 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1309 2256, 2600, 1440, 1441, 1444, 1500, 0, 1310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1311 /* 0x4a - 1920x1440@75Hz */ 1312 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1313 2288, 2640, 1440, 1441, 1444, 1500, 0, 1314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1315 /* 0x4b - 1920x1440@120Hz RB */ 1316 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1317 2000, 2080, 1440, 1443, 1447, 1525, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1319 /* 0x54 - 2048x1152@60Hz */ 1320 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1321 2154, 2250, 1152, 1153, 1156, 1200, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1323 /* 0x4c - 2560x1600@60Hz RB */ 1324 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1325 2640, 2720, 1600, 1603, 1609, 1646, 0, 1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1327 /* 0x4d - 2560x1600@60Hz */ 1328 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1329 3032, 3504, 1600, 1603, 1609, 1658, 0, 1330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1331 /* 0x4e - 2560x1600@75Hz */ 1332 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1333 3048, 3536, 1600, 1603, 1609, 1672, 0, 1334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1335 /* 0x4f - 2560x1600@85Hz */ 1336 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1337 3048, 3536, 1600, 1603, 1609, 1682, 0, 1338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1339 /* 0x50 - 2560x1600@120Hz RB */ 1340 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1341 2640, 2720, 1600, 1603, 1609, 1694, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1343 /* 0x57 - 4096x2160@60Hz RB */ 1344 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1345 4136, 4176, 2160, 2208, 2216, 2222, 0, 1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1347 /* 0x58 - 4096x2160@59.94Hz RB */ 1348 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1349 4136, 4176, 2160, 2208, 2216, 2222, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1351 }; 1352 1353 /* 1354 * These more or less come from the DMT spec. The 720x400 modes are 1355 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1356 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1357 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1358 * mode. 1359 * 1360 * The DMT modes have been fact-checked; the rest are mild guesses. 1361 */ 1362 static const struct drm_display_mode edid_est_modes[] = { 1363 /* 800x600@60Hz */ 1364 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1365 968, 1056, 600, 601, 605, 628, 0, 1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1367 /* 800x600@56Hz */ 1368 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1369 896, 1024, 600, 601, 603, 625, 0, 1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1371 /* 640x480@75Hz */ 1372 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1373 720, 840, 480, 481, 484, 500, 0, 1374 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1375 /* 640x480@72Hz */ 1376 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1377 704, 832, 480, 489, 492, 520, 0, 1378 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1379 /* 640x480@67Hz */ 1380 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1381 768, 864, 480, 483, 486, 525, 0, 1382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1383 /* 640x480@60Hz */ 1384 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1385 752, 800, 480, 490, 492, 525, 0, 1386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1387 /* 720x400@88Hz */ 1388 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1389 846, 900, 400, 421, 423, 449, 0, 1390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1391 /* 720x400@70Hz */ 1392 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1393 846, 900, 400, 412, 414, 449, 0, 1394 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1395 /* 1280x1024@75Hz */ 1396 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1397 1440, 1688, 1024, 1025, 1028, 1066, 0, 1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1399 /* 1024x768@75Hz */ 1400 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1401 1136, 1312, 768, 769, 772, 800, 0, 1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1403 /* 1024x768@70Hz */ 1404 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1405 1184, 1328, 768, 771, 777, 806, 0, 1406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1407 /* 1024x768@60Hz */ 1408 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1409 1184, 1344, 768, 771, 777, 806, 0, 1410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1411 /* 1024x768@43Hz */ 1412 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1413 1208, 1264, 768, 768, 776, 817, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1415 DRM_MODE_FLAG_INTERLACE) }, 1416 /* 832x624@75Hz */ 1417 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1418 928, 1152, 624, 625, 628, 667, 0, 1419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1420 /* 800x600@75Hz */ 1421 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1422 896, 1056, 600, 601, 604, 625, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1424 /* 800x600@72Hz */ 1425 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1426 976, 1040, 600, 637, 643, 666, 0, 1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1428 /* 1152x864@75Hz */ 1429 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1430 1344, 1600, 864, 865, 868, 900, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1432 }; 1433 1434 static const struct drm_display_mode resolution_white[] = { 1435 /* 0. vic:2 - 720x480@60Hz */ 1436 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 1437 798, 858, 480, 489, 495, 525, 0, 1438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1439 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1440 /* 1. vic:3 - 720x480@60Hz */ 1441 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 1442 798, 858, 480, 489, 495, 525, 0, 1443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1444 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1445 /* 1024x768@60Hz */ 1446 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1447 1184, 1344, 768, 771, 777, 806, 0, 1448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1449 /* 2. vic:4 - 1280x720@60Hz */ 1450 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1451 1430, 1650, 720, 725, 730, 750, 0, 1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1453 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1454 /* 3. vic:5 - 1920x1080i@60Hz */ 1455 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1456 2052, 2200, 1080, 1084, 1094, 1125, 0, 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1458 DRM_MODE_FLAG_INTERLACE), 1459 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1460 /* 4. vic:6 - 720(1440)x480i@60Hz */ 1461 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 1462 801, 858, 480, 488, 494, 525, 0, 1463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1464 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1465 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1466 /* 5. vic:16 - 1920x1080@60Hz */ 1467 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1468 2052, 2200, 1080, 1084, 1089, 1125, 0, 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1470 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1471 /* 6. vic:17 - 720x576@50Hz */ 1472 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 1473 796, 864, 576, 581, 586, 625, 0, 1474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1475 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1476 /* 7. vic:18 - 720x576@50Hz */ 1477 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 1478 796, 864, 576, 581, 586, 625, 0, 1479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1480 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1481 /* 8. vic:19 - 1280x720@50Hz */ 1482 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1483 1760, 1980, 720, 725, 730, 750, 0, 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1485 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1486 /* 9. vic:20 - 1920x1080i@50Hz */ 1487 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1488 2492, 2640, 1080, 1084, 1094, 1125, 0, 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1490 DRM_MODE_FLAG_INTERLACE), 1491 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1492 /* 10. vic:21 - 720(1440)x576i@50Hz */ 1493 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 1494 795, 864, 576, 580, 586, 625, 0, 1495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1496 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1497 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1498 /* 11. vic:31 - 1920x1080@50Hz */ 1499 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1500 2492, 2640, 1080, 1084, 1089, 1125, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1503 /* 12. vic:32 - 1920x1080@24Hz */ 1504 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1505 2602, 2750, 1080, 1084, 1089, 1125, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1508 /* 13. vic:33 - 1920x1080@25Hz */ 1509 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1510 2492, 2640, 1080, 1084, 1089, 1125, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1513 /* 14. vic:34 - 1920x1080@30Hz */ 1514 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1515 2052, 2200, 1080, 1084, 1089, 1125, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1518 /* 15. vic:39 - 1920x1080i@50Hz */ 1519 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 1520 2120, 2304, 1080, 1126, 1136, 1250, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 1522 DRM_MODE_FLAG_INTERLACE), 1523 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1524 /* 16. vic:60 - 1280x720@24Hz */ 1525 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1526 3080, 3300, 720, 725, 730, 750, 0, 1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1528 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1529 /* 17. vic:61 - 1280x720@25Hz */ 1530 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1531 3740, 3960, 720, 725, 730, 750, 0, 1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1533 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1534 /* 18. vic:62 - 1280x720@30Hz */ 1535 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1536 3080, 3300, 720, 725, 730, 750, 0, 1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1538 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1539 /* 19. vic:93 - 3840x2160p@24Hz 16:9 */ 1540 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1541 5204, 5500, 2160, 2168, 2178, 2250, 0, 1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1543 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1544 /* 20. vic:94 - 3840x2160p@25Hz 16:9 */ 1545 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1546 4984, 5280, 2160, 2168, 2178, 2250, 0, 1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1548 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1549 /* 21. vic:95 - 3840x2160p@30Hz 16:9 */ 1550 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1551 4104, 4400, 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1554 /* 22. vic:96 - 3840x2160p@50Hz 16:9 */ 1555 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1556 4984, 5280, 2160, 2168, 2178, 2250, 0, 1557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1558 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1559 /* 23. vic:97 - 3840x2160p@60Hz 16:9 */ 1560 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1561 4104, 4400, 2160, 2168, 2178, 2250, 0, 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1563 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1564 /* 24. vic:98 - 4096x2160p@24Hz 256:135 */ 1565 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1566 5204, 5500, 2160, 2168, 2178, 2250, 0, 1567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1568 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1569 /* 25. vic:99 - 4096x2160p@25Hz 256:135 */ 1570 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1571 5152, 5280, 2160, 2168, 2178, 2250, 0, 1572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1573 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1574 /* 26. vic:100 - 4096x2160p@30Hz 256:135 */ 1575 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1576 4272, 4400, 2160, 2168, 2178, 2250, 0, 1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1578 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1579 /* 27. vic:101 - 4096x2160p@50Hz 256:135 */ 1580 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1581 5152, 5280, 2160, 2168, 2178, 2250, 0, 1582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1583 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1584 /* 28. vic:102 - 4096x2160p@60Hz 256:135 */ 1585 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1586 4272, 4400, 2160, 2168, 2178, 2250, 0, 1587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1588 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1589 /* 29. vic:118 - 3840x2160@120Hz 16:9 */ 1590 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1591 4104, 4400, 2160, 2168, 2178, 2250, 0, 1592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1593 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1594 /* 30. vic:196 - 7680x4320@30Hz 16:9 */ 1595 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1596 8408, 9000, 4320, 4336, 4356, 4400, 0, 1597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1598 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1599 /* 31. vic:198 - 7680x4320@50Hz 16:9 */ 1600 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1601 10208, 10800, 4320, 4336, 4356, 4400, 0, 1602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1603 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1604 /* 32. vic:199 - 7680x4320@60Hz 16:9 */ 1605 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1606 8408, 9000, 4320, 4336, 4356, 4400, 0, 1607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1608 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1609 }; 1610 1611 struct minimode { 1612 short w; 1613 short h; 1614 short r; 1615 short rb; 1616 }; 1617 1618 static const struct minimode est3_modes[] = { 1619 /* byte 6 */ 1620 { 640, 350, 85, 0 }, 1621 { 640, 400, 85, 0 }, 1622 { 720, 400, 85, 0 }, 1623 { 640, 480, 85, 0 }, 1624 { 848, 480, 60, 0 }, 1625 { 800, 600, 85, 0 }, 1626 { 1024, 768, 85, 0 }, 1627 { 1152, 864, 75, 0 }, 1628 /* byte 7 */ 1629 { 1280, 768, 60, 1 }, 1630 { 1280, 768, 60, 0 }, 1631 { 1280, 768, 75, 0 }, 1632 { 1280, 768, 85, 0 }, 1633 { 1280, 960, 60, 0 }, 1634 { 1280, 960, 85, 0 }, 1635 { 1280, 1024, 60, 0 }, 1636 { 1280, 1024, 85, 0 }, 1637 /* byte 8 */ 1638 { 1360, 768, 60, 0 }, 1639 { 1440, 900, 60, 1 }, 1640 { 1440, 900, 60, 0 }, 1641 { 1440, 900, 75, 0 }, 1642 { 1440, 900, 85, 0 }, 1643 { 1400, 1050, 60, 1 }, 1644 { 1400, 1050, 60, 0 }, 1645 { 1400, 1050, 75, 0 }, 1646 /* byte 9 */ 1647 { 1400, 1050, 85, 0 }, 1648 { 1680, 1050, 60, 1 }, 1649 { 1680, 1050, 60, 0 }, 1650 { 1680, 1050, 75, 0 }, 1651 { 1680, 1050, 85, 0 }, 1652 { 1600, 1200, 60, 0 }, 1653 { 1600, 1200, 65, 0 }, 1654 { 1600, 1200, 70, 0 }, 1655 /* byte 10 */ 1656 { 1600, 1200, 75, 0 }, 1657 { 1600, 1200, 85, 0 }, 1658 { 1792, 1344, 60, 0 }, 1659 { 1792, 1344, 75, 0 }, 1660 { 1856, 1392, 60, 0 }, 1661 { 1856, 1392, 75, 0 }, 1662 { 1920, 1200, 60, 1 }, 1663 { 1920, 1200, 60, 0 }, 1664 /* byte 11 */ 1665 { 1920, 1200, 75, 0 }, 1666 { 1920, 1200, 85, 0 }, 1667 { 1920, 1440, 60, 0 }, 1668 { 1920, 1440, 75, 0 }, 1669 }; 1670 1671 static const struct minimode extra_modes[] = { 1672 { 1024, 576, 60, 0 }, 1673 { 1366, 768, 60, 0 }, 1674 { 1600, 900, 60, 0 }, 1675 { 1680, 945, 60, 0 }, 1676 { 1920, 1080, 60, 0 }, 1677 { 2048, 1152, 60, 0 }, 1678 { 2048, 1536, 60, 0 }, 1679 }; 1680 1681 static const struct drm_display_mode *cea_mode_for_vic(u8 vic) 1682 { 1683 if (!vic) 1684 return NULL; 1685 else if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 1686 return &edid_cea_modes_1[vic - 1]; 1687 else if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 1688 return &edid_cea_modes_193[vic - 193]; 1689 1690 return NULL; 1691 } 1692 1693 static u8 cea_num_vics(void) 1694 { 1695 return 193 + ARRAY_SIZE(edid_cea_modes_193); 1696 } 1697 1698 static u8 cea_next_vic(u8 vic) 1699 { 1700 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 1701 vic = 193; 1702 1703 return vic; 1704 } 1705 1706 int edid_check_info(struct edid1_info *edid_info) 1707 { 1708 if ((edid_info == NULL) || (edid_info->version == 0)) 1709 return -1; 1710 1711 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1712 return -1; 1713 1714 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1715 return -1; 1716 1717 return 0; 1718 } 1719 1720 int edid_check_checksum(u8 *edid_block) 1721 { 1722 u8 checksum = 0; 1723 int i; 1724 1725 for (i = 0; i < 128; i++) 1726 checksum += edid_block[i]; 1727 1728 return (checksum == 0) ? 0 : -EINVAL; 1729 } 1730 1731 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1732 unsigned int *hmax, unsigned int *vmin, 1733 unsigned int *vmax) 1734 { 1735 int i; 1736 struct edid_monitor_descriptor *monitor; 1737 1738 *hmin = *hmax = *vmin = *vmax = 0; 1739 if (edid_check_info(edid)) 1740 return -1; 1741 1742 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1743 monitor = &edid->monitor_details.descriptor[i]; 1744 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1745 *hmin = monitor->data.range_data.horizontal_min; 1746 *hmax = monitor->data.range_data.horizontal_max; 1747 *vmin = monitor->data.range_data.vertical_min; 1748 *vmax = monitor->data.range_data.vertical_max; 1749 return 0; 1750 } 1751 } 1752 return -1; 1753 } 1754 1755 /* Set all parts of a timing entry to the same value */ 1756 static void set_entry(struct timing_entry *entry, u32 value) 1757 { 1758 entry->min = value; 1759 entry->typ = value; 1760 entry->max = value; 1761 } 1762 1763 /** 1764 * decode_timing() - Decoding an 18-byte detailed timing record 1765 * 1766 * @buf: Pointer to EDID detailed timing record 1767 * @timing: Place to put timing 1768 */ 1769 static void decode_timing(u8 *buf, struct display_timing *timing) 1770 { 1771 uint x_mm, y_mm; 1772 unsigned int ha, hbl, hso, hspw, hborder; 1773 unsigned int va, vbl, vso, vspw, vborder; 1774 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1775 1776 /* Edid contains pixel clock in terms of 10KHz */ 1777 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1778 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1779 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1780 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1781 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1782 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1783 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1784 hborder = buf[15]; 1785 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1786 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1787 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1788 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1789 vborder = buf[16]; 1790 1791 set_entry(&timing->hactive, ha); 1792 set_entry(&timing->hfront_porch, hso); 1793 set_entry(&timing->hback_porch, hbl - hso - hspw); 1794 set_entry(&timing->hsync_len, hspw); 1795 1796 set_entry(&timing->vactive, va); 1797 set_entry(&timing->vfront_porch, vso); 1798 set_entry(&timing->vback_porch, vbl - vso - vspw); 1799 set_entry(&timing->vsync_len, vspw); 1800 1801 timing->flags = 0; 1802 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1803 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1804 else 1805 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1806 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1807 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1808 else 1809 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1810 1811 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1812 timing->flags = DISPLAY_FLAGS_INTERLACED; 1813 1814 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1815 " %04x %04x %04x %04x hborder %x\n" 1816 " %04x %04x %04x %04x vborder %x\n", 1817 timing->pixelclock.typ, 1818 x_mm, y_mm, 1819 ha, ha + hso, ha + hso + hspw, 1820 ha + hbl, hborder, 1821 va, va + vso, va + vso + vspw, 1822 va + vbl, vborder); 1823 } 1824 1825 /** 1826 * decode_mode() - Decoding an 18-byte detailed timing record 1827 * 1828 * @buf: Pointer to EDID detailed timing record 1829 * @timing: Place to put timing 1830 */ 1831 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1832 { 1833 uint x_mm, y_mm; 1834 unsigned int ha, hbl, hso, hspw, hborder; 1835 unsigned int va, vbl, vso, vspw, vborder; 1836 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1837 1838 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1839 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1840 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1841 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1842 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1843 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1844 hborder = buf[15]; 1845 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1846 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1847 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1848 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1849 vborder = buf[16]; 1850 1851 /* Edid contains pixel clock in terms of 10KHz */ 1852 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1853 mode->hdisplay = ha; 1854 mode->hsync_start = ha + hso; 1855 mode->hsync_end = ha + hso + hspw; 1856 mode->htotal = ha + hbl; 1857 mode->vdisplay = va; 1858 mode->vsync_start = va + vso; 1859 mode->vsync_end = va + vso + vspw; 1860 mode->vtotal = va + vbl; 1861 1862 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1863 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1864 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1865 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1866 1867 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1868 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1869 1870 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1871 " %04d %04d %04d %04d hborder %d\n" 1872 " %04d %04d %04d %04d vborder %d\n", 1873 mode->clock, 1874 x_mm, y_mm, mode->flags, 1875 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1876 mode->htotal, hborder, 1877 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1878 mode->vtotal, vborder); 1879 } 1880 1881 /** 1882 * edid_vendor - match a string against EDID's obfuscated vendor field 1883 * @edid: EDID to match 1884 * @vendor: vendor string 1885 * 1886 * Returns true if @vendor is in @edid, false otherwise 1887 */ 1888 static bool edid_vendor(struct edid *edid, char *vendor) 1889 { 1890 char edid_vendor[3]; 1891 1892 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1893 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1894 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1895 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1896 1897 return !strncmp(edid_vendor, vendor, 3); 1898 } 1899 1900 /** 1901 * Check if HDMI vendor specific data block is present in CEA block 1902 * @param info CEA extension block 1903 * @return true if block is found 1904 */ 1905 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1906 { 1907 u8 end, i = 0; 1908 1909 /* check for end of data block */ 1910 end = info->dtd_offset; 1911 if (end == 0) 1912 end = sizeof(info->data); 1913 if (end < 4 || end > sizeof(info->data)) 1914 return false; 1915 end -= 4; 1916 1917 while (i < end) { 1918 /* Look for vendor specific data block of appropriate size */ 1919 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1920 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1921 u8 *db = &info->data[i + 1]; 1922 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1923 1924 if (oui == HDMI_IEEE_OUI) 1925 return true; 1926 } 1927 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1928 } 1929 1930 return false; 1931 } 1932 1933 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1934 { 1935 int refresh = 0; 1936 unsigned int calc_val; 1937 1938 if (mode->vrefresh > 0) { 1939 refresh = mode->vrefresh; 1940 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1941 int vtotal; 1942 1943 vtotal = mode->vtotal; 1944 /* work out vrefresh the value will be x1000 */ 1945 calc_val = (mode->clock * 1000); 1946 calc_val /= mode->htotal; 1947 refresh = (calc_val + vtotal / 2) / vtotal; 1948 1949 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1950 refresh *= 2; 1951 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1952 refresh /= 2; 1953 if (mode->vscan > 1) 1954 refresh /= mode->vscan; 1955 } 1956 return refresh; 1957 } 1958 1959 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1960 int *panel_bits_per_colourp) 1961 { 1962 struct edid1_info *edid = (struct edid1_info *)buf; 1963 bool timing_done; 1964 int i; 1965 1966 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1967 debug("%s: Invalid buffer\n", __func__); 1968 return -EINVAL; 1969 } 1970 1971 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1972 debug("%s: No preferred timing\n", __func__); 1973 return -ENOENT; 1974 } 1975 1976 /* Look for detailed timing */ 1977 timing_done = false; 1978 for (i = 0; i < 4; i++) { 1979 struct edid_monitor_descriptor *desc; 1980 1981 desc = &edid->monitor_details.descriptor[i]; 1982 if (desc->zero_flag_1 != 0) { 1983 decode_mode((u8 *)desc, mode); 1984 timing_done = true; 1985 break; 1986 } 1987 } 1988 if (!timing_done) 1989 return -EINVAL; 1990 1991 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1992 debug("%s: Not a digital display\n", __func__); 1993 return -ENOSYS; 1994 } 1995 if (edid->version != 1 || edid->revision < 4) { 1996 debug("%s: EDID version %d.%d does not have required info\n", 1997 __func__, edid->version, edid->revision); 1998 *panel_bits_per_colourp = -1; 1999 } else { 2000 *panel_bits_per_colourp = 2001 ((edid->video_input_definition & 0x70) >> 3) + 4; 2002 } 2003 2004 return 0; 2005 } 2006 2007 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 2008 int *panel_bits_per_colourp) 2009 { 2010 struct edid1_info *edid = (struct edid1_info *)buf; 2011 bool timing_done; 2012 int i; 2013 2014 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 2015 debug("%s: Invalid buffer\n", __func__); 2016 return -EINVAL; 2017 } 2018 2019 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 2020 debug("%s: No preferred timing\n", __func__); 2021 return -ENOENT; 2022 } 2023 2024 /* Look for detailed timing */ 2025 timing_done = false; 2026 for (i = 0; i < 4; i++) { 2027 struct edid_monitor_descriptor *desc; 2028 2029 desc = &edid->monitor_details.descriptor[i]; 2030 if (desc->zero_flag_1 != 0) { 2031 decode_timing((u8 *)desc, timing); 2032 timing_done = true; 2033 break; 2034 } 2035 } 2036 if (!timing_done) 2037 return -EINVAL; 2038 2039 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 2040 debug("%s: Not a digital display\n", __func__); 2041 return -ENOSYS; 2042 } 2043 if (edid->version != 1 || edid->revision < 4) { 2044 debug("%s: EDID version %d.%d does not have required info\n", 2045 __func__, edid->version, edid->revision); 2046 *panel_bits_per_colourp = -1; 2047 } else { 2048 *panel_bits_per_colourp = 2049 ((edid->video_input_definition & 0x70) >> 3) + 4; 2050 } 2051 2052 timing->hdmi_monitor = false; 2053 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 2054 struct edid_cea861_info *info = 2055 (struct edid_cea861_info *)(buf + sizeof(*edid)); 2056 2057 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 2058 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 2059 } 2060 2061 return 0; 2062 } 2063 2064 /** 2065 * Snip the tailing whitespace/return of a string. 2066 * 2067 * @param string The string to be snipped 2068 * @return the snipped string 2069 */ 2070 static char *snip(char *string) 2071 { 2072 char *s; 2073 2074 /* 2075 * This is always a 13 character buffer 2076 * and it's not always terminated. 2077 */ 2078 string[12] = '\0'; 2079 s = &string[strlen(string) - 1]; 2080 2081 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 2082 *s == '\0')) 2083 *(s--) = '\0'; 2084 2085 return string; 2086 } 2087 2088 /** 2089 * Print an EDID monitor descriptor block 2090 * 2091 * @param monitor The EDID monitor descriptor block 2092 * @have_timing Modifies to 1 if the desciptor contains timing info 2093 */ 2094 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 2095 unsigned int *have_timing) 2096 { 2097 unsigned char *bytes = (unsigned char *)monitor; 2098 struct edid_detailed_timing *timing = 2099 (struct edid_detailed_timing *)monitor; 2100 2101 if (bytes[0] == 0 && bytes[1] == 0) { 2102 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 2103 printf("Monitor serial number: %s\n", 2104 snip(monitor->data.string)); 2105 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 2106 printf("Monitor ID: %s\n", 2107 snip(monitor->data.string)); 2108 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 2109 printf("Monitor name: %s\n", 2110 snip(monitor->data.string)); 2111 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 2112 printf("Monitor range limits, horizontal sync: " 2113 "%d-%d kHz, vertical refresh: " 2114 "%d-%d Hz, max pixel clock: " 2115 "%d MHz\n", 2116 monitor->data.range_data.horizontal_min, 2117 monitor->data.range_data.horizontal_max, 2118 monitor->data.range_data.vertical_min, 2119 monitor->data.range_data.vertical_max, 2120 monitor->data.range_data.pixel_clock_max * 10); 2121 } else { 2122 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 2123 u32 h_total, v_total, vfreq; 2124 2125 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 2126 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 2127 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 2128 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 2129 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 2130 2131 h_total = h_active + h_blanking; 2132 v_total = v_active + v_blanking; 2133 if (v_total > 0 && h_total > 0) 2134 vfreq = pixclock / (v_total * h_total); 2135 else 2136 vfreq = 1; /* Error case */ 2137 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 2138 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 2139 *have_timing = 1; 2140 } 2141 } 2142 2143 /** 2144 * Get the manufacturer name from an EDID info. 2145 * 2146 * @param edid_info The EDID info to be printed 2147 * @param name Returns the string of the manufacturer name 2148 */ 2149 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 2150 { 2151 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 2152 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 2153 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 2154 name[3] = '\0'; 2155 } 2156 2157 void edid_print_info(struct edid1_info *edid_info) 2158 { 2159 int i; 2160 char manufacturer[4]; 2161 unsigned int have_timing = 0; 2162 u32 serial_number; 2163 2164 if (edid_check_info(edid_info)) { 2165 printf("Not a valid EDID\n"); 2166 return; 2167 } 2168 2169 printf("EDID version: %d.%d\n", 2170 edid_info->version, edid_info->revision); 2171 2172 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 2173 2174 edid_get_manufacturer_name(edid_info, manufacturer); 2175 printf("Manufacturer: %s\n", manufacturer); 2176 2177 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 2178 if (serial_number != 0xffffffff) { 2179 if (strcmp(manufacturer, "MAG") == 0) 2180 serial_number -= 0x7000000; 2181 if (strcmp(manufacturer, "OQI") == 0) 2182 serial_number -= 456150000; 2183 if (strcmp(manufacturer, "VSC") == 0) 2184 serial_number -= 640000000; 2185 } 2186 printf("Serial number: %08x\n", serial_number); 2187 printf("Manufactured in week: %d year: %d\n", 2188 edid_info->week, edid_info->year + 1990); 2189 2190 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 2191 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 2192 "digital signal, " : "analog signal, ", 2193 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 2194 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 2195 ", blank to black" : "", 2196 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 2197 ", separate sync" : "", 2198 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 2199 ", composite sync" : "", 2200 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 2201 ", sync on green" : "", 2202 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 2203 ", serration v" : ""); 2204 2205 printf("Monitor is %s\n", 2206 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 2207 2208 printf("Maximum visible display size: %d cm x %d cm\n", 2209 edid_info->max_size_horizontal, 2210 edid_info->max_size_vertical); 2211 2212 printf("Power management features: %s%s, %s%s, %s%s\n", 2213 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 2214 "" : "no ", "active off", 2215 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 2216 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 2217 2218 printf("Estabilished timings:\n"); 2219 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 2220 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 2221 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 2222 printf("\t720x400\t\t88 Hz (XGA2)\n"); 2223 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 2224 printf("\t640x480\t\t60 Hz (VGA)\n"); 2225 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 2226 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 2227 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 2228 printf("\t640x480\t\t72 Hz (VESA)\n"); 2229 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 2230 printf("\t640x480\t\t75 Hz (VESA)\n"); 2231 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 2232 printf("\t800x600\t\t56 Hz (VESA)\n"); 2233 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 2234 printf("\t800x600\t\t60 Hz (VESA)\n"); 2235 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 2236 printf("\t800x600\t\t72 Hz (VESA)\n"); 2237 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 2238 printf("\t800x600\t\t75 Hz (VESA)\n"); 2239 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 2240 printf("\t832x624\t\t75 Hz (Mac II)\n"); 2241 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 2242 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 2243 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 2244 printf("\t1024x768\t60 Hz (VESA)\n"); 2245 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 2246 printf("\t1024x768\t70 Hz (VESA)\n"); 2247 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 2248 printf("\t1024x768\t75 Hz (VESA)\n"); 2249 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 2250 printf("\t1280x1024\t75 (VESA)\n"); 2251 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 2252 printf("\t1152x870\t75 (Mac II)\n"); 2253 2254 /* Standard timings. */ 2255 printf("Standard timings:\n"); 2256 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 2257 unsigned int aspect = 10000; 2258 unsigned int x, y; 2259 unsigned char xres, vfreq; 2260 2261 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 2262 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 2263 if ((xres != vfreq) || 2264 ((xres != 0) && (xres != 1)) || 2265 ((vfreq != 0) && (vfreq != 1))) { 2266 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 2267 i)) { 2268 case ASPECT_625: 2269 aspect = 6250; 2270 break; 2271 case ASPECT_75: 2272 aspect = 7500; 2273 break; 2274 case ASPECT_8: 2275 aspect = 8000; 2276 break; 2277 case ASPECT_5625: 2278 aspect = 5625; 2279 break; 2280 } 2281 x = (xres + 31) * 8; 2282 y = x * aspect / 10000; 2283 printf("\t%dx%d%c\t%d Hz\n", x, y, 2284 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 2285 have_timing = 1; 2286 } 2287 } 2288 2289 /* Detailed timing information. */ 2290 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 2291 i++) { 2292 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 2293 &have_timing); 2294 } 2295 2296 if (!have_timing) 2297 printf("\tNone\n"); 2298 } 2299 2300 /** 2301 * drm_cvt_mode -create a modeline based on the CVT algorithm 2302 * @hdisplay: hdisplay size 2303 * @vdisplay: vdisplay size 2304 * @vrefresh: vrefresh rate 2305 * @reduced: whether to use reduced blanking 2306 * @interlaced: whether to compute an interlaced mode 2307 * @margins: whether to add margins (borders) 2308 * 2309 * This function is called to generate the modeline based on CVT algorithm 2310 * according to the hdisplay, vdisplay, vrefresh. 2311 * It is based from the VESA(TM) Coordinated Video Timing Generator by 2312 * Graham Loveridge April 9, 2003 available at 2313 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 2314 * 2315 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 2316 * What I have done is to translate it by using integer calculation. 2317 * 2318 * Returns: 2319 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 2320 * The display mode object is allocated with drm_mode_create(). Returns NULL 2321 * when no mode could be allocated. 2322 */ 2323 static 2324 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 2325 bool reduced, bool interlaced, 2326 bool margins) 2327 { 2328 #define HV_FACTOR 1000 2329 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 2330 #define CVT_MARGIN_PERCENTAGE 18 2331 /* 2) character cell horizontal granularity (pixels) - default 8 */ 2332 #define CVT_H_GRANULARITY 8 2333 /* 3) Minimum vertical porch (lines) - default 3 */ 2334 #define CVT_MIN_V_PORCH 3 2335 /* 4) Minimum number of vertical back porch lines - default 6 */ 2336 #define CVT_MIN_V_BPORCH 6 2337 /* Pixel Clock step (kHz) */ 2338 #define CVT_CLOCK_STEP 250 2339 struct drm_display_mode *drm_mode; 2340 unsigned int vfieldrate, hperiod; 2341 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 2342 int interlace; 2343 2344 /* allocate the drm_display_mode structure. If failure, we will 2345 * return directly 2346 */ 2347 drm_mode = drm_mode_create(); 2348 if (!drm_mode) 2349 return NULL; 2350 2351 /* the CVT default refresh rate is 60Hz */ 2352 if (!vrefresh) 2353 vrefresh = 60; 2354 2355 /* the required field fresh rate */ 2356 if (interlaced) 2357 vfieldrate = vrefresh * 2; 2358 else 2359 vfieldrate = vrefresh; 2360 2361 /* horizontal pixels */ 2362 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 2363 2364 /* determine the left&right borders */ 2365 hmargin = 0; 2366 if (margins) { 2367 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2368 hmargin -= hmargin % CVT_H_GRANULARITY; 2369 } 2370 /* find the total active pixels */ 2371 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 2372 2373 /* find the number of lines per field */ 2374 if (interlaced) 2375 vdisplay_rnd = vdisplay / 2; 2376 else 2377 vdisplay_rnd = vdisplay; 2378 2379 /* find the top & bottom borders */ 2380 vmargin = 0; 2381 if (margins) 2382 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2383 2384 drm_mode->vdisplay = vdisplay + 2 * vmargin; 2385 2386 /* Interlaced */ 2387 if (interlaced) 2388 interlace = 1; 2389 else 2390 interlace = 0; 2391 2392 /* Determine VSync Width from aspect ratio */ 2393 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 2394 vsync = 4; 2395 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 2396 vsync = 5; 2397 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 2398 vsync = 6; 2399 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 2400 vsync = 7; 2401 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 2402 vsync = 7; 2403 else /* custom */ 2404 vsync = 10; 2405 2406 if (!reduced) { 2407 /* simplify the GTF calculation */ 2408 /* 4) Minimum time of vertical sync + back porch interval 2409 * default 550.0 2410 */ 2411 int tmp1, tmp2; 2412 #define CVT_MIN_VSYNC_BP 550 2413 /* 3) Nominal HSync width (% of line period) - default 8 */ 2414 #define CVT_HSYNC_PERCENTAGE 8 2415 unsigned int hblank_percentage; 2416 int vsyncandback_porch, hblank; 2417 2418 /* estimated the horizontal period */ 2419 tmp1 = HV_FACTOR * 1000000 - 2420 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2421 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2422 interlace; 2423 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2424 2425 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2426 /* 9. Find number of lines in sync + backporch */ 2427 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2428 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2429 else 2430 vsyncandback_porch = tmp1; 2431 /* 10. Find number of lines in back porch 2432 * vback_porch = vsyncandback_porch - vsync; 2433 */ 2434 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2435 vsyncandback_porch + CVT_MIN_V_PORCH; 2436 /* 5) Definition of Horizontal blanking time limitation */ 2437 /* Gradient (%/kHz) - default 600 */ 2438 #define CVT_M_FACTOR 600 2439 /* Offset (%) - default 40 */ 2440 #define CVT_C_FACTOR 40 2441 /* Blanking time scaling factor - default 128 */ 2442 #define CVT_K_FACTOR 128 2443 /* Scaling factor weighting - default 20 */ 2444 #define CVT_J_FACTOR 20 2445 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2446 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2447 CVT_J_FACTOR) 2448 /* 12. Find ideal blanking duty cycle from formula */ 2449 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2450 hperiod / 1000; 2451 /* 13. Blanking time */ 2452 if (hblank_percentage < 20 * HV_FACTOR) 2453 hblank_percentage = 20 * HV_FACTOR; 2454 hblank = drm_mode->hdisplay * hblank_percentage / 2455 (100 * HV_FACTOR - hblank_percentage); 2456 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2457 /* 14. find the total pixels per line */ 2458 drm_mode->htotal = drm_mode->hdisplay + hblank; 2459 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2460 drm_mode->hsync_start = drm_mode->hsync_end - 2461 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2462 drm_mode->hsync_start += CVT_H_GRANULARITY - 2463 drm_mode->hsync_start % CVT_H_GRANULARITY; 2464 /* fill the Vsync values */ 2465 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2466 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2467 } else { 2468 /* Reduced blanking */ 2469 /* Minimum vertical blanking interval time - default 460 */ 2470 #define CVT_RB_MIN_VBLANK 460 2471 /* Fixed number of clocks for horizontal sync */ 2472 #define CVT_RB_H_SYNC 32 2473 /* Fixed number of clocks for horizontal blanking */ 2474 #define CVT_RB_H_BLANK 160 2475 /* Fixed number of lines for vertical front porch - default 3*/ 2476 #define CVT_RB_VFPORCH 3 2477 int vbilines; 2478 int tmp1, tmp2; 2479 /* 8. Estimate Horizontal period. */ 2480 tmp1 = HV_FACTOR * 1000000 - 2481 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2482 tmp2 = vdisplay_rnd + 2 * vmargin; 2483 hperiod = tmp1 / (tmp2 * vfieldrate); 2484 /* 9. Find number of lines in vertical blanking */ 2485 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2486 /* 10. Check if vertical blanking is sufficient */ 2487 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2488 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2489 /* 11. Find total number of lines in vertical field */ 2490 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2491 /* 12. Find total number of pixels in a line */ 2492 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2493 /* Fill in HSync values */ 2494 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2495 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2496 /* Fill in VSync values */ 2497 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2498 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2499 } 2500 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2501 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2502 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2503 /* 18/16. Find actual vertical frame frequency */ 2504 /* ignore - just set the mode flag for interlaced */ 2505 if (interlaced) { 2506 drm_mode->vtotal *= 2; 2507 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2508 } 2509 2510 if (reduced) 2511 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2512 DRM_MODE_FLAG_NVSYNC); 2513 else 2514 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2515 DRM_MODE_FLAG_NHSYNC); 2516 2517 return drm_mode; 2518 } 2519 2520 static int 2521 cea_db_payload_len(const u8 *db) 2522 { 2523 return db[0] & 0x1f; 2524 } 2525 2526 static int 2527 cea_db_extended_tag(const u8 *db) 2528 { 2529 return db[1]; 2530 } 2531 2532 static int 2533 cea_db_tag(const u8 *db) 2534 { 2535 return db[0] >> 5; 2536 } 2537 2538 #define for_each_cea_db(cea, i, start, end) \ 2539 for ((i) = (start); (i) < (end) && (i) + \ 2540 cea_db_payload_len(&(cea)[(i)]) < \ 2541 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2542 2543 static int 2544 cea_revision(const u8 *cea) 2545 { 2546 return cea[1]; 2547 } 2548 2549 static int 2550 cea_db_offsets(const u8 *cea, int *start, int *end) 2551 { 2552 /* Data block offset in CEA extension block */ 2553 *start = 4; 2554 *end = cea[2]; 2555 if (*end == 0) 2556 *end = 127; 2557 if (*end < 4 || *end > 127) 2558 return -ERANGE; 2559 2560 /* 2561 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2562 */ 2563 if (*end != 4) { 2564 int i; 2565 2566 i = *start; 2567 while (i < (*end) && 2568 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2569 i += cea_db_payload_len(&(cea)[i]) + 1; 2570 2571 if (cea_db_payload_len(&(cea)[i]) && 2572 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2573 (*end)++; 2574 } 2575 2576 return 0; 2577 } 2578 2579 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2580 { 2581 int hdmi_id; 2582 2583 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2584 return false; 2585 2586 if (cea_db_payload_len(db) < 5) 2587 return false; 2588 2589 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2590 2591 return hdmi_id == HDMI_IEEE_OUI; 2592 } 2593 2594 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2595 { 2596 unsigned int oui; 2597 2598 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2599 return false; 2600 2601 if (cea_db_payload_len(db) < 7) 2602 return false; 2603 2604 oui = db[3] << 16 | db[2] << 8 | db[1]; 2605 2606 return oui == HDMI_FORUM_IEEE_OUI; 2607 } 2608 2609 static bool cea_db_is_y420cmdb(const u8 *db) 2610 { 2611 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2612 return false; 2613 2614 if (!cea_db_payload_len(db)) 2615 return false; 2616 2617 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2618 return false; 2619 2620 return true; 2621 } 2622 2623 static bool cea_db_is_y420vdb(const u8 *db) 2624 { 2625 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2626 return false; 2627 2628 if (!cea_db_payload_len(db)) 2629 return false; 2630 2631 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2632 return false; 2633 2634 return true; 2635 } 2636 2637 static bool drm_valid_hdmi_vic(u8 vic) 2638 { 2639 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2640 } 2641 2642 void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2643 const struct drm_display_mode *mode) 2644 { 2645 struct drm_display_mode *mode_buf = data->mode_buf; 2646 2647 if (data->modes >= MODE_LEN) 2648 return; 2649 mode_buf[(data->modes)++] = *mode; 2650 } 2651 2652 static bool drm_valid_cea_vic(u8 vic) 2653 { 2654 return cea_mode_for_vic(vic) ? true : false; 2655 } 2656 2657 static u8 svd_to_vic(u8 svd) 2658 { 2659 /* 0-6 bit vic, 7th bit native mode indicator */ 2660 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2661 return svd & 127; 2662 2663 return svd; 2664 } 2665 2666 static struct drm_display_mode * 2667 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2668 u8 video_index) 2669 { 2670 struct drm_display_mode *newmode; 2671 u8 vic; 2672 2673 if (!video_db || video_index >= video_len) 2674 return NULL; 2675 2676 /* CEA modes are numbered 1..127 */ 2677 vic = svd_to_vic(video_db[video_index]); 2678 if (!drm_valid_cea_vic(vic)) 2679 return NULL; 2680 2681 newmode = drm_mode_create(); 2682 if (!newmode) 2683 return NULL; 2684 2685 *newmode = *cea_mode_for_vic(vic); 2686 newmode->vrefresh = 0; 2687 2688 return newmode; 2689 } 2690 2691 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2692 { 2693 unsigned long *p = map + BIT_WORD(start); 2694 const unsigned int size = start + len; 2695 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2696 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2697 2698 while (len - bits_to_set >= 0) { 2699 *p |= mask_to_set; 2700 len -= bits_to_set; 2701 bits_to_set = BITS_PER_LONG; 2702 mask_to_set = ~0UL; 2703 p++; 2704 } 2705 if (len) { 2706 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2707 *p |= mask_to_set; 2708 } 2709 } 2710 2711 static void 2712 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2713 { 2714 u8 vic = svd_to_vic(svd); 2715 2716 if (!drm_valid_cea_vic(vic)) 2717 return; 2718 2719 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2720 } 2721 2722 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2723 { 2724 int i, modes = 0; 2725 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2726 2727 for (i = 0; i < len; i++) { 2728 struct drm_display_mode *mode; 2729 2730 mode = drm_display_mode_from_vic_index(db, len, i); 2731 if (mode) { 2732 /* 2733 * YCBCR420 capability block contains a bitmap which 2734 * gives the index of CEA modes from CEA VDB, which 2735 * can support YCBCR 420 sampling output also (apart 2736 * from RGB/YCBCR444 etc). 2737 * For example, if the bit 0 in bitmap is set, 2738 * first mode in VDB can support YCBCR420 output too. 2739 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2740 */ 2741 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2742 drm_add_cmdb_modes(db[i], hdmi); 2743 drm_add_hdmi_modes(data, mode); 2744 drm_mode_destroy(mode); 2745 modes++; 2746 } 2747 } 2748 2749 return modes; 2750 } 2751 2752 /* 2753 * do_y420vdb_modes - Parse YCBCR 420 only modes 2754 * @data: the structure that save parsed hdmi edid data 2755 * @svds: start of the data block of CEA YCBCR 420 VDB 2756 * @svds_len: length of the CEA YCBCR 420 VDB 2757 * @hdmi: runtime information about the connected HDMI sink 2758 * 2759 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2760 * which contains modes which can be supported in YCBCR 420 2761 * output format only. 2762 */ 2763 static int 2764 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2765 { 2766 int modes = 0, i; 2767 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2768 2769 for (i = 0; i < svds_len; i++) { 2770 u8 vic = svd_to_vic(svds[i]); 2771 2772 if (!drm_valid_cea_vic(vic)) 2773 continue; 2774 2775 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2776 drm_add_hdmi_modes(data, cea_mode_for_vic(vic)); 2777 modes++; 2778 } 2779 2780 return modes; 2781 } 2782 2783 struct stereo_mandatory_mode { 2784 int width, height, vrefresh; 2785 unsigned int flags; 2786 }; 2787 2788 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2789 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2790 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2791 { 1920, 1080, 50, 2792 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2793 { 1920, 1080, 60, 2794 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2795 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2796 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2797 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2798 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2799 }; 2800 2801 static bool 2802 stereo_match_mandatory(const struct drm_display_mode *mode, 2803 const struct stereo_mandatory_mode *stereo_mode) 2804 { 2805 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2806 2807 return mode->hdisplay == stereo_mode->width && 2808 mode->vdisplay == stereo_mode->height && 2809 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2810 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2811 } 2812 2813 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2814 { 2815 const struct drm_display_mode *mode; 2816 int num = data->modes, modes = 0, i, k; 2817 2818 for (k = 0; k < num; k++) { 2819 mode = &data->mode_buf[k]; 2820 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2821 const struct stereo_mandatory_mode *mandatory; 2822 struct drm_display_mode *new_mode; 2823 2824 if (!stereo_match_mandatory(mode, 2825 &stereo_mandatory_modes[i])) 2826 continue; 2827 2828 mandatory = &stereo_mandatory_modes[i]; 2829 new_mode = drm_mode_create(); 2830 if (!new_mode) 2831 continue; 2832 2833 *new_mode = *mode; 2834 new_mode->flags |= mandatory->flags; 2835 drm_add_hdmi_modes(data, new_mode); 2836 drm_mode_destroy(new_mode); 2837 modes++; 2838 } 2839 } 2840 2841 return modes; 2842 } 2843 2844 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2845 const u8 *video_db, u8 video_len, u8 video_index) 2846 { 2847 struct drm_display_mode *newmode; 2848 int modes = 0; 2849 2850 if (structure & (1 << 0)) { 2851 newmode = drm_display_mode_from_vic_index(video_db, 2852 video_len, 2853 video_index); 2854 if (newmode) { 2855 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2856 drm_add_hdmi_modes(data, newmode); 2857 modes++; 2858 drm_mode_destroy(newmode); 2859 } 2860 } 2861 if (structure & (1 << 6)) { 2862 newmode = drm_display_mode_from_vic_index(video_db, 2863 video_len, 2864 video_index); 2865 if (newmode) { 2866 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2867 drm_add_hdmi_modes(data, newmode); 2868 modes++; 2869 drm_mode_destroy(newmode); 2870 } 2871 } 2872 if (structure & (1 << 8)) { 2873 newmode = drm_display_mode_from_vic_index(video_db, 2874 video_len, 2875 video_index); 2876 if (newmode) { 2877 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2878 drm_add_hdmi_modes(data, newmode); 2879 modes++; 2880 drm_mode_destroy(newmode); 2881 } 2882 } 2883 2884 return modes; 2885 } 2886 2887 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2888 { 2889 if (!drm_valid_hdmi_vic(vic)) { 2890 debug("Unknown HDMI VIC: %d\n", vic); 2891 return 0; 2892 } 2893 2894 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2895 2896 return 1; 2897 } 2898 2899 /* 2900 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2901 * @db: start of the CEA vendor specific block 2902 * @len: length of the CEA block payload, ie. one can access up to db[len] 2903 * 2904 * Parses the HDMI VSDB looking for modes to add to @data. This function 2905 * also adds the stereo 3d modes when applicable. 2906 */ 2907 static int 2908 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2909 struct hdmi_edid_data *data) 2910 { 2911 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2912 u8 vic_len, hdmi_3d_len = 0; 2913 u16 mask; 2914 u16 structure_all; 2915 2916 if (len < 8) 2917 goto out; 2918 2919 /* no HDMI_Video_Present */ 2920 if (!(db[8] & (1 << 5))) 2921 goto out; 2922 2923 /* Latency_Fields_Present */ 2924 if (db[8] & (1 << 7)) 2925 offset += 2; 2926 2927 /* I_Latency_Fields_Present */ 2928 if (db[8] & (1 << 6)) 2929 offset += 2; 2930 2931 /* the declared length is not long enough for the 2 first bytes 2932 * of additional video format capabilities 2933 */ 2934 if (len < (8 + offset + 2)) 2935 goto out; 2936 2937 /* 3D_Present */ 2938 offset++; 2939 if (db[8 + offset] & (1 << 7)) { 2940 modes += add_hdmi_mandatory_stereo_modes(data); 2941 2942 /* 3D_Multi_present */ 2943 multi_present = (db[8 + offset] & 0x60) >> 5; 2944 } 2945 2946 offset++; 2947 vic_len = db[8 + offset] >> 5; 2948 hdmi_3d_len = db[8 + offset] & 0x1f; 2949 2950 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2951 u8 vic; 2952 2953 vic = db[9 + offset + i]; 2954 modes += add_hdmi_mode(data, vic); 2955 } 2956 2957 offset += 1 + vic_len; 2958 2959 if (multi_present == 1) 2960 multi_len = 2; 2961 else if (multi_present == 2) 2962 multi_len = 4; 2963 else 2964 multi_len = 0; 2965 2966 if (len < (8 + offset + hdmi_3d_len - 1)) 2967 goto out; 2968 2969 if (hdmi_3d_len < multi_len) 2970 goto out; 2971 2972 if (multi_present == 1 || multi_present == 2) { 2973 /* 3D_Structure_ALL */ 2974 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2975 2976 /* check if 3D_MASK is present */ 2977 if (multi_present == 2) 2978 mask = (db[10 + offset] << 8) | db[11 + offset]; 2979 else 2980 mask = 0xffff; 2981 2982 for (i = 0; i < 16; i++) { 2983 if (mask & (1 << i)) 2984 modes += add_3d_struct_modes(data, 2985 structure_all, 2986 video_db, 2987 video_len, i); 2988 } 2989 } 2990 2991 offset += multi_len; 2992 2993 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2994 int vic_index; 2995 struct drm_display_mode *newmode = NULL; 2996 unsigned int newflag = 0; 2997 bool detail_present; 2998 2999 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3000 3001 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3002 break; 3003 3004 /* 2D_VIC_order_X */ 3005 vic_index = db[8 + offset + i] >> 4; 3006 3007 /* 3D_Structure_X */ 3008 switch (db[8 + offset + i] & 0x0f) { 3009 case 0: 3010 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3011 break; 3012 case 6: 3013 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3014 break; 3015 case 8: 3016 /* 3D_Detail_X */ 3017 if ((db[9 + offset + i] >> 4) == 1) 3018 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3019 break; 3020 } 3021 3022 if (newflag != 0) { 3023 newmode = drm_display_mode_from_vic_index( 3024 video_db, 3025 video_len, 3026 vic_index); 3027 3028 if (newmode) { 3029 newmode->flags |= newflag; 3030 drm_add_hdmi_modes(data, newmode); 3031 modes++; 3032 drm_mode_destroy(newmode); 3033 } 3034 } 3035 3036 if (detail_present) 3037 i++; 3038 } 3039 3040 out: 3041 return modes; 3042 } 3043 3044 /** 3045 * edid_get_quirks - return quirk flags for a given EDID 3046 * @edid: EDID to process 3047 * 3048 * This tells subsequent routines what fixes they need to apply. 3049 */ 3050 static u32 edid_get_quirks(struct edid *edid) 3051 { 3052 struct edid_quirk *quirk; 3053 int i; 3054 3055 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 3056 quirk = &edid_quirk_list[i]; 3057 3058 if (edid_vendor(edid, quirk->vendor) && 3059 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 3060 return quirk->quirks; 3061 } 3062 3063 return 0; 3064 } 3065 3066 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 3067 const u8 *db) 3068 { 3069 struct drm_display_info *info = &data->display_info; 3070 struct drm_hdmi_info *hdmi = &info->hdmi; 3071 u8 map_len = cea_db_payload_len(db) - 1; 3072 u8 count; 3073 u64 map = 0; 3074 3075 if (map_len == 0) { 3076 /* All CEA modes support ycbcr420 sampling also.*/ 3077 hdmi->y420_cmdb_map = U64_MAX; 3078 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3079 return; 3080 } 3081 3082 /* 3083 * This map indicates which of the existing CEA block modes 3084 * from VDB can support YCBCR420 output too. So if bit=0 is 3085 * set, first mode from VDB can support YCBCR420 output too. 3086 * We will parse and keep this map, before parsing VDB itself 3087 * to avoid going through the same block again and again. 3088 * 3089 * Spec is not clear about max possible size of this block. 3090 * Clamping max bitmap block size at 8 bytes. Every byte can 3091 * address 8 CEA modes, in this way this map can address 3092 * 8*8 = first 64 SVDs. 3093 */ 3094 if (map_len > 8) 3095 map_len = 8; 3096 3097 for (count = 0; count < map_len; count++) 3098 map |= (u64)db[2 + count] << (8 * count); 3099 3100 if (map) 3101 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3102 3103 hdmi->y420_cmdb_map = map; 3104 } 3105 3106 static 3107 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 3108 { 3109 switch (max_frl_rate) { 3110 case 1: 3111 *max_lanes = 3; 3112 *max_rate_per_lane = 3; 3113 break; 3114 case 2: 3115 *max_lanes = 3; 3116 *max_rate_per_lane = 6; 3117 break; 3118 case 3: 3119 *max_lanes = 4; 3120 *max_rate_per_lane = 6; 3121 break; 3122 case 4: 3123 *max_lanes = 4; 3124 *max_rate_per_lane = 8; 3125 break; 3126 case 5: 3127 *max_lanes = 4; 3128 *max_rate_per_lane = 10; 3129 break; 3130 case 6: 3131 *max_lanes = 4; 3132 *max_rate_per_lane = 12; 3133 break; 3134 case 0: 3135 default: 3136 *max_lanes = 0; 3137 *max_rate_per_lane = 0; 3138 } 3139 } 3140 3141 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 3142 const u8 *db) 3143 { 3144 u8 dc_mask; 3145 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 3146 3147 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 3148 hdmi->y420_dc_modes |= dc_mask; 3149 } 3150 3151 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 3152 const u8 *hf_vsdb) 3153 { 3154 struct drm_display_info *display = &data->display_info; 3155 struct drm_hdmi_info *hdmi = &display->hdmi; 3156 3157 if (hf_vsdb[6] & 0x80) { 3158 hdmi->scdc.supported = true; 3159 if (hf_vsdb[6] & 0x40) 3160 hdmi->scdc.read_request = true; 3161 } 3162 3163 /* 3164 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 3165 * And as per the spec, three factors confirm this: 3166 * * Availability of a HF-VSDB block in EDID (check) 3167 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 3168 * * SCDC support available (let's check) 3169 * Lets check it out. 3170 */ 3171 3172 if (hf_vsdb[5]) { 3173 /* max clock is 5000 KHz times block value */ 3174 u32 max_tmds_clock = hf_vsdb[5] * 5000; 3175 struct drm_scdc *scdc = &hdmi->scdc; 3176 3177 if (max_tmds_clock > 340000) { 3178 display->max_tmds_clock = max_tmds_clock; 3179 debug("HF-VSDB: max TMDS clock %d kHz\n", 3180 display->max_tmds_clock); 3181 } 3182 3183 if (scdc->supported) { 3184 scdc->scrambling.supported = true; 3185 3186 /* Few sinks support scrambling for cloks < 340M */ 3187 if ((hf_vsdb[6] & 0x8)) 3188 scdc->scrambling.low_rates = true; 3189 } 3190 } 3191 3192 if (hf_vsdb[7]) { 3193 u8 max_frl_rate; 3194 u8 dsc_max_frl_rate; 3195 u8 dsc_max_slices; 3196 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 3197 3198 debug("hdmi_21 sink detected. parsing edid\n"); 3199 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 3200 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 3201 &hdmi->max_frl_rate_per_lane); 3202 hdmi->add_func = hf_vsdb[8]; 3203 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 3204 3205 if (hdmi_dsc->v_1p2) { 3206 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 3207 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 3208 3209 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 3210 hdmi_dsc->bpc_supported = 16; 3211 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 3212 hdmi_dsc->bpc_supported = 12; 3213 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 3214 hdmi_dsc->bpc_supported = 10; 3215 else 3216 hdmi_dsc->bpc_supported = 0; 3217 3218 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 3219 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 3220 &hdmi_dsc->max_frl_rate_per_lane); 3221 hdmi_dsc->total_chunk_kbytes = 3222 hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 3223 3224 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 3225 switch (dsc_max_slices) { 3226 case 1: 3227 hdmi_dsc->max_slices = 1; 3228 hdmi_dsc->clk_per_slice = 340; 3229 break; 3230 case 2: 3231 hdmi_dsc->max_slices = 2; 3232 hdmi_dsc->clk_per_slice = 340; 3233 break; 3234 case 3: 3235 hdmi_dsc->max_slices = 4; 3236 hdmi_dsc->clk_per_slice = 340; 3237 break; 3238 case 4: 3239 hdmi_dsc->max_slices = 8; 3240 hdmi_dsc->clk_per_slice = 340; 3241 break; 3242 case 5: 3243 hdmi_dsc->max_slices = 8; 3244 hdmi_dsc->clk_per_slice = 400; 3245 break; 3246 case 6: 3247 hdmi_dsc->max_slices = 12; 3248 hdmi_dsc->clk_per_slice = 400; 3249 break; 3250 case 7: 3251 hdmi_dsc->max_slices = 16; 3252 hdmi_dsc->clk_per_slice = 400; 3253 break; 3254 case 0: 3255 default: 3256 hdmi_dsc->max_slices = 0; 3257 hdmi_dsc->clk_per_slice = 0; 3258 } 3259 } 3260 } 3261 3262 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 3263 } 3264 3265 /** 3266 * drm_default_rgb_quant_range - default RGB quantization range 3267 * @mode: display mode 3268 * 3269 * Determine the default RGB quantization range for the mode, 3270 * as specified in CEA-861. 3271 * 3272 * Return: The default RGB quantization range for the mode 3273 */ 3274 enum hdmi_quantization_range 3275 drm_default_rgb_quant_range(struct drm_display_mode *mode) 3276 { 3277 /* All CEA modes other than VIC 1 use limited quantization range. */ 3278 return drm_match_cea_mode(mode) > 1 ? 3279 HDMI_QUANTIZATION_RANGE_LIMITED : 3280 HDMI_QUANTIZATION_RANGE_FULL; 3281 } 3282 3283 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 3284 const u8 *hdmi) 3285 { 3286 struct drm_display_info *info = &data->display_info; 3287 unsigned int dc_bpc = 0; 3288 3289 /* HDMI supports at least 8 bpc */ 3290 info->bpc = 8; 3291 3292 if (cea_db_payload_len(hdmi) < 6) 3293 return; 3294 3295 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3296 dc_bpc = 10; 3297 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3298 debug("HDMI sink does deep color 30.\n"); 3299 } 3300 3301 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3302 dc_bpc = 12; 3303 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3304 debug("HDMI sink does deep color 36.\n"); 3305 } 3306 3307 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3308 dc_bpc = 16; 3309 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3310 debug("HDMI sink does deep color 48.\n"); 3311 } 3312 3313 if (dc_bpc == 0) { 3314 debug("No deep color support on this HDMI sink.\n"); 3315 return; 3316 } 3317 3318 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 3319 info->bpc = dc_bpc; 3320 3321 /* YCRCB444 is optional according to spec. */ 3322 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3323 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 3324 debug("HDMI sink does YCRCB444 in deep color.\n"); 3325 } 3326 3327 /* 3328 * Spec says that if any deep color mode is supported at all, 3329 * then deep color 36 bit must be supported. 3330 */ 3331 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 3332 debug("HDMI sink should do DC_36, but does not!\n"); 3333 } 3334 3335 /* 3336 * References: 3337 * - CTA-861-H section 7.3.3 CTA Extension Version 3 3338 */ 3339 static int cea_db_collection_size(const u8 *cta) 3340 { 3341 u8 d = cta[2]; 3342 3343 if (d < 4 || d > 127) 3344 return 0; 3345 3346 return d - 4; 3347 } 3348 3349 #define CTA_EXT_DB_HF_EEODB 0x78 3350 #define CTA_DB_EXTENDED_TAG 7 3351 3352 static int cea_db_tag(const u8 *db); 3353 static int cea_db_payload_len(const u8 *db); 3354 static int cea_db_extended_tag(const u8 *db); 3355 3356 static bool cea_db_is_extended_tag(const void *db, int tag) 3357 { 3358 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 3359 cea_db_payload_len(db) >= 1 && 3360 cea_db_extended_tag(db) == tag; 3361 } 3362 3363 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 3364 { 3365 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 3366 cea_db_payload_len(db) >= 2; 3367 } 3368 3369 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 3370 { 3371 const u8 *cta; 3372 3373 /* No extensions according to base block, no HF-EEODB. */ 3374 if (!edid->extensions) 3375 return 0; 3376 3377 /* HF-EEODB is always in the first EDID extension block only */ 3378 cta = (u8 *)edid + HDMI_EDID_BLOCK_SIZE * 1; 3379 if (cta[0] != CEA_EXT || cta[1] < 3) 3380 return 0; 3381 3382 /* Need to have the data block collection, and at least 3 bytes. */ 3383 if (cea_db_collection_size(cta) < 3) 3384 return 0; 3385 3386 /* 3387 * Sinks that include the HF-EEODB in their E-EDID shall include one and 3388 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 3389 * through 6 of Block 1 of the E-EDID. 3390 */ 3391 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 3392 return 0; 3393 3394 return cta[4 + 2]; 3395 } 3396 3397 static int edid_hfeeodb_block_count(const struct edid *edid) 3398 { 3399 int eeodb = edid_hfeeodb_extension_block_count(edid); 3400 3401 return eeodb ? eeodb + 1 : 0; 3402 } 3403 3404 /* 3405 * Search EDID for CEA extension block. 3406 */ 3407 static u8 *drm_find_edid_extension(const struct edid *edid, 3408 int ext_id) 3409 { 3410 u8 *edid_ext = NULL; 3411 int i; 3412 int len; 3413 3414 /* No EDID or EDID extensions */ 3415 if (edid == NULL || edid->extensions == 0) 3416 return NULL; 3417 3418 if (edid_hfeeodb_extension_block_count(edid)) 3419 len = edid_hfeeodb_extension_block_count(edid); 3420 else 3421 len = edid->extensions; 3422 3423 /* Find CEA extension */ 3424 for (i = 0; i < len; i++) { 3425 edid_ext = (u8 *)edid + HDMI_EDID_BLOCK_SIZE * (i + 1); 3426 if (edid_ext[0] == ext_id) 3427 break; 3428 } 3429 3430 if (i >= len) 3431 return NULL; 3432 3433 return edid_ext; 3434 } 3435 3436 static u8 *drm_find_cea_extension(struct edid *edid) 3437 { 3438 return drm_find_edid_extension(edid, 0x02); 3439 } 3440 3441 #define AUDIO_BLOCK 0x01 3442 #define VIDEO_BLOCK 0x02 3443 #define VENDOR_BLOCK 0x03 3444 #define SPEAKER_BLOCK 0x04 3445 #define EDID_BASIC_AUDIO BIT(6) 3446 3447 /** 3448 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3449 * @edid: monitor EDID information 3450 * 3451 * Parse the CEA extension according to CEA-861-B. 3452 * 3453 * Return: True if the monitor is HDMI, false if not or unknown. 3454 */ 3455 bool drm_detect_hdmi_monitor(struct edid *edid) 3456 { 3457 u8 *edid_ext; 3458 int i; 3459 int start_offset, end_offset; 3460 3461 edid_ext = drm_find_cea_extension(edid); 3462 if (!edid_ext) 3463 return false; 3464 3465 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3466 return false; 3467 3468 /* 3469 * Because HDMI identifier is in Vendor Specific Block, 3470 * search it from all data blocks of CEA extension. 3471 */ 3472 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3473 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3474 return true; 3475 } 3476 3477 return false; 3478 } 3479 3480 /** 3481 * drm_detect_monitor_audio - check monitor audio capability 3482 * @edid: EDID block to scan 3483 * 3484 * Monitor should have CEA extension block. 3485 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3486 * audio' only. If there is any audio extension block and supported 3487 * audio format, assume at least 'basic audio' support, even if 'basic 3488 * audio' is not defined in EDID. 3489 * 3490 * Return: True if the monitor supports audio, false otherwise. 3491 */ 3492 bool drm_detect_monitor_audio(struct edid *edid) 3493 { 3494 u8 *edid_ext; 3495 int i, j; 3496 bool has_audio = false; 3497 int start_offset, end_offset; 3498 3499 edid_ext = drm_find_cea_extension(edid); 3500 if (!edid_ext) 3501 goto end; 3502 3503 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3504 3505 if (has_audio) { 3506 printf("Monitor has basic audio support\n"); 3507 goto end; 3508 } 3509 3510 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3511 goto end; 3512 3513 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3514 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3515 has_audio = true; 3516 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 3517 j += 3) 3518 debug("CEA audio format %d\n", 3519 (edid_ext[i + j] >> 3) & 0xf); 3520 goto end; 3521 } 3522 } 3523 end: 3524 return has_audio; 3525 } 3526 3527 static void 3528 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 3529 { 3530 struct drm_display_info *info = &data->display_info; 3531 u8 len = cea_db_payload_len(db); 3532 3533 if (len >= 6) 3534 info->dvi_dual = db[6] & 1; 3535 if (len >= 7) 3536 info->max_tmds_clock = db[7] * 5000; 3537 3538 drm_parse_hdmi_deep_color_info(data, db); 3539 } 3540 3541 #define USE_EXTENDED_TAG 0x07 3542 #define CTA_EXT_DB_HF_SCDB 0x000079 3543 3544 static bool cea_db_is_scdb(const u8 *db) 3545 { 3546 unsigned int oui; 3547 3548 if (cea_db_tag(db) != USE_EXTENDED_TAG) 3549 return false; 3550 3551 if (cea_db_payload_len(db) < 7) 3552 return false; 3553 3554 oui = db[3] << 16 | db[2] << 8 | db[1]; 3555 3556 return oui == CTA_EXT_DB_HF_SCDB; 3557 } 3558 3559 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 3560 struct edid *edid) 3561 { 3562 struct drm_display_info *info = &data->display_info; 3563 const u8 *edid_ext; 3564 int i, start, end; 3565 3566 edid_ext = drm_find_cea_extension(edid); 3567 if (!edid_ext) 3568 return; 3569 3570 info->cea_rev = edid_ext[1]; 3571 3572 /* The existence of a CEA block should imply RGB support */ 3573 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3574 if (edid_ext[3] & EDID_CEA_YCRCB444) 3575 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3576 if (edid_ext[3] & EDID_CEA_YCRCB422) 3577 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3578 3579 if (cea_db_offsets(edid_ext, &start, &end)) 3580 return; 3581 3582 for_each_cea_db(edid_ext, i, start, end) { 3583 const u8 *db = &edid_ext[i]; 3584 3585 if (cea_db_is_hdmi_vsdb(db)) 3586 drm_parse_hdmi_vsdb_video(data, db); 3587 if (cea_db_is_hdmi_forum_vsdb(db) || cea_db_is_scdb(db)) 3588 drm_parse_hdmi_forum_vsdb(data, db); 3589 if (cea_db_is_y420cmdb(db)) 3590 drm_parse_y420cmdb_bitmap(data, db); 3591 } 3592 } 3593 3594 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 3595 { 3596 struct drm_display_info *info = &data->display_info; 3597 3598 info->width_mm = edid->width_cm * 10; 3599 info->height_mm = edid->height_cm * 10; 3600 3601 /* driver figures it out in this case */ 3602 info->bpc = 0; 3603 info->color_formats = 0; 3604 info->cea_rev = 0; 3605 info->max_tmds_clock = 0; 3606 info->dvi_dual = false; 3607 info->edid_hdmi_dc_modes = 0; 3608 3609 memset(&info->hdmi, 0, sizeof(info->hdmi)); 3610 3611 if (edid->revision < 3) 3612 return; 3613 3614 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3615 return; 3616 3617 drm_parse_cea_ext(data, edid); 3618 3619 /* 3620 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3621 * 3622 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3623 * tells us to assume 8 bpc color depth if the EDID doesn't have 3624 * extensions which tell otherwise. 3625 */ 3626 if ((info->bpc == 0) && (edid->revision < 4) && 3627 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3628 info->bpc = 8; 3629 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3630 } 3631 3632 /* Only defined for 1.4 with digital displays */ 3633 if (edid->revision < 4) 3634 return; 3635 3636 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3637 case DRM_EDID_DIGITAL_DEPTH_6: 3638 info->bpc = 6; 3639 break; 3640 case DRM_EDID_DIGITAL_DEPTH_8: 3641 info->bpc = 8; 3642 break; 3643 case DRM_EDID_DIGITAL_DEPTH_10: 3644 info->bpc = 10; 3645 break; 3646 case DRM_EDID_DIGITAL_DEPTH_12: 3647 info->bpc = 12; 3648 break; 3649 case DRM_EDID_DIGITAL_DEPTH_14: 3650 info->bpc = 14; 3651 break; 3652 case DRM_EDID_DIGITAL_DEPTH_16: 3653 info->bpc = 16; 3654 break; 3655 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3656 default: 3657 info->bpc = 0; 3658 break; 3659 } 3660 3661 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3662 info->bpc); 3663 3664 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3665 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3666 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3667 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3668 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3669 } 3670 3671 /* 3672 * Search EDID for CEA extension block. 3673 */ 3674 static u8 *drm_find_edid_extension_from_index(const struct edid *edid, 3675 int ext_id, int *ext_index) 3676 { 3677 u8 *edid_ext = NULL; 3678 int i; 3679 int len; 3680 3681 /* No EDID or EDID extensions */ 3682 if (edid == NULL || edid->extensions == 0) 3683 return NULL; 3684 3685 if (edid_hfeeodb_extension_block_count(edid)) 3686 len = edid_hfeeodb_extension_block_count(edid); 3687 else 3688 len = edid->extensions; 3689 3690 /* Find CEA extension */ 3691 for (i = *ext_index; i < len; i++) { 3692 edid_ext = (u8 *)edid + HDMI_EDID_BLOCK_SIZE * (i + 1); 3693 if (edid_ext[0] == ext_id) 3694 break; 3695 } 3696 3697 if (i >= len) 3698 return NULL; 3699 3700 *ext_index = i + 1; 3701 3702 return edid_ext; 3703 } 3704 3705 static 3706 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3707 { 3708 const u8 *cea; 3709 const u8 *db, *hdmi = NULL, *video = NULL; 3710 u8 dbl, hdmi_len, video_len = 0; 3711 int i, count = 0, modes = 0; 3712 int ext_index = 0; 3713 3714 if (edid_hfeeodb_extension_block_count(edid)) 3715 count = edid_hfeeodb_extension_block_count(edid); 3716 else 3717 count = edid->extensions; 3718 3719 for (i = 0; i < count; i++) { 3720 ext_index = i; 3721 cea = drm_find_edid_extension_from_index(edid, CEA_EXT, &ext_index); 3722 if (cea && cea_revision(cea) >= 3) { 3723 int i, start, end; 3724 3725 if (cea_db_offsets(cea, &start, &end)) 3726 return 0; 3727 3728 for_each_cea_db(cea, i, start, end) { 3729 db = &cea[i]; 3730 dbl = cea_db_payload_len(db); 3731 3732 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3733 video = db + 1; 3734 video_len = dbl; 3735 modes += do_cea_modes(data, video, dbl); 3736 } else if (cea_db_is_hdmi_vsdb(db)) { 3737 hdmi = db; 3738 hdmi_len = dbl; 3739 } else if (cea_db_is_y420vdb(db)) { 3740 const u8 *vdb420 = &db[2]; 3741 3742 /* Add 4:2:0(only) modes present in EDID */ 3743 modes += do_y420vdb_modes(data, vdb420, 3744 dbl - 1); 3745 } 3746 } 3747 } 3748 3749 /* 3750 * We parse the HDMI VSDB after having added the cea modes as we will 3751 * be patching their flags when the sink supports stereo 3D. 3752 */ 3753 if (hdmi) 3754 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3755 video_len, data); 3756 } 3757 return modes; 3758 } 3759 3760 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3761 3762 static void 3763 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3764 { 3765 int i, n = 0; 3766 u8 d = ext[0x02]; 3767 u8 *det_base = ext + d; 3768 3769 if (d < 4 || d > 127) 3770 return; 3771 3772 n = (127 - d) / 18; 3773 for (i = 0; i < n; i++) 3774 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3775 } 3776 3777 static void 3778 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3779 { 3780 unsigned int i, n = min((int)ext[0x02], 6); 3781 u8 *det_base = ext + 5; 3782 3783 if (ext[0x01] != 1) 3784 return; /* unknown version */ 3785 3786 for (i = 0; i < n; i++) 3787 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3788 } 3789 3790 static void 3791 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3792 { 3793 int i; 3794 struct edid *edid = (struct edid *)raw_edid; 3795 3796 if (!edid) 3797 return; 3798 3799 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3800 cb(&edid->detailed_timings[i], closure); 3801 3802 for (i = 1; i <= raw_edid[0x7e]; i++) { 3803 u8 *ext = raw_edid + (i * EDID_SIZE); 3804 3805 switch (*ext) { 3806 case CEA_EXT: 3807 cea_for_each_detailed_block(ext, cb, closure); 3808 break; 3809 case VTB_EXT: 3810 vtb_for_each_detailed_block(ext, cb, closure); 3811 break; 3812 default: 3813 break; 3814 } 3815 } 3816 } 3817 3818 /* 3819 * EDID is delightfully ambiguous about how interlaced modes are to be 3820 * encoded. Our internal representation is of frame height, but some 3821 * HDTV detailed timings are encoded as field height. 3822 * 3823 * The format list here is from CEA, in frame size. Technically we 3824 * should be checking refresh rate too. Whatever. 3825 */ 3826 static void 3827 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3828 struct detailed_pixel_timing *pt) 3829 { 3830 int i; 3831 3832 static const struct { 3833 int w, h; 3834 } cea_interlaced[] = { 3835 { 1920, 1080 }, 3836 { 720, 480 }, 3837 { 1440, 480 }, 3838 { 2880, 480 }, 3839 { 720, 576 }, 3840 { 1440, 576 }, 3841 { 2880, 576 }, 3842 }; 3843 3844 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3845 return; 3846 3847 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3848 if ((mode->hdisplay == cea_interlaced[i].w) && 3849 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3850 mode->vdisplay *= 2; 3851 mode->vsync_start *= 2; 3852 mode->vsync_end *= 2; 3853 mode->vtotal *= 2; 3854 mode->vtotal |= 1; 3855 } 3856 } 3857 3858 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3859 } 3860 3861 /** 3862 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3863 * @edid: EDID block 3864 * @timing: EDID detailed timing info 3865 * @quirks: quirks to apply 3866 * 3867 * An EDID detailed timing block contains enough info for us to create and 3868 * return a new struct drm_display_mode. 3869 */ 3870 static 3871 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3872 struct detailed_timing *timing, 3873 u32 quirks) 3874 { 3875 struct drm_display_mode *mode; 3876 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3877 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3878 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3879 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3880 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3881 unsigned hsync_offset = 3882 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3883 pt->hsync_offset_lo; 3884 unsigned hsync_pulse_width = 3885 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3886 pt->hsync_pulse_width_lo; 3887 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3888 2 | pt->vsync_offset_pulse_width_lo >> 4; 3889 unsigned vsync_pulse_width = 3890 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3891 (pt->vsync_offset_pulse_width_lo & 0xf); 3892 3893 /* ignore tiny modes */ 3894 if (hactive < 64 || vactive < 64) 3895 return NULL; 3896 3897 if (pt->misc & DRM_EDID_PT_STEREO) { 3898 debug("stereo mode not supported\n"); 3899 return NULL; 3900 } 3901 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3902 debug("composite sync not supported\n"); 3903 3904 /* it is incorrect if hsync/vsync width is zero */ 3905 if (!hsync_pulse_width || !vsync_pulse_width) { 3906 debug("Incorrect Detailed timing. "); 3907 debug("Wrong Hsync/Vsync pulse width\n"); 3908 return NULL; 3909 } 3910 3911 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3912 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3913 if (!mode) 3914 return NULL; 3915 3916 goto set_refresh; 3917 } 3918 3919 mode = drm_mode_create(); 3920 if (!mode) 3921 return NULL; 3922 3923 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3924 timing->pixel_clock = cpu_to_le16(1088); 3925 3926 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3927 3928 mode->hdisplay = hactive; 3929 mode->hsync_start = mode->hdisplay + hsync_offset; 3930 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3931 mode->htotal = mode->hdisplay + hblank; 3932 3933 mode->vdisplay = vactive; 3934 mode->vsync_start = mode->vdisplay + vsync_offset; 3935 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3936 mode->vtotal = mode->vdisplay + vblank; 3937 3938 /* Some EDIDs have bogus h/vtotal values */ 3939 if (mode->hsync_end > mode->htotal) 3940 mode->htotal = mode->hsync_end + 1; 3941 if (mode->vsync_end > mode->vtotal) 3942 mode->vtotal = mode->vsync_end + 1; 3943 3944 drm_mode_do_interlace_quirk(mode, pt); 3945 3946 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3947 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3948 DRM_EDID_PT_VSYNC_POSITIVE; 3949 3950 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3951 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3952 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3953 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3954 3955 set_refresh: 3956 3957 mode->type = DRM_MODE_TYPE_DRIVER; 3958 mode->vrefresh = drm_get_vrefresh(mode); 3959 3960 return mode; 3961 } 3962 3963 /* 3964 * Calculate the alternate clock for the CEA mode 3965 * (60Hz vs. 59.94Hz etc.) 3966 */ 3967 static unsigned int 3968 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3969 { 3970 unsigned int clock = cea_mode->clock; 3971 3972 if (cea_mode->vrefresh % 6 != 0) 3973 return clock; 3974 3975 /* 3976 * edid_cea_modes contains the 59.94Hz 3977 * variant for 240 and 480 line modes, 3978 * and the 60Hz variant otherwise. 3979 */ 3980 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3981 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3982 else 3983 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3984 3985 return clock; 3986 } 3987 3988 /** 3989 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3990 * @mode1: first mode 3991 * @mode2: second mode 3992 * 3993 * Check to see if @mode1 and @mode2 are equivalent, but 3994 * don't check the pixel clocks nor the stereo layout. 3995 * 3996 * Returns: 3997 * True if the modes are equal, false otherwise. 3998 */ 3999 4000 static 4001 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 4002 const struct drm_display_mode *mode2) 4003 { 4004 unsigned int flags_mask = 4005 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 4006 4007 if (mode1->hdisplay == mode2->hdisplay && 4008 mode1->hsync_start == mode2->hsync_start && 4009 mode1->hsync_end == mode2->hsync_end && 4010 mode1->htotal == mode2->htotal && 4011 mode1->vdisplay == mode2->vdisplay && 4012 mode1->vsync_start == mode2->vsync_start && 4013 mode1->vsync_end == mode2->vsync_end && 4014 mode1->vtotal == mode2->vtotal && 4015 mode1->vscan == mode2->vscan && 4016 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 4017 return true; 4018 4019 return false; 4020 } 4021 4022 /** 4023 * drm_mode_equal_no_clocks - test modes for equality 4024 * @mode1: first mode 4025 * @mode2: second mode 4026 * 4027 * Check to see if @mode1 and @mode2 are equivalent, but 4028 * don't check the pixel clocks. 4029 * 4030 * Returns: 4031 * True if the modes are equal, false otherwise. 4032 */ 4033 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 4034 const struct drm_display_mode *mode2) 4035 { 4036 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 4037 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 4038 return false; 4039 4040 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 4041 } 4042 4043 static 4044 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4045 unsigned int clock_tolerance) 4046 { 4047 u8 vic; 4048 4049 if (!to_match->clock) 4050 return 0; 4051 4052 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4053 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 4054 unsigned int clock1, clock2; 4055 4056 /* Check both 60Hz and 59.94Hz */ 4057 clock1 = cea_mode->clock; 4058 clock2 = cea_mode_alternate_clock(cea_mode); 4059 4060 if (abs(to_match->clock - clock1) > clock_tolerance && 4061 abs(to_match->clock - clock2) > clock_tolerance) 4062 continue; 4063 4064 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 4065 return vic; 4066 } 4067 4068 return 0; 4069 } 4070 4071 static unsigned int 4072 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4073 { 4074 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 4075 return hdmi_mode->clock; 4076 4077 return cea_mode_alternate_clock(hdmi_mode); 4078 } 4079 4080 static 4081 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4082 unsigned int clock_tolerance) 4083 { 4084 u8 vic; 4085 4086 if (!to_match->clock) 4087 return 0; 4088 4089 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4090 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4091 unsigned int clock1, clock2; 4092 4093 /* Make sure to also match alternate clocks */ 4094 clock1 = hdmi_mode->clock; 4095 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4096 4097 if (abs(to_match->clock - clock1) > clock_tolerance && 4098 abs(to_match->clock - clock2) > clock_tolerance) 4099 continue; 4100 4101 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 4102 return vic; 4103 } 4104 4105 return 0; 4106 } 4107 4108 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4109 { 4110 const struct drm_display_mode *cea_mode; 4111 int clock1, clock2, clock; 4112 u8 vic; 4113 const char *type; 4114 4115 /* 4116 * allow 5kHz clock difference either way to account for 4117 * the 10kHz clock resolution limit of detailed timings. 4118 */ 4119 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4120 if (drm_valid_cea_vic(vic)) { 4121 type = "CEA"; 4122 cea_mode = cea_mode_for_vic(vic); 4123 clock1 = cea_mode->clock; 4124 clock2 = cea_mode_alternate_clock(cea_mode); 4125 } else { 4126 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4127 if (drm_valid_hdmi_vic(vic)) { 4128 type = "HDMI"; 4129 cea_mode = &edid_4k_modes[vic]; 4130 clock1 = cea_mode->clock; 4131 clock2 = hdmi_mode_alternate_clock(cea_mode); 4132 } else { 4133 return; 4134 } 4135 } 4136 4137 /* pick whichever is closest */ 4138 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4139 clock = clock1; 4140 else 4141 clock = clock2; 4142 4143 if (mode->clock == clock) 4144 return; 4145 4146 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4147 type, vic, mode->clock, clock); 4148 mode->clock = clock; 4149 } 4150 4151 static void 4152 do_detailed_mode(struct detailed_timing *timing, void *c) 4153 { 4154 struct detailed_mode_closure *closure = c; 4155 struct drm_display_mode *newmode; 4156 4157 if (timing->pixel_clock) { 4158 newmode = drm_mode_detailed( 4159 closure->edid, timing, 4160 closure->quirks); 4161 if (!newmode) 4162 return; 4163 4164 if (closure->preferred) 4165 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4166 4167 /* 4168 * Detailed modes are limited to 10kHz pixel clock resolution, 4169 * so fix up anything that looks like CEA/HDMI mode, 4170 * but the clock is just slightly off. 4171 */ 4172 fixup_detailed_cea_mode_clock(newmode); 4173 drm_add_hdmi_modes(closure->data, newmode); 4174 drm_mode_destroy(newmode); 4175 closure->modes++; 4176 closure->preferred = 0; 4177 } 4178 } 4179 4180 /* 4181 * add_detailed_modes - Add modes from detailed timings 4182 * @data: attached data 4183 * @edid: EDID block to scan 4184 * @quirks: quirks to apply 4185 */ 4186 static int 4187 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 4188 u32 quirks) 4189 { 4190 struct detailed_mode_closure closure = { 4191 .data = data, 4192 .edid = edid, 4193 .preferred = 1, 4194 .quirks = quirks, 4195 }; 4196 4197 if (closure.preferred && !version_greater(edid, 1, 3)) 4198 closure.preferred = 4199 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 4200 4201 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 4202 4203 return closure.modes; 4204 } 4205 4206 static int drm_cvt_modes(struct hdmi_edid_data *data, 4207 struct detailed_timing *timing) 4208 { 4209 int i, j, modes = 0; 4210 struct drm_display_mode *newmode; 4211 struct cvt_timing *cvt; 4212 const int rates[] = { 60, 85, 75, 60, 50 }; 4213 const u8 empty[3] = { 0, 0, 0 }; 4214 4215 for (i = 0; i < 4; i++) { 4216 int uninitialized_var(width), height; 4217 4218 cvt = &timing->data.other_data.data.cvt[i]; 4219 4220 if (!memcmp(cvt->code, empty, 3)) 4221 continue; 4222 4223 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4224 switch (cvt->code[1] & 0x0c) { 4225 case 0x00: 4226 width = height * 4 / 3; 4227 break; 4228 case 0x04: 4229 width = height * 16 / 9; 4230 break; 4231 case 0x08: 4232 width = height * 16 / 10; 4233 break; 4234 case 0x0c: 4235 width = height * 15 / 9; 4236 break; 4237 } 4238 4239 for (j = 1; j < 5; j++) { 4240 if (cvt->code[2] & (1 << j)) { 4241 newmode = drm_cvt_mode(width, height, 4242 rates[j], j == 0, 4243 false, false); 4244 if (newmode) { 4245 drm_add_hdmi_modes(data, newmode); 4246 modes++; 4247 drm_mode_destroy(newmode); 4248 } 4249 } 4250 } 4251 } 4252 4253 return modes; 4254 } 4255 4256 static void 4257 do_cvt_mode(struct detailed_timing *timing, void *c) 4258 { 4259 struct detailed_mode_closure *closure = c; 4260 struct detailed_non_pixel *data = &timing->data.other_data; 4261 4262 if (data->type == EDID_DETAIL_CVT_3BYTE) 4263 closure->modes += drm_cvt_modes(closure->data, timing); 4264 } 4265 4266 static int 4267 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 4268 { 4269 struct detailed_mode_closure closure = { 4270 .data = data, 4271 .edid = edid, 4272 }; 4273 4274 if (version_greater(edid, 1, 2)) 4275 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 4276 4277 /* XXX should also look for CVT codes in VTB blocks */ 4278 4279 return closure.modes; 4280 } 4281 4282 static void 4283 find_gtf2(struct detailed_timing *t, void *data) 4284 { 4285 u8 *r = (u8 *)t; 4286 4287 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 4288 *(u8 **)data = r; 4289 } 4290 4291 /* Secondary GTF curve kicks in above some break frequency */ 4292 static int 4293 drm_gtf2_hbreak(struct edid *edid) 4294 { 4295 u8 *r = NULL; 4296 4297 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4298 return r ? (r[12] * 2) : 0; 4299 } 4300 4301 static int 4302 drm_gtf2_2c(struct edid *edid) 4303 { 4304 u8 *r = NULL; 4305 4306 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4307 return r ? r[13] : 0; 4308 } 4309 4310 static int 4311 drm_gtf2_m(struct edid *edid) 4312 { 4313 u8 *r = NULL; 4314 4315 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4316 return r ? (r[15] << 8) + r[14] : 0; 4317 } 4318 4319 static int 4320 drm_gtf2_k(struct edid *edid) 4321 { 4322 u8 *r = NULL; 4323 4324 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4325 return r ? r[16] : 0; 4326 } 4327 4328 static int 4329 drm_gtf2_2j(struct edid *edid) 4330 { 4331 u8 *r = NULL; 4332 4333 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4334 return r ? r[17] : 0; 4335 } 4336 4337 /** 4338 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 4339 * @edid: EDID block to scan 4340 */ 4341 static int standard_timing_level(struct edid *edid) 4342 { 4343 if (edid->revision >= 2) { 4344 if (edid->revision >= 4 && 4345 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 4346 return LEVEL_CVT; 4347 if (drm_gtf2_hbreak(edid)) 4348 return LEVEL_GTF2; 4349 return LEVEL_GTF; 4350 } 4351 return LEVEL_DMT; 4352 } 4353 4354 /* 4355 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 4356 * monitors fill with ascii space (0x20) instead. 4357 */ 4358 static int 4359 bad_std_timing(u8 a, u8 b) 4360 { 4361 return (a == 0x00 && b == 0x00) || 4362 (a == 0x01 && b == 0x01) || 4363 (a == 0x20 && b == 0x20); 4364 } 4365 4366 static void 4367 is_rb(struct detailed_timing *t, void *data) 4368 { 4369 u8 *r = (u8 *)t; 4370 4371 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 4372 if (r[15] & 0x10) 4373 *(bool *)data = true; 4374 } 4375 4376 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 4377 static bool 4378 drm_monitor_supports_rb(struct edid *edid) 4379 { 4380 if (edid->revision >= 4) { 4381 bool ret = false; 4382 4383 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 4384 return ret; 4385 } 4386 4387 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 4388 } 4389 4390 static bool 4391 mode_is_rb(const struct drm_display_mode *mode) 4392 { 4393 return (mode->htotal - mode->hdisplay == 160) && 4394 (mode->hsync_end - mode->hdisplay == 80) && 4395 (mode->hsync_end - mode->hsync_start == 32) && 4396 (mode->vsync_start - mode->vdisplay == 3); 4397 } 4398 4399 /* 4400 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 4401 * @hsize: Mode width 4402 * @vsize: Mode height 4403 * @fresh: Mode refresh rate 4404 * @rb: Mode reduced-blanking-ness 4405 * 4406 * Walk the DMT mode list looking for a match for the given parameters. 4407 * 4408 * Return: A newly allocated copy of the mode, or NULL if not found. 4409 */ 4410 static struct drm_display_mode *drm_mode_find_dmt( 4411 int hsize, int vsize, int fresh, 4412 bool rb) 4413 { 4414 int i; 4415 struct drm_display_mode *newmode; 4416 4417 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4418 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4419 4420 if (hsize != ptr->hdisplay) 4421 continue; 4422 if (vsize != ptr->vdisplay) 4423 continue; 4424 if (fresh != drm_get_vrefresh(ptr)) 4425 continue; 4426 if (rb != mode_is_rb(ptr)) 4427 continue; 4428 4429 newmode = drm_mode_create(); 4430 *newmode = *ptr; 4431 return newmode; 4432 } 4433 4434 return NULL; 4435 } 4436 4437 static struct drm_display_mode * 4438 drm_gtf_mode_complex(int hdisplay, int vdisplay, 4439 int vrefresh, bool interlaced, int margins, 4440 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 4441 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 4442 #define GTF_MARGIN_PERCENTAGE 18 4443 /* 2) character cell horizontal granularity (pixels) - default 8 */ 4444 #define GTF_CELL_GRAN 8 4445 /* 3) Minimum vertical porch (lines) - default 3 */ 4446 #define GTF_MIN_V_PORCH 1 4447 /* width of vsync in lines */ 4448 #define V_SYNC_RQD 3 4449 /* width of hsync as % of total line */ 4450 #define H_SYNC_PERCENT 8 4451 /* min time of vsync + back porch (microsec) */ 4452 #define MIN_VSYNC_PLUS_BP 550 4453 /* C' and M' are part of the Blanking Duty Cycle computation */ 4454 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 4455 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 4456 struct drm_display_mode *drm_mode; 4457 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 4458 int top_margin, bottom_margin; 4459 int interlace; 4460 unsigned int hfreq_est; 4461 int vsync_plus_bp; 4462 unsigned int vtotal_lines; 4463 int left_margin, right_margin; 4464 unsigned int total_active_pixels, ideal_duty_cycle; 4465 unsigned int hblank, total_pixels, pixel_freq; 4466 int hsync, hfront_porch, vodd_front_porch_lines; 4467 unsigned int tmp1, tmp2; 4468 4469 drm_mode = drm_mode_create(); 4470 if (!drm_mode) 4471 return NULL; 4472 4473 /* 1. In order to give correct results, the number of horizontal 4474 * pixels requested is first processed to ensure that it is divisible 4475 * by the character size, by rounding it to the nearest character 4476 * cell boundary: 4477 */ 4478 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4479 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 4480 4481 /* 2. If interlace is requested, the number of vertical lines assumed 4482 * by the calculation must be halved, as the computation calculates 4483 * the number of vertical lines per field. 4484 */ 4485 if (interlaced) 4486 vdisplay_rnd = vdisplay / 2; 4487 else 4488 vdisplay_rnd = vdisplay; 4489 4490 /* 3. Find the frame rate required: */ 4491 if (interlaced) 4492 vfieldrate_rqd = vrefresh * 2; 4493 else 4494 vfieldrate_rqd = vrefresh; 4495 4496 /* 4. Find number of lines in Top margin: */ 4497 top_margin = 0; 4498 if (margins) 4499 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4500 1000; 4501 /* 5. Find number of lines in bottom margin: */ 4502 bottom_margin = top_margin; 4503 4504 /* 6. If interlace is required, then set variable interlace: */ 4505 if (interlaced) 4506 interlace = 1; 4507 else 4508 interlace = 0; 4509 4510 /* 7. Estimate the Horizontal frequency */ 4511 { 4512 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 4513 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 4514 2 + interlace; 4515 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 4516 } 4517 4518 /* 8. Find the number of lines in V sync + back porch */ 4519 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 4520 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 4521 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 4522 /* 9. Find the number of lines in V back porch alone: 4523 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 4524 */ 4525 /* 10. Find the total number of lines in Vertical field period: */ 4526 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 4527 vsync_plus_bp + GTF_MIN_V_PORCH; 4528 /* 11. Estimate the Vertical field frequency: 4529 * vfieldrate_est = hfreq_est / vtotal_lines; 4530 */ 4531 4532 /* 12. Find the actual horizontal period: 4533 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 4534 */ 4535 /* 13. Find the actual Vertical field frequency: 4536 * vfield_rate = hfreq_est / vtotal_lines; 4537 */ 4538 /* 14. Find the Vertical frame frequency: 4539 * if (interlaced) 4540 * vframe_rate = vfield_rate / 2; 4541 * else 4542 * vframe_rate = vfield_rate; 4543 */ 4544 /* 15. Find number of pixels in left margin: */ 4545 if (margins) 4546 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4547 1000; 4548 else 4549 left_margin = 0; 4550 4551 /* 16.Find number of pixels in right margin: */ 4552 right_margin = left_margin; 4553 /* 17.Find total number of active pixels in image and left and right */ 4554 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 4555 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 4556 ideal_duty_cycle = GTF_C_PRIME * 1000 - 4557 (GTF_M_PRIME * 1000000 / hfreq_est); 4558 /* 19.Find the number of pixels in the blanking time to the nearest 4559 * double character cell: 4560 */ 4561 hblank = total_active_pixels * ideal_duty_cycle / 4562 (100000 - ideal_duty_cycle); 4563 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 4564 hblank = hblank * 2 * GTF_CELL_GRAN; 4565 /* 20.Find total number of pixels: */ 4566 total_pixels = total_active_pixels + hblank; 4567 /* 21.Find pixel clock frequency: */ 4568 pixel_freq = total_pixels * hfreq_est / 1000; 4569 /* Stage 1 computations are now complete; I should really pass 4570 * the results to another function and do the Stage 2 computations, 4571 * but I only need a few more values so I'll just append the 4572 * computations here for now 4573 */ 4574 4575 /* 17. Find the number of pixels in the horizontal sync period: */ 4576 hsync = H_SYNC_PERCENT * total_pixels / 100; 4577 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4578 hsync = hsync * GTF_CELL_GRAN; 4579 /* 18. Find the number of pixels in horizontal front porch period */ 4580 hfront_porch = hblank / 2 - hsync; 4581 /* 36. Find the number of lines in the odd front porch period: */ 4582 vodd_front_porch_lines = GTF_MIN_V_PORCH; 4583 4584 /* finally, pack the results in the mode struct */ 4585 drm_mode->hdisplay = hdisplay_rnd; 4586 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 4587 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 4588 drm_mode->htotal = total_pixels; 4589 drm_mode->vdisplay = vdisplay_rnd; 4590 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 4591 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 4592 drm_mode->vtotal = vtotal_lines; 4593 4594 drm_mode->clock = pixel_freq; 4595 4596 if (interlaced) { 4597 drm_mode->vtotal *= 2; 4598 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 4599 } 4600 4601 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 4602 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 4603 else 4604 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 4605 4606 return drm_mode; 4607 } 4608 4609 /** 4610 * drm_gtf_mode - create the mode based on the GTF algorithm 4611 * @hdisplay: hdisplay size 4612 * @vdisplay: vdisplay size 4613 * @vrefresh: vrefresh rate. 4614 * @interlaced: whether to compute an interlaced mode 4615 * @margins: desired margin (borders) size 4616 * 4617 * return the mode based on GTF algorithm 4618 * 4619 * This function is to create the mode based on the GTF algorithm. 4620 * Generalized Timing Formula is derived from: 4621 * GTF Spreadsheet by Andy Morrish (1/5/97) 4622 * available at http://www.vesa.org 4623 * 4624 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 4625 * What I have done is to translate it by using integer calculation. 4626 * I also refer to the function of fb_get_mode in the file of 4627 * drivers/video/fbmon.c 4628 * 4629 * Standard GTF parameters: 4630 * M = 600 4631 * C = 40 4632 * K = 128 4633 * J = 20 4634 * 4635 * Returns: 4636 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 4637 * The display mode object is allocated with drm_mode_create(). Returns NULL 4638 * when no mode could be allocated. 4639 */ 4640 static struct drm_display_mode * 4641 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 4642 bool interlaced, int margins) 4643 { 4644 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 4645 interlaced, margins, 4646 600, 40 * 2, 128, 20 * 2); 4647 } 4648 4649 /** drm_mode_hsync - get the hsync of a mode 4650 * @mode: mode 4651 * 4652 * Returns: 4653 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 4654 * value first if it is not yet set. 4655 */ 4656 static int drm_mode_hsync(const struct drm_display_mode *mode) 4657 { 4658 unsigned int calc_val; 4659 4660 if (mode->htotal < 0) 4661 return 0; 4662 4663 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 4664 calc_val += 500; /* round to 1000Hz */ 4665 calc_val /= 1000; /* truncate to kHz */ 4666 4667 return calc_val; 4668 } 4669 4670 /** 4671 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 4672 * @data: the structure that save parsed hdmi edid data 4673 * @edid: EDID block to scan 4674 * @t: standard timing params 4675 * 4676 * Take the standard timing params (in this case width, aspect, and refresh) 4677 * and convert them into a real mode using CVT/GTF/DMT. 4678 */ 4679 static struct drm_display_mode * 4680 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4681 struct std_timing *t) 4682 { 4683 struct drm_display_mode *mode = NULL; 4684 int i, hsize, vsize; 4685 int vrefresh_rate; 4686 int num = data->modes; 4687 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4688 >> EDID_TIMING_ASPECT_SHIFT; 4689 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4690 >> EDID_TIMING_VFREQ_SHIFT; 4691 int timing_level = standard_timing_level(edid); 4692 4693 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4694 return NULL; 4695 4696 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4697 hsize = t->hsize * 8 + 248; 4698 /* vrefresh_rate = vfreq + 60 */ 4699 vrefresh_rate = vfreq + 60; 4700 /* the vdisplay is calculated based on the aspect ratio */ 4701 if (aspect_ratio == 0) { 4702 if (edid->revision < 3) 4703 vsize = hsize; 4704 else 4705 vsize = (hsize * 10) / 16; 4706 } else if (aspect_ratio == 1) { 4707 vsize = (hsize * 3) / 4; 4708 } else if (aspect_ratio == 2) { 4709 vsize = (hsize * 4) / 5; 4710 } else { 4711 vsize = (hsize * 9) / 16; 4712 } 4713 4714 /* HDTV hack, part 1 */ 4715 if (vrefresh_rate == 60 && 4716 ((hsize == 1360 && vsize == 765) || 4717 (hsize == 1368 && vsize == 769))) { 4718 hsize = 1366; 4719 vsize = 768; 4720 } 4721 4722 /* 4723 * If we already has a mode for this size and refresh 4724 * rate (because it came from detailed or CVT info), use that 4725 * instead. This way we don't have to guess at interlace or 4726 * reduced blanking. 4727 */ 4728 for (i = 0; i < num; i++) 4729 if (data->mode_buf[i].hdisplay == hsize && 4730 data->mode_buf[i].vdisplay == vsize && 4731 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4732 return NULL; 4733 4734 /* HDTV hack, part 2 */ 4735 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4736 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4737 false); 4738 mode->hdisplay = 1366; 4739 mode->hsync_start = mode->hsync_start - 1; 4740 mode->hsync_end = mode->hsync_end - 1; 4741 return mode; 4742 } 4743 4744 /* check whether it can be found in default mode table */ 4745 if (drm_monitor_supports_rb(edid)) { 4746 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4747 true); 4748 if (mode) 4749 return mode; 4750 } 4751 4752 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4753 if (mode) 4754 return mode; 4755 4756 /* okay, generate it */ 4757 switch (timing_level) { 4758 case LEVEL_DMT: 4759 break; 4760 case LEVEL_GTF: 4761 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4762 break; 4763 case LEVEL_GTF2: 4764 /* 4765 * This is potentially wrong if there's ever a monitor with 4766 * more than one ranges section, each claiming a different 4767 * secondary GTF curve. Please don't do that. 4768 */ 4769 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4770 if (!mode) 4771 return NULL; 4772 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4773 drm_mode_destroy(mode); 4774 mode = drm_gtf_mode_complex(hsize, vsize, 4775 vrefresh_rate, 0, 0, 4776 drm_gtf2_m(edid), 4777 drm_gtf2_2c(edid), 4778 drm_gtf2_k(edid), 4779 drm_gtf2_2j(edid)); 4780 } 4781 break; 4782 case LEVEL_CVT: 4783 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4784 false); 4785 break; 4786 } 4787 4788 return mode; 4789 } 4790 4791 static void 4792 do_standard_modes(struct detailed_timing *timing, void *c) 4793 { 4794 struct detailed_mode_closure *closure = c; 4795 struct detailed_non_pixel *data = &timing->data.other_data; 4796 struct edid *edid = closure->edid; 4797 4798 if (data->type == EDID_DETAIL_STD_MODES) { 4799 int i; 4800 4801 for (i = 0; i < 6; i++) { 4802 struct std_timing *std; 4803 struct drm_display_mode *newmode; 4804 4805 std = &data->data.timings[i]; 4806 newmode = drm_mode_std(closure->data, edid, std); 4807 if (newmode) { 4808 drm_add_hdmi_modes(closure->data, newmode); 4809 closure->modes++; 4810 drm_mode_destroy(newmode); 4811 } 4812 } 4813 } 4814 } 4815 4816 /** 4817 * add_standard_modes - get std. modes from EDID and add them 4818 * @data: data to add mode(s) to 4819 * @edid: EDID block to scan 4820 * 4821 * Standard modes can be calculated using the appropriate standard (DMT, 4822 * GTF or CVT. Grab them from @edid and add them to the list. 4823 */ 4824 static int 4825 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4826 { 4827 int i, modes = 0; 4828 struct detailed_mode_closure closure = { 4829 .data = data, 4830 .edid = edid, 4831 }; 4832 4833 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4834 struct drm_display_mode *newmode; 4835 4836 newmode = drm_mode_std(data, edid, 4837 &edid->standard_timings[i]); 4838 if (newmode) { 4839 drm_add_hdmi_modes(data, newmode); 4840 modes++; 4841 drm_mode_destroy(newmode); 4842 } 4843 } 4844 4845 if (version_greater(edid, 1, 0)) 4846 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4847 &closure); 4848 4849 /* XXX should also look for standard codes in VTB blocks */ 4850 4851 return modes + closure.modes; 4852 } 4853 4854 static int 4855 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4856 { 4857 int i, j, m, modes = 0; 4858 struct drm_display_mode *mode; 4859 u8 *est = ((u8 *)timing) + 6; 4860 4861 for (i = 0; i < 6; i++) { 4862 for (j = 7; j >= 0; j--) { 4863 m = (i * 8) + (7 - j); 4864 if (m >= ARRAY_SIZE(est3_modes)) 4865 break; 4866 if (est[i] & (1 << j)) { 4867 mode = drm_mode_find_dmt( 4868 est3_modes[m].w, 4869 est3_modes[m].h, 4870 est3_modes[m].r, 4871 est3_modes[m].rb); 4872 if (mode) { 4873 drm_add_hdmi_modes(data, mode); 4874 modes++; 4875 drm_mode_destroy(mode); 4876 } 4877 } 4878 } 4879 } 4880 4881 return modes; 4882 } 4883 4884 static void 4885 do_established_modes(struct detailed_timing *timing, void *c) 4886 { 4887 struct detailed_mode_closure *closure = c; 4888 struct detailed_non_pixel *data = &timing->data.other_data; 4889 4890 if (data->type == EDID_DETAIL_EST_TIMINGS) 4891 closure->modes += drm_est3_modes(closure->data, timing); 4892 } 4893 4894 /** 4895 * add_established_modes - get est. modes from EDID and add them 4896 * @data: data to add mode(s) to 4897 * @edid: EDID block to scan 4898 * 4899 * Each EDID block contains a bitmap of the supported "established modes" list 4900 * (defined above). Tease them out and add them to the modes list. 4901 */ 4902 static int 4903 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4904 { 4905 unsigned long est_bits = edid->established_timings.t1 | 4906 (edid->established_timings.t2 << 8) | 4907 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4908 int i, modes = 0; 4909 struct detailed_mode_closure closure = { 4910 .data = data, 4911 .edid = edid, 4912 }; 4913 4914 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4915 if (est_bits & (1 << i)) { 4916 struct drm_display_mode *newmode = drm_mode_create(); 4917 *newmode = edid_est_modes[i]; 4918 if (newmode) { 4919 drm_add_hdmi_modes(data, newmode); 4920 modes++; 4921 drm_mode_destroy(newmode); 4922 } 4923 } 4924 } 4925 4926 if (version_greater(edid, 1, 0)) 4927 drm_for_each_detailed_block((u8 *)edid, 4928 do_established_modes, &closure); 4929 4930 return modes + closure.modes; 4931 } 4932 4933 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4934 { 4935 u8 vic; 4936 4937 if (!to_match->clock) 4938 return 0; 4939 4940 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4941 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4942 unsigned int clock1, clock2; 4943 4944 /* Make sure to also match alternate clocks */ 4945 clock1 = hdmi_mode->clock; 4946 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4947 4948 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4949 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4950 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4951 return vic; 4952 } 4953 return 0; 4954 } 4955 4956 static int 4957 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4958 { 4959 struct drm_display_mode *mode; 4960 int i, num, modes = 0; 4961 4962 /* Don't add CEA modes if the CEA extension block is missing */ 4963 if (!drm_find_cea_extension(edid)) 4964 return 0; 4965 4966 /* 4967 * Go through all probed modes and create a new mode 4968 * with the alternate clock for certain CEA modes. 4969 */ 4970 num = data->modes; 4971 4972 for (i = 0; i < num; i++) { 4973 const struct drm_display_mode *cea_mode = NULL; 4974 struct drm_display_mode *newmode; 4975 u8 vic; 4976 unsigned int clock1, clock2; 4977 4978 mode = &data->mode_buf[i]; 4979 vic = drm_match_cea_mode(mode); 4980 4981 if (drm_valid_cea_vic(vic)) { 4982 cea_mode = cea_mode_for_vic(vic); 4983 clock2 = cea_mode_alternate_clock(cea_mode); 4984 } else { 4985 vic = drm_match_hdmi_mode(mode); 4986 if (drm_valid_hdmi_vic(vic)) { 4987 cea_mode = &edid_4k_modes[vic]; 4988 clock2 = hdmi_mode_alternate_clock(cea_mode); 4989 } 4990 } 4991 4992 if (!cea_mode) 4993 continue; 4994 4995 clock1 = cea_mode->clock; 4996 4997 if (clock1 == clock2) 4998 continue; 4999 5000 if (mode->clock != clock1 && mode->clock != clock2) 5001 continue; 5002 5003 newmode = drm_mode_create(); 5004 *newmode = *cea_mode; 5005 if (!newmode) 5006 continue; 5007 5008 /* Carry over the stereo flags */ 5009 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 5010 5011 /* 5012 * The current mode could be either variant. Make 5013 * sure to pick the "other" clock for the new mode. 5014 */ 5015 if (mode->clock != clock1) 5016 newmode->clock = clock1; 5017 else 5018 newmode->clock = clock2; 5019 5020 drm_add_hdmi_modes(data, newmode); 5021 modes++; 5022 drm_mode_destroy(newmode); 5023 } 5024 5025 return modes; 5026 } 5027 5028 static u8 *drm_find_displayid_extension(struct edid *edid) 5029 { 5030 return drm_find_edid_extension(edid, DISPLAYID_EXT); 5031 } 5032 5033 static int validate_displayid(u8 *displayid, int length, int idx) 5034 { 5035 int i; 5036 u8 csum = 0; 5037 struct displayid_hdr *base; 5038 5039 base = (struct displayid_hdr *)&displayid[idx]; 5040 5041 debug("base revision 0x%x, length %d, %d %d\n", 5042 base->rev, base->bytes, base->prod_id, base->ext_count); 5043 5044 if (base->bytes + 5 > length - idx) 5045 return -EINVAL; 5046 for (i = idx; i <= base->bytes + 5; i++) 5047 csum += displayid[i]; 5048 if (csum) { 5049 debug("DisplayID checksum invalid, remainder is %d\n", csum); 5050 return -EINVAL; 5051 } 5052 return 0; 5053 } 5054 5055 static struct 5056 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 5057 *timings) 5058 { 5059 struct drm_display_mode *mode; 5060 unsigned pixel_clock = (timings->pixel_clock[0] | 5061 (timings->pixel_clock[1] << 8) | 5062 (timings->pixel_clock[2] << 16)); 5063 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5064 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5065 unsigned hsync = (timings->hsync[0] | 5066 (timings->hsync[1] & 0x7f) << 8) + 1; 5067 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5068 unsigned vactive = (timings->vactive[0] | 5069 timings->vactive[1] << 8) + 1; 5070 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5071 unsigned vsync = (timings->vsync[0] | 5072 (timings->vsync[1] & 0x7f) << 8) + 1; 5073 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5074 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5075 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5076 5077 mode = drm_mode_create(); 5078 if (!mode) 5079 return NULL; 5080 5081 mode->clock = pixel_clock * 10; 5082 mode->hdisplay = hactive; 5083 mode->hsync_start = mode->hdisplay + hsync; 5084 mode->hsync_end = mode->hsync_start + hsync_width; 5085 mode->htotal = mode->hdisplay + hblank; 5086 5087 mode->vdisplay = vactive; 5088 mode->vsync_start = mode->vdisplay + vsync; 5089 mode->vsync_end = mode->vsync_start + vsync_width; 5090 mode->vtotal = mode->vdisplay + vblank; 5091 5092 mode->flags = 0; 5093 mode->flags |= 5094 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5095 mode->flags |= 5096 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5097 mode->type = DRM_MODE_TYPE_DRIVER; 5098 5099 if (timings->flags & 0x80) 5100 mode->type |= DRM_MODE_TYPE_PREFERRED; 5101 mode->vrefresh = drm_get_vrefresh(mode); 5102 5103 return mode; 5104 } 5105 5106 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 5107 struct displayid_block *block) 5108 { 5109 struct displayid_detailed_timing_block *det; 5110 int i; 5111 int num_timings; 5112 struct drm_display_mode *newmode; 5113 int num_modes = 0; 5114 5115 det = (struct displayid_detailed_timing_block *)block; 5116 /* blocks must be multiple of 20 bytes length */ 5117 if (block->num_bytes % 20) 5118 return 0; 5119 5120 num_timings = block->num_bytes / 20; 5121 for (i = 0; i < num_timings; i++) { 5122 struct displayid_detailed_timings_1 *timings = 5123 &det->timings[i]; 5124 5125 newmode = drm_displayid_detailed(timings); 5126 if (!newmode) 5127 continue; 5128 5129 drm_add_hdmi_modes(data, newmode); 5130 num_modes++; 5131 drm_mode_destroy(newmode); 5132 } 5133 return num_modes; 5134 } 5135 5136 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 5137 struct edid *edid) 5138 { 5139 u8 *displayid; 5140 int ret; 5141 int idx = 1; 5142 int length = EDID_SIZE; 5143 struct displayid_block *block; 5144 int num_modes = 0; 5145 5146 displayid = drm_find_displayid_extension(edid); 5147 if (!displayid) 5148 return 0; 5149 5150 ret = validate_displayid(displayid, length, idx); 5151 if (ret) 5152 return 0; 5153 5154 idx += sizeof(struct displayid_hdr); 5155 while (block = (struct displayid_block *)&displayid[idx], 5156 idx + sizeof(struct displayid_block) <= length && 5157 idx + sizeof(struct displayid_block) + block->num_bytes <= 5158 length && block->num_bytes > 0) { 5159 idx += block->num_bytes + sizeof(struct displayid_block); 5160 switch (block->tag) { 5161 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5162 num_modes += 5163 add_displayid_detailed_1_modes(data, block); 5164 break; 5165 } 5166 } 5167 return num_modes; 5168 } 5169 5170 static bool 5171 mode_in_hsync_range(const struct drm_display_mode *mode, 5172 struct edid *edid, u8 *t) 5173 { 5174 int hsync, hmin, hmax; 5175 5176 hmin = t[7]; 5177 if (edid->revision >= 4) 5178 hmin += ((t[4] & 0x04) ? 255 : 0); 5179 hmax = t[8]; 5180 if (edid->revision >= 4) 5181 hmax += ((t[4] & 0x08) ? 255 : 0); 5182 hsync = drm_mode_hsync(mode); 5183 5184 return (hsync <= hmax && hsync >= hmin); 5185 } 5186 5187 static bool 5188 mode_in_vsync_range(const struct drm_display_mode *mode, 5189 struct edid *edid, u8 *t) 5190 { 5191 int vsync, vmin, vmax; 5192 5193 vmin = t[5]; 5194 if (edid->revision >= 4) 5195 vmin += ((t[4] & 0x01) ? 255 : 0); 5196 vmax = t[6]; 5197 if (edid->revision >= 4) 5198 vmax += ((t[4] & 0x02) ? 255 : 0); 5199 vsync = drm_get_vrefresh(mode); 5200 5201 return (vsync <= vmax && vsync >= vmin); 5202 } 5203 5204 static u32 5205 range_pixel_clock(struct edid *edid, u8 *t) 5206 { 5207 /* unspecified */ 5208 if (t[9] == 0 || t[9] == 255) 5209 return 0; 5210 5211 /* 1.4 with CVT support gives us real precision, yay */ 5212 if (edid->revision >= 4 && t[10] == 0x04) 5213 return (t[9] * 10000) - ((t[12] >> 2) * 250); 5214 5215 /* 1.3 is pathetic, so fuzz up a bit */ 5216 return t[9] * 10000 + 5001; 5217 } 5218 5219 static bool 5220 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 5221 struct detailed_timing *timing) 5222 { 5223 u32 max_clock; 5224 u8 *t = (u8 *)timing; 5225 5226 if (!mode_in_hsync_range(mode, edid, t)) 5227 return false; 5228 5229 if (!mode_in_vsync_range(mode, edid, t)) 5230 return false; 5231 5232 max_clock = range_pixel_clock(edid, t); 5233 if (max_clock) 5234 if (mode->clock > max_clock) 5235 return false; 5236 5237 /* 1.4 max horizontal check */ 5238 if (edid->revision >= 4 && t[10] == 0x04) 5239 if (t[13] && mode->hdisplay > 8 * 5240 (t[13] + (256 * (t[12] & 0x3)))) 5241 return false; 5242 5243 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 5244 return false; 5245 5246 return true; 5247 } 5248 5249 static bool valid_inferred_mode(struct hdmi_edid_data *data, 5250 const struct drm_display_mode *mode) 5251 { 5252 const struct drm_display_mode *m; 5253 bool ok = false; 5254 int i; 5255 5256 for (i = 0; i < data->modes; i++) { 5257 m = &data->mode_buf[i]; 5258 if (mode->hdisplay == m->hdisplay && 5259 mode->vdisplay == m->vdisplay && 5260 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 5261 return false; /* duplicated */ 5262 if (mode->hdisplay <= m->hdisplay && 5263 mode->vdisplay <= m->vdisplay) 5264 ok = true; 5265 } 5266 return ok; 5267 } 5268 5269 static int 5270 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5271 struct detailed_timing *timing) 5272 { 5273 int i, modes = 0; 5274 5275 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 5276 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 5277 valid_inferred_mode(data, drm_dmt_modes + i)) { 5278 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 5279 modes++; 5280 } 5281 } 5282 5283 return modes; 5284 } 5285 5286 /* fix up 1366x768 mode from 1368x768; 5287 * GFT/CVT can't express 1366 width which isn't dividable by 8 5288 */ 5289 static void fixup_mode_1366x768(struct drm_display_mode *mode) 5290 { 5291 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 5292 mode->hdisplay = 1366; 5293 mode->hsync_start--; 5294 mode->hsync_end--; 5295 } 5296 } 5297 5298 static int 5299 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5300 struct detailed_timing *timing) 5301 { 5302 int i, modes = 0; 5303 struct drm_display_mode *newmode; 5304 5305 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5306 const struct minimode *m = &extra_modes[i]; 5307 5308 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 5309 if (!newmode) 5310 return modes; 5311 5312 fixup_mode_1366x768(newmode); 5313 if (!mode_in_range(newmode, edid, timing) || 5314 !valid_inferred_mode(data, newmode)) { 5315 drm_mode_destroy(newmode); 5316 continue; 5317 } 5318 5319 drm_add_hdmi_modes(data, newmode); 5320 modes++; 5321 drm_mode_destroy(newmode); 5322 } 5323 5324 return modes; 5325 } 5326 5327 static int 5328 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5329 struct detailed_timing *timing) 5330 { 5331 int i, modes = 0; 5332 struct drm_display_mode *newmode; 5333 bool rb = drm_monitor_supports_rb(edid); 5334 5335 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5336 const struct minimode *m = &extra_modes[i]; 5337 5338 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 5339 if (!newmode) 5340 return modes; 5341 5342 fixup_mode_1366x768(newmode); 5343 if (!mode_in_range(newmode, edid, timing) || 5344 !valid_inferred_mode(data, newmode)) { 5345 drm_mode_destroy(newmode); 5346 continue; 5347 } 5348 5349 drm_add_hdmi_modes(data, newmode); 5350 modes++; 5351 drm_mode_destroy(newmode); 5352 } 5353 5354 return modes; 5355 } 5356 5357 static void 5358 do_inferred_modes(struct detailed_timing *timing, void *c) 5359 { 5360 struct detailed_mode_closure *closure = c; 5361 struct detailed_non_pixel *data = &timing->data.other_data; 5362 struct detailed_data_monitor_range *range = &data->data.range; 5363 5364 if (data->type != EDID_DETAIL_MONITOR_RANGE) 5365 return; 5366 5367 closure->modes += drm_dmt_modes_for_range(closure->data, 5368 closure->edid, 5369 timing); 5370 5371 if (!version_greater(closure->edid, 1, 1)) 5372 return; /* GTF not defined yet */ 5373 5374 switch (range->flags) { 5375 case 0x02: /* secondary gtf, XXX could do more */ 5376 case 0x00: /* default gtf */ 5377 closure->modes += drm_gtf_modes_for_range(closure->data, 5378 closure->edid, 5379 timing); 5380 break; 5381 case 0x04: /* cvt, only in 1.4+ */ 5382 if (!version_greater(closure->edid, 1, 3)) 5383 break; 5384 5385 closure->modes += drm_cvt_modes_for_range(closure->data, 5386 closure->edid, 5387 timing); 5388 break; 5389 case 0x01: /* just the ranges, no formula */ 5390 default: 5391 break; 5392 } 5393 } 5394 5395 static int 5396 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 5397 { 5398 struct detailed_mode_closure closure = { 5399 .data = data, 5400 .edid = edid, 5401 }; 5402 5403 if (version_greater(edid, 1, 0)) 5404 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 5405 &closure); 5406 5407 return closure.modes; 5408 } 5409 5410 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 5411 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 5412 5413 /** 5414 * edid_fixup_preferred - set preferred modes based on quirk list 5415 * @data: the structure that save parsed hdmi edid data 5416 * @quirks: quirks list 5417 * 5418 * Walk the mode list, clearing the preferred status 5419 * on existing modes and setting it anew for the right mode ala @quirks. 5420 */ 5421 static void edid_fixup_preferred(struct hdmi_edid_data *data, 5422 u32 quirks) 5423 { 5424 struct drm_display_mode *cur_mode, *preferred_mode; 5425 int i, target_refresh = 0; 5426 int num = data->modes; 5427 int cur_vrefresh, preferred_vrefresh; 5428 5429 if (!num) 5430 return; 5431 5432 preferred_mode = data->preferred_mode; 5433 5434 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 5435 target_refresh = 60; 5436 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 5437 target_refresh = 75; 5438 5439 for (i = 0; i < num; i++) { 5440 cur_mode = &data->mode_buf[i]; 5441 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 5442 5443 if (cur_mode == preferred_mode) 5444 continue; 5445 5446 /* Largest mode is preferred */ 5447 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 5448 preferred_mode = cur_mode; 5449 5450 cur_vrefresh = cur_mode->vrefresh ? 5451 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 5452 preferred_vrefresh = preferred_mode->vrefresh ? 5453 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 5454 /* At a given size, try to get closest to target refresh */ 5455 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 5456 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 5457 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 5458 preferred_mode = cur_mode; 5459 } 5460 } 5461 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 5462 data->preferred_mode = preferred_mode; 5463 } 5464 5465 static const u8 edid_header[] = { 5466 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 5467 }; 5468 5469 /** 5470 * drm_edid_header_is_valid - sanity check the header of the base EDID block 5471 * @raw_edid: pointer to raw base EDID block 5472 * 5473 * Sanity check the header of the base EDID block. 5474 * 5475 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 5476 */ 5477 static int drm_edid_header_is_valid(const u8 *raw_edid) 5478 { 5479 int i, score = 0; 5480 5481 for (i = 0; i < sizeof(edid_header); i++) 5482 if (raw_edid[i] == edid_header[i]) 5483 score++; 5484 5485 return score; 5486 } 5487 5488 static int drm_edid_block_checksum(const u8 *raw_edid) 5489 { 5490 int i; 5491 u8 csum = 0; 5492 5493 for (i = 0; i < EDID_SIZE; i++) 5494 csum += raw_edid[i]; 5495 5496 return csum; 5497 } 5498 5499 static bool drm_edid_is_zero(const u8 *in_edid, int length) 5500 { 5501 if (memchr_inv(in_edid, 0, length)) 5502 return false; 5503 5504 return true; 5505 } 5506 5507 /** 5508 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 5509 * @raw_edid: pointer to raw EDID block 5510 * @block: type of block to validate (0 for base, extension otherwise) 5511 * @print_bad_edid: if true, dump bad EDID blocks to the console 5512 * @edid_corrupt: if true, the header or checksum is invalid 5513 * 5514 * Validate a base or extension EDID block and optionally dump bad blocks to 5515 * the console. 5516 * 5517 * Return: True if the block is valid, false otherwise. 5518 */ 5519 static 5520 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 5521 bool *edid_corrupt) 5522 { 5523 u8 csum; 5524 int edid_fixup = 6; 5525 struct edid *edid = (struct edid *)raw_edid; 5526 5527 if ((!raw_edid)) 5528 return false; 5529 5530 if (block == 0) { 5531 int score = drm_edid_header_is_valid(raw_edid); 5532 5533 if (score == 8) { 5534 if (edid_corrupt) 5535 *edid_corrupt = false; 5536 } else if (score >= edid_fixup) { 5537 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 5538 * The corrupt flag needs to be set here otherwise, the 5539 * fix-up code here will correct the problem, the 5540 * checksum is correct and the test fails 5541 */ 5542 if (edid_corrupt) 5543 *edid_corrupt = true; 5544 debug("Fixing header, your hardware may be failing\n"); 5545 memcpy(raw_edid, edid_header, sizeof(edid_header)); 5546 } else { 5547 if (edid_corrupt) 5548 *edid_corrupt = true; 5549 goto bad; 5550 } 5551 } 5552 5553 csum = drm_edid_block_checksum(raw_edid); 5554 if (csum) { 5555 if (print_bad_edid) { 5556 debug("EDID checksum is invalid, remainder is %d\n", 5557 csum); 5558 } 5559 5560 if (edid_corrupt) 5561 *edid_corrupt = true; 5562 5563 /* allow CEA to slide through, switches mangle this */ 5564 if (raw_edid[0] != 0x02) 5565 goto bad; 5566 } 5567 5568 /* per-block-type checks */ 5569 switch (raw_edid[0]) { 5570 case 0: /* base */ 5571 if (edid->version != 1) { 5572 debug("EDID has major version %d, instead of 1\n", 5573 edid->version); 5574 goto bad; 5575 } 5576 5577 if (edid->revision > 4) 5578 debug("minor > 4, assuming backward compatibility\n"); 5579 break; 5580 5581 default: 5582 break; 5583 } 5584 5585 return true; 5586 5587 bad: 5588 if (print_bad_edid) { 5589 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 5590 debug("EDID block is all zeroes\n"); 5591 } else { 5592 debug("Raw EDID:\n"); 5593 print_hex_dump("", DUMP_PREFIX_NONE, 16, 1, 5594 raw_edid, EDID_SIZE, false); 5595 } 5596 } 5597 return false; 5598 } 5599 5600 /** 5601 * drm_edid_is_valid - sanity check EDID data 5602 * @edid: EDID data 5603 * 5604 * Sanity-check an entire EDID record (including extensions) 5605 * 5606 * Return: True if the EDID data is valid, false otherwise. 5607 */ 5608 static bool drm_edid_is_valid(struct edid *edid) 5609 { 5610 int i; 5611 u8 *raw = (u8 *)edid; 5612 5613 if (!edid) 5614 return false; 5615 5616 for (i = 0; i <= edid->extensions; i++) 5617 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 5618 return false; 5619 5620 return true; 5621 } 5622 5623 /** 5624 * drm_add_edid_modes - add modes from EDID data, if available 5625 * @data: data we're probing 5626 * @edid: EDID data 5627 * 5628 * Add the specified modes to the data's mode list. 5629 * 5630 * Return: The number of modes added or 0 if we couldn't find any. 5631 */ 5632 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 5633 { 5634 int num_modes = 0; 5635 u32 quirks; 5636 struct edid *edid = (struct edid *)raw_edid; 5637 5638 if (!edid) { 5639 debug("no edid\n"); 5640 return 0; 5641 } 5642 5643 if (!drm_edid_is_valid(edid)) { 5644 debug("EDID invalid\n"); 5645 return 0; 5646 } 5647 5648 if (!data->mode_buf) { 5649 debug("mode buff is null\n"); 5650 return 0; 5651 } 5652 5653 quirks = edid_get_quirks(edid); 5654 /* 5655 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5656 * To avoid multiple parsing of same block, lets parse that map 5657 * from sink info, before parsing CEA modes. 5658 */ 5659 drm_add_display_info(data, edid); 5660 5661 /* 5662 * EDID spec says modes should be preferred in this order: 5663 * - preferred detailed mode 5664 * - other detailed modes from base block 5665 * - detailed modes from extension blocks 5666 * - CVT 3-byte code modes 5667 * - standard timing codes 5668 * - established timing codes 5669 * - modes inferred from GTF or CVT range information 5670 * 5671 * We get this pretty much right. 5672 * 5673 * XXX order for additional mode types in extension blocks? 5674 */ 5675 num_modes += add_detailed_modes(data, edid, quirks); 5676 num_modes += add_cvt_modes(data, edid); 5677 num_modes += add_standard_modes(data, edid); 5678 num_modes += add_established_modes(data, edid); 5679 num_modes += add_cea_modes(data, edid); 5680 num_modes += add_alternate_cea_modes(data, edid); 5681 num_modes += add_displayid_detailed_modes(data, edid); 5682 5683 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5684 num_modes += add_inferred_modes(data, edid); 5685 5686 if (num_modes > 0) 5687 data->preferred_mode = &data->mode_buf[0]; 5688 5689 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5690 edid_fixup_preferred(data, quirks); 5691 5692 if (quirks & EDID_QUIRK_FORCE_6BPC) 5693 data->display_info.bpc = 6; 5694 5695 if (quirks & EDID_QUIRK_FORCE_8BPC) 5696 data->display_info.bpc = 8; 5697 5698 if (quirks & EDID_QUIRK_FORCE_10BPC) 5699 data->display_info.bpc = 10; 5700 5701 if (quirks & EDID_QUIRK_FORCE_12BPC) 5702 data->display_info.bpc = 12; 5703 5704 return num_modes; 5705 } 5706 5707 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5708 { 5709 u8 vic; 5710 5711 if (!to_match->clock) { 5712 printf("can't find to match\n"); 5713 return 0; 5714 } 5715 5716 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 5717 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 5718 unsigned int clock1, clock2; 5719 5720 /* Check both 60Hz and 59.94Hz */ 5721 clock1 = cea_mode->clock; 5722 clock2 = cea_mode_alternate_clock(cea_mode); 5723 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5724 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5725 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5726 return vic; 5727 } 5728 5729 return 0; 5730 } 5731 5732 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5733 { 5734 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 5735 5736 if (mode) 5737 return mode->picture_aspect_ratio; 5738 5739 return HDMI_PICTURE_ASPECT_NONE; 5740 } 5741 5742 int 5743 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5744 struct drm_display_mode *mode, 5745 bool is_hdmi2_sink) 5746 { 5747 int err; 5748 5749 if (!frame || !mode) 5750 return -EINVAL; 5751 5752 err = hdmi_avi_infoframe_init(frame); 5753 if (err < 0) 5754 return err; 5755 5756 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5757 frame->pixel_repeat = 1; 5758 5759 frame->video_code = drm_match_cea_mode(mode); 5760 5761 /* 5762 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5763 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5764 * have to make sure we dont break HDMI 1.4 sinks. 5765 */ 5766 if (!is_hdmi2_sink && frame->video_code > 64) 5767 frame->video_code = 0; 5768 5769 /* 5770 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5771 * we should send its VIC in vendor infoframes, else send the 5772 * VIC in AVI infoframes. Lets check if this mode is present in 5773 * HDMI 1.4b 4K modes 5774 */ 5775 if (frame->video_code) { 5776 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5777 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5778 5779 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5780 frame->video_code = 0; 5781 } 5782 5783 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5784 5785 /* 5786 * Populate picture aspect ratio from either 5787 * user input (if specified) or from the CEA mode list. 5788 */ 5789 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5790 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5791 frame->picture_aspect = mode->picture_aspect_ratio; 5792 else if (frame->video_code > 0) 5793 frame->picture_aspect = drm_get_cea_aspect_ratio( 5794 frame->video_code); 5795 5796 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5797 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5798 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5799 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5800 5801 return 0; 5802 } 5803 5804 /** 5805 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5806 * @frame: HDMI vendor infoframe 5807 * 5808 * Returns 0 on success or a negative error code on failure. 5809 */ 5810 int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5811 { 5812 memset(frame, 0, sizeof(*frame)); 5813 5814 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5815 frame->version = 1; 5816 5817 frame->oui = HDMI_IEEE_OUI; 5818 5819 /* 5820 * 0 is a valid value for s3d_struct, so we use a special "not set" 5821 * value 5822 */ 5823 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5824 5825 return 0; 5826 } 5827 5828 /** 5829 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5830 * quantization range information 5831 * @frame: HDMI AVI infoframe 5832 * @rgb_quant_range: RGB quantization range (Q) 5833 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 5834 */ 5835 void 5836 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5837 struct drm_display_mode *mode, 5838 enum hdmi_quantization_range rgb_quant_range, 5839 bool rgb_quant_range_selectable, bool is_hdmi2_sink) 5840 { 5841 /* 5842 * CEA-861: 5843 * "A Source shall not send a non-zero Q value that does not correspond 5844 * to the default RGB Quantization Range for the transmitted Picture 5845 * unless the Sink indicates support for the Q bit in a Video 5846 * Capabilities Data Block." 5847 * 5848 * HDMI 2.0 recommends sending non-zero Q when it does match the 5849 * default RGB quantization range for the mode, even when QS=0. 5850 */ 5851 if (rgb_quant_range_selectable || 5852 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5853 frame->quantization_range = rgb_quant_range; 5854 else 5855 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5856 5857 /* 5858 * CEA-861-F: 5859 * "When transmitting any RGB colorimetry, the Source should set the 5860 * YQ-field to match the RGB Quantization Range being transmitted 5861 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5862 * set YQ=1) and the Sink shall ignore the YQ-field." 5863 */ 5864 if (!is_hdmi2_sink || rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5865 frame->ycc_quantization_range = 5866 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5867 else 5868 frame->ycc_quantization_range = 5869 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5870 } 5871 5872 static enum hdmi_3d_structure 5873 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5874 { 5875 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5876 5877 switch (layout) { 5878 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5879 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5880 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5881 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5882 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5883 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5884 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5885 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5886 case DRM_MODE_FLAG_3D_L_DEPTH: 5887 return HDMI_3D_STRUCTURE_L_DEPTH; 5888 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5889 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5890 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5891 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5892 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5893 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5894 default: 5895 return HDMI_3D_STRUCTURE_INVALID; 5896 } 5897 } 5898 5899 int 5900 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5901 struct drm_display_mode *mode) 5902 { 5903 int err; 5904 u32 s3d_flags; 5905 u8 vic; 5906 5907 if (!frame || !mode) 5908 return -EINVAL; 5909 5910 vic = drm_match_hdmi_mode(mode); 5911 5912 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5913 5914 if (!vic && !s3d_flags) 5915 return -EINVAL; 5916 5917 if (vic && s3d_flags) 5918 return -EINVAL; 5919 5920 err = hdmi_vendor_infoframe_init(frame); 5921 if (err < 0) 5922 return err; 5923 5924 if (vic) 5925 frame->vic = vic; 5926 else 5927 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5928 5929 return 0; 5930 } 5931 5932 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5933 { 5934 u8 csum = 0; 5935 size_t i; 5936 5937 /* compute checksum */ 5938 for (i = 0; i < size; i++) 5939 csum += ptr[i]; 5940 5941 return 256 - csum; 5942 } 5943 5944 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5945 { 5946 u8 *ptr = buffer; 5947 5948 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5949 } 5950 5951 /** 5952 * hdmi_avi_infoframe_init() - initialize an HDMI AVI infoframe 5953 * @frame: HDMI AVI infoframe 5954 * 5955 * Returns 0 on success or a negative error code on failure. 5956 */ 5957 int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5958 { 5959 memset(frame, 0, sizeof(*frame)); 5960 5961 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5962 frame->version = 2; 5963 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5964 5965 return 0; 5966 } 5967 EXPORT_SYMBOL(hdmi_avi_infoframe_init); 5968 5969 /** 5970 * hdmi_avi_infoframe_pack() - write HDMI AVI infoframe to binary buffer 5971 * @frame: HDMI AVI infoframe 5972 * @buffer: destination buffer 5973 * @size: size of buffer 5974 * 5975 * Packs the information contained in the @frame structure into a binary 5976 * representation that can be written into the corresponding controller 5977 * registers. Also computes the checksum as required by section 5.3.5 of 5978 * the HDMI 1.4 specification. 5979 * 5980 * Returns the number of bytes packed into the binary buffer or a negative 5981 * error code on failure. 5982 */ 5983 ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, 5984 size_t size) 5985 { 5986 u8 *ptr = buffer; 5987 size_t length; 5988 5989 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5990 5991 if (size < length) 5992 return -ENOSPC; 5993 5994 memset(buffer, 0, size); 5995 5996 ptr[0] = frame->type; 5997 ptr[1] = frame->version; 5998 ptr[2] = frame->length; 5999 ptr[3] = 0; /* checksum */ 6000 6001 /* start infoframe payload */ 6002 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6003 6004 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 6005 6006 /* 6007 * Data byte 1, bit 4 has to be set if we provide the active format 6008 * aspect ratio 6009 */ 6010 if (frame->active_aspect & 0xf) 6011 ptr[0] |= BIT(4); 6012 6013 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 6014 if (frame->top_bar || frame->bottom_bar) 6015 ptr[0] |= BIT(3); 6016 6017 if (frame->left_bar || frame->right_bar) 6018 ptr[0] |= BIT(2); 6019 6020 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 6021 ((frame->picture_aspect & 0x3) << 4) | 6022 (frame->active_aspect & 0xf); 6023 6024 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 6025 ((frame->quantization_range & 0x3) << 2) | 6026 (frame->nups & 0x3); 6027 6028 if (frame->itc) 6029 ptr[2] |= BIT(7); 6030 6031 ptr[3] = frame->video_code & 0x7f; 6032 6033 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 6034 ((frame->content_type & 0x3) << 4) | 6035 (frame->pixel_repeat & 0xf); 6036 6037 ptr[5] = frame->top_bar & 0xff; 6038 ptr[6] = (frame->top_bar >> 8) & 0xff; 6039 ptr[7] = frame->bottom_bar & 0xff; 6040 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 6041 ptr[9] = frame->left_bar & 0xff; 6042 ptr[10] = (frame->left_bar >> 8) & 0xff; 6043 ptr[11] = frame->right_bar & 0xff; 6044 ptr[12] = (frame->right_bar >> 8) & 0xff; 6045 6046 hdmi_infoframe_set_checksum(buffer, length); 6047 6048 return length; 6049 } 6050 EXPORT_SYMBOL(hdmi_avi_infoframe_pack); 6051 6052 static int hdmi_avi_infoframe_check_only(const struct hdmi_avi_infoframe *frame) 6053 { 6054 if (frame->type != HDMI_INFOFRAME_TYPE_AVI || 6055 frame->version != 2 || 6056 frame->length != HDMI_AVI_INFOFRAME_SIZE) 6057 return -EINVAL; 6058 6059 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 6060 return -EINVAL; 6061 6062 return 0; 6063 } 6064 6065 /** 6066 * hdmi_avi_infoframe_check() - check a HDMI AVI infoframe 6067 * @frame: HDMI AVI infoframe 6068 * 6069 * Validates that the infoframe is consistent and updates derived fields 6070 * (eg. length) based on other fields. 6071 * 6072 * Returns 0 on success or a negative error code on failure. 6073 */ 6074 int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame) 6075 { 6076 return hdmi_avi_infoframe_check_only(frame); 6077 } 6078 EXPORT_SYMBOL(hdmi_avi_infoframe_check); 6079 6080 /** 6081 * hdmi_avi_infoframe_pack_only() - write HDMI AVI infoframe to binary buffer 6082 * @frame: HDMI AVI infoframe 6083 * @buffer: destination buffer 6084 * @size: size of buffer 6085 * 6086 * Packs the information contained in the @frame structure into a binary 6087 * representation that can be written into the corresponding controller 6088 * registers. Also computes the checksum as required by section 5.3.5 of 6089 * the HDMI 1.4 specification. 6090 * 6091 * Returns the number of bytes packed into the binary buffer or a negative 6092 * error code on failure. 6093 */ 6094 ssize_t hdmi_avi_infoframe_pack_only(const struct hdmi_avi_infoframe *frame, 6095 void *buffer, size_t size) 6096 { 6097 u8 *ptr = buffer; 6098 size_t length; 6099 int ret; 6100 6101 ret = hdmi_avi_infoframe_check_only(frame); 6102 if (ret) 6103 return ret; 6104 6105 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6106 6107 if (size < length) 6108 return -ENOSPC; 6109 6110 memset(buffer, 0, size); 6111 6112 ptr[0] = frame->type; 6113 ptr[1] = frame->version; 6114 ptr[2] = frame->length; 6115 ptr[3] = 0; /* checksum */ 6116 6117 /* start infoframe payload */ 6118 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6119 6120 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 6121 6122 /* 6123 * Data byte 1, bit 4 has to be set if we provide the active format 6124 * aspect ratio 6125 */ 6126 if (frame->active_aspect & 0xf) 6127 ptr[0] |= BIT(4); 6128 6129 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 6130 if (frame->top_bar || frame->bottom_bar) 6131 ptr[0] |= BIT(3); 6132 6133 if (frame->left_bar || frame->right_bar) 6134 ptr[0] |= BIT(2); 6135 6136 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 6137 ((frame->picture_aspect & 0x3) << 4) | 6138 (frame->active_aspect & 0xf); 6139 6140 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 6141 ((frame->quantization_range & 0x3) << 2) | 6142 (frame->nups & 0x3); 6143 6144 if (frame->itc) 6145 ptr[2] |= BIT(7); 6146 6147 ptr[3] = frame->video_code & 0xff; 6148 6149 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 6150 ((frame->content_type & 0x3) << 4) | 6151 (frame->pixel_repeat & 0xf); 6152 6153 ptr[5] = frame->top_bar & 0xff; 6154 ptr[6] = (frame->top_bar >> 8) & 0xff; 6155 ptr[7] = frame->bottom_bar & 0xff; 6156 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 6157 ptr[9] = frame->left_bar & 0xff; 6158 ptr[10] = (frame->left_bar >> 8) & 0xff; 6159 ptr[11] = frame->right_bar & 0xff; 6160 ptr[12] = (frame->right_bar >> 8) & 0xff; 6161 6162 hdmi_infoframe_set_checksum(buffer, length); 6163 6164 return length; 6165 } 6166 EXPORT_SYMBOL(hdmi_avi_infoframe_pack_only); 6167 6168 /** 6169 * hdmi_spd_infoframe_init() - initialize an HDMI SPD infoframe 6170 * @frame: HDMI SPD infoframe 6171 * @vendor: vendor string 6172 * @product: product string 6173 * 6174 * Returns 0 on success or a negative error code on failure. 6175 */ 6176 int hdmi_spd_infoframe_init(struct hdmi_spd_infoframe *frame, 6177 const char *vendor, const char *product) 6178 { 6179 memset(frame, 0, sizeof(*frame)); 6180 6181 frame->type = HDMI_INFOFRAME_TYPE_SPD; 6182 frame->version = 1; 6183 frame->length = HDMI_SPD_INFOFRAME_SIZE; 6184 6185 strncpy(frame->vendor, vendor, sizeof(frame->vendor)); 6186 strncpy(frame->product, product, sizeof(frame->product)); 6187 6188 return 0; 6189 } 6190 EXPORT_SYMBOL(hdmi_spd_infoframe_init); 6191 6192 /** 6193 * hdmi_spd_infoframe_pack() - write HDMI SPD infoframe to binary buffer 6194 * @frame: HDMI SPD infoframe 6195 * @buffer: destination buffer 6196 * @size: size of buffer 6197 * 6198 * Packs the information contained in the @frame structure into a binary 6199 * representation that can be written into the corresponding controller 6200 * registers. Also computes the checksum as required by section 5.3.5 of 6201 * the HDMI 1.4 specification. 6202 * 6203 * Returns the number of bytes packed into the binary buffer or a negative 6204 * error code on failure. 6205 */ 6206 ssize_t hdmi_spd_infoframe_pack(struct hdmi_spd_infoframe *frame, void *buffer, 6207 size_t size) 6208 { 6209 u8 *ptr = buffer; 6210 size_t length; 6211 6212 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6213 6214 if (size < length) 6215 return -ENOSPC; 6216 6217 memset(buffer, 0, size); 6218 6219 ptr[0] = frame->type; 6220 ptr[1] = frame->version; 6221 ptr[2] = frame->length; 6222 ptr[3] = 0; /* checksum */ 6223 6224 /* start infoframe payload */ 6225 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6226 6227 memcpy(ptr, frame->vendor, sizeof(frame->vendor)); 6228 memcpy(ptr + 8, frame->product, sizeof(frame->product)); 6229 6230 ptr[24] = frame->sdi; 6231 6232 hdmi_infoframe_set_checksum(buffer, length); 6233 6234 return length; 6235 } 6236 EXPORT_SYMBOL(hdmi_spd_infoframe_pack); 6237 6238 /** 6239 * hdmi_audio_infoframe_init() - initialize an HDMI audio infoframe 6240 * @frame: HDMI audio infoframe 6241 * 6242 * Returns 0 on success or a negative error code on failure. 6243 */ 6244 int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame) 6245 { 6246 memset(frame, 0, sizeof(*frame)); 6247 6248 frame->type = HDMI_INFOFRAME_TYPE_AUDIO; 6249 frame->version = 1; 6250 frame->length = HDMI_AUDIO_INFOFRAME_SIZE; 6251 6252 return 0; 6253 } 6254 6255 /** 6256 * hdmi_audio_infoframe_pack() - write HDMI audio infoframe to binary buffer 6257 * @frame: HDMI audio infoframe 6258 * @buffer: destination buffer 6259 * @size: size of buffer 6260 * 6261 * Packs the information contained in the @frame structure into a binary 6262 * representation that can be written into the corresponding controller 6263 * registers. Also computes the checksum as required by section 5.3.5 of 6264 * the HDMI 1.4 specification. 6265 * 6266 * Returns the number of bytes packed into the binary buffer or a negative 6267 * error code on failure. 6268 */ 6269 ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame, 6270 void *buffer, size_t size) 6271 { 6272 unsigned char channels; 6273 char *ptr = buffer; 6274 size_t length; 6275 6276 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6277 6278 if (size < length) 6279 return -ENOSPC; 6280 6281 memset(buffer, 0, size); 6282 6283 if (frame->channels >= 2) 6284 channels = frame->channels - 1; 6285 else 6286 channels = 0; 6287 6288 ptr[0] = frame->type; 6289 ptr[1] = frame->version; 6290 ptr[2] = frame->length; 6291 ptr[3] = 0; /* checksum */ 6292 6293 /* start infoframe payload */ 6294 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6295 6296 ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7); 6297 ptr[1] = ((frame->sample_frequency & 0x7) << 2) | 6298 (frame->sample_size & 0x3); 6299 ptr[2] = frame->coding_type_ext & 0x1f; 6300 ptr[3] = frame->channel_allocation; 6301 ptr[4] = (frame->level_shift_value & 0xf) << 3; 6302 6303 if (frame->downmix_inhibit) 6304 ptr[4] |= BIT(7); 6305 6306 hdmi_infoframe_set_checksum(buffer, length); 6307 6308 return length; 6309 } 6310 6311 /** 6312 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 6313 * @frame: HDMI infoframe 6314 * @buffer: destination buffer 6315 * @size: size of buffer 6316 * 6317 * Packs the information contained in the @frame structure into a binary 6318 * representation that can be written into the corresponding controller 6319 * registers. Also computes the checksum as required by section 5.3.5 of 6320 * the HDMI 1.4 specification. 6321 * 6322 * Returns the number of bytes packed into the binary buffer or a negative 6323 * error code on failure. 6324 */ 6325 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 6326 void *buffer, size_t size) 6327 { 6328 char *ptr = buffer; 6329 size_t length; 6330 6331 /* empty info frame */ 6332 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 6333 return -EINVAL; 6334 6335 /* only one of those can be supplied */ 6336 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 6337 return -EINVAL; 6338 6339 /* for side by side (half) we also need to provide 3D_Ext_Data */ 6340 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6341 frame->length = 6; 6342 else 6343 frame->length = 5; 6344 6345 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6346 6347 if (size < length) 6348 return -ENOSPC; 6349 6350 memset(buffer, 0, size); 6351 6352 ptr[0] = frame->type; 6353 ptr[1] = frame->version; 6354 ptr[2] = frame->length; 6355 ptr[3] = 0; /* checksum */ 6356 6357 /* HDMI OUI */ 6358 ptr[4] = 0x03; 6359 ptr[5] = 0x0c; 6360 ptr[6] = 0x00; 6361 6362 if (frame->vic) { 6363 ptr[7] = 0x1 << 5; /* video format */ 6364 ptr[8] = frame->vic; 6365 } else { 6366 ptr[7] = 0x2 << 5; /* video format */ 6367 ptr[8] = (frame->s3d_struct & 0xf) << 4; 6368 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6369 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 6370 } 6371 6372 hdmi_infoframe_set_checksum(buffer, length); 6373 6374 return length; 6375 } 6376 6377 /** 6378 * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and 6379 * mastering infoframe 6380 * @frame: HDMI DRM infoframe 6381 * 6382 * Returns 0 on success or a negative error code on failure. 6383 */ 6384 int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame) 6385 { 6386 memset(frame, 0, sizeof(*frame)); 6387 6388 frame->type = HDMI_INFOFRAME_TYPE_DRM; 6389 frame->version = 1; 6390 6391 return 0; 6392 } 6393 6394 /** 6395 * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer 6396 * @frame: HDMI DRM infoframe 6397 * @buffer: destination buffer 6398 * @size: size of buffer 6399 * 6400 * Packs the information contained in the @frame structure into a binary 6401 * representation that can be written into the corresponding controller 6402 * registers. Also computes the checksum as required by section 5.3.5 of 6403 * the HDMI 1.4 specification. 6404 * 6405 * Returns the number of bytes packed into the binary buffer or a negative 6406 * error code on failure. 6407 */ 6408 ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer, 6409 size_t size) 6410 { 6411 u8 *ptr = buffer; 6412 size_t length; 6413 6414 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6415 6416 if (size < length) 6417 return -ENOSPC; 6418 6419 memset(buffer, 0, size); 6420 6421 ptr[0] = frame->type; 6422 ptr[1] = frame->version; 6423 ptr[2] = frame->length; 6424 ptr[3] = 0; /* checksum */ 6425 6426 /* start infoframe payload */ 6427 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6428 6429 ptr[0] = frame->eotf; 6430 ptr[1] = frame->metadata_type; 6431 6432 ptr[2] = frame->display_primaries_x[0] & 0xff; 6433 ptr[3] = frame->display_primaries_x[0] >> 8; 6434 6435 ptr[4] = frame->display_primaries_x[1] & 0xff; 6436 ptr[5] = frame->display_primaries_x[1] >> 8; 6437 6438 ptr[6] = frame->display_primaries_x[2] & 0xff; 6439 ptr[7] = frame->display_primaries_x[2] >> 8; 6440 6441 ptr[9] = frame->display_primaries_y[0] & 0xff; 6442 ptr[10] = frame->display_primaries_y[0] >> 8; 6443 6444 ptr[11] = frame->display_primaries_y[1] & 0xff; 6445 ptr[12] = frame->display_primaries_y[1] >> 8; 6446 6447 ptr[13] = frame->display_primaries_y[2] & 0xff; 6448 ptr[14] = frame->display_primaries_y[2] >> 8; 6449 6450 ptr[15] = frame->white_point_x & 0xff; 6451 ptr[16] = frame->white_point_x >> 8; 6452 6453 ptr[17] = frame->white_point_y & 0xff; 6454 ptr[18] = frame->white_point_y >> 8; 6455 6456 ptr[19] = frame->max_mastering_display_luminance & 0xff; 6457 ptr[20] = frame->max_mastering_display_luminance >> 8; 6458 6459 ptr[21] = frame->min_mastering_display_luminance & 0xff; 6460 ptr[22] = frame->min_mastering_display_luminance >> 8; 6461 6462 ptr[23] = frame->max_cll & 0xff; 6463 ptr[24] = frame->max_cll >> 8; 6464 6465 ptr[25] = frame->max_fall & 0xff; 6466 ptr[26] = frame->max_fall >> 8; 6467 6468 hdmi_infoframe_set_checksum(buffer, length); 6469 6470 return length; 6471 } 6472 6473 /* 6474 * hdmi_vendor_any_infoframe_pack() - write a vendor infoframe to binary buffer 6475 */ 6476 static ssize_t 6477 hdmi_vendor_any_infoframe_pack(union hdmi_vendor_any_infoframe *frame, 6478 void *buffer, size_t size) 6479 { 6480 /* we only know about HDMI vendor infoframes */ 6481 if (frame->any.oui != HDMI_IEEE_OUI) 6482 return -EINVAL; 6483 6484 return hdmi_vendor_infoframe_pack(&frame->hdmi, buffer, size); 6485 } 6486 6487 /** 6488 * hdmi_infoframe_pack() - write a HDMI infoframe to binary buffer 6489 * @frame: HDMI infoframe 6490 * @buffer: destination buffer 6491 * @size: size of buffer 6492 * 6493 * Packs the information contained in the @frame structure into a binary 6494 * representation that can be written into the corresponding controller 6495 * registers. Also computes the checksum as required by section 5.3.5 of 6496 * the HDMI 1.4 specification. 6497 * 6498 * Returns the number of bytes packed into the binary buffer or a negative 6499 * error code on failure. 6500 */ 6501 ssize_t 6502 hdmi_infoframe_pack(union hdmi_infoframe *frame, void *buffer, size_t size) 6503 { 6504 ssize_t length; 6505 6506 switch (frame->any.type) { 6507 case HDMI_INFOFRAME_TYPE_AVI: 6508 length = hdmi_avi_infoframe_pack(&frame->avi, buffer, size); 6509 break; 6510 case HDMI_INFOFRAME_TYPE_DRM: 6511 length = hdmi_drm_infoframe_pack(&frame->drm, buffer, size); 6512 break; 6513 case HDMI_INFOFRAME_TYPE_SPD: 6514 length = hdmi_spd_infoframe_pack(&frame->spd, buffer, size); 6515 break; 6516 case HDMI_INFOFRAME_TYPE_AUDIO: 6517 length = hdmi_audio_infoframe_pack(&frame->audio, buffer, size); 6518 break; 6519 case HDMI_INFOFRAME_TYPE_VENDOR: 6520 length = hdmi_vendor_any_infoframe_pack(&frame->vendor, 6521 buffer, size); 6522 break; 6523 default: 6524 printf("Bad infoframe type %d\n", frame->any.type); 6525 length = -EINVAL; 6526 } 6527 6528 return length; 6529 } 6530 6531 /** 6532 * hdmi_avi_infoframe_unpack() - unpack binary buffer to a HDMI AVI infoframe 6533 * @buffer: source buffer 6534 * @frame: HDMI AVI infoframe 6535 * 6536 * Unpacks the information contained in binary @buffer into a structured 6537 * @frame of the HDMI Auxiliary Video (AVI) information frame. 6538 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6539 * specification. 6540 * 6541 * Returns 0 on success or a negative error code on failure. 6542 */ 6543 static int hdmi_avi_infoframe_unpack(struct hdmi_avi_infoframe *frame, 6544 void *buffer) 6545 { 6546 u8 *ptr = buffer; 6547 int ret; 6548 6549 if (ptr[0] != HDMI_INFOFRAME_TYPE_AVI || 6550 ptr[1] != 2 || 6551 ptr[2] != HDMI_AVI_INFOFRAME_SIZE) 6552 return -EINVAL; 6553 6554 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AVI)) != 0) 6555 return -EINVAL; 6556 6557 ret = hdmi_avi_infoframe_init(frame); 6558 if (ret) 6559 return ret; 6560 6561 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6562 6563 frame->colorspace = (ptr[0] >> 5) & 0x3; 6564 if (ptr[0] & 0x10) 6565 frame->active_aspect = ptr[1] & 0xf; 6566 if (ptr[0] & 0x8) { 6567 frame->top_bar = (ptr[5] << 8) + ptr[6]; 6568 frame->bottom_bar = (ptr[7] << 8) + ptr[8]; 6569 } 6570 if (ptr[0] & 0x4) { 6571 frame->left_bar = (ptr[9] << 8) + ptr[10]; 6572 frame->right_bar = (ptr[11] << 8) + ptr[12]; 6573 } 6574 frame->scan_mode = ptr[0] & 0x3; 6575 6576 frame->colorimetry = (ptr[1] >> 6) & 0x3; 6577 frame->picture_aspect = (ptr[1] >> 4) & 0x3; 6578 frame->active_aspect = ptr[1] & 0xf; 6579 6580 frame->itc = ptr[2] & 0x80 ? true : false; 6581 frame->extended_colorimetry = (ptr[2] >> 4) & 0x7; 6582 frame->quantization_range = (ptr[2] >> 2) & 0x3; 6583 frame->nups = ptr[2] & 0x3; 6584 6585 frame->video_code = ptr[3] & 0x7f; 6586 frame->ycc_quantization_range = (ptr[4] >> 6) & 0x3; 6587 frame->content_type = (ptr[4] >> 4) & 0x3; 6588 6589 frame->pixel_repeat = ptr[4] & 0xf; 6590 6591 return 0; 6592 } 6593 6594 /** 6595 * hdmi_spd_infoframe_unpack() - unpack binary buffer to a HDMI SPD infoframe 6596 * @buffer: source buffer 6597 * @frame: HDMI SPD infoframe 6598 * 6599 * Unpacks the information contained in binary @buffer into a structured 6600 * @frame of the HDMI Source Product Description (SPD) information frame. 6601 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6602 * specification. 6603 * 6604 * Returns 0 on success or a negative error code on failure. 6605 */ 6606 static int hdmi_spd_infoframe_unpack(struct hdmi_spd_infoframe *frame, 6607 void *buffer) 6608 { 6609 char *ptr = buffer; 6610 int ret; 6611 6612 if (ptr[0] != HDMI_INFOFRAME_TYPE_SPD || 6613 ptr[1] != 1 || 6614 ptr[2] != HDMI_SPD_INFOFRAME_SIZE) { 6615 return -EINVAL; 6616 } 6617 6618 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(SPD)) != 0) 6619 return -EINVAL; 6620 6621 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6622 6623 ret = hdmi_spd_infoframe_init(frame, ptr, ptr + 8); 6624 if (ret) 6625 return ret; 6626 6627 frame->sdi = ptr[24]; 6628 6629 return 0; 6630 } 6631 6632 /** 6633 * hdmi_audio_infoframe_unpack() - unpack binary buffer to a HDMI AUDIO infoframe 6634 * @buffer: source buffer 6635 * @frame: HDMI Audio infoframe 6636 * 6637 * Unpacks the information contained in binary @buffer into a structured 6638 * @frame of the HDMI Audio information frame. 6639 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6640 * specification. 6641 * 6642 * Returns 0 on success or a negative error code on failure. 6643 */ 6644 static int hdmi_audio_infoframe_unpack(struct hdmi_audio_infoframe *frame, 6645 void *buffer) 6646 { 6647 u8 *ptr = buffer; 6648 int ret; 6649 6650 if (ptr[0] != HDMI_INFOFRAME_TYPE_AUDIO || 6651 ptr[1] != 1 || 6652 ptr[2] != HDMI_AUDIO_INFOFRAME_SIZE) { 6653 return -EINVAL; 6654 } 6655 6656 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AUDIO)) != 0) 6657 return -EINVAL; 6658 6659 ret = hdmi_audio_infoframe_init(frame); 6660 if (ret) 6661 return ret; 6662 6663 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6664 6665 frame->channels = ptr[0] & 0x7; 6666 frame->coding_type = (ptr[0] >> 4) & 0xf; 6667 frame->sample_size = ptr[1] & 0x3; 6668 frame->sample_frequency = (ptr[1] >> 2) & 0x7; 6669 frame->coding_type_ext = ptr[2] & 0x1f; 6670 frame->channel_allocation = ptr[3]; 6671 frame->level_shift_value = (ptr[4] >> 3) & 0xf; 6672 frame->downmix_inhibit = ptr[4] & 0x80 ? true : false; 6673 6674 return 0; 6675 } 6676 6677 /** 6678 * hdmi_vendor_infoframe_unpack() - unpack binary buffer to a HDMI vendor infoframe 6679 * @buffer: source buffer 6680 * @frame: HDMI Vendor infoframe 6681 * 6682 * Unpacks the information contained in binary @buffer into a structured 6683 * @frame of the HDMI Vendor information frame. 6684 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6685 * specification. 6686 * 6687 * Returns 0 on success or a negative error code on failure. 6688 */ 6689 static int 6690 hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame, 6691 void *buffer) 6692 { 6693 u8 *ptr = buffer; 6694 size_t length; 6695 int ret; 6696 u8 hdmi_video_format; 6697 struct hdmi_vendor_infoframe *hvf = &frame->hdmi; 6698 6699 if (ptr[0] != HDMI_INFOFRAME_TYPE_VENDOR || 6700 ptr[1] != 1 || 6701 (ptr[2] != 4 && ptr[2] != 5 && ptr[2] != 6)) 6702 return -EINVAL; 6703 6704 length = ptr[2]; 6705 6706 if (hdmi_infoframe_checksum(buffer, 6707 HDMI_INFOFRAME_HEADER_SIZE + length) != 0) 6708 return -EINVAL; 6709 6710 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6711 6712 /* HDMI OUI */ 6713 if (ptr[0] != 0x03 || 6714 ptr[1] != 0x0c || 6715 ptr[2] != 0x00) 6716 return -EINVAL; 6717 6718 hdmi_video_format = ptr[3] >> 5; 6719 6720 if (hdmi_video_format > 0x2) 6721 return -EINVAL; 6722 6723 ret = hdmi_vendor_infoframe_init(hvf); 6724 if (ret) 6725 return ret; 6726 6727 hvf->length = length; 6728 6729 if (hdmi_video_format == 0x2) { 6730 if (length != 5 && length != 6) 6731 return -EINVAL; 6732 hvf->s3d_struct = ptr[4] >> 4; 6733 if (hvf->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) { 6734 if (length != 6) 6735 return -EINVAL; 6736 hvf->s3d_ext_data = ptr[5] >> 4; 6737 } 6738 } else if (hdmi_video_format == 0x1) { 6739 if (length != 5) 6740 return -EINVAL; 6741 hvf->vic = ptr[4]; 6742 } else { 6743 if (length != 4) 6744 return -EINVAL; 6745 } 6746 6747 return 0; 6748 } 6749 6750 /** 6751 * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe 6752 * @buffer: source buffer 6753 * @frame: HDMI infoframe 6754 * 6755 * Unpacks the information contained in binary buffer @buffer into a structured 6756 * @frame of a HDMI infoframe. 6757 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6758 * specification. 6759 * 6760 * Returns 0 on success or a negative error code on failure. 6761 */ 6762 int hdmi_infoframe_unpack(union hdmi_infoframe *frame, void *buffer) 6763 { 6764 int ret; 6765 u8 *ptr = buffer; 6766 6767 switch (ptr[0]) { 6768 case HDMI_INFOFRAME_TYPE_AVI: 6769 ret = hdmi_avi_infoframe_unpack(&frame->avi, buffer); 6770 break; 6771 case HDMI_INFOFRAME_TYPE_SPD: 6772 ret = hdmi_spd_infoframe_unpack(&frame->spd, buffer); 6773 break; 6774 case HDMI_INFOFRAME_TYPE_AUDIO: 6775 ret = hdmi_audio_infoframe_unpack(&frame->audio, buffer); 6776 break; 6777 case HDMI_INFOFRAME_TYPE_VENDOR: 6778 ret = hdmi_vendor_any_infoframe_unpack(&frame->vendor, buffer); 6779 break; 6780 default: 6781 ret = -EINVAL; 6782 break; 6783 } 6784 6785 return ret; 6786 } 6787 6788 /** 6789 * drm_mode_sort - sort mode list 6790 * @edid_data: modes structures to sort 6791 * 6792 * Sort @edid_data by favorability, moving good modes to the head of the list. 6793 */ 6794 void drm_mode_sort(struct hdmi_edid_data *edid_data) 6795 { 6796 struct drm_display_mode *a, *b; 6797 struct drm_display_mode c; 6798 int diff, i, j; 6799 6800 for (i = 0; i < (edid_data->modes - 1); i++) { 6801 a = &edid_data->mode_buf[i]; 6802 for (j = i + 1; j < edid_data->modes; j++) { 6803 b = &edid_data->mode_buf[j]; 6804 diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) - 6805 ((a->type & DRM_MODE_TYPE_PREFERRED) != 0); 6806 if (diff) { 6807 if (diff > 0) { 6808 c = *a; 6809 *a = *b; 6810 *b = c; 6811 } 6812 continue; 6813 } 6814 6815 diff = b->hdisplay * b->vdisplay 6816 - a->hdisplay * a->vdisplay; 6817 if (diff) { 6818 if (diff > 0) { 6819 c = *a; 6820 *a = *b; 6821 *b = c; 6822 } 6823 continue; 6824 } 6825 6826 diff = b->vrefresh - a->vrefresh; 6827 if (diff) { 6828 if (diff > 0) { 6829 c = *a; 6830 *a = *b; 6831 *b = c; 6832 } 6833 continue; 6834 } 6835 6836 diff = b->clock - a->clock; 6837 if (diff > 0) { 6838 c = *a; 6839 *a = *b; 6840 *b = c; 6841 } 6842 } 6843 } 6844 edid_data->preferred_mode = &edid_data->mode_buf[0]; 6845 } 6846 6847 /** 6848 * drm_mode_prune_invalid - remove invalid modes from mode list 6849 * @edid_data: structure store mode list 6850 * Returns: 6851 * Number of valid modes. 6852 */ 6853 int drm_mode_prune_invalid(struct hdmi_edid_data *edid_data) 6854 { 6855 int i, j; 6856 int num = edid_data->modes; 6857 int len = sizeof(struct drm_display_mode); 6858 struct drm_display_mode *mode_buf = edid_data->mode_buf; 6859 6860 for (i = 0; i < num; i++) { 6861 if (mode_buf[i].invalid) { 6862 /* If mode is invalid, delete it. */ 6863 for (j = i; j < num - 1; j++) 6864 memcpy(&mode_buf[j], &mode_buf[j + 1], len); 6865 6866 num--; 6867 i--; 6868 } 6869 } 6870 /* Clear redundant modes of mode_buf. */ 6871 memset(&mode_buf[num], 0, len * (edid_data->modes - num)); 6872 6873 edid_data->modes = num; 6874 return num; 6875 } 6876 6877 /** 6878 * drm_rk_filter_whitelist - mark modes out of white list from mode list 6879 * @edid_data: structure store mode list 6880 */ 6881 void drm_rk_filter_whitelist(struct hdmi_edid_data *edid_data) 6882 { 6883 int i, j, white_len; 6884 6885 if (sizeof(resolution_white)) { 6886 white_len = sizeof(resolution_white) / 6887 sizeof(resolution_white[0]); 6888 for (i = 0; i < edid_data->modes; i++) { 6889 for (j = 0; j < white_len; j++) { 6890 if (drm_mode_match(&resolution_white[j], 6891 &edid_data->mode_buf[i], 6892 DRM_MODE_MATCH_TIMINGS | 6893 DRM_MODE_MATCH_CLOCK | 6894 DRM_MODE_MATCH_FLAGS)) 6895 break; 6896 } 6897 6898 if (j == white_len) 6899 edid_data->mode_buf[i].invalid = true; 6900 } 6901 } 6902 } 6903 6904 static void drm_display_mode_convert(struct drm_display_mode *mode, 6905 struct base_drm_display_mode *base_mode) 6906 { 6907 mode->clock = base_mode->clock; 6908 mode->hdisplay = base_mode->hdisplay; 6909 mode->hsync_start = base_mode->hsync_start; 6910 mode->hsync_end = base_mode->hsync_end; 6911 mode->htotal = base_mode->htotal; 6912 mode->vdisplay = base_mode->vdisplay; 6913 mode->vsync_start = base_mode->vsync_start; 6914 mode->vsync_end = base_mode->vsync_end; 6915 mode->vtotal = base_mode->vtotal; 6916 mode->vrefresh = base_mode->vrefresh; 6917 mode->vscan = base_mode->vscan; 6918 mode->flags = base_mode->flags; 6919 mode->picture_aspect_ratio = base_mode->picture_aspect_ratio; 6920 } 6921 6922 void drm_rk_select_mode(struct hdmi_edid_data *edid_data, 6923 struct base_screen_info *screen_info) 6924 { 6925 int i; 6926 struct drm_display_mode mode; 6927 6928 if (!screen_info) { 6929 /* define init resolution here */ 6930 } else { 6931 memset(&mode, 0, sizeof(struct drm_display_mode)); 6932 6933 drm_display_mode_convert(&mode, &screen_info->mode); 6934 for (i = 0; i < edid_data->modes; i++) { 6935 if (drm_mode_match(&mode, 6936 &edid_data->mode_buf[i], 6937 DRM_MODE_MATCH_TIMINGS | 6938 DRM_MODE_MATCH_CLOCK | 6939 DRM_MODE_MATCH_FLAGS)) { 6940 edid_data->preferred_mode = 6941 &edid_data->mode_buf[i]; 6942 6943 if (edid_data->mode_buf[i].picture_aspect_ratio) 6944 break; 6945 } 6946 } 6947 } 6948 } 6949 6950 /** 6951 * drm_do_probe_ddc_edid() - get EDID information via I2C 6952 * @adap: ddc adapter 6953 * @buf: EDID data buffer to be filled 6954 * @block: 128 byte EDID block to start fetching from 6955 * @len: EDID data buffer length to fetch 6956 * 6957 * Try to fetch EDID information by calling I2C driver functions. 6958 * 6959 * Return: 0 on success or -1 on failure. 6960 */ 6961 static int 6962 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 6963 size_t len) 6964 { 6965 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 6966 unsigned char segment = block >> 1; 6967 unsigned char xfers = segment ? 3 : 2; 6968 int ret, retries = 5; 6969 6970 do { 6971 struct i2c_msg msgs[] = { 6972 { 6973 .addr = DDC_SEGMENT_ADDR, 6974 .flags = 0, 6975 .len = 1, 6976 .buf = &segment, 6977 }, { 6978 .addr = DDC_ADDR, 6979 .flags = 0, 6980 .len = 1, 6981 .buf = &start, 6982 }, { 6983 .addr = DDC_ADDR, 6984 .flags = I2C_M_RD, 6985 .len = len, 6986 .buf = buf, 6987 } 6988 }; 6989 6990 if (adap->ops) { 6991 ret = adap->ops->xfer(adap->i2c_bus, &msgs[3 - xfers], 6992 xfers); 6993 if (!ret) 6994 ret = xfers; 6995 } else { 6996 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 6997 } 6998 } while (ret != xfers && --retries); 6999 7000 /* All msg transfer successfully. */ 7001 return ret == xfers ? 0 : -1; 7002 } 7003 7004 u8 *drm_do_get_edid(struct ddc_adapter *adap) 7005 { 7006 int i, j, block_num, valid_extensions = 0, invalid_blocks = 0, block = 0; 7007 bool edid_corrupt; 7008 u8 *new, *edid; 7009 #ifdef DEBUG 7010 u8 *buff; 7011 #endif 7012 7013 edid = malloc(HDMI_EDID_BLOCK_SIZE); 7014 if (!edid) 7015 goto err; 7016 7017 /* base block fetch */ 7018 for (i = 0; i < 4; i++) { 7019 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 7020 goto err; 7021 if (drm_edid_block_valid(edid, 0, true, 7022 &edid_corrupt)) 7023 break; 7024 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 7025 printf("edid base block is 0, get edid failed\n"); 7026 goto err; 7027 } 7028 } 7029 7030 if (i == 4) 7031 goto err; 7032 7033 /* if there's no extensions, we're done */ 7034 valid_extensions = edid[0x7e]; 7035 if (valid_extensions == 0) 7036 return 0; 7037 7038 new = realloc(edid, (valid_extensions + 1) * HDMI_EDID_BLOCK_SIZE); 7039 if (!new) 7040 goto err; 7041 edid = new; 7042 7043 /* get the number of extensions */ 7044 block_num = edid[0x7e] + 1; 7045 7046 for (j = 1; j < block_num; j++) { 7047 u8 *block = edid + j * HDMI_EDID_BLOCK_SIZE; 7048 7049 for (i = 0; i < 4; i++) { 7050 if (drm_do_probe_ddc_edid(adap, block, j, 7051 HDMI_EDID_BLOCK_SIZE)) 7052 goto err; 7053 if (drm_edid_block_valid(block, j, 7054 true, NULL)) 7055 break; 7056 } 7057 7058 if (i == 4) 7059 invalid_blocks++; 7060 7061 if (j == 1) { 7062 /* 7063 * If the first EDID extension is a CTA extension, and 7064 * the first Data Block is HF-EEODB, override the 7065 * extension block count. 7066 * 7067 * Note: HF-EEODB could specify a smaller extension 7068 * count too, but we can't risk allocating a smaller 7069 * amount. 7070 */ 7071 int eeodb = edid_hfeeodb_block_count((const struct edid *)edid); 7072 7073 if (eeodb > block_num) { 7074 block_num = eeodb; 7075 new = realloc(edid, block_num * HDMI_EDID_BLOCK_SIZE); 7076 if (!new) 7077 goto err; 7078 edid = new; 7079 } 7080 } 7081 } 7082 7083 if (invalid_blocks) { 7084 u8 *base; 7085 7086 new = kcalloc(valid_extensions + 1, HDMI_EDID_BLOCK_SIZE, GFP_KERNEL); 7087 if (!new) 7088 goto err; 7089 7090 base = new; 7091 for (i = 0; i <= edid[0x7e]; i++) { 7092 u8 *block = edid + i * HDMI_EDID_BLOCK_SIZE; 7093 7094 if (!drm_edid_block_valid(block, i, false, NULL)) 7095 continue; 7096 7097 memcpy(base, block, HDMI_EDID_BLOCK_SIZE); 7098 base += HDMI_EDID_BLOCK_SIZE; 7099 } 7100 7101 new[HDMI_EDID_BLOCK_SIZE - 1] += new[0x7e] - valid_extensions; 7102 new[0x7e] = valid_extensions; 7103 7104 kfree(edid); 7105 edid = new; 7106 } 7107 7108 #ifdef DEBUG 7109 printf("RAW EDID:\n"); 7110 for (i = 0; i < block_num; i++) { 7111 buff = &edid[0x80 * i]; 7112 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 7113 if (j % 16 == 0) 7114 printf("\n"); 7115 printf("0x%02x, ", buff[j]); 7116 } 7117 printf("\n"); 7118 } 7119 #endif 7120 7121 return edid; 7122 7123 err: 7124 printf("can't get edid block:%d\n", block); 7125 7126 return NULL; 7127 } 7128 7129 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 7130 void *buffer, size_t size) 7131 { 7132 struct i2c_msg msgs[2] = { 7133 { 7134 .addr = addr, 7135 .flags = 0, 7136 .len = 1, 7137 .buf = &offset, 7138 }, { 7139 .addr = addr, 7140 .flags = I2C_M_RD, 7141 .len = size, 7142 .buf = buffer, 7143 } 7144 }; 7145 7146 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 7147 } 7148 7149 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 7150 const void *buffer, size_t size) 7151 { 7152 struct i2c_msg msg = { 7153 .addr = addr, 7154 .flags = 0, 7155 .len = 1 + size, 7156 .buf = NULL, 7157 }; 7158 void *data; 7159 int err; 7160 7161 data = malloc(1 + size); 7162 if (!data) 7163 return -ENOMEM; 7164 7165 msg.buf = data; 7166 7167 memcpy(data, &offset, sizeof(offset)); 7168 memcpy(data + 1, buffer, size); 7169 7170 err = adap->ddc_xfer(adap, &msg, 1); 7171 7172 free(data); 7173 7174 return err; 7175 } 7176 7177 /** 7178 * drm_scdc_readb - read a single byte from SCDC 7179 * @adap: ddc adapter 7180 * @offset: offset of register to read 7181 * @value: return location for the register value 7182 * 7183 * Reads a single byte from SCDC. This is a convenience wrapper around the 7184 * drm_scdc_read() function. 7185 * 7186 * Returns: 7187 * 0 on success or a negative error code on failure. 7188 */ 7189 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 7190 u8 *value) 7191 { 7192 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 7193 sizeof(*value)); 7194 } 7195 7196 /** 7197 * drm_scdc_writeb - write a single byte to SCDC 7198 * @adap: ddc adapter 7199 * @offset: offset of register to read 7200 * @value: return location for the register value 7201 * 7202 * Writes a single byte to SCDC. This is a convenience wrapper around the 7203 * drm_scdc_write() function. 7204 * 7205 * Returns: 7206 * 0 on success or a negative error code on failure. 7207 */ 7208 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 7209 u8 value) 7210 { 7211 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 7212 sizeof(value)); 7213 } 7214 7215