1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <hexdump.h> 22 #include <malloc.h> 23 #include <linux/compat.h> 24 #include <linux/ctype.h> 25 #include <linux/fb.h> 26 #include <linux/hdmi.h> 27 #include <linux/string.h> 28 29 #define EDID_EST_TIMINGS 16 30 #define EDID_STD_TIMINGS 8 31 #define EDID_DETAILED_TIMINGS 4 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 bool preferred; 78 u32 quirks; 79 int modes; 80 }; 81 82 #define LEVEL_DMT 0 83 #define LEVEL_GTF 1 84 #define LEVEL_GTF2 2 85 #define LEVEL_CVT 3 86 87 static struct edid_quirk { 88 char vendor[4]; 89 int product_id; 90 u32 quirks; 91 } edid_quirk_list[] = { 92 /* Acer AL1706 */ 93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Acer F51 */ 95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Unknown Acer */ 97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 98 99 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 100 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 116 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 146 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 147 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Probably taken from CEA-861 spec. 152 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 153 * 154 * Index using the VIC. 155 */ 156 static const struct drm_display_mode edid_cea_modes[] = { 157 /* 0 - dummy, VICs start at 1 */ 158 { }, 159 /* 1 - 640x480@60Hz */ 160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 161 752, 800, 480, 490, 492, 525, 0, 162 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 163 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 164 /* 2 - 720x480@60Hz */ 165 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 166 798, 858, 480, 489, 495, 525, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 168 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 169 /* 3 - 720x480@60Hz */ 170 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 171 798, 858, 480, 489, 495, 525, 0, 172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 173 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 174 /* 4 - 1280x720@60Hz */ 175 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 176 1430, 1650, 720, 725, 730, 750, 0, 177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 178 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 179 /* 5 - 1920x1080i@60Hz */ 180 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 181 2052, 2200, 1080, 1084, 1094, 1125, 0, 182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 183 DRM_MODE_FLAG_INTERLACE), 184 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 185 /* 6 - 720(1440)x480i@60Hz */ 186 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 187 801, 858, 480, 488, 494, 525, 0, 188 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 189 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 190 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 191 /* 7 - 720(1440)x480i@60Hz */ 192 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 193 801, 858, 480, 488, 494, 525, 0, 194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 195 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 196 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 197 /* 8 - 720(1440)x240@60Hz */ 198 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 199 801, 858, 240, 244, 247, 262, 0, 200 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 201 DRM_MODE_FLAG_DBLCLK), 202 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 203 /* 9 - 720(1440)x240@60Hz */ 204 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 205 801, 858, 240, 244, 247, 262, 0, 206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 207 DRM_MODE_FLAG_DBLCLK), 208 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 209 /* 10 - 2880x480i@60Hz */ 210 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 211 3204, 3432, 480, 488, 494, 525, 0, 212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 213 DRM_MODE_FLAG_INTERLACE), 214 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 215 /* 11 - 2880x480i@60Hz */ 216 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 217 3204, 3432, 480, 488, 494, 525, 0, 218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 219 DRM_MODE_FLAG_INTERLACE), 220 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 221 /* 12 - 2880x240@60Hz */ 222 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 223 3204, 3432, 240, 244, 247, 262, 0, 224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 225 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 226 /* 13 - 2880x240@60Hz */ 227 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 228 3204, 3432, 240, 244, 247, 262, 0, 229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 230 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 231 /* 14 - 1440x480@60Hz */ 232 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 233 1596, 1716, 480, 489, 495, 525, 0, 234 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 235 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 236 /* 15 - 1440x480@60Hz */ 237 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 238 1596, 1716, 480, 489, 495, 525, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 240 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 241 /* 16 - 1920x1080@60Hz */ 242 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 243 2052, 2200, 1080, 1084, 1089, 1125, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 245 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 246 /* 17 - 720x576@50Hz */ 247 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 248 796, 864, 576, 581, 586, 625, 0, 249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 250 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 251 /* 18 - 720x576@50Hz */ 252 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 253 796, 864, 576, 581, 586, 625, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 255 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 256 /* 19 - 1280x720@50Hz */ 257 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 258 1760, 1980, 720, 725, 730, 750, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 260 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 261 /* 20 - 1920x1080i@50Hz */ 262 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 263 2492, 2640, 1080, 1084, 1094, 1125, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 265 DRM_MODE_FLAG_INTERLACE), 266 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 267 /* 21 - 720(1440)x576i@50Hz */ 268 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 269 795, 864, 576, 580, 586, 625, 0, 270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 271 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 273 /* 22 - 720(1440)x576i@50Hz */ 274 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 275 795, 864, 576, 580, 586, 625, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 277 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 278 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 279 /* 23 - 720(1440)x288@50Hz */ 280 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 281 795, 864, 288, 290, 293, 312, 0, 282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 283 DRM_MODE_FLAG_DBLCLK), 284 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 285 /* 24 - 720(1440)x288@50Hz */ 286 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 287 795, 864, 288, 290, 293, 312, 0, 288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 289 DRM_MODE_FLAG_DBLCLK), 290 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 291 /* 25 - 2880x576i@50Hz */ 292 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 293 3180, 3456, 576, 580, 586, 625, 0, 294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 295 DRM_MODE_FLAG_INTERLACE), 296 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 297 /* 26 - 2880x576i@50Hz */ 298 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 299 3180, 3456, 576, 580, 586, 625, 0, 300 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 301 DRM_MODE_FLAG_INTERLACE), 302 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 303 /* 27 - 2880x288@50Hz */ 304 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 305 3180, 3456, 288, 290, 293, 312, 0, 306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 307 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 308 /* 28 - 2880x288@50Hz */ 309 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 310 3180, 3456, 288, 290, 293, 312, 0, 311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 312 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 313 /* 29 - 1440x576@50Hz */ 314 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 315 1592, 1728, 576, 581, 586, 625, 0, 316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 317 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 318 /* 30 - 1440x576@50Hz */ 319 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 320 1592, 1728, 576, 581, 586, 625, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 322 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 323 /* 31 - 1920x1080@50Hz */ 324 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 325 2492, 2640, 1080, 1084, 1089, 1125, 0, 326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 327 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 328 /* 32 - 1920x1080@24Hz */ 329 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 330 2602, 2750, 1080, 1084, 1089, 1125, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 332 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 333 /* 33 - 1920x1080@25Hz */ 334 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 335 2492, 2640, 1080, 1084, 1089, 1125, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 337 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 338 /* 34 - 1920x1080@30Hz */ 339 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 340 2052, 2200, 1080, 1084, 1089, 1125, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 342 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 343 /* 35 - 2880x480@60Hz */ 344 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 345 3192, 3432, 480, 489, 495, 525, 0, 346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 347 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 348 /* 36 - 2880x480@60Hz */ 349 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 350 3192, 3432, 480, 489, 495, 525, 0, 351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 352 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 353 /* 37 - 2880x576@50Hz */ 354 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 355 3184, 3456, 576, 581, 586, 625, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 357 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 358 /* 38 - 2880x576@50Hz */ 359 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 360 3184, 3456, 576, 581, 586, 625, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 362 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 363 /* 39 - 1920x1080i@50Hz */ 364 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 365 2120, 2304, 1080, 1126, 1136, 1250, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 367 DRM_MODE_FLAG_INTERLACE), 368 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 369 /* 40 - 1920x1080i@100Hz */ 370 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 371 2492, 2640, 1080, 1084, 1094, 1125, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 373 DRM_MODE_FLAG_INTERLACE), 374 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 375 /* 41 - 1280x720@100Hz */ 376 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 377 1760, 1980, 720, 725, 730, 750, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 379 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 380 /* 42 - 720x576@100Hz */ 381 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 382 796, 864, 576, 581, 586, 625, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 384 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 385 /* 43 - 720x576@100Hz */ 386 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 387 796, 864, 576, 581, 586, 625, 0, 388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 389 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 390 /* 44 - 720(1440)x576i@100Hz */ 391 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 392 795, 864, 576, 580, 586, 625, 0, 393 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 394 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 395 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 396 /* 45 - 720(1440)x576i@100Hz */ 397 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 398 795, 864, 576, 580, 586, 625, 0, 399 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 400 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 401 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 402 /* 46 - 1920x1080i@120Hz */ 403 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 404 2052, 2200, 1080, 1084, 1094, 1125, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 406 DRM_MODE_FLAG_INTERLACE), 407 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 408 /* 47 - 1280x720@120Hz */ 409 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 410 1430, 1650, 720, 725, 730, 750, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 412 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 413 /* 48 - 720x480@120Hz */ 414 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 415 798, 858, 480, 489, 495, 525, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 417 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 418 /* 49 - 720x480@120Hz */ 419 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 420 798, 858, 480, 489, 495, 525, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 422 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 423 /* 50 - 720(1440)x480i@120Hz */ 424 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 425 801, 858, 480, 488, 494, 525, 0, 426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 427 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 428 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 429 /* 51 - 720(1440)x480i@120Hz */ 430 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 431 801, 858, 480, 488, 494, 525, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 433 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 434 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 435 /* 52 - 720x576@200Hz */ 436 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 437 796, 864, 576, 581, 586, 625, 0, 438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 439 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 440 /* 53 - 720x576@200Hz */ 441 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 442 796, 864, 576, 581, 586, 625, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 444 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 445 /* 54 - 720(1440)x576i@200Hz */ 446 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 447 795, 864, 576, 580, 586, 625, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 449 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 450 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 451 /* 55 - 720(1440)x576i@200Hz */ 452 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 453 795, 864, 576, 580, 586, 625, 0, 454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 455 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 456 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 457 /* 56 - 720x480@240Hz */ 458 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 459 798, 858, 480, 489, 495, 525, 0, 460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 461 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 462 /* 57 - 720x480@240Hz */ 463 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 464 798, 858, 480, 489, 495, 525, 0, 465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 466 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 467 /* 58 - 720(1440)x480i@240 */ 468 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 469 801, 858, 480, 488, 494, 525, 0, 470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 471 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 472 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 473 /* 59 - 720(1440)x480i@240 */ 474 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 475 801, 858, 480, 488, 494, 525, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 477 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 478 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 479 /* 60 - 1280x720@24Hz */ 480 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 481 3080, 3300, 720, 725, 730, 750, 0, 482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 483 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 484 /* 61 - 1280x720@25Hz */ 485 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 486 3740, 3960, 720, 725, 730, 750, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 488 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 489 /* 62 - 1280x720@30Hz */ 490 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 491 3080, 3300, 720, 725, 730, 750, 0, 492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 493 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 494 /* 63 - 1920x1080@120Hz */ 495 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 496 2052, 2200, 1080, 1084, 1089, 1125, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 498 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 499 /* 64 - 1920x1080@100Hz */ 500 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 501 2492, 2640, 1080, 1084, 1089, 1125, 0, 502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 503 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 504 /* 65 - 1280x720@24Hz */ 505 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 506 3080, 3300, 720, 725, 730, 750, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 508 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 509 /* 66 - 1280x720@25Hz */ 510 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 511 3740, 3960, 720, 725, 730, 750, 0, 512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 513 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 514 /* 67 - 1280x720@30Hz */ 515 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 516 3080, 3300, 720, 725, 730, 750, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 518 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 519 /* 68 - 1280x720@50Hz */ 520 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 521 1760, 1980, 720, 725, 730, 750, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 523 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 524 /* 69 - 1280x720@60Hz */ 525 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 526 1430, 1650, 720, 725, 730, 750, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 528 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 529 /* 70 - 1280x720@100Hz */ 530 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 531 1760, 1980, 720, 725, 730, 750, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 533 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 534 /* 71 - 1280x720@120Hz */ 535 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 536 1430, 1650, 720, 725, 730, 750, 0, 537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 538 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 539 /* 72 - 1920x1080@24Hz */ 540 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 541 2602, 2750, 1080, 1084, 1089, 1125, 0, 542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 543 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 544 /* 73 - 1920x1080@25Hz */ 545 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 546 2492, 2640, 1080, 1084, 1089, 1125, 0, 547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 548 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 549 /* 74 - 1920x1080@30Hz */ 550 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 551 2052, 2200, 1080, 1084, 1089, 1125, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 553 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 554 /* 75 - 1920x1080@50Hz */ 555 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 556 2492, 2640, 1080, 1084, 1089, 1125, 0, 557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 558 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 559 /* 76 - 1920x1080@60Hz */ 560 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 561 2052, 2200, 1080, 1084, 1089, 1125, 0, 562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 563 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 564 /* 77 - 1920x1080@100Hz */ 565 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 566 2492, 2640, 1080, 1084, 1089, 1125, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 568 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 569 /* 78 - 1920x1080@120Hz */ 570 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 571 2052, 2200, 1080, 1084, 1089, 1125, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 573 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 574 /* 79 - 1680x720@24Hz */ 575 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 576 3080, 3300, 720, 725, 730, 750, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 578 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 579 /* 80 - 1680x720@25Hz */ 580 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 581 2948, 3168, 720, 725, 730, 750, 0, 582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 583 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 584 /* 81 - 1680x720@30Hz */ 585 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 586 2420, 2640, 720, 725, 730, 750, 0, 587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 588 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 589 /* 82 - 1680x720@50Hz */ 590 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 591 1980, 2200, 720, 725, 730, 750, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 593 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 594 /* 83 - 1680x720@60Hz */ 595 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 596 1980, 2200, 720, 725, 730, 750, 0, 597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 598 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 599 /* 84 - 1680x720@100Hz */ 600 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 601 1780, 2000, 720, 725, 730, 825, 0, 602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 603 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 604 /* 85 - 1680x720@120Hz */ 605 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 606 1780, 2000, 720, 725, 730, 825, 0, 607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 608 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 609 /* 86 - 2560x1080@24Hz */ 610 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 611 3602, 3750, 1080, 1084, 1089, 1100, 0, 612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 613 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 614 /* 87 - 2560x1080@25Hz */ 615 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 616 3052, 3200, 1080, 1084, 1089, 1125, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 618 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 619 /* 88 - 2560x1080@30Hz */ 620 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 621 3372, 3520, 1080, 1084, 1089, 1125, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 623 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 624 /* 89 - 2560x1080@50Hz */ 625 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 626 3152, 3300, 1080, 1084, 1089, 1125, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 628 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 629 /* 90 - 2560x1080@60Hz */ 630 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 631 2852, 3000, 1080, 1084, 1089, 1100, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 633 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 634 /* 91 - 2560x1080@100Hz */ 635 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 636 2822, 2970, 1080, 1084, 1089, 1250, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 638 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 639 /* 92 - 2560x1080@120Hz */ 640 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 641 3152, 3300, 1080, 1084, 1089, 1250, 0, 642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 643 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 644 /* 93 - 3840x2160p@24Hz 16:9 */ 645 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 646 5204, 5500, 2160, 2168, 2178, 2250, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 648 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 649 /* 94 - 3840x2160p@25Hz 16:9 */ 650 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 651 4984, 5280, 2160, 2168, 2178, 2250, 0, 652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 653 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 654 /* 95 - 3840x2160p@30Hz 16:9 */ 655 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 656 4104, 4400, 2160, 2168, 2178, 2250, 0, 657 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 658 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 659 /* 96 - 3840x2160p@50Hz 16:9 */ 660 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 661 4984, 5280, 2160, 2168, 2178, 2250, 0, 662 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 663 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 664 /* 97 - 3840x2160p@60Hz 16:9 */ 665 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 666 4104, 4400, 2160, 2168, 2178, 2250, 0, 667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 669 /* 98 - 4096x2160p@24Hz 256:135 */ 670 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 671 5204, 5500, 2160, 2168, 2178, 2250, 0, 672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 673 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 674 /* 99 - 4096x2160p@25Hz 256:135 */ 675 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 676 5152, 5280, 2160, 2168, 2178, 2250, 0, 677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 678 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 679 /* 100 - 4096x2160p@30Hz 256:135 */ 680 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 681 4272, 4400, 2160, 2168, 2178, 2250, 0, 682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 683 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 684 /* 101 - 4096x2160p@50Hz 256:135 */ 685 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 686 5152, 5280, 2160, 2168, 2178, 2250, 0, 687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 688 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 689 /* 102 - 4096x2160p@60Hz 256:135 */ 690 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 691 4272, 4400, 2160, 2168, 2178, 2250, 0, 692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 693 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 694 /* 103 - 3840x2160p@24Hz 64:27 */ 695 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 696 5204, 5500, 2160, 2168, 2178, 2250, 0, 697 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 698 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 699 /* 104 - 3840x2160p@25Hz 64:27 */ 700 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 701 4104, 4400, 2160, 2168, 2178, 2250, 0, 702 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 703 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 704 /* 105 - 3840x2160p@30Hz 64:27 */ 705 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 706 4104, 4400, 2160, 2168, 2178, 2250, 0, 707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 708 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 709 /* 106 - 3840x2160p@50Hz 64:27 */ 710 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 711 4984, 5280, 2160, 2168, 2178, 2250, 0, 712 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 713 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 714 /* 107 - 3840x2160p@60Hz 64:27 */ 715 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 716 4104, 4400, 2160, 2168, 2178, 2250, 0, 717 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 718 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 719 }; 720 721 /* 722 * HDMI 1.4 4k modes. Index using the VIC. 723 */ 724 static const struct drm_display_mode edid_4k_modes[] = { 725 /* 0 - dummy, VICs start at 1 */ 726 { }, 727 /* 1 - 3840x2160@30Hz */ 728 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 729 3840, 4016, 4104, 4400, 730 2160, 2168, 2178, 2250, 0, 731 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 732 .vrefresh = 30, }, 733 /* 2 - 3840x2160@25Hz */ 734 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 735 3840, 4896, 4984, 5280, 736 2160, 2168, 2178, 2250, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .vrefresh = 25, }, 739 /* 3 - 3840x2160@24Hz */ 740 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 741 3840, 5116, 5204, 5500, 742 2160, 2168, 2178, 2250, 0, 743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 744 .vrefresh = 24, }, 745 /* 4 - 4096x2160@24Hz (SMPTE) */ 746 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 747 4096, 5116, 5204, 5500, 748 2160, 2168, 2178, 2250, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 24, }, 751 }; 752 753 /* 754 * Autogenerated from the DMT spec. 755 * This table is copied from xfree86/modes/xf86EdidModes.c. 756 */ 757 static const struct drm_display_mode drm_dmt_modes[] = { 758 /* 0x01 - 640x350@85Hz */ 759 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 760 736, 832, 350, 382, 385, 445, 0, 761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 762 /* 0x02 - 640x400@85Hz */ 763 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 764 736, 832, 400, 401, 404, 445, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 766 /* 0x03 - 720x400@85Hz */ 767 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 768 828, 936, 400, 401, 404, 446, 0, 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 770 /* 0x04 - 640x480@60Hz */ 771 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 772 752, 800, 480, 490, 492, 525, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 774 /* 0x05 - 640x480@72Hz */ 775 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 776 704, 832, 480, 489, 492, 520, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 778 /* 0x06 - 640x480@75Hz */ 779 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 780 720, 840, 480, 481, 484, 500, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 782 /* 0x07 - 640x480@85Hz */ 783 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 784 752, 832, 480, 481, 484, 509, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 786 /* 0x08 - 800x600@56Hz */ 787 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 788 896, 1024, 600, 601, 603, 625, 0, 789 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 790 /* 0x09 - 800x600@60Hz */ 791 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 792 968, 1056, 600, 601, 605, 628, 0, 793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 794 /* 0x0a - 800x600@72Hz */ 795 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 796 976, 1040, 600, 637, 643, 666, 0, 797 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 798 /* 0x0b - 800x600@75Hz */ 799 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 800 896, 1056, 600, 601, 604, 625, 0, 801 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 802 /* 0x0c - 800x600@85Hz */ 803 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 804 896, 1048, 600, 601, 604, 631, 0, 805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 806 /* 0x0d - 800x600@120Hz RB */ 807 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 808 880, 960, 600, 603, 607, 636, 0, 809 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 810 /* 0x0e - 848x480@60Hz */ 811 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 812 976, 1088, 480, 486, 494, 517, 0, 813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 814 /* 0x0f - 1024x768@43Hz, interlace */ 815 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 816 1208, 1264, 768, 768, 772, 817, 0, 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 818 DRM_MODE_FLAG_INTERLACE) }, 819 /* 0x10 - 1024x768@60Hz */ 820 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 821 1184, 1344, 768, 771, 777, 806, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 823 /* 0x11 - 1024x768@70Hz */ 824 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 825 1184, 1328, 768, 771, 777, 806, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 827 /* 0x12 - 1024x768@75Hz */ 828 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 829 1136, 1312, 768, 769, 772, 800, 0, 830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 831 /* 0x13 - 1024x768@85Hz */ 832 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 833 1168, 1376, 768, 769, 772, 808, 0, 834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 835 /* 0x14 - 1024x768@120Hz RB */ 836 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 837 1104, 1184, 768, 771, 775, 813, 0, 838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 839 /* 0x15 - 1152x864@75Hz */ 840 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 841 1344, 1600, 864, 865, 868, 900, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 843 /* 0x55 - 1280x720@60Hz */ 844 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 845 1430, 1650, 720, 725, 730, 750, 0, 846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 847 /* 0x16 - 1280x768@60Hz RB */ 848 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 849 1360, 1440, 768, 771, 778, 790, 0, 850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 851 /* 0x17 - 1280x768@60Hz */ 852 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 853 1472, 1664, 768, 771, 778, 798, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 855 /* 0x18 - 1280x768@75Hz */ 856 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 857 1488, 1696, 768, 771, 778, 805, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 859 /* 0x19 - 1280x768@85Hz */ 860 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 861 1496, 1712, 768, 771, 778, 809, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 863 /* 0x1a - 1280x768@120Hz RB */ 864 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 865 1360, 1440, 768, 771, 778, 813, 0, 866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 867 /* 0x1b - 1280x800@60Hz RB */ 868 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 869 1360, 1440, 800, 803, 809, 823, 0, 870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 871 /* 0x1c - 1280x800@60Hz */ 872 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 873 1480, 1680, 800, 803, 809, 831, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 875 /* 0x1d - 1280x800@75Hz */ 876 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 877 1488, 1696, 800, 803, 809, 838, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 879 /* 0x1e - 1280x800@85Hz */ 880 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 881 1496, 1712, 800, 803, 809, 843, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 883 /* 0x1f - 1280x800@120Hz RB */ 884 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 885 1360, 1440, 800, 803, 809, 847, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 887 /* 0x20 - 1280x960@60Hz */ 888 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 889 1488, 1800, 960, 961, 964, 1000, 0, 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 891 /* 0x21 - 1280x960@85Hz */ 892 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 893 1504, 1728, 960, 961, 964, 1011, 0, 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 895 /* 0x22 - 1280x960@120Hz RB */ 896 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 897 1360, 1440, 960, 963, 967, 1017, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 899 /* 0x23 - 1280x1024@60Hz */ 900 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 901 1440, 1688, 1024, 1025, 1028, 1066, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 903 /* 0x24 - 1280x1024@75Hz */ 904 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 905 1440, 1688, 1024, 1025, 1028, 1066, 0, 906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 907 /* 0x25 - 1280x1024@85Hz */ 908 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 909 1504, 1728, 1024, 1025, 1028, 1072, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 911 /* 0x26 - 1280x1024@120Hz RB */ 912 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 913 1360, 1440, 1024, 1027, 1034, 1084, 0, 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 915 /* 0x27 - 1360x768@60Hz */ 916 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 917 1536, 1792, 768, 771, 777, 795, 0, 918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 919 /* 0x28 - 1360x768@120Hz RB */ 920 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 921 1440, 1520, 768, 771, 776, 813, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 923 /* 0x51 - 1366x768@60Hz */ 924 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 925 1579, 1792, 768, 771, 774, 798, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 927 /* 0x56 - 1366x768@60Hz */ 928 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 929 1436, 1500, 768, 769, 772, 800, 0, 930 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 931 /* 0x29 - 1400x1050@60Hz RB */ 932 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 933 1480, 1560, 1050, 1053, 1057, 1080, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 935 /* 0x2a - 1400x1050@60Hz */ 936 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 937 1632, 1864, 1050, 1053, 1057, 1089, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 939 /* 0x2b - 1400x1050@75Hz */ 940 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 941 1648, 1896, 1050, 1053, 1057, 1099, 0, 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 943 /* 0x2c - 1400x1050@85Hz */ 944 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 945 1656, 1912, 1050, 1053, 1057, 1105, 0, 946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 947 /* 0x2d - 1400x1050@120Hz RB */ 948 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 949 1480, 1560, 1050, 1053, 1057, 1112, 0, 950 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 951 /* 0x2e - 1440x900@60Hz RB */ 952 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 953 1520, 1600, 900, 903, 909, 926, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 955 /* 0x2f - 1440x900@60Hz */ 956 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 957 1672, 1904, 900, 903, 909, 934, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 959 /* 0x30 - 1440x900@75Hz */ 960 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 961 1688, 1936, 900, 903, 909, 942, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 963 /* 0x31 - 1440x900@85Hz */ 964 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 965 1696, 1952, 900, 903, 909, 948, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 967 /* 0x32 - 1440x900@120Hz RB */ 968 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 969 1520, 1600, 900, 903, 909, 953, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 971 /* 0x53 - 1600x900@60Hz */ 972 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 973 1704, 1800, 900, 901, 904, 1000, 0, 974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 975 /* 0x33 - 1600x1200@60Hz */ 976 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 977 1856, 2160, 1200, 1201, 1204, 1250, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 979 /* 0x34 - 1600x1200@65Hz */ 980 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 981 1856, 2160, 1200, 1201, 1204, 1250, 0, 982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 983 /* 0x35 - 1600x1200@70Hz */ 984 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 985 1856, 2160, 1200, 1201, 1204, 1250, 0, 986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 987 /* 0x36 - 1600x1200@75Hz */ 988 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 989 1856, 2160, 1200, 1201, 1204, 1250, 0, 990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 991 /* 0x37 - 1600x1200@85Hz */ 992 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 993 1856, 2160, 1200, 1201, 1204, 1250, 0, 994 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 995 /* 0x38 - 1600x1200@120Hz RB */ 996 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 997 1680, 1760, 1200, 1203, 1207, 1271, 0, 998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 999 /* 0x39 - 1680x1050@60Hz RB */ 1000 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1001 1760, 1840, 1050, 1053, 1059, 1080, 0, 1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1003 /* 0x3a - 1680x1050@60Hz */ 1004 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1005 1960, 2240, 1050, 1053, 1059, 1089, 0, 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1007 /* 0x3b - 1680x1050@75Hz */ 1008 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1009 1976, 2272, 1050, 1053, 1059, 1099, 0, 1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1011 /* 0x3c - 1680x1050@85Hz */ 1012 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1013 1984, 2288, 1050, 1053, 1059, 1105, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1015 /* 0x3d - 1680x1050@120Hz RB */ 1016 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1017 1760, 1840, 1050, 1053, 1059, 1112, 0, 1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1019 /* 0x3e - 1792x1344@60Hz */ 1020 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1021 2120, 2448, 1344, 1345, 1348, 1394, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1023 /* 0x3f - 1792x1344@75Hz */ 1024 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1025 2104, 2456, 1344, 1345, 1348, 1417, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1027 /* 0x40 - 1792x1344@120Hz RB */ 1028 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1029 1872, 1952, 1344, 1347, 1351, 1423, 0, 1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1031 /* 0x41 - 1856x1392@60Hz */ 1032 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1033 2176, 2528, 1392, 1393, 1396, 1439, 0, 1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1035 /* 0x42 - 1856x1392@75Hz */ 1036 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1037 2208, 2560, 1392, 1393, 1396, 1500, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1039 /* 0x43 - 1856x1392@120Hz RB */ 1040 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1041 1936, 2016, 1392, 1395, 1399, 1474, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1043 /* 0x52 - 1920x1080@60Hz */ 1044 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1045 2052, 2200, 1080, 1084, 1089, 1125, 0, 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1047 /* 0x44 - 1920x1200@60Hz RB */ 1048 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1049 2000, 2080, 1200, 1203, 1209, 1235, 0, 1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1051 /* 0x45 - 1920x1200@60Hz */ 1052 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1053 2256, 2592, 1200, 1203, 1209, 1245, 0, 1054 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1055 /* 0x46 - 1920x1200@75Hz */ 1056 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1057 2264, 2608, 1200, 1203, 1209, 1255, 0, 1058 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1059 /* 0x47 - 1920x1200@85Hz */ 1060 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1061 2272, 2624, 1200, 1203, 1209, 1262, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1063 /* 0x48 - 1920x1200@120Hz RB */ 1064 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1065 2000, 2080, 1200, 1203, 1209, 1271, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1067 /* 0x49 - 1920x1440@60Hz */ 1068 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1069 2256, 2600, 1440, 1441, 1444, 1500, 0, 1070 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1071 /* 0x4a - 1920x1440@75Hz */ 1072 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1073 2288, 2640, 1440, 1441, 1444, 1500, 0, 1074 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1075 /* 0x4b - 1920x1440@120Hz RB */ 1076 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1077 2000, 2080, 1440, 1443, 1447, 1525, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1079 /* 0x54 - 2048x1152@60Hz */ 1080 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1081 2154, 2250, 1152, 1153, 1156, 1200, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1083 /* 0x4c - 2560x1600@60Hz RB */ 1084 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1085 2640, 2720, 1600, 1603, 1609, 1646, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1087 /* 0x4d - 2560x1600@60Hz */ 1088 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1089 3032, 3504, 1600, 1603, 1609, 1658, 0, 1090 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1091 /* 0x4e - 2560x1600@75Hz */ 1092 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1093 3048, 3536, 1600, 1603, 1609, 1672, 0, 1094 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1095 /* 0x4f - 2560x1600@85Hz */ 1096 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1097 3048, 3536, 1600, 1603, 1609, 1682, 0, 1098 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1099 /* 0x50 - 2560x1600@120Hz RB */ 1100 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1101 2640, 2720, 1600, 1603, 1609, 1694, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1103 /* 0x57 - 4096x2160@60Hz RB */ 1104 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1105 4136, 4176, 2160, 2208, 2216, 2222, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1107 /* 0x58 - 4096x2160@59.94Hz RB */ 1108 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1109 4136, 4176, 2160, 2208, 2216, 2222, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1111 }; 1112 1113 /* 1114 * These more or less come from the DMT spec. The 720x400 modes are 1115 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1116 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1117 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1118 * mode. 1119 * 1120 * The DMT modes have been fact-checked; the rest are mild guesses. 1121 */ 1122 static const struct drm_display_mode edid_est_modes[] = { 1123 /* 800x600@60Hz */ 1124 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1125 968, 1056, 600, 601, 605, 628, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1127 /* 800x600@56Hz */ 1128 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1129 896, 1024, 600, 601, 603, 625, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1131 /* 640x480@75Hz */ 1132 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1133 720, 840, 480, 481, 484, 500, 0, 1134 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1135 /* 640x480@72Hz */ 1136 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1137 704, 832, 480, 489, 492, 520, 0, 1138 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1139 /* 640x480@67Hz */ 1140 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1141 768, 864, 480, 483, 486, 525, 0, 1142 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1143 /* 640x480@60Hz */ 1144 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1145 752, 800, 480, 490, 492, 525, 0, 1146 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1147 /* 720x400@88Hz */ 1148 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1149 846, 900, 400, 421, 423, 449, 0, 1150 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1151 /* 720x400@70Hz */ 1152 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1153 846, 900, 400, 412, 414, 449, 0, 1154 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1155 /* 1280x1024@75Hz */ 1156 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1157 1440, 1688, 1024, 1025, 1028, 1066, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1159 /* 1024x768@75Hz */ 1160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1161 1136, 1312, 768, 769, 772, 800, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1163 /* 1024x768@70Hz */ 1164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1165 1184, 1328, 768, 771, 777, 806, 0, 1166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1167 /* 1024x768@60Hz */ 1168 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1169 1184, 1344, 768, 771, 777, 806, 0, 1170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1171 /* 1024x768@43Hz */ 1172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1173 1208, 1264, 768, 768, 776, 817, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1175 DRM_MODE_FLAG_INTERLACE) }, 1176 /* 832x624@75Hz */ 1177 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1178 928, 1152, 624, 625, 628, 667, 0, 1179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1180 /* 800x600@75Hz */ 1181 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1182 896, 1056, 600, 601, 604, 625, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1184 /* 800x600@72Hz */ 1185 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1186 976, 1040, 600, 637, 643, 666, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1188 /* 1152x864@75Hz */ 1189 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1190 1344, 1600, 864, 865, 868, 900, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1192 }; 1193 1194 struct minimode { 1195 short w; 1196 short h; 1197 short r; 1198 short rb; 1199 }; 1200 1201 static const struct minimode est3_modes[] = { 1202 /* byte 6 */ 1203 { 640, 350, 85, 0 }, 1204 { 640, 400, 85, 0 }, 1205 { 720, 400, 85, 0 }, 1206 { 640, 480, 85, 0 }, 1207 { 848, 480, 60, 0 }, 1208 { 800, 600, 85, 0 }, 1209 { 1024, 768, 85, 0 }, 1210 { 1152, 864, 75, 0 }, 1211 /* byte 7 */ 1212 { 1280, 768, 60, 1 }, 1213 { 1280, 768, 60, 0 }, 1214 { 1280, 768, 75, 0 }, 1215 { 1280, 768, 85, 0 }, 1216 { 1280, 960, 60, 0 }, 1217 { 1280, 960, 85, 0 }, 1218 { 1280, 1024, 60, 0 }, 1219 { 1280, 1024, 85, 0 }, 1220 /* byte 8 */ 1221 { 1360, 768, 60, 0 }, 1222 { 1440, 900, 60, 1 }, 1223 { 1440, 900, 60, 0 }, 1224 { 1440, 900, 75, 0 }, 1225 { 1440, 900, 85, 0 }, 1226 { 1400, 1050, 60, 1 }, 1227 { 1400, 1050, 60, 0 }, 1228 { 1400, 1050, 75, 0 }, 1229 /* byte 9 */ 1230 { 1400, 1050, 85, 0 }, 1231 { 1680, 1050, 60, 1 }, 1232 { 1680, 1050, 60, 0 }, 1233 { 1680, 1050, 75, 0 }, 1234 { 1680, 1050, 85, 0 }, 1235 { 1600, 1200, 60, 0 }, 1236 { 1600, 1200, 65, 0 }, 1237 { 1600, 1200, 70, 0 }, 1238 /* byte 10 */ 1239 { 1600, 1200, 75, 0 }, 1240 { 1600, 1200, 85, 0 }, 1241 { 1792, 1344, 60, 0 }, 1242 { 1792, 1344, 75, 0 }, 1243 { 1856, 1392, 60, 0 }, 1244 { 1856, 1392, 75, 0 }, 1245 { 1920, 1200, 60, 1 }, 1246 { 1920, 1200, 60, 0 }, 1247 /* byte 11 */ 1248 { 1920, 1200, 75, 0 }, 1249 { 1920, 1200, 85, 0 }, 1250 { 1920, 1440, 60, 0 }, 1251 { 1920, 1440, 75, 0 }, 1252 }; 1253 1254 static const struct minimode extra_modes[] = { 1255 { 1024, 576, 60, 0 }, 1256 { 1366, 768, 60, 0 }, 1257 { 1600, 900, 60, 0 }, 1258 { 1680, 945, 60, 0 }, 1259 { 1920, 1080, 60, 0 }, 1260 { 2048, 1152, 60, 0 }, 1261 { 2048, 1536, 60, 0 }, 1262 }; 1263 1264 int edid_check_info(struct edid1_info *edid_info) 1265 { 1266 if ((edid_info == NULL) || (edid_info->version == 0)) 1267 return -1; 1268 1269 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1270 return -1; 1271 1272 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1273 return -1; 1274 1275 return 0; 1276 } 1277 1278 int edid_check_checksum(u8 *edid_block) 1279 { 1280 u8 checksum = 0; 1281 int i; 1282 1283 for (i = 0; i < 128; i++) 1284 checksum += edid_block[i]; 1285 1286 return (checksum == 0) ? 0 : -EINVAL; 1287 } 1288 1289 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1290 unsigned int *hmax, unsigned int *vmin, 1291 unsigned int *vmax) 1292 { 1293 int i; 1294 struct edid_monitor_descriptor *monitor; 1295 1296 *hmin = *hmax = *vmin = *vmax = 0; 1297 if (edid_check_info(edid)) 1298 return -1; 1299 1300 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1301 monitor = &edid->monitor_details.descriptor[i]; 1302 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1303 *hmin = monitor->data.range_data.horizontal_min; 1304 *hmax = monitor->data.range_data.horizontal_max; 1305 *vmin = monitor->data.range_data.vertical_min; 1306 *vmax = monitor->data.range_data.vertical_max; 1307 return 0; 1308 } 1309 } 1310 return -1; 1311 } 1312 1313 /* Set all parts of a timing entry to the same value */ 1314 static void set_entry(struct timing_entry *entry, u32 value) 1315 { 1316 entry->min = value; 1317 entry->typ = value; 1318 entry->max = value; 1319 } 1320 1321 /** 1322 * decode_timing() - Decoding an 18-byte detailed timing record 1323 * 1324 * @buf: Pointer to EDID detailed timing record 1325 * @timing: Place to put timing 1326 */ 1327 static void decode_timing(u8 *buf, struct display_timing *timing) 1328 { 1329 uint x_mm, y_mm; 1330 unsigned int ha, hbl, hso, hspw, hborder; 1331 unsigned int va, vbl, vso, vspw, vborder; 1332 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1333 1334 /* Edid contains pixel clock in terms of 10KHz */ 1335 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1336 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1337 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1338 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1339 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1340 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1341 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1342 hborder = buf[15]; 1343 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1344 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1345 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1346 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1347 vborder = buf[16]; 1348 1349 set_entry(&timing->hactive, ha); 1350 set_entry(&timing->hfront_porch, hso); 1351 set_entry(&timing->hback_porch, hbl - hso - hspw); 1352 set_entry(&timing->hsync_len, hspw); 1353 1354 set_entry(&timing->vactive, va); 1355 set_entry(&timing->vfront_porch, vso); 1356 set_entry(&timing->vback_porch, vbl - vso - vspw); 1357 set_entry(&timing->vsync_len, vspw); 1358 1359 timing->flags = 0; 1360 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1361 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1362 else 1363 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1364 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1365 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1366 else 1367 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1368 1369 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1370 timing->flags = DISPLAY_FLAGS_INTERLACED; 1371 1372 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1373 " %04x %04x %04x %04x hborder %x\n" 1374 " %04x %04x %04x %04x vborder %x\n", 1375 timing->pixelclock.typ, 1376 x_mm, y_mm, 1377 ha, ha + hso, ha + hso + hspw, 1378 ha + hbl, hborder, 1379 va, va + vso, va + vso + vspw, 1380 va + vbl, vborder); 1381 } 1382 1383 /** 1384 * decode_mode() - Decoding an 18-byte detailed timing record 1385 * 1386 * @buf: Pointer to EDID detailed timing record 1387 * @timing: Place to put timing 1388 */ 1389 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1390 { 1391 uint x_mm, y_mm; 1392 unsigned int ha, hbl, hso, hspw, hborder; 1393 unsigned int va, vbl, vso, vspw, vborder; 1394 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1395 1396 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1397 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1398 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1399 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1400 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1401 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1402 hborder = buf[15]; 1403 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1404 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1405 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1406 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1407 vborder = buf[16]; 1408 1409 /* Edid contains pixel clock in terms of 10KHz */ 1410 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1411 mode->hdisplay = ha; 1412 mode->hsync_start = ha + hso; 1413 mode->hsync_end = ha + hso + hspw; 1414 mode->htotal = ha + hbl; 1415 mode->vdisplay = va; 1416 mode->vsync_start = va + vso; 1417 mode->vsync_end = va + vso + vspw; 1418 mode->vtotal = va + vbl; 1419 1420 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1421 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1422 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1423 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1424 1425 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1426 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1427 1428 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1429 " %04d %04d %04d %04d hborder %d\n" 1430 " %04d %04d %04d %04d vborder %d\n", 1431 mode->clock, 1432 x_mm, y_mm, mode->flags, 1433 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1434 mode->htotal, hborder, 1435 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1436 mode->vtotal, vborder); 1437 } 1438 1439 /** 1440 * edid_vendor - match a string against EDID's obfuscated vendor field 1441 * @edid: EDID to match 1442 * @vendor: vendor string 1443 * 1444 * Returns true if @vendor is in @edid, false otherwise 1445 */ 1446 static bool edid_vendor(struct edid *edid, char *vendor) 1447 { 1448 char edid_vendor[3]; 1449 1450 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1451 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1452 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1453 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1454 1455 return !strncmp(edid_vendor, vendor, 3); 1456 } 1457 1458 /** 1459 * Check if HDMI vendor specific data block is present in CEA block 1460 * @param info CEA extension block 1461 * @return true if block is found 1462 */ 1463 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1464 { 1465 u8 end, i = 0; 1466 1467 /* check for end of data block */ 1468 end = info->dtd_offset; 1469 if (end == 0) 1470 end = sizeof(info->data); 1471 if (end < 4 || end > sizeof(info->data)) 1472 return false; 1473 end -= 4; 1474 1475 while (i < end) { 1476 /* Look for vendor specific data block of appropriate size */ 1477 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1478 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1479 u8 *db = &info->data[i + 1]; 1480 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1481 1482 if (oui == HDMI_IEEE_OUI) 1483 return true; 1484 } 1485 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1486 } 1487 1488 return false; 1489 } 1490 1491 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1492 { 1493 int refresh = 0; 1494 unsigned int calc_val; 1495 1496 if (mode->vrefresh > 0) { 1497 refresh = mode->vrefresh; 1498 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1499 int vtotal; 1500 1501 vtotal = mode->vtotal; 1502 /* work out vrefresh the value will be x1000 */ 1503 calc_val = (mode->clock * 1000); 1504 calc_val /= mode->htotal; 1505 refresh = (calc_val + vtotal / 2) / vtotal; 1506 1507 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1508 refresh *= 2; 1509 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1510 refresh /= 2; 1511 if (mode->vscan > 1) 1512 refresh /= mode->vscan; 1513 } 1514 return refresh; 1515 } 1516 1517 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1518 int *panel_bits_per_colourp) 1519 { 1520 struct edid1_info *edid = (struct edid1_info *)buf; 1521 bool timing_done; 1522 int i; 1523 1524 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1525 debug("%s: Invalid buffer\n", __func__); 1526 return -EINVAL; 1527 } 1528 1529 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1530 debug("%s: No preferred timing\n", __func__); 1531 return -ENOENT; 1532 } 1533 1534 /* Look for detailed timing */ 1535 timing_done = false; 1536 for (i = 0; i < 4; i++) { 1537 struct edid_monitor_descriptor *desc; 1538 1539 desc = &edid->monitor_details.descriptor[i]; 1540 if (desc->zero_flag_1 != 0) { 1541 decode_mode((u8 *)desc, mode); 1542 timing_done = true; 1543 break; 1544 } 1545 } 1546 if (!timing_done) 1547 return -EINVAL; 1548 1549 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1550 debug("%s: Not a digital display\n", __func__); 1551 return -ENOSYS; 1552 } 1553 if (edid->version != 1 || edid->revision < 4) { 1554 debug("%s: EDID version %d.%d does not have required info\n", 1555 __func__, edid->version, edid->revision); 1556 *panel_bits_per_colourp = -1; 1557 } else { 1558 *panel_bits_per_colourp = 1559 ((edid->video_input_definition & 0x70) >> 3) + 4; 1560 } 1561 1562 return 0; 1563 } 1564 1565 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 1566 int *panel_bits_per_colourp) 1567 { 1568 struct edid1_info *edid = (struct edid1_info *)buf; 1569 bool timing_done; 1570 int i; 1571 1572 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1573 debug("%s: Invalid buffer\n", __func__); 1574 return -EINVAL; 1575 } 1576 1577 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1578 debug("%s: No preferred timing\n", __func__); 1579 return -ENOENT; 1580 } 1581 1582 /* Look for detailed timing */ 1583 timing_done = false; 1584 for (i = 0; i < 4; i++) { 1585 struct edid_monitor_descriptor *desc; 1586 1587 desc = &edid->monitor_details.descriptor[i]; 1588 if (desc->zero_flag_1 != 0) { 1589 decode_timing((u8 *)desc, timing); 1590 timing_done = true; 1591 break; 1592 } 1593 } 1594 if (!timing_done) 1595 return -EINVAL; 1596 1597 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1598 debug("%s: Not a digital display\n", __func__); 1599 return -ENOSYS; 1600 } 1601 if (edid->version != 1 || edid->revision < 4) { 1602 debug("%s: EDID version %d.%d does not have required info\n", 1603 __func__, edid->version, edid->revision); 1604 *panel_bits_per_colourp = -1; 1605 } else { 1606 *panel_bits_per_colourp = 1607 ((edid->video_input_definition & 0x70) >> 3) + 4; 1608 } 1609 1610 timing->hdmi_monitor = false; 1611 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 1612 struct edid_cea861_info *info = 1613 (struct edid_cea861_info *)(buf + sizeof(*edid)); 1614 1615 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 1616 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 1617 } 1618 1619 return 0; 1620 } 1621 1622 /** 1623 * Snip the tailing whitespace/return of a string. 1624 * 1625 * @param string The string to be snipped 1626 * @return the snipped string 1627 */ 1628 static char *snip(char *string) 1629 { 1630 char *s; 1631 1632 /* 1633 * This is always a 13 character buffer 1634 * and it's not always terminated. 1635 */ 1636 string[12] = '\0'; 1637 s = &string[strlen(string) - 1]; 1638 1639 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 1640 *s == '\0')) 1641 *(s--) = '\0'; 1642 1643 return string; 1644 } 1645 1646 /** 1647 * Print an EDID monitor descriptor block 1648 * 1649 * @param monitor The EDID monitor descriptor block 1650 * @have_timing Modifies to 1 if the desciptor contains timing info 1651 */ 1652 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 1653 unsigned int *have_timing) 1654 { 1655 unsigned char *bytes = (unsigned char *)monitor; 1656 struct edid_detailed_timing *timing = 1657 (struct edid_detailed_timing *)monitor; 1658 1659 if (bytes[0] == 0 && bytes[1] == 0) { 1660 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 1661 printf("Monitor serial number: %s\n", 1662 snip(monitor->data.string)); 1663 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 1664 printf("Monitor ID: %s\n", 1665 snip(monitor->data.string)); 1666 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 1667 printf("Monitor name: %s\n", 1668 snip(monitor->data.string)); 1669 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 1670 printf("Monitor range limits, horizontal sync: " 1671 "%d-%d kHz, vertical refresh: " 1672 "%d-%d Hz, max pixel clock: " 1673 "%d MHz\n", 1674 monitor->data.range_data.horizontal_min, 1675 monitor->data.range_data.horizontal_max, 1676 monitor->data.range_data.vertical_min, 1677 monitor->data.range_data.vertical_max, 1678 monitor->data.range_data.pixel_clock_max * 10); 1679 } else { 1680 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 1681 u32 h_total, v_total, vfreq; 1682 1683 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 1684 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 1685 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 1686 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 1687 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 1688 1689 h_total = h_active + h_blanking; 1690 v_total = v_active + v_blanking; 1691 if (v_total > 0 && h_total > 0) 1692 vfreq = pixclock / (v_total * h_total); 1693 else 1694 vfreq = 1; /* Error case */ 1695 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 1696 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 1697 *have_timing = 1; 1698 } 1699 } 1700 1701 /** 1702 * Get the manufacturer name from an EDID info. 1703 * 1704 * @param edid_info The EDID info to be printed 1705 * @param name Returns the string of the manufacturer name 1706 */ 1707 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 1708 { 1709 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 1710 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 1711 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 1712 name[3] = '\0'; 1713 } 1714 1715 void edid_print_info(struct edid1_info *edid_info) 1716 { 1717 int i; 1718 char manufacturer[4]; 1719 unsigned int have_timing = 0; 1720 u32 serial_number; 1721 1722 if (edid_check_info(edid_info)) { 1723 printf("Not a valid EDID\n"); 1724 return; 1725 } 1726 1727 printf("EDID version: %d.%d\n", 1728 edid_info->version, edid_info->revision); 1729 1730 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 1731 1732 edid_get_manufacturer_name(edid_info, manufacturer); 1733 printf("Manufacturer: %s\n", manufacturer); 1734 1735 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 1736 if (serial_number != 0xffffffff) { 1737 if (strcmp(manufacturer, "MAG") == 0) 1738 serial_number -= 0x7000000; 1739 if (strcmp(manufacturer, "OQI") == 0) 1740 serial_number -= 456150000; 1741 if (strcmp(manufacturer, "VSC") == 0) 1742 serial_number -= 640000000; 1743 } 1744 printf("Serial number: %08x\n", serial_number); 1745 printf("Manufactured in week: %d year: %d\n", 1746 edid_info->week, edid_info->year + 1990); 1747 1748 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 1749 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 1750 "digital signal, " : "analog signal, ", 1751 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 1752 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 1753 ", blank to black" : "", 1754 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 1755 ", separate sync" : "", 1756 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 1757 ", composite sync" : "", 1758 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 1759 ", sync on green" : "", 1760 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 1761 ", serration v" : ""); 1762 1763 printf("Monitor is %s\n", 1764 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 1765 1766 printf("Maximum visible display size: %d cm x %d cm\n", 1767 edid_info->max_size_horizontal, 1768 edid_info->max_size_vertical); 1769 1770 printf("Power management features: %s%s, %s%s, %s%s\n", 1771 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 1772 "" : "no ", "active off", 1773 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 1774 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 1775 1776 printf("Estabilished timings:\n"); 1777 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 1778 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 1779 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 1780 printf("\t720x400\t\t88 Hz (XGA2)\n"); 1781 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 1782 printf("\t640x480\t\t60 Hz (VGA)\n"); 1783 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 1784 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 1785 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 1786 printf("\t640x480\t\t72 Hz (VESA)\n"); 1787 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 1788 printf("\t640x480\t\t75 Hz (VESA)\n"); 1789 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 1790 printf("\t800x600\t\t56 Hz (VESA)\n"); 1791 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 1792 printf("\t800x600\t\t60 Hz (VESA)\n"); 1793 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 1794 printf("\t800x600\t\t72 Hz (VESA)\n"); 1795 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 1796 printf("\t800x600\t\t75 Hz (VESA)\n"); 1797 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 1798 printf("\t832x624\t\t75 Hz (Mac II)\n"); 1799 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 1800 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 1801 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 1802 printf("\t1024x768\t60 Hz (VESA)\n"); 1803 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 1804 printf("\t1024x768\t70 Hz (VESA)\n"); 1805 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 1806 printf("\t1024x768\t75 Hz (VESA)\n"); 1807 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 1808 printf("\t1280x1024\t75 (VESA)\n"); 1809 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 1810 printf("\t1152x870\t75 (Mac II)\n"); 1811 1812 /* Standard timings. */ 1813 printf("Standard timings:\n"); 1814 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 1815 unsigned int aspect = 10000; 1816 unsigned int x, y; 1817 unsigned char xres, vfreq; 1818 1819 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 1820 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 1821 if ((xres != vfreq) || 1822 ((xres != 0) && (xres != 1)) || 1823 ((vfreq != 0) && (vfreq != 1))) { 1824 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 1825 i)) { 1826 case ASPECT_625: 1827 aspect = 6250; 1828 break; 1829 case ASPECT_75: 1830 aspect = 7500; 1831 break; 1832 case ASPECT_8: 1833 aspect = 8000; 1834 break; 1835 case ASPECT_5625: 1836 aspect = 5625; 1837 break; 1838 } 1839 x = (xres + 31) * 8; 1840 y = x * aspect / 10000; 1841 printf("\t%dx%d%c\t%d Hz\n", x, y, 1842 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 1843 have_timing = 1; 1844 } 1845 } 1846 1847 /* Detailed timing information. */ 1848 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 1849 i++) { 1850 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 1851 &have_timing); 1852 } 1853 1854 if (!have_timing) 1855 printf("\tNone\n"); 1856 } 1857 1858 /** 1859 * drm_mode_create - create a new display mode 1860 * 1861 * Create a new, cleared drm_display_mode. 1862 * 1863 * Returns: 1864 * Pointer to new mode on success, NULL on error. 1865 */ 1866 static struct drm_display_mode *drm_mode_create(void) 1867 { 1868 struct drm_display_mode *nmode; 1869 1870 nmode = malloc(sizeof(struct drm_display_mode)); 1871 memset(nmode, 0, sizeof(struct drm_display_mode)); 1872 if (!nmode) 1873 return NULL; 1874 1875 return nmode; 1876 } 1877 1878 /** 1879 * drm_mode_destroy - remove a mode 1880 * @mode: mode to remove 1881 * 1882 */ 1883 static void drm_mode_destroy(struct drm_display_mode *mode) 1884 { 1885 if (!mode) 1886 return; 1887 1888 kfree(mode); 1889 } 1890 1891 /** 1892 * drm_cvt_mode -create a modeline based on the CVT algorithm 1893 * @hdisplay: hdisplay size 1894 * @vdisplay: vdisplay size 1895 * @vrefresh: vrefresh rate 1896 * @reduced: whether to use reduced blanking 1897 * @interlaced: whether to compute an interlaced mode 1898 * @margins: whether to add margins (borders) 1899 * 1900 * This function is called to generate the modeline based on CVT algorithm 1901 * according to the hdisplay, vdisplay, vrefresh. 1902 * It is based from the VESA(TM) Coordinated Video Timing Generator by 1903 * Graham Loveridge April 9, 2003 available at 1904 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 1905 * 1906 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 1907 * What I have done is to translate it by using integer calculation. 1908 * 1909 * Returns: 1910 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 1911 * The display mode object is allocated with drm_mode_create(). Returns NULL 1912 * when no mode could be allocated. 1913 */ 1914 static 1915 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 1916 bool reduced, bool interlaced, 1917 bool margins) 1918 { 1919 #define HV_FACTOR 1000 1920 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 1921 #define CVT_MARGIN_PERCENTAGE 18 1922 /* 2) character cell horizontal granularity (pixels) - default 8 */ 1923 #define CVT_H_GRANULARITY 8 1924 /* 3) Minimum vertical porch (lines) - default 3 */ 1925 #define CVT_MIN_V_PORCH 3 1926 /* 4) Minimum number of vertical back porch lines - default 6 */ 1927 #define CVT_MIN_V_BPORCH 6 1928 /* Pixel Clock step (kHz) */ 1929 #define CVT_CLOCK_STEP 250 1930 struct drm_display_mode *drm_mode; 1931 unsigned int vfieldrate, hperiod; 1932 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 1933 int interlace; 1934 1935 /* allocate the drm_display_mode structure. If failure, we will 1936 * return directly 1937 */ 1938 drm_mode = drm_mode_create(); 1939 if (!drm_mode) 1940 return NULL; 1941 1942 /* the CVT default refresh rate is 60Hz */ 1943 if (!vrefresh) 1944 vrefresh = 60; 1945 1946 /* the required field fresh rate */ 1947 if (interlaced) 1948 vfieldrate = vrefresh * 2; 1949 else 1950 vfieldrate = vrefresh; 1951 1952 /* horizontal pixels */ 1953 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 1954 1955 /* determine the left&right borders */ 1956 hmargin = 0; 1957 if (margins) { 1958 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1959 hmargin -= hmargin % CVT_H_GRANULARITY; 1960 } 1961 /* find the total active pixels */ 1962 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 1963 1964 /* find the number of lines per field */ 1965 if (interlaced) 1966 vdisplay_rnd = vdisplay / 2; 1967 else 1968 vdisplay_rnd = vdisplay; 1969 1970 /* find the top & bottom borders */ 1971 vmargin = 0; 1972 if (margins) 1973 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1974 1975 drm_mode->vdisplay = vdisplay + 2 * vmargin; 1976 1977 /* Interlaced */ 1978 if (interlaced) 1979 interlace = 1; 1980 else 1981 interlace = 0; 1982 1983 /* Determine VSync Width from aspect ratio */ 1984 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 1985 vsync = 4; 1986 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 1987 vsync = 5; 1988 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 1989 vsync = 6; 1990 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 1991 vsync = 7; 1992 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 1993 vsync = 7; 1994 else /* custom */ 1995 vsync = 10; 1996 1997 if (!reduced) { 1998 /* simplify the GTF calculation */ 1999 /* 4) Minimum time of vertical sync + back porch interval 2000 * default 550.0 2001 */ 2002 int tmp1, tmp2; 2003 #define CVT_MIN_VSYNC_BP 550 2004 /* 3) Nominal HSync width (% of line period) - default 8 */ 2005 #define CVT_HSYNC_PERCENTAGE 8 2006 unsigned int hblank_percentage; 2007 int vsyncandback_porch, hblank; 2008 2009 /* estimated the horizontal period */ 2010 tmp1 = HV_FACTOR * 1000000 - 2011 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2012 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2013 interlace; 2014 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2015 2016 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2017 /* 9. Find number of lines in sync + backporch */ 2018 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2019 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2020 else 2021 vsyncandback_porch = tmp1; 2022 /* 10. Find number of lines in back porch 2023 * vback_porch = vsyncandback_porch - vsync; 2024 */ 2025 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2026 vsyncandback_porch + CVT_MIN_V_PORCH; 2027 /* 5) Definition of Horizontal blanking time limitation */ 2028 /* Gradient (%/kHz) - default 600 */ 2029 #define CVT_M_FACTOR 600 2030 /* Offset (%) - default 40 */ 2031 #define CVT_C_FACTOR 40 2032 /* Blanking time scaling factor - default 128 */ 2033 #define CVT_K_FACTOR 128 2034 /* Scaling factor weighting - default 20 */ 2035 #define CVT_J_FACTOR 20 2036 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2037 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2038 CVT_J_FACTOR) 2039 /* 12. Find ideal blanking duty cycle from formula */ 2040 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2041 hperiod / 1000; 2042 /* 13. Blanking time */ 2043 if (hblank_percentage < 20 * HV_FACTOR) 2044 hblank_percentage = 20 * HV_FACTOR; 2045 hblank = drm_mode->hdisplay * hblank_percentage / 2046 (100 * HV_FACTOR - hblank_percentage); 2047 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2048 /* 14. find the total pixels per line */ 2049 drm_mode->htotal = drm_mode->hdisplay + hblank; 2050 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2051 drm_mode->hsync_start = drm_mode->hsync_end - 2052 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2053 drm_mode->hsync_start += CVT_H_GRANULARITY - 2054 drm_mode->hsync_start % CVT_H_GRANULARITY; 2055 /* fill the Vsync values */ 2056 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2057 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2058 } else { 2059 /* Reduced blanking */ 2060 /* Minimum vertical blanking interval time - default 460 */ 2061 #define CVT_RB_MIN_VBLANK 460 2062 /* Fixed number of clocks for horizontal sync */ 2063 #define CVT_RB_H_SYNC 32 2064 /* Fixed number of clocks for horizontal blanking */ 2065 #define CVT_RB_H_BLANK 160 2066 /* Fixed number of lines for vertical front porch - default 3*/ 2067 #define CVT_RB_VFPORCH 3 2068 int vbilines; 2069 int tmp1, tmp2; 2070 /* 8. Estimate Horizontal period. */ 2071 tmp1 = HV_FACTOR * 1000000 - 2072 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2073 tmp2 = vdisplay_rnd + 2 * vmargin; 2074 hperiod = tmp1 / (tmp2 * vfieldrate); 2075 /* 9. Find number of lines in vertical blanking */ 2076 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2077 /* 10. Check if vertical blanking is sufficient */ 2078 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2079 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2080 /* 11. Find total number of lines in vertical field */ 2081 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2082 /* 12. Find total number of pixels in a line */ 2083 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2084 /* Fill in HSync values */ 2085 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2086 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2087 /* Fill in VSync values */ 2088 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2089 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2090 } 2091 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2092 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2093 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2094 /* 18/16. Find actual vertical frame frequency */ 2095 /* ignore - just set the mode flag for interlaced */ 2096 if (interlaced) { 2097 drm_mode->vtotal *= 2; 2098 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2099 } 2100 2101 if (reduced) 2102 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2103 DRM_MODE_FLAG_NVSYNC); 2104 else 2105 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2106 DRM_MODE_FLAG_NHSYNC); 2107 2108 return drm_mode; 2109 } 2110 2111 static int 2112 cea_db_payload_len(const u8 *db) 2113 { 2114 return db[0] & 0x1f; 2115 } 2116 2117 static int 2118 cea_db_extended_tag(const u8 *db) 2119 { 2120 return db[1]; 2121 } 2122 2123 static int 2124 cea_db_tag(const u8 *db) 2125 { 2126 return db[0] >> 5; 2127 } 2128 2129 #define for_each_cea_db(cea, i, start, end) \ 2130 for ((i) = (start); (i) < (end) && (i) + \ 2131 cea_db_payload_len(&(cea)[(i)]) < \ 2132 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2133 2134 static int 2135 cea_revision(const u8 *cea) 2136 { 2137 return cea[1]; 2138 } 2139 2140 static int 2141 cea_db_offsets(const u8 *cea, int *start, int *end) 2142 { 2143 /* Data block offset in CEA extension block */ 2144 *start = 4; 2145 *end = cea[2]; 2146 if (*end == 0) 2147 *end = 127; 2148 if (*end < 4 || *end > 127) 2149 return -ERANGE; 2150 2151 /* 2152 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2153 */ 2154 if (*end != 4) { 2155 int i; 2156 2157 i = *start; 2158 while (i < (*end) && 2159 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2160 i += cea_db_payload_len(&(cea)[i]) + 1; 2161 2162 if (cea_db_payload_len(&(cea)[i]) && 2163 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2164 (*end)++; 2165 } 2166 2167 return 0; 2168 } 2169 2170 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2171 { 2172 int hdmi_id; 2173 2174 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2175 return false; 2176 2177 if (cea_db_payload_len(db) < 5) 2178 return false; 2179 2180 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2181 2182 return hdmi_id == HDMI_IEEE_OUI; 2183 } 2184 2185 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2186 { 2187 unsigned int oui; 2188 2189 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2190 return false; 2191 2192 if (cea_db_payload_len(db) < 7) 2193 return false; 2194 2195 oui = db[3] << 16 | db[2] << 8 | db[1]; 2196 2197 return oui == HDMI_FORUM_IEEE_OUI; 2198 } 2199 2200 static bool cea_db_is_y420cmdb(const u8 *db) 2201 { 2202 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2203 return false; 2204 2205 if (!cea_db_payload_len(db)) 2206 return false; 2207 2208 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2209 return false; 2210 2211 return true; 2212 } 2213 2214 static bool cea_db_is_y420vdb(const u8 *db) 2215 { 2216 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2217 return false; 2218 2219 if (!cea_db_payload_len(db)) 2220 return false; 2221 2222 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2223 return false; 2224 2225 return true; 2226 } 2227 2228 static bool drm_valid_hdmi_vic(u8 vic) 2229 { 2230 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2231 } 2232 2233 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2234 const struct drm_display_mode *mode) 2235 { 2236 struct drm_display_mode *mode_buf = data->mode_buf; 2237 2238 if (data->modes >= MODE_LEN) 2239 return; 2240 mode_buf[(data->modes)++] = *mode; 2241 } 2242 2243 static bool drm_valid_cea_vic(u8 vic) 2244 { 2245 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2246 } 2247 2248 static u8 svd_to_vic(u8 svd) 2249 { 2250 /* 0-6 bit vic, 7th bit native mode indicator */ 2251 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2252 return svd & 127; 2253 2254 return svd; 2255 } 2256 2257 static struct drm_display_mode * 2258 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2259 u8 video_index) 2260 { 2261 struct drm_display_mode *newmode; 2262 u8 vic; 2263 2264 if (!video_db || video_index >= video_len) 2265 return NULL; 2266 2267 /* CEA modes are numbered 1..127 */ 2268 vic = svd_to_vic(video_db[video_index]); 2269 if (!drm_valid_cea_vic(vic)) 2270 return NULL; 2271 2272 newmode = drm_mode_create(); 2273 if (!newmode) 2274 return NULL; 2275 2276 *newmode = edid_cea_modes[vic]; 2277 newmode->vrefresh = 0; 2278 2279 return newmode; 2280 } 2281 2282 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2283 { 2284 unsigned long *p = map + BIT_WORD(start); 2285 const unsigned int size = start + len; 2286 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2287 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2288 2289 while (len - bits_to_set >= 0) { 2290 *p |= mask_to_set; 2291 len -= bits_to_set; 2292 bits_to_set = BITS_PER_LONG; 2293 mask_to_set = ~0UL; 2294 p++; 2295 } 2296 if (len) { 2297 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2298 *p |= mask_to_set; 2299 } 2300 } 2301 2302 static void 2303 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2304 { 2305 u8 vic = svd_to_vic(svd); 2306 2307 if (!drm_valid_cea_vic(vic)) 2308 return; 2309 2310 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2311 } 2312 2313 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2314 { 2315 int i, modes = 0; 2316 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2317 2318 for (i = 0; i < len; i++) { 2319 struct drm_display_mode *mode; 2320 2321 mode = drm_display_mode_from_vic_index(db, len, i); 2322 if (mode) { 2323 /* 2324 * YCBCR420 capability block contains a bitmap which 2325 * gives the index of CEA modes from CEA VDB, which 2326 * can support YCBCR 420 sampling output also (apart 2327 * from RGB/YCBCR444 etc). 2328 * For example, if the bit 0 in bitmap is set, 2329 * first mode in VDB can support YCBCR420 output too. 2330 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2331 */ 2332 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2333 drm_add_cmdb_modes(db[i], hdmi); 2334 drm_add_hdmi_modes(data, mode); 2335 drm_mode_destroy(mode); 2336 modes++; 2337 } 2338 } 2339 2340 return modes; 2341 } 2342 2343 /* 2344 * do_y420vdb_modes - Parse YCBCR 420 only modes 2345 * @data: the structure that save parsed hdmi edid data 2346 * @svds: start of the data block of CEA YCBCR 420 VDB 2347 * @svds_len: length of the CEA YCBCR 420 VDB 2348 * @hdmi: runtime information about the connected HDMI sink 2349 * 2350 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2351 * which contains modes which can be supported in YCBCR 420 2352 * output format only. 2353 */ 2354 static int 2355 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2356 { 2357 int modes = 0, i; 2358 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2359 2360 for (i = 0; i < svds_len; i++) { 2361 u8 vic = svd_to_vic(svds[i]); 2362 2363 if (!drm_valid_cea_vic(vic)) 2364 continue; 2365 2366 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2367 drm_add_hdmi_modes(data, &edid_cea_modes[vic]); 2368 modes++; 2369 } 2370 2371 return modes; 2372 } 2373 2374 struct stereo_mandatory_mode { 2375 int width, height, vrefresh; 2376 unsigned int flags; 2377 }; 2378 2379 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2380 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2381 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2382 { 1920, 1080, 50, 2383 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2384 { 1920, 1080, 60, 2385 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2386 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2387 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2388 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2389 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2390 }; 2391 2392 static bool 2393 stereo_match_mandatory(const struct drm_display_mode *mode, 2394 const struct stereo_mandatory_mode *stereo_mode) 2395 { 2396 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2397 2398 return mode->hdisplay == stereo_mode->width && 2399 mode->vdisplay == stereo_mode->height && 2400 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2401 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2402 } 2403 2404 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2405 { 2406 const struct drm_display_mode *mode; 2407 int num = data->modes, modes = 0, i, k; 2408 2409 for (k = 0; k < num; k++) { 2410 mode = &data->mode_buf[k]; 2411 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2412 const struct stereo_mandatory_mode *mandatory; 2413 struct drm_display_mode *new_mode; 2414 2415 if (!stereo_match_mandatory(mode, 2416 &stereo_mandatory_modes[i])) 2417 continue; 2418 2419 mandatory = &stereo_mandatory_modes[i]; 2420 new_mode = drm_mode_create(); 2421 if (!new_mode) 2422 continue; 2423 2424 *new_mode = *mode; 2425 new_mode->flags |= mandatory->flags; 2426 drm_add_hdmi_modes(data, new_mode); 2427 drm_mode_destroy(new_mode); 2428 modes++; 2429 } 2430 } 2431 2432 return modes; 2433 } 2434 2435 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2436 const u8 *video_db, u8 video_len, u8 video_index) 2437 { 2438 struct drm_display_mode *newmode; 2439 int modes = 0; 2440 2441 if (structure & (1 << 0)) { 2442 newmode = drm_display_mode_from_vic_index(video_db, 2443 video_len, 2444 video_index); 2445 if (newmode) { 2446 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2447 drm_add_hdmi_modes(data, newmode); 2448 modes++; 2449 drm_mode_destroy(newmode); 2450 } 2451 } 2452 if (structure & (1 << 6)) { 2453 newmode = drm_display_mode_from_vic_index(video_db, 2454 video_len, 2455 video_index); 2456 if (newmode) { 2457 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2458 drm_add_hdmi_modes(data, newmode); 2459 modes++; 2460 drm_mode_destroy(newmode); 2461 } 2462 } 2463 if (structure & (1 << 8)) { 2464 newmode = drm_display_mode_from_vic_index(video_db, 2465 video_len, 2466 video_index); 2467 if (newmode) { 2468 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2469 drm_add_hdmi_modes(data, newmode); 2470 modes++; 2471 drm_mode_destroy(newmode); 2472 } 2473 } 2474 2475 return modes; 2476 } 2477 2478 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2479 { 2480 if (!drm_valid_hdmi_vic(vic)) { 2481 debug("Unknown HDMI VIC: %d\n", vic); 2482 return 0; 2483 } 2484 2485 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2486 2487 return 1; 2488 } 2489 2490 /* 2491 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2492 * @db: start of the CEA vendor specific block 2493 * @len: length of the CEA block payload, ie. one can access up to db[len] 2494 * 2495 * Parses the HDMI VSDB looking for modes to add to @data. This function 2496 * also adds the stereo 3d modes when applicable. 2497 */ 2498 static int 2499 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2500 struct hdmi_edid_data *data) 2501 { 2502 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2503 u8 vic_len, hdmi_3d_len = 0; 2504 u16 mask; 2505 u16 structure_all; 2506 2507 if (len < 8) 2508 goto out; 2509 2510 /* no HDMI_Video_Present */ 2511 if (!(db[8] & (1 << 5))) 2512 goto out; 2513 2514 /* Latency_Fields_Present */ 2515 if (db[8] & (1 << 7)) 2516 offset += 2; 2517 2518 /* I_Latency_Fields_Present */ 2519 if (db[8] & (1 << 6)) 2520 offset += 2; 2521 2522 /* the declared length is not long enough for the 2 first bytes 2523 * of additional video format capabilities 2524 */ 2525 if (len < (8 + offset + 2)) 2526 goto out; 2527 2528 /* 3D_Present */ 2529 offset++; 2530 if (db[8 + offset] & (1 << 7)) { 2531 modes += add_hdmi_mandatory_stereo_modes(data); 2532 2533 /* 3D_Multi_present */ 2534 multi_present = (db[8 + offset] & 0x60) >> 5; 2535 } 2536 2537 offset++; 2538 vic_len = db[8 + offset] >> 5; 2539 hdmi_3d_len = db[8 + offset] & 0x1f; 2540 2541 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2542 u8 vic; 2543 2544 vic = db[9 + offset + i]; 2545 modes += add_hdmi_mode(data, vic); 2546 } 2547 2548 offset += 1 + vic_len; 2549 2550 if (multi_present == 1) 2551 multi_len = 2; 2552 else if (multi_present == 2) 2553 multi_len = 4; 2554 else 2555 multi_len = 0; 2556 2557 if (len < (8 + offset + hdmi_3d_len - 1)) 2558 goto out; 2559 2560 if (hdmi_3d_len < multi_len) 2561 goto out; 2562 2563 if (multi_present == 1 || multi_present == 2) { 2564 /* 3D_Structure_ALL */ 2565 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2566 2567 /* check if 3D_MASK is present */ 2568 if (multi_present == 2) 2569 mask = (db[10 + offset] << 8) | db[11 + offset]; 2570 else 2571 mask = 0xffff; 2572 2573 for (i = 0; i < 16; i++) { 2574 if (mask & (1 << i)) 2575 modes += add_3d_struct_modes(data, 2576 structure_all, 2577 video_db, 2578 video_len, i); 2579 } 2580 } 2581 2582 offset += multi_len; 2583 2584 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2585 int vic_index; 2586 struct drm_display_mode *newmode = NULL; 2587 unsigned int newflag = 0; 2588 bool detail_present; 2589 2590 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2591 2592 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2593 break; 2594 2595 /* 2D_VIC_order_X */ 2596 vic_index = db[8 + offset + i] >> 4; 2597 2598 /* 3D_Structure_X */ 2599 switch (db[8 + offset + i] & 0x0f) { 2600 case 0: 2601 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2602 break; 2603 case 6: 2604 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2605 break; 2606 case 8: 2607 /* 3D_Detail_X */ 2608 if ((db[9 + offset + i] >> 4) == 1) 2609 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2610 break; 2611 } 2612 2613 if (newflag != 0) { 2614 newmode = drm_display_mode_from_vic_index( 2615 video_db, 2616 video_len, 2617 vic_index); 2618 2619 if (newmode) { 2620 newmode->flags |= newflag; 2621 drm_add_hdmi_modes(data, newmode); 2622 modes++; 2623 drm_mode_destroy(newmode); 2624 } 2625 } 2626 2627 if (detail_present) 2628 i++; 2629 } 2630 2631 out: 2632 return modes; 2633 } 2634 2635 /** 2636 * edid_get_quirks - return quirk flags for a given EDID 2637 * @edid: EDID to process 2638 * 2639 * This tells subsequent routines what fixes they need to apply. 2640 */ 2641 static u32 edid_get_quirks(struct edid *edid) 2642 { 2643 struct edid_quirk *quirk; 2644 int i; 2645 2646 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2647 quirk = &edid_quirk_list[i]; 2648 2649 if (edid_vendor(edid, quirk->vendor) && 2650 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2651 return quirk->quirks; 2652 } 2653 2654 return 0; 2655 } 2656 2657 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 2658 const u8 *db) 2659 { 2660 struct drm_display_info *info = &data->display_info; 2661 struct drm_hdmi_info *hdmi = &info->hdmi; 2662 u8 map_len = cea_db_payload_len(db) - 1; 2663 u8 count; 2664 u64 map = 0; 2665 2666 if (map_len == 0) { 2667 /* All CEA modes support ycbcr420 sampling also.*/ 2668 hdmi->y420_cmdb_map = U64_MAX; 2669 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2670 return; 2671 } 2672 2673 /* 2674 * This map indicates which of the existing CEA block modes 2675 * from VDB can support YCBCR420 output too. So if bit=0 is 2676 * set, first mode from VDB can support YCBCR420 output too. 2677 * We will parse and keep this map, before parsing VDB itself 2678 * to avoid going through the same block again and again. 2679 * 2680 * Spec is not clear about max possible size of this block. 2681 * Clamping max bitmap block size at 8 bytes. Every byte can 2682 * address 8 CEA modes, in this way this map can address 2683 * 8*8 = first 64 SVDs. 2684 */ 2685 if (map_len > 8) 2686 map_len = 8; 2687 2688 for (count = 0; count < map_len; count++) 2689 map |= (u64)db[2 + count] << (8 * count); 2690 2691 if (map) 2692 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2693 2694 hdmi->y420_cmdb_map = map; 2695 } 2696 2697 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 2698 const u8 *db) 2699 { 2700 u8 dc_mask; 2701 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2702 2703 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 2704 hdmi->y420_dc_modes |= dc_mask; 2705 } 2706 2707 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 2708 const u8 *hf_vsdb) 2709 { 2710 struct drm_display_info *display = &data->display_info; 2711 struct drm_hdmi_info *hdmi = &display->hdmi; 2712 2713 if (hf_vsdb[6] & 0x80) { 2714 hdmi->scdc.supported = true; 2715 if (hf_vsdb[6] & 0x40) 2716 hdmi->scdc.read_request = true; 2717 } 2718 2719 /* 2720 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 2721 * And as per the spec, three factors confirm this: 2722 * * Availability of a HF-VSDB block in EDID (check) 2723 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 2724 * * SCDC support available (let's check) 2725 * Lets check it out. 2726 */ 2727 2728 if (hf_vsdb[5]) { 2729 /* max clock is 5000 KHz times block value */ 2730 u32 max_tmds_clock = hf_vsdb[5] * 5000; 2731 struct drm_scdc *scdc = &hdmi->scdc; 2732 2733 if (max_tmds_clock > 340000) { 2734 display->max_tmds_clock = max_tmds_clock; 2735 debug("HF-VSDB: max TMDS clock %d kHz\n", 2736 display->max_tmds_clock); 2737 } 2738 2739 if (scdc->supported) { 2740 scdc->scrambling.supported = true; 2741 2742 /* Few sinks support scrambling for cloks < 340M */ 2743 if ((hf_vsdb[6] & 0x8)) 2744 scdc->scrambling.low_rates = true; 2745 } 2746 } 2747 2748 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 2749 } 2750 2751 /** 2752 * drm_default_rgb_quant_range - default RGB quantization range 2753 * @mode: display mode 2754 * 2755 * Determine the default RGB quantization range for the mode, 2756 * as specified in CEA-861. 2757 * 2758 * Return: The default RGB quantization range for the mode 2759 */ 2760 enum hdmi_quantization_range 2761 drm_default_rgb_quant_range(struct drm_display_mode *mode) 2762 { 2763 /* All CEA modes other than VIC 1 use limited quantization range. */ 2764 return drm_match_cea_mode(mode) > 1 ? 2765 HDMI_QUANTIZATION_RANGE_LIMITED : 2766 HDMI_QUANTIZATION_RANGE_FULL; 2767 } 2768 2769 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 2770 const u8 *hdmi) 2771 { 2772 struct drm_display_info *info = &data->display_info; 2773 unsigned int dc_bpc = 0; 2774 2775 /* HDMI supports at least 8 bpc */ 2776 info->bpc = 8; 2777 2778 if (cea_db_payload_len(hdmi) < 6) 2779 return; 2780 2781 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 2782 dc_bpc = 10; 2783 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 2784 debug("HDMI sink does deep color 30.\n"); 2785 } 2786 2787 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 2788 dc_bpc = 12; 2789 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 2790 debug("HDMI sink does deep color 36.\n"); 2791 } 2792 2793 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 2794 dc_bpc = 16; 2795 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 2796 debug("HDMI sink does deep color 48.\n"); 2797 } 2798 2799 if (dc_bpc == 0) { 2800 debug("No deep color support on this HDMI sink.\n"); 2801 return; 2802 } 2803 2804 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 2805 info->bpc = dc_bpc; 2806 2807 /* YCRCB444 is optional according to spec. */ 2808 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 2809 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 2810 debug("HDMI sink does YCRCB444 in deep color.\n"); 2811 } 2812 2813 /* 2814 * Spec says that if any deep color mode is supported at all, 2815 * then deep color 36 bit must be supported. 2816 */ 2817 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 2818 debug("HDMI sink should do DC_36, but does not!\n"); 2819 } 2820 2821 /* 2822 * Search EDID for CEA extension block. 2823 */ 2824 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2825 { 2826 u8 *edid_ext = NULL; 2827 int i; 2828 2829 /* No EDID or EDID extensions */ 2830 if (!edid || !edid->extensions) 2831 return NULL; 2832 2833 /* Find CEA extension */ 2834 for (i = 0; i < edid->extensions; i++) { 2835 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 2836 if (edid_ext[0] == ext_id) 2837 break; 2838 } 2839 2840 if (i == edid->extensions) 2841 return NULL; 2842 2843 return edid_ext; 2844 } 2845 2846 static u8 *drm_find_cea_extension(struct edid *edid) 2847 { 2848 return drm_find_edid_extension(edid, 0x02); 2849 } 2850 2851 #define AUDIO_BLOCK 0x01 2852 #define VIDEO_BLOCK 0x02 2853 #define VENDOR_BLOCK 0x03 2854 #define SPEAKER_BLOCK 0x04 2855 #define EDID_BASIC_AUDIO BIT(6) 2856 2857 /** 2858 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 2859 * @edid: monitor EDID information 2860 * 2861 * Parse the CEA extension according to CEA-861-B. 2862 * 2863 * Return: True if the monitor is HDMI, false if not or unknown. 2864 */ 2865 bool drm_detect_hdmi_monitor(struct edid *edid) 2866 { 2867 u8 *edid_ext; 2868 int i; 2869 int start_offset, end_offset; 2870 2871 edid_ext = drm_find_cea_extension(edid); 2872 if (!edid_ext) 2873 return false; 2874 2875 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2876 return false; 2877 2878 /* 2879 * Because HDMI identifier is in Vendor Specific Block, 2880 * search it from all data blocks of CEA extension. 2881 */ 2882 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2883 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 2884 return true; 2885 } 2886 2887 return false; 2888 } 2889 2890 /** 2891 * drm_detect_monitor_audio - check monitor audio capability 2892 * @edid: EDID block to scan 2893 * 2894 * Monitor should have CEA extension block. 2895 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 2896 * audio' only. If there is any audio extension block and supported 2897 * audio format, assume at least 'basic audio' support, even if 'basic 2898 * audio' is not defined in EDID. 2899 * 2900 * Return: True if the monitor supports audio, false otherwise. 2901 */ 2902 bool drm_detect_monitor_audio(struct edid *edid) 2903 { 2904 u8 *edid_ext; 2905 int i, j; 2906 bool has_audio = false; 2907 int start_offset, end_offset; 2908 2909 edid_ext = drm_find_cea_extension(edid); 2910 if (!edid_ext) 2911 goto end; 2912 2913 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 2914 2915 if (has_audio) { 2916 printf("Monitor has basic audio support\n"); 2917 goto end; 2918 } 2919 2920 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2921 goto end; 2922 2923 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2924 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 2925 has_audio = true; 2926 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 2927 j += 3) 2928 debug("CEA audio format %d\n", 2929 (edid_ext[i + j] >> 3) & 0xf); 2930 goto end; 2931 } 2932 } 2933 end: 2934 return has_audio; 2935 } 2936 2937 static void 2938 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 2939 { 2940 struct drm_display_info *info = &data->display_info; 2941 u8 len = cea_db_payload_len(db); 2942 2943 if (len >= 6) 2944 info->dvi_dual = db[6] & 1; 2945 if (len >= 7) 2946 info->max_tmds_clock = db[7] * 5000; 2947 2948 drm_parse_hdmi_deep_color_info(data, db); 2949 } 2950 2951 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 2952 struct edid *edid) 2953 { 2954 struct drm_display_info *info = &data->display_info; 2955 const u8 *edid_ext; 2956 int i, start, end; 2957 2958 edid_ext = drm_find_cea_extension(edid); 2959 if (!edid_ext) 2960 return; 2961 2962 info->cea_rev = edid_ext[1]; 2963 2964 /* The existence of a CEA block should imply RGB support */ 2965 info->color_formats = DRM_COLOR_FORMAT_RGB444; 2966 if (edid_ext[3] & EDID_CEA_YCRCB444) 2967 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 2968 if (edid_ext[3] & EDID_CEA_YCRCB422) 2969 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 2970 2971 if (cea_db_offsets(edid_ext, &start, &end)) 2972 return; 2973 2974 for_each_cea_db(edid_ext, i, start, end) { 2975 const u8 *db = &edid_ext[i]; 2976 2977 if (cea_db_is_hdmi_vsdb(db)) 2978 drm_parse_hdmi_vsdb_video(data, db); 2979 if (cea_db_is_hdmi_forum_vsdb(db)) 2980 drm_parse_hdmi_forum_vsdb(data, db); 2981 if (cea_db_is_y420cmdb(db)) 2982 drm_parse_y420cmdb_bitmap(data, db); 2983 } 2984 } 2985 2986 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 2987 { 2988 struct drm_display_info *info = &data->display_info; 2989 2990 info->width_mm = edid->width_cm * 10; 2991 info->height_mm = edid->height_cm * 10; 2992 2993 /* driver figures it out in this case */ 2994 info->bpc = 0; 2995 info->color_formats = 0; 2996 info->cea_rev = 0; 2997 info->max_tmds_clock = 0; 2998 info->dvi_dual = false; 2999 info->edid_hdmi_dc_modes = 0; 3000 3001 memset(&info->hdmi, 0, sizeof(info->hdmi)); 3002 3003 if (edid->revision < 3) 3004 return; 3005 3006 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3007 return; 3008 3009 drm_parse_cea_ext(data, edid); 3010 3011 /* 3012 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3013 * 3014 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3015 * tells us to assume 8 bpc color depth if the EDID doesn't have 3016 * extensions which tell otherwise. 3017 */ 3018 if ((info->bpc == 0) && (edid->revision < 4) && 3019 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3020 info->bpc = 8; 3021 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3022 } 3023 3024 /* Only defined for 1.4 with digital displays */ 3025 if (edid->revision < 4) 3026 return; 3027 3028 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3029 case DRM_EDID_DIGITAL_DEPTH_6: 3030 info->bpc = 6; 3031 break; 3032 case DRM_EDID_DIGITAL_DEPTH_8: 3033 info->bpc = 8; 3034 break; 3035 case DRM_EDID_DIGITAL_DEPTH_10: 3036 info->bpc = 10; 3037 break; 3038 case DRM_EDID_DIGITAL_DEPTH_12: 3039 info->bpc = 12; 3040 break; 3041 case DRM_EDID_DIGITAL_DEPTH_14: 3042 info->bpc = 14; 3043 break; 3044 case DRM_EDID_DIGITAL_DEPTH_16: 3045 info->bpc = 16; 3046 break; 3047 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3048 default: 3049 info->bpc = 0; 3050 break; 3051 } 3052 3053 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3054 info->bpc); 3055 3056 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3057 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3058 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3059 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3060 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3061 } 3062 3063 static 3064 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3065 { 3066 const u8 *cea = drm_find_cea_extension(edid); 3067 const u8 *db, *hdmi = NULL, *video = NULL; 3068 u8 dbl, hdmi_len, video_len = 0; 3069 int modes = 0; 3070 3071 if (cea && cea_revision(cea) >= 3) { 3072 int i, start, end; 3073 3074 if (cea_db_offsets(cea, &start, &end)) 3075 return 0; 3076 3077 for_each_cea_db(cea, i, start, end) { 3078 db = &cea[i]; 3079 dbl = cea_db_payload_len(db); 3080 3081 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3082 video = db + 1; 3083 video_len = dbl; 3084 modes += do_cea_modes(data, video, dbl); 3085 } else if (cea_db_is_hdmi_vsdb(db)) { 3086 hdmi = db; 3087 hdmi_len = dbl; 3088 } else if (cea_db_is_y420vdb(db)) { 3089 const u8 *vdb420 = &db[2]; 3090 3091 /* Add 4:2:0(only) modes present in EDID */ 3092 modes += do_y420vdb_modes(data, vdb420, 3093 dbl - 1); 3094 } 3095 } 3096 } 3097 3098 /* 3099 * We parse the HDMI VSDB after having added the cea modes as we will 3100 * be patching their flags when the sink supports stereo 3D. 3101 */ 3102 if (hdmi) 3103 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3104 video_len, data); 3105 3106 return modes; 3107 } 3108 3109 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3110 3111 static void 3112 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3113 { 3114 int i, n = 0; 3115 u8 d = ext[0x02]; 3116 u8 *det_base = ext + d; 3117 3118 n = (127 - d) / 18; 3119 for (i = 0; i < n; i++) 3120 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3121 } 3122 3123 static void 3124 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3125 { 3126 unsigned int i, n = min((int)ext[0x02], 6); 3127 u8 *det_base = ext + 5; 3128 3129 if (ext[0x01] != 1) 3130 return; /* unknown version */ 3131 3132 for (i = 0; i < n; i++) 3133 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3134 } 3135 3136 static void 3137 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3138 { 3139 int i; 3140 struct edid *edid = (struct edid *)raw_edid; 3141 3142 if (!edid) 3143 return; 3144 3145 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3146 cb(&edid->detailed_timings[i], closure); 3147 3148 for (i = 1; i <= raw_edid[0x7e]; i++) { 3149 u8 *ext = raw_edid + (i * EDID_SIZE); 3150 3151 switch (*ext) { 3152 case CEA_EXT: 3153 cea_for_each_detailed_block(ext, cb, closure); 3154 break; 3155 case VTB_EXT: 3156 vtb_for_each_detailed_block(ext, cb, closure); 3157 break; 3158 default: 3159 break; 3160 } 3161 } 3162 } 3163 3164 /* 3165 * EDID is delightfully ambiguous about how interlaced modes are to be 3166 * encoded. Our internal representation is of frame height, but some 3167 * HDTV detailed timings are encoded as field height. 3168 * 3169 * The format list here is from CEA, in frame size. Technically we 3170 * should be checking refresh rate too. Whatever. 3171 */ 3172 static void 3173 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3174 struct detailed_pixel_timing *pt) 3175 { 3176 int i; 3177 3178 static const struct { 3179 int w, h; 3180 } cea_interlaced[] = { 3181 { 1920, 1080 }, 3182 { 720, 480 }, 3183 { 1440, 480 }, 3184 { 2880, 480 }, 3185 { 720, 576 }, 3186 { 1440, 576 }, 3187 { 2880, 576 }, 3188 }; 3189 3190 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3191 return; 3192 3193 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3194 if ((mode->hdisplay == cea_interlaced[i].w) && 3195 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3196 mode->vdisplay *= 2; 3197 mode->vsync_start *= 2; 3198 mode->vsync_end *= 2; 3199 mode->vtotal *= 2; 3200 mode->vtotal |= 1; 3201 } 3202 } 3203 3204 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3205 } 3206 3207 /** 3208 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3209 * @edid: EDID block 3210 * @timing: EDID detailed timing info 3211 * @quirks: quirks to apply 3212 * 3213 * An EDID detailed timing block contains enough info for us to create and 3214 * return a new struct drm_display_mode. 3215 */ 3216 static 3217 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3218 struct detailed_timing *timing, 3219 u32 quirks) 3220 { 3221 struct drm_display_mode *mode; 3222 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3223 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3224 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3225 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3226 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3227 unsigned hsync_offset = 3228 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3229 pt->hsync_offset_lo; 3230 unsigned hsync_pulse_width = 3231 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3232 pt->hsync_pulse_width_lo; 3233 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3234 2 | pt->vsync_offset_pulse_width_lo >> 4; 3235 unsigned vsync_pulse_width = 3236 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3237 (pt->vsync_offset_pulse_width_lo & 0xf); 3238 3239 /* ignore tiny modes */ 3240 if (hactive < 64 || vactive < 64) 3241 return NULL; 3242 3243 if (pt->misc & DRM_EDID_PT_STEREO) { 3244 debug("stereo mode not supported\n"); 3245 return NULL; 3246 } 3247 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3248 debug("composite sync not supported\n"); 3249 3250 /* it is incorrect if hsync/vsync width is zero */ 3251 if (!hsync_pulse_width || !vsync_pulse_width) { 3252 debug("Incorrect Detailed timing. "); 3253 debug("Wrong Hsync/Vsync pulse width\n"); 3254 return NULL; 3255 } 3256 3257 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3258 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3259 if (!mode) 3260 return NULL; 3261 3262 goto set_refresh; 3263 } 3264 3265 mode = drm_mode_create(); 3266 if (!mode) 3267 return NULL; 3268 3269 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3270 timing->pixel_clock = cpu_to_le16(1088); 3271 3272 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3273 3274 mode->hdisplay = hactive; 3275 mode->hsync_start = mode->hdisplay + hsync_offset; 3276 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3277 mode->htotal = mode->hdisplay + hblank; 3278 3279 mode->vdisplay = vactive; 3280 mode->vsync_start = mode->vdisplay + vsync_offset; 3281 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3282 mode->vtotal = mode->vdisplay + vblank; 3283 3284 /* Some EDIDs have bogus h/vtotal values */ 3285 if (mode->hsync_end > mode->htotal) 3286 mode->htotal = mode->hsync_end + 1; 3287 if (mode->vsync_end > mode->vtotal) 3288 mode->vtotal = mode->vsync_end + 1; 3289 3290 drm_mode_do_interlace_quirk(mode, pt); 3291 3292 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3293 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3294 DRM_EDID_PT_VSYNC_POSITIVE; 3295 3296 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3297 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3298 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3299 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3300 3301 set_refresh: 3302 3303 mode->type = DRM_MODE_TYPE_DRIVER; 3304 mode->vrefresh = drm_get_vrefresh(mode); 3305 3306 return mode; 3307 } 3308 3309 /* 3310 * Calculate the alternate clock for the CEA mode 3311 * (60Hz vs. 59.94Hz etc.) 3312 */ 3313 static unsigned int 3314 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3315 { 3316 unsigned int clock = cea_mode->clock; 3317 3318 if (cea_mode->vrefresh % 6 != 0) 3319 return clock; 3320 3321 /* 3322 * edid_cea_modes contains the 59.94Hz 3323 * variant for 240 and 480 line modes, 3324 * and the 60Hz variant otherwise. 3325 */ 3326 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3327 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3328 else 3329 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3330 3331 return clock; 3332 } 3333 3334 /** 3335 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3336 * @mode1: first mode 3337 * @mode2: second mode 3338 * 3339 * Check to see if @mode1 and @mode2 are equivalent, but 3340 * don't check the pixel clocks nor the stereo layout. 3341 * 3342 * Returns: 3343 * True if the modes are equal, false otherwise. 3344 */ 3345 3346 static 3347 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3348 const struct drm_display_mode *mode2) 3349 { 3350 unsigned int flags_mask = 3351 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3352 3353 if (mode1->hdisplay == mode2->hdisplay && 3354 mode1->hsync_start == mode2->hsync_start && 3355 mode1->hsync_end == mode2->hsync_end && 3356 mode1->htotal == mode2->htotal && 3357 mode1->vdisplay == mode2->vdisplay && 3358 mode1->vsync_start == mode2->vsync_start && 3359 mode1->vsync_end == mode2->vsync_end && 3360 mode1->vtotal == mode2->vtotal && 3361 mode1->vscan == mode2->vscan && 3362 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3363 return true; 3364 3365 return false; 3366 } 3367 3368 /** 3369 * drm_mode_equal_no_clocks - test modes for equality 3370 * @mode1: first mode 3371 * @mode2: second mode 3372 * 3373 * Check to see if @mode1 and @mode2 are equivalent, but 3374 * don't check the pixel clocks. 3375 * 3376 * Returns: 3377 * True if the modes are equal, false otherwise. 3378 */ 3379 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3380 const struct drm_display_mode *mode2) 3381 { 3382 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3383 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3384 return false; 3385 3386 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3387 } 3388 3389 static 3390 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3391 unsigned int clock_tolerance) 3392 { 3393 u8 vic; 3394 3395 if (!to_match->clock) 3396 return 0; 3397 3398 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3399 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 3400 unsigned int clock1, clock2; 3401 3402 /* Check both 60Hz and 59.94Hz */ 3403 clock1 = cea_mode->clock; 3404 clock2 = cea_mode_alternate_clock(cea_mode); 3405 3406 if (abs(to_match->clock - clock1) > clock_tolerance && 3407 abs(to_match->clock - clock2) > clock_tolerance) 3408 continue; 3409 3410 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3411 return vic; 3412 } 3413 3414 return 0; 3415 } 3416 3417 static unsigned int 3418 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3419 { 3420 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3421 return hdmi_mode->clock; 3422 3423 return cea_mode_alternate_clock(hdmi_mode); 3424 } 3425 3426 static 3427 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3428 unsigned int clock_tolerance) 3429 { 3430 u8 vic; 3431 3432 if (!to_match->clock) 3433 return 0; 3434 3435 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3436 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3437 unsigned int clock1, clock2; 3438 3439 /* Make sure to also match alternate clocks */ 3440 clock1 = hdmi_mode->clock; 3441 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3442 3443 if (abs(to_match->clock - clock1) > clock_tolerance && 3444 abs(to_match->clock - clock2) > clock_tolerance) 3445 continue; 3446 3447 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3448 return vic; 3449 } 3450 3451 return 0; 3452 } 3453 3454 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3455 { 3456 const struct drm_display_mode *cea_mode; 3457 int clock1, clock2, clock; 3458 u8 vic; 3459 const char *type; 3460 3461 /* 3462 * allow 5kHz clock difference either way to account for 3463 * the 10kHz clock resolution limit of detailed timings. 3464 */ 3465 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3466 if (drm_valid_cea_vic(vic)) { 3467 type = "CEA"; 3468 cea_mode = &edid_cea_modes[vic]; 3469 clock1 = cea_mode->clock; 3470 clock2 = cea_mode_alternate_clock(cea_mode); 3471 } else { 3472 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3473 if (drm_valid_hdmi_vic(vic)) { 3474 type = "HDMI"; 3475 cea_mode = &edid_4k_modes[vic]; 3476 clock1 = cea_mode->clock; 3477 clock2 = hdmi_mode_alternate_clock(cea_mode); 3478 } else { 3479 return; 3480 } 3481 } 3482 3483 /* pick whichever is closest */ 3484 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3485 clock = clock1; 3486 else 3487 clock = clock2; 3488 3489 if (mode->clock == clock) 3490 return; 3491 3492 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3493 type, vic, mode->clock, clock); 3494 mode->clock = clock; 3495 } 3496 3497 static void 3498 do_detailed_mode(struct detailed_timing *timing, void *c) 3499 { 3500 struct detailed_mode_closure *closure = c; 3501 struct drm_display_mode *newmode; 3502 3503 if (timing->pixel_clock) { 3504 newmode = drm_mode_detailed( 3505 closure->edid, timing, 3506 closure->quirks); 3507 if (!newmode) 3508 return; 3509 3510 if (closure->preferred) 3511 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3512 3513 /* 3514 * Detailed modes are limited to 10kHz pixel clock resolution, 3515 * so fix up anything that looks like CEA/HDMI mode, 3516 * but the clock is just slightly off. 3517 */ 3518 fixup_detailed_cea_mode_clock(newmode); 3519 drm_add_hdmi_modes(closure->data, newmode); 3520 drm_mode_destroy(newmode); 3521 closure->modes++; 3522 closure->preferred = 0; 3523 } 3524 } 3525 3526 /* 3527 * add_detailed_modes - Add modes from detailed timings 3528 * @data: attached data 3529 * @edid: EDID block to scan 3530 * @quirks: quirks to apply 3531 */ 3532 static int 3533 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 3534 u32 quirks) 3535 { 3536 struct detailed_mode_closure closure = { 3537 .data = data, 3538 .edid = edid, 3539 .preferred = 1, 3540 .quirks = quirks, 3541 }; 3542 3543 if (closure.preferred && !version_greater(edid, 1, 3)) 3544 closure.preferred = 3545 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3546 3547 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3548 3549 return closure.modes; 3550 } 3551 3552 static int drm_cvt_modes(struct hdmi_edid_data *data, 3553 struct detailed_timing *timing) 3554 { 3555 int i, j, modes = 0; 3556 struct drm_display_mode *newmode; 3557 struct cvt_timing *cvt; 3558 const int rates[] = { 60, 85, 75, 60, 50 }; 3559 const u8 empty[3] = { 0, 0, 0 }; 3560 3561 for (i = 0; i < 4; i++) { 3562 int uninitialized_var(width), height; 3563 3564 cvt = &timing->data.other_data.data.cvt[i]; 3565 3566 if (!memcmp(cvt->code, empty, 3)) 3567 continue; 3568 3569 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3570 switch (cvt->code[1] & 0x0c) { 3571 case 0x00: 3572 width = height * 4 / 3; 3573 break; 3574 case 0x04: 3575 width = height * 16 / 9; 3576 break; 3577 case 0x08: 3578 width = height * 16 / 10; 3579 break; 3580 case 0x0c: 3581 width = height * 15 / 9; 3582 break; 3583 } 3584 3585 for (j = 1; j < 5; j++) { 3586 if (cvt->code[2] & (1 << j)) { 3587 newmode = drm_cvt_mode(width, height, 3588 rates[j], j == 0, 3589 false, false); 3590 if (newmode) { 3591 drm_add_hdmi_modes(data, newmode); 3592 modes++; 3593 drm_mode_destroy(newmode); 3594 } 3595 } 3596 } 3597 } 3598 3599 return modes; 3600 } 3601 3602 static void 3603 do_cvt_mode(struct detailed_timing *timing, void *c) 3604 { 3605 struct detailed_mode_closure *closure = c; 3606 struct detailed_non_pixel *data = &timing->data.other_data; 3607 3608 if (data->type == EDID_DETAIL_CVT_3BYTE) 3609 closure->modes += drm_cvt_modes(closure->data, timing); 3610 } 3611 3612 static int 3613 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 3614 { 3615 struct detailed_mode_closure closure = { 3616 .data = data, 3617 .edid = edid, 3618 }; 3619 3620 if (version_greater(edid, 1, 2)) 3621 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3622 3623 /* XXX should also look for CVT codes in VTB blocks */ 3624 3625 return closure.modes; 3626 } 3627 3628 static void 3629 find_gtf2(struct detailed_timing *t, void *data) 3630 { 3631 u8 *r = (u8 *)t; 3632 3633 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 3634 *(u8 **)data = r; 3635 } 3636 3637 /* Secondary GTF curve kicks in above some break frequency */ 3638 static int 3639 drm_gtf2_hbreak(struct edid *edid) 3640 { 3641 u8 *r = NULL; 3642 3643 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3644 return r ? (r[12] * 2) : 0; 3645 } 3646 3647 static int 3648 drm_gtf2_2c(struct edid *edid) 3649 { 3650 u8 *r = NULL; 3651 3652 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3653 return r ? r[13] : 0; 3654 } 3655 3656 static int 3657 drm_gtf2_m(struct edid *edid) 3658 { 3659 u8 *r = NULL; 3660 3661 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3662 return r ? (r[15] << 8) + r[14] : 0; 3663 } 3664 3665 static int 3666 drm_gtf2_k(struct edid *edid) 3667 { 3668 u8 *r = NULL; 3669 3670 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3671 return r ? r[16] : 0; 3672 } 3673 3674 static int 3675 drm_gtf2_2j(struct edid *edid) 3676 { 3677 u8 *r = NULL; 3678 3679 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3680 return r ? r[17] : 0; 3681 } 3682 3683 /** 3684 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 3685 * @edid: EDID block to scan 3686 */ 3687 static int standard_timing_level(struct edid *edid) 3688 { 3689 if (edid->revision >= 2) { 3690 if (edid->revision >= 4 && 3691 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 3692 return LEVEL_CVT; 3693 if (drm_gtf2_hbreak(edid)) 3694 return LEVEL_GTF2; 3695 return LEVEL_GTF; 3696 } 3697 return LEVEL_DMT; 3698 } 3699 3700 /* 3701 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3702 * monitors fill with ascii space (0x20) instead. 3703 */ 3704 static int 3705 bad_std_timing(u8 a, u8 b) 3706 { 3707 return (a == 0x00 && b == 0x00) || 3708 (a == 0x01 && b == 0x01) || 3709 (a == 0x20 && b == 0x20); 3710 } 3711 3712 static void 3713 is_rb(struct detailed_timing *t, void *data) 3714 { 3715 u8 *r = (u8 *)t; 3716 3717 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 3718 if (r[15] & 0x10) 3719 *(bool *)data = true; 3720 } 3721 3722 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3723 static bool 3724 drm_monitor_supports_rb(struct edid *edid) 3725 { 3726 if (edid->revision >= 4) { 3727 bool ret = false; 3728 3729 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 3730 return ret; 3731 } 3732 3733 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3734 } 3735 3736 static bool 3737 mode_is_rb(const struct drm_display_mode *mode) 3738 { 3739 return (mode->htotal - mode->hdisplay == 160) && 3740 (mode->hsync_end - mode->hdisplay == 80) && 3741 (mode->hsync_end - mode->hsync_start == 32) && 3742 (mode->vsync_start - mode->vdisplay == 3); 3743 } 3744 3745 /* 3746 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3747 * @hsize: Mode width 3748 * @vsize: Mode height 3749 * @fresh: Mode refresh rate 3750 * @rb: Mode reduced-blanking-ness 3751 * 3752 * Walk the DMT mode list looking for a match for the given parameters. 3753 * 3754 * Return: A newly allocated copy of the mode, or NULL if not found. 3755 */ 3756 static struct drm_display_mode *drm_mode_find_dmt( 3757 int hsize, int vsize, int fresh, 3758 bool rb) 3759 { 3760 int i; 3761 struct drm_display_mode *newmode; 3762 3763 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3764 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3765 3766 if (hsize != ptr->hdisplay) 3767 continue; 3768 if (vsize != ptr->vdisplay) 3769 continue; 3770 if (fresh != drm_get_vrefresh(ptr)) 3771 continue; 3772 if (rb != mode_is_rb(ptr)) 3773 continue; 3774 3775 newmode = drm_mode_create(); 3776 *newmode = *ptr; 3777 return newmode; 3778 } 3779 3780 return NULL; 3781 } 3782 3783 static struct drm_display_mode * 3784 drm_gtf_mode_complex(int hdisplay, int vdisplay, 3785 int vrefresh, bool interlaced, int margins, 3786 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 3787 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 3788 #define GTF_MARGIN_PERCENTAGE 18 3789 /* 2) character cell horizontal granularity (pixels) - default 8 */ 3790 #define GTF_CELL_GRAN 8 3791 /* 3) Minimum vertical porch (lines) - default 3 */ 3792 #define GTF_MIN_V_PORCH 1 3793 /* width of vsync in lines */ 3794 #define V_SYNC_RQD 3 3795 /* width of hsync as % of total line */ 3796 #define H_SYNC_PERCENT 8 3797 /* min time of vsync + back porch (microsec) */ 3798 #define MIN_VSYNC_PLUS_BP 550 3799 /* C' and M' are part of the Blanking Duty Cycle computation */ 3800 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 3801 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 3802 struct drm_display_mode *drm_mode; 3803 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 3804 int top_margin, bottom_margin; 3805 int interlace; 3806 unsigned int hfreq_est; 3807 int vsync_plus_bp; 3808 unsigned int vtotal_lines; 3809 int left_margin, right_margin; 3810 unsigned int total_active_pixels, ideal_duty_cycle; 3811 unsigned int hblank, total_pixels, pixel_freq; 3812 int hsync, hfront_porch, vodd_front_porch_lines; 3813 unsigned int tmp1, tmp2; 3814 3815 drm_mode = drm_mode_create(); 3816 if (!drm_mode) 3817 return NULL; 3818 3819 /* 1. In order to give correct results, the number of horizontal 3820 * pixels requested is first processed to ensure that it is divisible 3821 * by the character size, by rounding it to the nearest character 3822 * cell boundary: 3823 */ 3824 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3825 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 3826 3827 /* 2. If interlace is requested, the number of vertical lines assumed 3828 * by the calculation must be halved, as the computation calculates 3829 * the number of vertical lines per field. 3830 */ 3831 if (interlaced) 3832 vdisplay_rnd = vdisplay / 2; 3833 else 3834 vdisplay_rnd = vdisplay; 3835 3836 /* 3. Find the frame rate required: */ 3837 if (interlaced) 3838 vfieldrate_rqd = vrefresh * 2; 3839 else 3840 vfieldrate_rqd = vrefresh; 3841 3842 /* 4. Find number of lines in Top margin: */ 3843 top_margin = 0; 3844 if (margins) 3845 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3846 1000; 3847 /* 5. Find number of lines in bottom margin: */ 3848 bottom_margin = top_margin; 3849 3850 /* 6. If interlace is required, then set variable interlace: */ 3851 if (interlaced) 3852 interlace = 1; 3853 else 3854 interlace = 0; 3855 3856 /* 7. Estimate the Horizontal frequency */ 3857 { 3858 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 3859 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 3860 2 + interlace; 3861 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 3862 } 3863 3864 /* 8. Find the number of lines in V sync + back porch */ 3865 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 3866 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 3867 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 3868 /* 9. Find the number of lines in V back porch alone: 3869 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 3870 */ 3871 /* 10. Find the total number of lines in Vertical field period: */ 3872 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 3873 vsync_plus_bp + GTF_MIN_V_PORCH; 3874 /* 11. Estimate the Vertical field frequency: 3875 * vfieldrate_est = hfreq_est / vtotal_lines; 3876 */ 3877 3878 /* 12. Find the actual horizontal period: 3879 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 3880 */ 3881 /* 13. Find the actual Vertical field frequency: 3882 * vfield_rate = hfreq_est / vtotal_lines; 3883 */ 3884 /* 14. Find the Vertical frame frequency: 3885 * if (interlaced) 3886 * vframe_rate = vfield_rate / 2; 3887 * else 3888 * vframe_rate = vfield_rate; 3889 */ 3890 /* 15. Find number of pixels in left margin: */ 3891 if (margins) 3892 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3893 1000; 3894 else 3895 left_margin = 0; 3896 3897 /* 16.Find number of pixels in right margin: */ 3898 right_margin = left_margin; 3899 /* 17.Find total number of active pixels in image and left and right */ 3900 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 3901 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 3902 ideal_duty_cycle = GTF_C_PRIME * 1000 - 3903 (GTF_M_PRIME * 1000000 / hfreq_est); 3904 /* 19.Find the number of pixels in the blanking time to the nearest 3905 * double character cell: 3906 */ 3907 hblank = total_active_pixels * ideal_duty_cycle / 3908 (100000 - ideal_duty_cycle); 3909 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 3910 hblank = hblank * 2 * GTF_CELL_GRAN; 3911 /* 20.Find total number of pixels: */ 3912 total_pixels = total_active_pixels + hblank; 3913 /* 21.Find pixel clock frequency: */ 3914 pixel_freq = total_pixels * hfreq_est / 1000; 3915 /* Stage 1 computations are now complete; I should really pass 3916 * the results to another function and do the Stage 2 computations, 3917 * but I only need a few more values so I'll just append the 3918 * computations here for now 3919 */ 3920 3921 /* 17. Find the number of pixels in the horizontal sync period: */ 3922 hsync = H_SYNC_PERCENT * total_pixels / 100; 3923 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3924 hsync = hsync * GTF_CELL_GRAN; 3925 /* 18. Find the number of pixels in horizontal front porch period */ 3926 hfront_porch = hblank / 2 - hsync; 3927 /* 36. Find the number of lines in the odd front porch period: */ 3928 vodd_front_porch_lines = GTF_MIN_V_PORCH; 3929 3930 /* finally, pack the results in the mode struct */ 3931 drm_mode->hdisplay = hdisplay_rnd; 3932 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 3933 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 3934 drm_mode->htotal = total_pixels; 3935 drm_mode->vdisplay = vdisplay_rnd; 3936 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 3937 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 3938 drm_mode->vtotal = vtotal_lines; 3939 3940 drm_mode->clock = pixel_freq; 3941 3942 if (interlaced) { 3943 drm_mode->vtotal *= 2; 3944 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 3945 } 3946 3947 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 3948 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 3949 else 3950 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 3951 3952 return drm_mode; 3953 } 3954 3955 /** 3956 * drm_gtf_mode - create the mode based on the GTF algorithm 3957 * @hdisplay: hdisplay size 3958 * @vdisplay: vdisplay size 3959 * @vrefresh: vrefresh rate. 3960 * @interlaced: whether to compute an interlaced mode 3961 * @margins: desired margin (borders) size 3962 * 3963 * return the mode based on GTF algorithm 3964 * 3965 * This function is to create the mode based on the GTF algorithm. 3966 * Generalized Timing Formula is derived from: 3967 * GTF Spreadsheet by Andy Morrish (1/5/97) 3968 * available at http://www.vesa.org 3969 * 3970 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 3971 * What I have done is to translate it by using integer calculation. 3972 * I also refer to the function of fb_get_mode in the file of 3973 * drivers/video/fbmon.c 3974 * 3975 * Standard GTF parameters: 3976 * M = 600 3977 * C = 40 3978 * K = 128 3979 * J = 20 3980 * 3981 * Returns: 3982 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 3983 * The display mode object is allocated with drm_mode_create(). Returns NULL 3984 * when no mode could be allocated. 3985 */ 3986 static struct drm_display_mode * 3987 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 3988 bool interlaced, int margins) 3989 { 3990 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 3991 interlaced, margins, 3992 600, 40 * 2, 128, 20 * 2); 3993 } 3994 3995 /** drm_mode_hsync - get the hsync of a mode 3996 * @mode: mode 3997 * 3998 * Returns: 3999 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 4000 * value first if it is not yet set. 4001 */ 4002 static int drm_mode_hsync(const struct drm_display_mode *mode) 4003 { 4004 unsigned int calc_val; 4005 4006 if (mode->htotal < 0) 4007 return 0; 4008 4009 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 4010 calc_val += 500; /* round to 1000Hz */ 4011 calc_val /= 1000; /* truncate to kHz */ 4012 4013 return calc_val; 4014 } 4015 4016 /** 4017 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 4018 * @data: the structure that save parsed hdmi edid data 4019 * @edid: EDID block to scan 4020 * @t: standard timing params 4021 * 4022 * Take the standard timing params (in this case width, aspect, and refresh) 4023 * and convert them into a real mode using CVT/GTF/DMT. 4024 */ 4025 static struct drm_display_mode * 4026 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4027 struct std_timing *t) 4028 { 4029 struct drm_display_mode *mode = NULL; 4030 int i, hsize, vsize; 4031 int vrefresh_rate; 4032 int num = data->modes; 4033 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4034 >> EDID_TIMING_ASPECT_SHIFT; 4035 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4036 >> EDID_TIMING_VFREQ_SHIFT; 4037 int timing_level = standard_timing_level(edid); 4038 4039 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4040 return NULL; 4041 4042 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4043 hsize = t->hsize * 8 + 248; 4044 /* vrefresh_rate = vfreq + 60 */ 4045 vrefresh_rate = vfreq + 60; 4046 /* the vdisplay is calculated based on the aspect ratio */ 4047 if (aspect_ratio == 0) { 4048 if (edid->revision < 3) 4049 vsize = hsize; 4050 else 4051 vsize = (hsize * 10) / 16; 4052 } else if (aspect_ratio == 1) { 4053 vsize = (hsize * 3) / 4; 4054 } else if (aspect_ratio == 2) { 4055 vsize = (hsize * 4) / 5; 4056 } else { 4057 vsize = (hsize * 9) / 16; 4058 } 4059 4060 /* HDTV hack, part 1 */ 4061 if (vrefresh_rate == 60 && 4062 ((hsize == 1360 && vsize == 765) || 4063 (hsize == 1368 && vsize == 769))) { 4064 hsize = 1366; 4065 vsize = 768; 4066 } 4067 4068 /* 4069 * If we already has a mode for this size and refresh 4070 * rate (because it came from detailed or CVT info), use that 4071 * instead. This way we don't have to guess at interlace or 4072 * reduced blanking. 4073 */ 4074 for (i = 0; i < num; i++) 4075 if (data->mode_buf[i].hdisplay == hsize && 4076 data->mode_buf[i].vdisplay == vsize && 4077 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4078 return NULL; 4079 4080 /* HDTV hack, part 2 */ 4081 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4082 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4083 false); 4084 mode->hdisplay = 1366; 4085 mode->hsync_start = mode->hsync_start - 1; 4086 mode->hsync_end = mode->hsync_end - 1; 4087 return mode; 4088 } 4089 4090 /* check whether it can be found in default mode table */ 4091 if (drm_monitor_supports_rb(edid)) { 4092 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4093 true); 4094 if (mode) 4095 return mode; 4096 } 4097 4098 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4099 if (mode) 4100 return mode; 4101 4102 /* okay, generate it */ 4103 switch (timing_level) { 4104 case LEVEL_DMT: 4105 break; 4106 case LEVEL_GTF: 4107 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4108 break; 4109 case LEVEL_GTF2: 4110 /* 4111 * This is potentially wrong if there's ever a monitor with 4112 * more than one ranges section, each claiming a different 4113 * secondary GTF curve. Please don't do that. 4114 */ 4115 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4116 if (!mode) 4117 return NULL; 4118 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4119 drm_mode_destroy(mode); 4120 mode = drm_gtf_mode_complex(hsize, vsize, 4121 vrefresh_rate, 0, 0, 4122 drm_gtf2_m(edid), 4123 drm_gtf2_2c(edid), 4124 drm_gtf2_k(edid), 4125 drm_gtf2_2j(edid)); 4126 } 4127 break; 4128 case LEVEL_CVT: 4129 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4130 false); 4131 break; 4132 } 4133 4134 return mode; 4135 } 4136 4137 static void 4138 do_standard_modes(struct detailed_timing *timing, void *c) 4139 { 4140 struct detailed_mode_closure *closure = c; 4141 struct detailed_non_pixel *data = &timing->data.other_data; 4142 struct edid *edid = closure->edid; 4143 4144 if (data->type == EDID_DETAIL_STD_MODES) { 4145 int i; 4146 4147 for (i = 0; i < 6; i++) { 4148 struct std_timing *std; 4149 struct drm_display_mode *newmode; 4150 4151 std = &data->data.timings[i]; 4152 newmode = drm_mode_std(closure->data, edid, std); 4153 if (newmode) { 4154 drm_add_hdmi_modes(closure->data, newmode); 4155 closure->modes++; 4156 drm_mode_destroy(newmode); 4157 } 4158 } 4159 } 4160 } 4161 4162 /** 4163 * add_standard_modes - get std. modes from EDID and add them 4164 * @data: data to add mode(s) to 4165 * @edid: EDID block to scan 4166 * 4167 * Standard modes can be calculated using the appropriate standard (DMT, 4168 * GTF or CVT. Grab them from @edid and add them to the list. 4169 */ 4170 static int 4171 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4172 { 4173 int i, modes = 0; 4174 struct detailed_mode_closure closure = { 4175 .data = data, 4176 .edid = edid, 4177 }; 4178 4179 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4180 struct drm_display_mode *newmode; 4181 4182 newmode = drm_mode_std(data, edid, 4183 &edid->standard_timings[i]); 4184 if (newmode) { 4185 drm_add_hdmi_modes(data, newmode); 4186 modes++; 4187 drm_mode_destroy(newmode); 4188 } 4189 } 4190 4191 if (version_greater(edid, 1, 0)) 4192 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4193 &closure); 4194 4195 /* XXX should also look for standard codes in VTB blocks */ 4196 4197 return modes + closure.modes; 4198 } 4199 4200 static int 4201 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4202 { 4203 int i, j, m, modes = 0; 4204 struct drm_display_mode *mode; 4205 u8 *est = ((u8 *)timing) + 6; 4206 4207 for (i = 0; i < 6; i++) { 4208 for (j = 7; j >= 0; j--) { 4209 m = (i * 8) + (7 - j); 4210 if (m >= ARRAY_SIZE(est3_modes)) 4211 break; 4212 if (est[i] & (1 << j)) { 4213 mode = drm_mode_find_dmt( 4214 est3_modes[m].w, 4215 est3_modes[m].h, 4216 est3_modes[m].r, 4217 est3_modes[m].rb); 4218 if (mode) { 4219 drm_add_hdmi_modes(data, mode); 4220 modes++; 4221 drm_mode_destroy(mode); 4222 } 4223 } 4224 } 4225 } 4226 4227 return modes; 4228 } 4229 4230 static void 4231 do_established_modes(struct detailed_timing *timing, void *c) 4232 { 4233 struct detailed_mode_closure *closure = c; 4234 struct detailed_non_pixel *data = &timing->data.other_data; 4235 4236 if (data->type == EDID_DETAIL_EST_TIMINGS) 4237 closure->modes += drm_est3_modes(closure->data, timing); 4238 } 4239 4240 /** 4241 * add_established_modes - get est. modes from EDID and add them 4242 * @data: data to add mode(s) to 4243 * @edid: EDID block to scan 4244 * 4245 * Each EDID block contains a bitmap of the supported "established modes" list 4246 * (defined above). Tease them out and add them to the modes list. 4247 */ 4248 static int 4249 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4250 { 4251 unsigned long est_bits = edid->established_timings.t1 | 4252 (edid->established_timings.t2 << 8) | 4253 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4254 int i, modes = 0; 4255 struct detailed_mode_closure closure = { 4256 .data = data, 4257 .edid = edid, 4258 }; 4259 4260 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4261 if (est_bits & (1 << i)) { 4262 struct drm_display_mode *newmode = drm_mode_create(); 4263 *newmode = edid_est_modes[i]; 4264 if (newmode) { 4265 drm_add_hdmi_modes(data, newmode); 4266 modes++; 4267 drm_mode_destroy(newmode); 4268 } 4269 } 4270 } 4271 4272 if (version_greater(edid, 1, 0)) 4273 drm_for_each_detailed_block((u8 *)edid, 4274 do_established_modes, &closure); 4275 4276 return modes + closure.modes; 4277 } 4278 4279 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4280 { 4281 u8 vic; 4282 4283 if (!to_match->clock) 4284 return 0; 4285 4286 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4287 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4288 unsigned int clock1, clock2; 4289 4290 /* Make sure to also match alternate clocks */ 4291 clock1 = hdmi_mode->clock; 4292 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4293 4294 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4295 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4296 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4297 return vic; 4298 } 4299 return 0; 4300 } 4301 4302 static int 4303 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4304 { 4305 struct drm_display_mode *mode; 4306 int i, num, modes = 0; 4307 4308 /* Don't add CEA modes if the CEA extension block is missing */ 4309 if (!drm_find_cea_extension(edid)) 4310 return 0; 4311 4312 /* 4313 * Go through all probed modes and create a new mode 4314 * with the alternate clock for certain CEA modes. 4315 */ 4316 num = data->modes; 4317 4318 for (i = 0; i < num; i++) { 4319 const struct drm_display_mode *cea_mode = NULL; 4320 struct drm_display_mode *newmode; 4321 u8 vic; 4322 unsigned int clock1, clock2; 4323 4324 mode = &data->mode_buf[i]; 4325 vic = drm_match_cea_mode(mode); 4326 4327 if (drm_valid_cea_vic(vic)) { 4328 cea_mode = &edid_cea_modes[vic]; 4329 clock2 = cea_mode_alternate_clock(cea_mode); 4330 } else { 4331 vic = drm_match_hdmi_mode(mode); 4332 if (drm_valid_hdmi_vic(vic)) { 4333 cea_mode = &edid_4k_modes[vic]; 4334 clock2 = hdmi_mode_alternate_clock(cea_mode); 4335 } 4336 } 4337 4338 if (!cea_mode) 4339 continue; 4340 4341 clock1 = cea_mode->clock; 4342 4343 if (clock1 == clock2) 4344 continue; 4345 4346 if (mode->clock != clock1 && mode->clock != clock2) 4347 continue; 4348 4349 newmode = drm_mode_create(); 4350 *newmode = *cea_mode; 4351 if (!newmode) 4352 continue; 4353 4354 /* Carry over the stereo flags */ 4355 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4356 4357 /* 4358 * The current mode could be either variant. Make 4359 * sure to pick the "other" clock for the new mode. 4360 */ 4361 if (mode->clock != clock1) 4362 newmode->clock = clock1; 4363 else 4364 newmode->clock = clock2; 4365 4366 drm_add_hdmi_modes(data, newmode); 4367 modes++; 4368 drm_mode_destroy(newmode); 4369 } 4370 4371 return modes; 4372 } 4373 4374 static u8 *drm_find_displayid_extension(struct edid *edid) 4375 { 4376 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4377 } 4378 4379 static int validate_displayid(u8 *displayid, int length, int idx) 4380 { 4381 int i; 4382 u8 csum = 0; 4383 struct displayid_hdr *base; 4384 4385 base = (struct displayid_hdr *)&displayid[idx]; 4386 4387 debug("base revision 0x%x, length %d, %d %d\n", 4388 base->rev, base->bytes, base->prod_id, base->ext_count); 4389 4390 if (base->bytes + 5 > length - idx) 4391 return -EINVAL; 4392 for (i = idx; i <= base->bytes + 5; i++) 4393 csum += displayid[i]; 4394 if (csum) { 4395 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4396 return -EINVAL; 4397 } 4398 return 0; 4399 } 4400 4401 static struct 4402 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4403 *timings) 4404 { 4405 struct drm_display_mode *mode; 4406 unsigned pixel_clock = (timings->pixel_clock[0] | 4407 (timings->pixel_clock[1] << 8) | 4408 (timings->pixel_clock[2] << 16)); 4409 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4410 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4411 unsigned hsync = (timings->hsync[0] | 4412 (timings->hsync[1] & 0x7f) << 8) + 1; 4413 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4414 unsigned vactive = (timings->vactive[0] | 4415 timings->vactive[1] << 8) + 1; 4416 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4417 unsigned vsync = (timings->vsync[0] | 4418 (timings->vsync[1] & 0x7f) << 8) + 1; 4419 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4420 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4421 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4422 4423 mode = drm_mode_create(); 4424 if (!mode) 4425 return NULL; 4426 4427 mode->clock = pixel_clock * 10; 4428 mode->hdisplay = hactive; 4429 mode->hsync_start = mode->hdisplay + hsync; 4430 mode->hsync_end = mode->hsync_start + hsync_width; 4431 mode->htotal = mode->hdisplay + hblank; 4432 4433 mode->vdisplay = vactive; 4434 mode->vsync_start = mode->vdisplay + vsync; 4435 mode->vsync_end = mode->vsync_start + vsync_width; 4436 mode->vtotal = mode->vdisplay + vblank; 4437 4438 mode->flags = 0; 4439 mode->flags |= 4440 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4441 mode->flags |= 4442 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4443 mode->type = DRM_MODE_TYPE_DRIVER; 4444 4445 if (timings->flags & 0x80) 4446 mode->type |= DRM_MODE_TYPE_PREFERRED; 4447 mode->vrefresh = drm_get_vrefresh(mode); 4448 4449 return mode; 4450 } 4451 4452 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 4453 struct displayid_block *block) 4454 { 4455 struct displayid_detailed_timing_block *det; 4456 int i; 4457 int num_timings; 4458 struct drm_display_mode *newmode; 4459 int num_modes = 0; 4460 4461 det = (struct displayid_detailed_timing_block *)block; 4462 /* blocks must be multiple of 20 bytes length */ 4463 if (block->num_bytes % 20) 4464 return 0; 4465 4466 num_timings = block->num_bytes / 20; 4467 for (i = 0; i < num_timings; i++) { 4468 struct displayid_detailed_timings_1 *timings = 4469 &det->timings[i]; 4470 4471 newmode = drm_displayid_detailed(timings); 4472 if (!newmode) 4473 continue; 4474 4475 drm_add_hdmi_modes(data, newmode); 4476 num_modes++; 4477 drm_mode_destroy(newmode); 4478 } 4479 return num_modes; 4480 } 4481 4482 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 4483 struct edid *edid) 4484 { 4485 u8 *displayid; 4486 int ret; 4487 int idx = 1; 4488 int length = EDID_SIZE; 4489 struct displayid_block *block; 4490 int num_modes = 0; 4491 4492 displayid = drm_find_displayid_extension(edid); 4493 if (!displayid) 4494 return 0; 4495 4496 ret = validate_displayid(displayid, length, idx); 4497 if (ret) 4498 return 0; 4499 4500 idx += sizeof(struct displayid_hdr); 4501 while (block = (struct displayid_block *)&displayid[idx], 4502 idx + sizeof(struct displayid_block) <= length && 4503 idx + sizeof(struct displayid_block) + block->num_bytes <= 4504 length && block->num_bytes > 0) { 4505 idx += block->num_bytes + sizeof(struct displayid_block); 4506 switch (block->tag) { 4507 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4508 num_modes += 4509 add_displayid_detailed_1_modes(data, block); 4510 break; 4511 } 4512 } 4513 return num_modes; 4514 } 4515 4516 static bool 4517 mode_in_hsync_range(const struct drm_display_mode *mode, 4518 struct edid *edid, u8 *t) 4519 { 4520 int hsync, hmin, hmax; 4521 4522 hmin = t[7]; 4523 if (edid->revision >= 4) 4524 hmin += ((t[4] & 0x04) ? 255 : 0); 4525 hmax = t[8]; 4526 if (edid->revision >= 4) 4527 hmax += ((t[4] & 0x08) ? 255 : 0); 4528 hsync = drm_mode_hsync(mode); 4529 4530 return (hsync <= hmax && hsync >= hmin); 4531 } 4532 4533 static bool 4534 mode_in_vsync_range(const struct drm_display_mode *mode, 4535 struct edid *edid, u8 *t) 4536 { 4537 int vsync, vmin, vmax; 4538 4539 vmin = t[5]; 4540 if (edid->revision >= 4) 4541 vmin += ((t[4] & 0x01) ? 255 : 0); 4542 vmax = t[6]; 4543 if (edid->revision >= 4) 4544 vmax += ((t[4] & 0x02) ? 255 : 0); 4545 vsync = drm_get_vrefresh(mode); 4546 4547 return (vsync <= vmax && vsync >= vmin); 4548 } 4549 4550 static u32 4551 range_pixel_clock(struct edid *edid, u8 *t) 4552 { 4553 /* unspecified */ 4554 if (t[9] == 0 || t[9] == 255) 4555 return 0; 4556 4557 /* 1.4 with CVT support gives us real precision, yay */ 4558 if (edid->revision >= 4 && t[10] == 0x04) 4559 return (t[9] * 10000) - ((t[12] >> 2) * 250); 4560 4561 /* 1.3 is pathetic, so fuzz up a bit */ 4562 return t[9] * 10000 + 5001; 4563 } 4564 4565 static bool 4566 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 4567 struct detailed_timing *timing) 4568 { 4569 u32 max_clock; 4570 u8 *t = (u8 *)timing; 4571 4572 if (!mode_in_hsync_range(mode, edid, t)) 4573 return false; 4574 4575 if (!mode_in_vsync_range(mode, edid, t)) 4576 return false; 4577 4578 max_clock = range_pixel_clock(edid, t); 4579 if (max_clock) 4580 if (mode->clock > max_clock) 4581 return false; 4582 4583 /* 1.4 max horizontal check */ 4584 if (edid->revision >= 4 && t[10] == 0x04) 4585 if (t[13] && mode->hdisplay > 8 * 4586 (t[13] + (256 * (t[12] & 0x3)))) 4587 return false; 4588 4589 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 4590 return false; 4591 4592 return true; 4593 } 4594 4595 static bool valid_inferred_mode(struct hdmi_edid_data *data, 4596 const struct drm_display_mode *mode) 4597 { 4598 const struct drm_display_mode *m; 4599 bool ok = false; 4600 int i; 4601 4602 for (i = 0; i < data->modes; i++) { 4603 m = &data->mode_buf[i]; 4604 if (mode->hdisplay == m->hdisplay && 4605 mode->vdisplay == m->vdisplay && 4606 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 4607 return false; /* duplicated */ 4608 if (mode->hdisplay <= m->hdisplay && 4609 mode->vdisplay <= m->vdisplay) 4610 ok = true; 4611 } 4612 return ok; 4613 } 4614 4615 static int 4616 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4617 struct detailed_timing *timing) 4618 { 4619 int i, modes = 0; 4620 4621 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4622 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 4623 valid_inferred_mode(data, drm_dmt_modes + i)) { 4624 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 4625 modes++; 4626 } 4627 } 4628 4629 return modes; 4630 } 4631 4632 /* fix up 1366x768 mode from 1368x768; 4633 * GFT/CVT can't express 1366 width which isn't dividable by 8 4634 */ 4635 static void fixup_mode_1366x768(struct drm_display_mode *mode) 4636 { 4637 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 4638 mode->hdisplay = 1366; 4639 mode->hsync_start--; 4640 mode->hsync_end--; 4641 } 4642 } 4643 4644 static int 4645 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4646 struct detailed_timing *timing) 4647 { 4648 int i, modes = 0; 4649 struct drm_display_mode *newmode; 4650 4651 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4652 const struct minimode *m = &extra_modes[i]; 4653 4654 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 4655 if (!newmode) 4656 return modes; 4657 4658 fixup_mode_1366x768(newmode); 4659 if (!mode_in_range(newmode, edid, timing) || 4660 !valid_inferred_mode(data, newmode)) { 4661 drm_mode_destroy(newmode); 4662 continue; 4663 } 4664 4665 drm_add_hdmi_modes(data, newmode); 4666 modes++; 4667 drm_mode_destroy(newmode); 4668 } 4669 4670 return modes; 4671 } 4672 4673 static int 4674 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4675 struct detailed_timing *timing) 4676 { 4677 int i, modes = 0; 4678 struct drm_display_mode *newmode; 4679 bool rb = drm_monitor_supports_rb(edid); 4680 4681 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4682 const struct minimode *m = &extra_modes[i]; 4683 4684 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 4685 if (!newmode) 4686 return modes; 4687 4688 fixup_mode_1366x768(newmode); 4689 if (!mode_in_range(newmode, edid, timing) || 4690 !valid_inferred_mode(data, newmode)) { 4691 drm_mode_destroy(newmode); 4692 continue; 4693 } 4694 4695 drm_add_hdmi_modes(data, newmode); 4696 modes++; 4697 drm_mode_destroy(newmode); 4698 } 4699 4700 return modes; 4701 } 4702 4703 static void 4704 do_inferred_modes(struct detailed_timing *timing, void *c) 4705 { 4706 struct detailed_mode_closure *closure = c; 4707 struct detailed_non_pixel *data = &timing->data.other_data; 4708 struct detailed_data_monitor_range *range = &data->data.range; 4709 4710 if (data->type != EDID_DETAIL_MONITOR_RANGE) 4711 return; 4712 4713 closure->modes += drm_dmt_modes_for_range(closure->data, 4714 closure->edid, 4715 timing); 4716 4717 if (!version_greater(closure->edid, 1, 1)) 4718 return; /* GTF not defined yet */ 4719 4720 switch (range->flags) { 4721 case 0x02: /* secondary gtf, XXX could do more */ 4722 case 0x00: /* default gtf */ 4723 closure->modes += drm_gtf_modes_for_range(closure->data, 4724 closure->edid, 4725 timing); 4726 break; 4727 case 0x04: /* cvt, only in 1.4+ */ 4728 if (!version_greater(closure->edid, 1, 3)) 4729 break; 4730 4731 closure->modes += drm_cvt_modes_for_range(closure->data, 4732 closure->edid, 4733 timing); 4734 break; 4735 case 0x01: /* just the ranges, no formula */ 4736 default: 4737 break; 4738 } 4739 } 4740 4741 static int 4742 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 4743 { 4744 struct detailed_mode_closure closure = { 4745 .data = data, 4746 .edid = edid, 4747 }; 4748 4749 if (version_greater(edid, 1, 0)) 4750 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 4751 &closure); 4752 4753 return closure.modes; 4754 } 4755 4756 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 4757 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 4758 4759 /** 4760 * edid_fixup_preferred - set preferred modes based on quirk list 4761 * @data: the structure that save parsed hdmi edid data 4762 * @quirks: quirks list 4763 * 4764 * Walk the mode list, clearing the preferred status 4765 * on existing modes and setting it anew for the right mode ala @quirks. 4766 */ 4767 static void edid_fixup_preferred(struct hdmi_edid_data *data, 4768 u32 quirks) 4769 { 4770 struct drm_display_mode *cur_mode, *preferred_mode; 4771 int i, target_refresh = 0; 4772 int num = data->modes; 4773 int cur_vrefresh, preferred_vrefresh; 4774 4775 if (!num) 4776 return; 4777 4778 preferred_mode = data->preferred_mode; 4779 4780 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 4781 target_refresh = 60; 4782 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 4783 target_refresh = 75; 4784 4785 for (i = 0; i < num; i++) { 4786 cur_mode = &data->mode_buf[i]; 4787 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 4788 4789 if (cur_mode == preferred_mode) 4790 continue; 4791 4792 /* Largest mode is preferred */ 4793 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 4794 preferred_mode = cur_mode; 4795 4796 cur_vrefresh = cur_mode->vrefresh ? 4797 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 4798 preferred_vrefresh = preferred_mode->vrefresh ? 4799 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 4800 /* At a given size, try to get closest to target refresh */ 4801 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 4802 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 4803 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 4804 preferred_mode = cur_mode; 4805 } 4806 } 4807 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 4808 data->preferred_mode = preferred_mode; 4809 } 4810 4811 static const u8 edid_header[] = { 4812 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 4813 }; 4814 4815 /** 4816 * drm_edid_header_is_valid - sanity check the header of the base EDID block 4817 * @raw_edid: pointer to raw base EDID block 4818 * 4819 * Sanity check the header of the base EDID block. 4820 * 4821 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 4822 */ 4823 static int drm_edid_header_is_valid(const u8 *raw_edid) 4824 { 4825 int i, score = 0; 4826 4827 for (i = 0; i < sizeof(edid_header); i++) 4828 if (raw_edid[i] == edid_header[i]) 4829 score++; 4830 4831 return score; 4832 } 4833 4834 static int drm_edid_block_checksum(const u8 *raw_edid) 4835 { 4836 int i; 4837 u8 csum = 0; 4838 4839 for (i = 0; i < EDID_SIZE; i++) 4840 csum += raw_edid[i]; 4841 4842 return csum; 4843 } 4844 4845 static bool drm_edid_is_zero(const u8 *in_edid, int length) 4846 { 4847 if (memchr_inv(in_edid, 0, length)) 4848 return false; 4849 4850 return true; 4851 } 4852 4853 /** 4854 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 4855 * @raw_edid: pointer to raw EDID block 4856 * @block: type of block to validate (0 for base, extension otherwise) 4857 * @print_bad_edid: if true, dump bad EDID blocks to the console 4858 * @edid_corrupt: if true, the header or checksum is invalid 4859 * 4860 * Validate a base or extension EDID block and optionally dump bad blocks to 4861 * the console. 4862 * 4863 * Return: True if the block is valid, false otherwise. 4864 */ 4865 static 4866 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 4867 bool *edid_corrupt) 4868 { 4869 u8 csum; 4870 int edid_fixup = 6; 4871 struct edid *edid = (struct edid *)raw_edid; 4872 4873 if ((!raw_edid)) 4874 return false; 4875 4876 if (block == 0) { 4877 int score = drm_edid_header_is_valid(raw_edid); 4878 4879 if (score == 8) { 4880 if (edid_corrupt) 4881 *edid_corrupt = false; 4882 } else if (score >= edid_fixup) { 4883 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 4884 * The corrupt flag needs to be set here otherwise, the 4885 * fix-up code here will correct the problem, the 4886 * checksum is correct and the test fails 4887 */ 4888 if (edid_corrupt) 4889 *edid_corrupt = true; 4890 debug("Fixing header, your hardware may be failing\n"); 4891 memcpy(raw_edid, edid_header, sizeof(edid_header)); 4892 } else { 4893 if (edid_corrupt) 4894 *edid_corrupt = true; 4895 goto bad; 4896 } 4897 } 4898 4899 csum = drm_edid_block_checksum(raw_edid); 4900 if (csum) { 4901 if (print_bad_edid) { 4902 debug("EDID checksum is invalid, remainder is %d\n", 4903 csum); 4904 } 4905 4906 if (edid_corrupt) 4907 *edid_corrupt = true; 4908 4909 /* allow CEA to slide through, switches mangle this */ 4910 if (raw_edid[0] != 0x02) 4911 goto bad; 4912 } 4913 4914 /* per-block-type checks */ 4915 switch (raw_edid[0]) { 4916 case 0: /* base */ 4917 if (edid->version != 1) { 4918 debug("EDID has major version %d, instead of 1\n", 4919 edid->version); 4920 goto bad; 4921 } 4922 4923 if (edid->revision > 4) 4924 debug("minor > 4, assuming backward compatibility\n"); 4925 break; 4926 4927 default: 4928 break; 4929 } 4930 4931 return true; 4932 4933 bad: 4934 if (print_bad_edid) { 4935 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 4936 debug("EDID block is all zeroes\n"); 4937 } else { 4938 debug("Raw EDID:\n"); 4939 print_hex_dump("", DUMP_PREFIX_NONE, 16, 1, 4940 raw_edid, EDID_SIZE, false); 4941 } 4942 } 4943 return false; 4944 } 4945 4946 /** 4947 * drm_edid_is_valid - sanity check EDID data 4948 * @edid: EDID data 4949 * 4950 * Sanity-check an entire EDID record (including extensions) 4951 * 4952 * Return: True if the EDID data is valid, false otherwise. 4953 */ 4954 static bool drm_edid_is_valid(struct edid *edid) 4955 { 4956 int i; 4957 u8 *raw = (u8 *)edid; 4958 4959 if (!edid) 4960 return false; 4961 4962 for (i = 0; i <= edid->extensions; i++) 4963 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 4964 return false; 4965 4966 return true; 4967 } 4968 4969 /** 4970 * drm_add_edid_modes - add modes from EDID data, if available 4971 * @data: data we're probing 4972 * @edid: EDID data 4973 * 4974 * Add the specified modes to the data's mode list. 4975 * 4976 * Return: The number of modes added or 0 if we couldn't find any. 4977 */ 4978 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 4979 { 4980 int num_modes = 0; 4981 u32 quirks; 4982 struct edid *edid = (struct edid *)raw_edid; 4983 4984 if (!edid) { 4985 debug("no edid\n"); 4986 return 0; 4987 } 4988 4989 if (!drm_edid_is_valid(edid)) { 4990 debug("EDID invalid\n"); 4991 return 0; 4992 } 4993 4994 if (!data->mode_buf) { 4995 debug("mode buff is null\n"); 4996 return 0; 4997 } 4998 4999 quirks = edid_get_quirks(edid); 5000 /* 5001 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5002 * To avoid multiple parsing of same block, lets parse that map 5003 * from sink info, before parsing CEA modes. 5004 */ 5005 drm_add_display_info(data, edid); 5006 5007 /* 5008 * EDID spec says modes should be preferred in this order: 5009 * - preferred detailed mode 5010 * - other detailed modes from base block 5011 * - detailed modes from extension blocks 5012 * - CVT 3-byte code modes 5013 * - standard timing codes 5014 * - established timing codes 5015 * - modes inferred from GTF or CVT range information 5016 * 5017 * We get this pretty much right. 5018 * 5019 * XXX order for additional mode types in extension blocks? 5020 */ 5021 num_modes += add_detailed_modes(data, edid, quirks); 5022 num_modes += add_cvt_modes(data, edid); 5023 num_modes += add_standard_modes(data, edid); 5024 num_modes += add_established_modes(data, edid); 5025 num_modes += add_cea_modes(data, edid); 5026 num_modes += add_alternate_cea_modes(data, edid); 5027 num_modes += add_displayid_detailed_modes(data, edid); 5028 5029 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5030 num_modes += add_inferred_modes(data, edid); 5031 5032 if (num_modes > 0) 5033 data->preferred_mode = &data->mode_buf[0]; 5034 5035 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5036 edid_fixup_preferred(data, quirks); 5037 5038 if (quirks & EDID_QUIRK_FORCE_6BPC) 5039 data->display_info.bpc = 6; 5040 5041 if (quirks & EDID_QUIRK_FORCE_8BPC) 5042 data->display_info.bpc = 8; 5043 5044 if (quirks & EDID_QUIRK_FORCE_10BPC) 5045 data->display_info.bpc = 10; 5046 5047 if (quirks & EDID_QUIRK_FORCE_12BPC) 5048 data->display_info.bpc = 12; 5049 5050 return num_modes; 5051 } 5052 5053 static int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5054 { 5055 memset(frame, 0, sizeof(*frame)); 5056 5057 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5058 frame->version = 2; 5059 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5060 5061 return 0; 5062 } 5063 5064 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5065 { 5066 u8 vic; 5067 5068 if (!to_match->clock) { 5069 printf("can't find to match\n"); 5070 return 0; 5071 } 5072 5073 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 5074 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 5075 unsigned int clock1, clock2; 5076 5077 /* Check both 60Hz and 59.94Hz */ 5078 clock1 = cea_mode->clock; 5079 clock2 = cea_mode_alternate_clock(cea_mode); 5080 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5081 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5082 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5083 return vic; 5084 } 5085 5086 return 0; 5087 } 5088 5089 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5090 { 5091 return edid_cea_modes[video_code].picture_aspect_ratio; 5092 } 5093 5094 int 5095 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5096 struct drm_display_mode *mode, 5097 bool is_hdmi2_sink) 5098 { 5099 int err; 5100 5101 if (!frame || !mode) 5102 return -EINVAL; 5103 5104 err = hdmi_avi_infoframe_init(frame); 5105 if (err < 0) 5106 return err; 5107 5108 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5109 frame->pixel_repeat = 1; 5110 5111 frame->video_code = drm_match_cea_mode(mode); 5112 5113 /* 5114 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5115 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5116 * have to make sure we dont break HDMI 1.4 sinks. 5117 */ 5118 if (!is_hdmi2_sink && frame->video_code > 64) 5119 frame->video_code = 0; 5120 5121 /* 5122 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5123 * we should send its VIC in vendor infoframes, else send the 5124 * VIC in AVI infoframes. Lets check if this mode is present in 5125 * HDMI 1.4b 4K modes 5126 */ 5127 if (frame->video_code) { 5128 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5129 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5130 5131 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5132 frame->video_code = 0; 5133 } 5134 5135 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5136 5137 /* 5138 * Populate picture aspect ratio from either 5139 * user input (if specified) or from the CEA mode list. 5140 */ 5141 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5142 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5143 frame->picture_aspect = mode->picture_aspect_ratio; 5144 else if (frame->video_code > 0) 5145 frame->picture_aspect = drm_get_cea_aspect_ratio( 5146 frame->video_code); 5147 5148 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5149 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5150 5151 return 0; 5152 } 5153 5154 /** 5155 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5156 * @frame: HDMI vendor infoframe 5157 * 5158 * Returns 0 on success or a negative error code on failure. 5159 */ 5160 static int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5161 { 5162 memset(frame, 0, sizeof(*frame)); 5163 5164 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5165 frame->version = 1; 5166 5167 frame->oui = HDMI_IEEE_OUI; 5168 5169 /* 5170 * 0 is a valid value for s3d_struct, so we use a special "not set" 5171 * value 5172 */ 5173 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5174 5175 return 0; 5176 } 5177 5178 /** 5179 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5180 * quantization range information 5181 * @frame: HDMI AVI infoframe 5182 * @rgb_quant_range: RGB quantization range (Q) 5183 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 5184 */ 5185 void 5186 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5187 struct drm_display_mode *mode, 5188 enum hdmi_quantization_range rgb_quant_range, 5189 bool rgb_quant_range_selectable) 5190 { 5191 /* 5192 * CEA-861: 5193 * "A Source shall not send a non-zero Q value that does not correspond 5194 * to the default RGB Quantization Range for the transmitted Picture 5195 * unless the Sink indicates support for the Q bit in a Video 5196 * Capabilities Data Block." 5197 * 5198 * HDMI 2.0 recommends sending non-zero Q when it does match the 5199 * default RGB quantization range for the mode, even when QS=0. 5200 */ 5201 if (rgb_quant_range_selectable || 5202 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5203 frame->quantization_range = rgb_quant_range; 5204 else 5205 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5206 5207 /* 5208 * CEA-861-F: 5209 * "When transmitting any RGB colorimetry, the Source should set the 5210 * YQ-field to match the RGB Quantization Range being transmitted 5211 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5212 * set YQ=1) and the Sink shall ignore the YQ-field." 5213 */ 5214 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5215 frame->ycc_quantization_range = 5216 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5217 else 5218 frame->ycc_quantization_range = 5219 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5220 } 5221 5222 static enum hdmi_3d_structure 5223 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5224 { 5225 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5226 5227 switch (layout) { 5228 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5229 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5230 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5231 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5232 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5233 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5234 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5235 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5236 case DRM_MODE_FLAG_3D_L_DEPTH: 5237 return HDMI_3D_STRUCTURE_L_DEPTH; 5238 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5239 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5240 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5241 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5242 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5243 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5244 default: 5245 return HDMI_3D_STRUCTURE_INVALID; 5246 } 5247 } 5248 5249 int 5250 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5251 struct drm_display_mode *mode) 5252 { 5253 int err; 5254 u32 s3d_flags; 5255 u8 vic; 5256 5257 if (!frame || !mode) 5258 return -EINVAL; 5259 5260 vic = drm_match_hdmi_mode(mode); 5261 5262 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5263 5264 if (!vic && !s3d_flags) 5265 return -EINVAL; 5266 5267 if (vic && s3d_flags) 5268 return -EINVAL; 5269 5270 err = hdmi_vendor_infoframe_init(frame); 5271 if (err < 0) 5272 return err; 5273 5274 if (vic) 5275 frame->vic = vic; 5276 else 5277 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5278 5279 return 0; 5280 } 5281 5282 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5283 { 5284 u8 csum = 0; 5285 size_t i; 5286 5287 /* compute checksum */ 5288 for (i = 0; i < size; i++) 5289 csum += ptr[i]; 5290 5291 return 256 - csum; 5292 } 5293 5294 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5295 { 5296 u8 *ptr = buffer; 5297 5298 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5299 } 5300 5301 /** 5302 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 5303 * @frame: HDMI infoframe 5304 * @buffer: destination buffer 5305 * @size: size of buffer 5306 * 5307 * Packs the information contained in the @frame structure into a binary 5308 * representation that can be written into the corresponding controller 5309 * registers. Also computes the checksum as required by section 5.3.5 of 5310 * the HDMI 1.4 specification. 5311 * 5312 * Returns the number of bytes packed into the binary buffer or a negative 5313 * error code on failure. 5314 */ 5315 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 5316 void *buffer, size_t size) 5317 { 5318 u8 *ptr = buffer; 5319 size_t length; 5320 5321 /* empty info frame */ 5322 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 5323 return -EINVAL; 5324 5325 /* only one of those can be supplied */ 5326 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 5327 return -EINVAL; 5328 5329 /* for side by side (half) we also need to provide 3D_Ext_Data */ 5330 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5331 frame->length = 6; 5332 else 5333 frame->length = 5; 5334 5335 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5336 5337 if (size < length) 5338 return -ENOSPC; 5339 5340 memset(buffer, 0, size); 5341 5342 ptr[0] = frame->type; 5343 ptr[1] = frame->version; 5344 ptr[2] = frame->length; 5345 ptr[3] = 0; /* checksum */ 5346 5347 /* HDMI OUI */ 5348 ptr[4] = 0x03; 5349 ptr[5] = 0x0c; 5350 ptr[6] = 0x00; 5351 5352 if (frame->vic) { 5353 ptr[7] = 0x1 << 5; /* video format */ 5354 ptr[8] = frame->vic; 5355 } else { 5356 ptr[7] = 0x2 << 5; /* video format */ 5357 ptr[8] = (frame->s3d_struct & 0xf) << 4; 5358 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5359 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 5360 } 5361 5362 hdmi_infoframe_set_checksum(buffer, length); 5363 5364 return length; 5365 } 5366 5367 /** 5368 * drm_do_probe_ddc_edid() - get EDID information via I2C 5369 * @adap: ddc adapter 5370 * @buf: EDID data buffer to be filled 5371 * @block: 128 byte EDID block to start fetching from 5372 * @len: EDID data buffer length to fetch 5373 * 5374 * Try to fetch EDID information by calling I2C driver functions. 5375 * 5376 * Return: 0 on success or -1 on failure. 5377 */ 5378 static int 5379 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 5380 size_t len) 5381 { 5382 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 5383 unsigned char segment = block >> 1; 5384 unsigned char xfers = segment ? 3 : 2; 5385 int ret, retries = 5; 5386 5387 do { 5388 struct i2c_msg msgs[] = { 5389 { 5390 .addr = DDC_SEGMENT_ADDR, 5391 .flags = 0, 5392 .len = 1, 5393 .buf = &segment, 5394 }, { 5395 .addr = DDC_ADDR, 5396 .flags = 0, 5397 .len = 1, 5398 .buf = &start, 5399 }, { 5400 .addr = DDC_ADDR, 5401 .flags = I2C_M_RD, 5402 .len = len, 5403 .buf = buf, 5404 } 5405 }; 5406 5407 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 5408 5409 } while (ret != xfers && --retries); 5410 5411 /* All msg transfer successfully. */ 5412 return ret == xfers ? 0 : -1; 5413 } 5414 5415 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid) 5416 { 5417 int i, j, block_num, block = 0; 5418 bool edid_corrupt; 5419 #ifdef DEBUG 5420 u8 *buff; 5421 #endif 5422 5423 /* base block fetch */ 5424 for (i = 0; i < 4; i++) { 5425 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 5426 goto err; 5427 if (drm_edid_block_valid(edid, 0, true, 5428 &edid_corrupt)) 5429 break; 5430 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 5431 printf("edid base block is 0, get edid failed\n"); 5432 goto err; 5433 } 5434 } 5435 5436 if (i == 4) 5437 goto err; 5438 5439 block++; 5440 /* get the number of extensions */ 5441 block_num = edid[0x7e]; 5442 5443 for (j = 1; j <= block_num; j++) { 5444 for (i = 0; i < 4; i++) { 5445 if (drm_do_probe_ddc_edid(adap, &edid[0x80 * j], j, 5446 HDMI_EDID_BLOCK_SIZE)) 5447 goto err; 5448 if (drm_edid_block_valid(&edid[0x80 * j], j, 5449 true, NULL)) 5450 break; 5451 } 5452 5453 if (i == 4) 5454 goto err; 5455 block++; 5456 } 5457 5458 #ifdef DEBUG 5459 printf("RAW EDID:\n"); 5460 for (i = 0; i < block_num + 1; i++) { 5461 buff = &edid[0x80 * i]; 5462 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 5463 if (j % 16 == 0) 5464 printf("\n"); 5465 printf("0x%02x, ", buff[j]); 5466 } 5467 printf("\n"); 5468 } 5469 #endif 5470 5471 return 0; 5472 5473 err: 5474 printf("can't get edid block:%d\n", block); 5475 /* clear all read edid block, include invalid block */ 5476 memset(edid, 0, HDMI_EDID_BLOCK_SIZE * (block + 1)); 5477 return -EFAULT; 5478 } 5479 5480 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 5481 void *buffer, size_t size) 5482 { 5483 struct i2c_msg msgs[2] = { 5484 { 5485 .addr = addr, 5486 .flags = 0, 5487 .len = 1, 5488 .buf = &offset, 5489 }, { 5490 .addr = addr, 5491 .flags = I2C_M_RD, 5492 .len = size, 5493 .buf = buffer, 5494 } 5495 }; 5496 5497 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 5498 } 5499 5500 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 5501 const void *buffer, size_t size) 5502 { 5503 struct i2c_msg msg = { 5504 .addr = addr, 5505 .flags = 0, 5506 .len = 1 + size, 5507 .buf = NULL, 5508 }; 5509 void *data; 5510 int err; 5511 5512 data = malloc(1 + size); 5513 if (!data) 5514 return -ENOMEM; 5515 5516 msg.buf = data; 5517 5518 memcpy(data, &offset, sizeof(offset)); 5519 memcpy(data + 1, buffer, size); 5520 5521 err = adap->ddc_xfer(adap, &msg, 1); 5522 5523 free(data); 5524 5525 return err; 5526 } 5527 5528 /** 5529 * drm_scdc_readb - read a single byte from SCDC 5530 * @adap: ddc adapter 5531 * @offset: offset of register to read 5532 * @value: return location for the register value 5533 * 5534 * Reads a single byte from SCDC. This is a convenience wrapper around the 5535 * drm_scdc_read() function. 5536 * 5537 * Returns: 5538 * 0 on success or a negative error code on failure. 5539 */ 5540 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 5541 u8 *value) 5542 { 5543 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 5544 sizeof(*value)); 5545 } 5546 5547 /** 5548 * drm_scdc_writeb - write a single byte to SCDC 5549 * @adap: ddc adapter 5550 * @offset: offset of register to read 5551 * @value: return location for the register value 5552 * 5553 * Writes a single byte to SCDC. This is a convenience wrapper around the 5554 * drm_scdc_write() function. 5555 * 5556 * Returns: 5557 * 0 on success or a negative error code on failure. 5558 */ 5559 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 5560 u8 value) 5561 { 5562 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 5563 sizeof(value)); 5564 } 5565 5566