1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <hexdump.h> 22 #include <malloc.h> 23 #include <linux/compat.h> 24 #include <linux/ctype.h> 25 #include <linux/fb.h> 26 #include <linux/hdmi.h> 27 #include <linux/string.h> 28 29 #define EDID_EST_TIMINGS 16 30 #define EDID_STD_TIMINGS 8 31 #define EDID_DETAILED_TIMINGS 4 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 bool preferred; 78 u32 quirks; 79 int modes; 80 }; 81 82 #define LEVEL_DMT 0 83 #define LEVEL_GTF 1 84 #define LEVEL_GTF2 2 85 #define LEVEL_CVT 3 86 87 static struct edid_quirk { 88 char vendor[4]; 89 int product_id; 90 u32 quirks; 91 } edid_quirk_list[] = { 92 /* Acer AL1706 */ 93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Acer F51 */ 95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Unknown Acer */ 97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 98 99 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 100 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 116 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 146 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 147 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Probably taken from CEA-861 spec. 152 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 153 * 154 * Index using the VIC. 155 */ 156 /* 157 * From CEA/CTA-861 spec. 158 * Do not access directly, instead always use cea_mode_for_vic(). 159 */ 160 static const struct drm_display_mode edid_cea_modes_1[] = { 161 /* 1 - 640x480@60Hz */ 162 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 163 752, 800, 480, 490, 492, 525, 0, 164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 165 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 166 /* 2 - 720x480@60Hz */ 167 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 168 798, 858, 480, 489, 495, 525, 0, 169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 170 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 171 /* 3 - 720x480@60Hz */ 172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 173 798, 858, 480, 489, 495, 525, 0, 174 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 175 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 176 /* 4 - 1280x720@60Hz */ 177 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 178 1430, 1650, 720, 725, 730, 750, 0, 179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 180 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 181 /* 5 - 1920x1080i@60Hz */ 182 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 183 2052, 2200, 1080, 1084, 1094, 1125, 0, 184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 185 DRM_MODE_FLAG_INTERLACE), 186 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 187 /* 6 - 720(1440)x480i@60Hz */ 188 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 189 801, 858, 480, 488, 494, 525, 0, 190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 191 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 193 /* 7 - 720(1440)x480i@60Hz */ 194 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 195 801, 858, 480, 488, 494, 525, 0, 196 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 197 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 198 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 199 /* 8 - 720(1440)x240@60Hz */ 200 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 201 801, 858, 240, 244, 247, 262, 0, 202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 203 DRM_MODE_FLAG_DBLCLK), 204 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 205 /* 9 - 720(1440)x240@60Hz */ 206 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 207 801, 858, 240, 244, 247, 262, 0, 208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 209 DRM_MODE_FLAG_DBLCLK), 210 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 211 /* 10 - 2880x480i@60Hz */ 212 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 213 3204, 3432, 480, 488, 494, 525, 0, 214 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 215 DRM_MODE_FLAG_INTERLACE), 216 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 217 /* 11 - 2880x480i@60Hz */ 218 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 219 3204, 3432, 480, 488, 494, 525, 0, 220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 221 DRM_MODE_FLAG_INTERLACE), 222 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 223 /* 12 - 2880x240@60Hz */ 224 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 225 3204, 3432, 240, 244, 247, 262, 0, 226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 228 /* 13 - 2880x240@60Hz */ 229 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 230 3204, 3432, 240, 244, 247, 262, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 232 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 233 /* 14 - 1440x480@60Hz */ 234 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 235 1596, 1716, 480, 489, 495, 525, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 237 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 238 /* 15 - 1440x480@60Hz */ 239 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 240 1596, 1716, 480, 489, 495, 525, 0, 241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 242 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 243 /* 16 - 1920x1080@60Hz */ 244 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 245 2052, 2200, 1080, 1084, 1089, 1125, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 247 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 248 /* 17 - 720x576@50Hz */ 249 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 250 796, 864, 576, 581, 586, 625, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 252 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 253 /* 18 - 720x576@50Hz */ 254 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 255 796, 864, 576, 581, 586, 625, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 257 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 258 /* 19 - 1280x720@50Hz */ 259 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 260 1760, 1980, 720, 725, 730, 750, 0, 261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 262 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 263 /* 20 - 1920x1080i@50Hz */ 264 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 265 2492, 2640, 1080, 1084, 1094, 1125, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 267 DRM_MODE_FLAG_INTERLACE), 268 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 269 /* 21 - 720(1440)x576i@50Hz */ 270 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 271 795, 864, 576, 580, 586, 625, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 273 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 274 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 275 /* 22 - 720(1440)x576i@50Hz */ 276 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 277 795, 864, 576, 580, 586, 625, 0, 278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 279 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 280 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 281 /* 23 - 720(1440)x288@50Hz */ 282 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 283 795, 864, 288, 290, 293, 312, 0, 284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 285 DRM_MODE_FLAG_DBLCLK), 286 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 287 /* 24 - 720(1440)x288@50Hz */ 288 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 289 795, 864, 288, 290, 293, 312, 0, 290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 291 DRM_MODE_FLAG_DBLCLK), 292 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 293 /* 25 - 2880x576i@50Hz */ 294 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 295 3180, 3456, 576, 580, 586, 625, 0, 296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 297 DRM_MODE_FLAG_INTERLACE), 298 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 299 /* 26 - 2880x576i@50Hz */ 300 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 301 3180, 3456, 576, 580, 586, 625, 0, 302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 303 DRM_MODE_FLAG_INTERLACE), 304 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 305 /* 27 - 2880x288@50Hz */ 306 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 307 3180, 3456, 288, 290, 293, 312, 0, 308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 309 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 310 /* 28 - 2880x288@50Hz */ 311 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 312 3180, 3456, 288, 290, 293, 312, 0, 313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 314 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 315 /* 29 - 1440x576@50Hz */ 316 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 317 1592, 1728, 576, 581, 586, 625, 0, 318 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 319 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 320 /* 30 - 1440x576@50Hz */ 321 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 322 1592, 1728, 576, 581, 586, 625, 0, 323 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 324 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 325 /* 31 - 1920x1080@50Hz */ 326 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 327 2492, 2640, 1080, 1084, 1089, 1125, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 329 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 330 /* 32 - 1920x1080@24Hz */ 331 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 332 2602, 2750, 1080, 1084, 1089, 1125, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 334 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 335 /* 33 - 1920x1080@25Hz */ 336 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 337 2492, 2640, 1080, 1084, 1089, 1125, 0, 338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 339 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 340 /* 34 - 1920x1080@30Hz */ 341 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 342 2052, 2200, 1080, 1084, 1089, 1125, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 344 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 345 /* 35 - 2880x480@60Hz */ 346 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 347 3192, 3432, 480, 489, 495, 525, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 349 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 350 /* 36 - 2880x480@60Hz */ 351 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 352 3192, 3432, 480, 489, 495, 525, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 354 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 355 /* 37 - 2880x576@50Hz */ 356 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 357 3184, 3456, 576, 581, 586, 625, 0, 358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 359 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 360 /* 38 - 2880x576@50Hz */ 361 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 362 3184, 3456, 576, 581, 586, 625, 0, 363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 364 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 365 /* 39 - 1920x1080i@50Hz */ 366 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 367 2120, 2304, 1080, 1126, 1136, 1250, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 369 DRM_MODE_FLAG_INTERLACE), 370 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 371 /* 40 - 1920x1080i@100Hz */ 372 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 373 2492, 2640, 1080, 1084, 1094, 1125, 0, 374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 375 DRM_MODE_FLAG_INTERLACE), 376 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 377 /* 41 - 1280x720@100Hz */ 378 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 379 1760, 1980, 720, 725, 730, 750, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 381 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 382 /* 42 - 720x576@100Hz */ 383 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 384 796, 864, 576, 581, 586, 625, 0, 385 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 386 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 387 /* 43 - 720x576@100Hz */ 388 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 389 796, 864, 576, 581, 586, 625, 0, 390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 391 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 392 /* 44 - 720(1440)x576i@100Hz */ 393 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 394 795, 864, 576, 580, 586, 625, 0, 395 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 396 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 397 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 398 /* 45 - 720(1440)x576i@100Hz */ 399 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 400 795, 864, 576, 580, 586, 625, 0, 401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 402 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 403 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 404 /* 46 - 1920x1080i@120Hz */ 405 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 406 2052, 2200, 1080, 1084, 1094, 1125, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 408 DRM_MODE_FLAG_INTERLACE), 409 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 410 /* 47 - 1280x720@120Hz */ 411 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 412 1430, 1650, 720, 725, 730, 750, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 414 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 415 /* 48 - 720x480@120Hz */ 416 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 417 798, 858, 480, 489, 495, 525, 0, 418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 419 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 420 /* 49 - 720x480@120Hz */ 421 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 422 798, 858, 480, 489, 495, 525, 0, 423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 424 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 425 /* 50 - 720(1440)x480i@120Hz */ 426 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 427 801, 858, 480, 488, 494, 525, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 429 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 430 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 431 /* 51 - 720(1440)x480i@120Hz */ 432 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 433 801, 858, 480, 488, 494, 525, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 435 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 436 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 437 /* 52 - 720x576@200Hz */ 438 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 439 796, 864, 576, 581, 586, 625, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 441 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 442 /* 53 - 720x576@200Hz */ 443 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 444 796, 864, 576, 581, 586, 625, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 446 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 447 /* 54 - 720(1440)x576i@200Hz */ 448 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 449 795, 864, 576, 580, 586, 625, 0, 450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 451 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 452 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 453 /* 55 - 720(1440)x576i@200Hz */ 454 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 455 795, 864, 576, 580, 586, 625, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 457 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 458 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 459 /* 56 - 720x480@240Hz */ 460 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 461 798, 858, 480, 489, 495, 525, 0, 462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 463 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 464 /* 57 - 720x480@240Hz */ 465 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 466 798, 858, 480, 489, 495, 525, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 468 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 469 /* 58 - 720(1440)x480i@240 */ 470 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 471 801, 858, 480, 488, 494, 525, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 473 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 474 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 475 /* 59 - 720(1440)x480i@240 */ 476 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 477 801, 858, 480, 488, 494, 525, 0, 478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 479 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 480 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 481 /* 60 - 1280x720@24Hz */ 482 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 483 3080, 3300, 720, 725, 730, 750, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 485 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 486 /* 61 - 1280x720@25Hz */ 487 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 488 3740, 3960, 720, 725, 730, 750, 0, 489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 490 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 491 /* 62 - 1280x720@30Hz */ 492 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 493 3080, 3300, 720, 725, 730, 750, 0, 494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 495 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 496 /* 63 - 1920x1080@120Hz */ 497 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 498 2052, 2200, 1080, 1084, 1089, 1125, 0, 499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 500 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 501 /* 64 - 1920x1080@100Hz */ 502 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 503 2492, 2640, 1080, 1084, 1089, 1125, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 505 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 506 /* 65 - 1280x720@24Hz */ 507 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 508 3080, 3300, 720, 725, 730, 750, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 510 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 511 /* 66 - 1280x720@25Hz */ 512 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 513 3740, 3960, 720, 725, 730, 750, 0, 514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 515 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 516 /* 67 - 1280x720@30Hz */ 517 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 518 3080, 3300, 720, 725, 730, 750, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 520 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 521 /* 68 - 1280x720@50Hz */ 522 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 523 1760, 1980, 720, 725, 730, 750, 0, 524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 525 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 526 /* 69 - 1280x720@60Hz */ 527 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 528 1430, 1650, 720, 725, 730, 750, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 530 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 531 /* 70 - 1280x720@100Hz */ 532 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 533 1760, 1980, 720, 725, 730, 750, 0, 534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 535 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 536 /* 71 - 1280x720@120Hz */ 537 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 538 1430, 1650, 720, 725, 730, 750, 0, 539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 540 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 541 /* 72 - 1920x1080@24Hz */ 542 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 543 2602, 2750, 1080, 1084, 1089, 1125, 0, 544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 545 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 546 /* 73 - 1920x1080@25Hz */ 547 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 548 2492, 2640, 1080, 1084, 1089, 1125, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 550 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 551 /* 74 - 1920x1080@30Hz */ 552 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 553 2052, 2200, 1080, 1084, 1089, 1125, 0, 554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 555 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 556 /* 75 - 1920x1080@50Hz */ 557 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 558 2492, 2640, 1080, 1084, 1089, 1125, 0, 559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 560 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 561 /* 76 - 1920x1080@60Hz */ 562 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 563 2052, 2200, 1080, 1084, 1089, 1125, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 565 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 566 /* 77 - 1920x1080@100Hz */ 567 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 568 2492, 2640, 1080, 1084, 1089, 1125, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 570 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 571 /* 78 - 1920x1080@120Hz */ 572 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 573 2052, 2200, 1080, 1084, 1089, 1125, 0, 574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 575 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 576 /* 79 - 1680x720@24Hz */ 577 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 578 3080, 3300, 720, 725, 730, 750, 0, 579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 580 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 581 /* 80 - 1680x720@25Hz */ 582 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 583 2948, 3168, 720, 725, 730, 750, 0, 584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 585 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 586 /* 81 - 1680x720@30Hz */ 587 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 588 2420, 2640, 720, 725, 730, 750, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 590 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 591 /* 82 - 1680x720@50Hz */ 592 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 593 1980, 2200, 720, 725, 730, 750, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 595 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 596 /* 83 - 1680x720@60Hz */ 597 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 598 1980, 2200, 720, 725, 730, 750, 0, 599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 600 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 601 /* 84 - 1680x720@100Hz */ 602 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 603 1780, 2000, 720, 725, 730, 825, 0, 604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 605 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 606 /* 85 - 1680x720@120Hz */ 607 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 608 1780, 2000, 720, 725, 730, 825, 0, 609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 610 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 611 /* 86 - 2560x1080@24Hz */ 612 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 613 3602, 3750, 1080, 1084, 1089, 1100, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 615 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 616 /* 87 - 2560x1080@25Hz */ 617 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 618 3052, 3200, 1080, 1084, 1089, 1125, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 620 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 621 /* 88 - 2560x1080@30Hz */ 622 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 623 3372, 3520, 1080, 1084, 1089, 1125, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 625 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 626 /* 89 - 2560x1080@50Hz */ 627 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 628 3152, 3300, 1080, 1084, 1089, 1125, 0, 629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 630 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 631 /* 90 - 2560x1080@60Hz */ 632 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 633 2852, 3000, 1080, 1084, 1089, 1100, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 635 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 636 /* 91 - 2560x1080@100Hz */ 637 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 638 2822, 2970, 1080, 1084, 1089, 1250, 0, 639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 640 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 641 /* 92 - 2560x1080@120Hz */ 642 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 643 3152, 3300, 1080, 1084, 1089, 1250, 0, 644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 645 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 646 /* 93 - 3840x2160p@24Hz 16:9 */ 647 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 648 5204, 5500, 2160, 2168, 2178, 2250, 0, 649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 650 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 651 /* 94 - 3840x2160p@25Hz 16:9 */ 652 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 653 4984, 5280, 2160, 2168, 2178, 2250, 0, 654 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 655 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 656 /* 95 - 3840x2160p@30Hz 16:9 */ 657 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 658 4104, 4400, 2160, 2168, 2178, 2250, 0, 659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 660 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 661 /* 96 - 3840x2160p@50Hz 16:9 */ 662 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 663 4984, 5280, 2160, 2168, 2178, 2250, 0, 664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 665 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 666 /* 97 - 3840x2160p@60Hz 16:9 */ 667 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 668 4104, 4400, 2160, 2168, 2178, 2250, 0, 669 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 671 /* 98 - 4096x2160p@24Hz 256:135 */ 672 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 673 5204, 5500, 2160, 2168, 2178, 2250, 0, 674 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 675 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 676 /* 99 - 4096x2160p@25Hz 256:135 */ 677 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 678 5152, 5280, 2160, 2168, 2178, 2250, 0, 679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 680 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 681 /* 100 - 4096x2160p@30Hz 256:135 */ 682 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 683 4272, 4400, 2160, 2168, 2178, 2250, 0, 684 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 685 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 686 /* 101 - 4096x2160p@50Hz 256:135 */ 687 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 688 5152, 5280, 2160, 2168, 2178, 2250, 0, 689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 690 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 691 /* 102 - 4096x2160p@60Hz 256:135 */ 692 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 693 4272, 4400, 2160, 2168, 2178, 2250, 0, 694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 696 /* 103 - 3840x2160p@24Hz 64:27 */ 697 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 698 5204, 5500, 2160, 2168, 2178, 2250, 0, 699 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 700 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 701 /* 104 - 3840x2160p@25Hz 64:27 */ 702 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 703 4104, 4400, 2160, 2168, 2178, 2250, 0, 704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 705 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 706 /* 105 - 3840x2160p@30Hz 64:27 */ 707 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 708 4104, 4400, 2160, 2168, 2178, 2250, 0, 709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 710 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 711 /* 106 - 3840x2160p@50Hz 64:27 */ 712 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 713 4984, 5280, 2160, 2168, 2178, 2250, 0, 714 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 715 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 716 /* 107 - 3840x2160p@60Hz 64:27 */ 717 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 718 4104, 4400, 2160, 2168, 2178, 2250, 0, 719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 721 /* 108 - 1280x720@48Hz 16:9 */ 722 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 723 2280, 2500, 720, 725, 730, 750, 0, 724 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 725 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 726 /* 109 - 1280x720@48Hz 64:27 */ 727 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 728 2280, 2500, 720, 725, 730, 750, 0, 729 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 730 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 731 /* 110 - 1680x720@48Hz 64:27 */ 732 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 733 2530, 2750, 720, 725, 730, 750, 0, 734 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 735 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 736 /* 111 - 1920x1080@48Hz 16:9 */ 737 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 738 2602, 2750, 1080, 1084, 1089, 1125, 0, 739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 740 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 112 - 1920x1080@48Hz 64:27 */ 742 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 743 2602, 2750, 1080, 1084, 1089, 1125, 0, 744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 745 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 746 /* 113 - 2560x1080@48Hz 64:27 */ 747 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 748 3602, 3750, 1080, 1084, 1089, 1100, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 751 /* 114 - 3840x2160@48Hz 16:9 */ 752 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 753 5204, 5500, 2160, 2168, 2178, 2250, 0, 754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 755 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 115 - 4096x2160@48Hz 256:135 */ 757 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 758 5204, 5500, 2160, 2168, 2178, 2250, 0, 759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 760 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 761 /* 116 - 3840x2160@48Hz 64:27 */ 762 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 763 5204, 5500, 2160, 2168, 2178, 2250, 0, 764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 765 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 766 /* 117 - 3840x2160@100Hz 16:9 */ 767 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 768 4984, 5280, 2160, 2168, 2178, 2250, 0, 769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 770 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 771 /* 118 - 3840x2160@120Hz 16:9 */ 772 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 773 4104, 4400, 2160, 2168, 2178, 2250, 0, 774 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 775 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 119 - 3840x2160@100Hz 64:27 */ 777 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 778 4984, 5280, 2160, 2168, 2178, 2250, 0, 779 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 780 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 781 /* 120 - 3840x2160@120Hz 64:27 */ 782 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 783 4104, 4400, 2160, 2168, 2178, 2250, 0, 784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 785 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 786 /* 121 - 5120x2160@24Hz 64:27 */ 787 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 788 7204, 7500, 2160, 2168, 2178, 2200, 0, 789 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 790 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 791 /* 122 - 5120x2160@25Hz 64:27 */ 792 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 793 6904, 7200, 2160, 2168, 2178, 2200, 0, 794 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 795 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 796 /* 123 - 5120x2160@30Hz 64:27 */ 797 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 798 5872, 6000, 2160, 2168, 2178, 2200, 0, 799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 800 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 801 /* 124 - 5120x2160@48Hz 64:27 */ 802 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 803 5954, 6250, 2160, 2168, 2178, 2475, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 806 /* 125 - 5120x2160@50Hz 64:27 */ 807 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 808 6304, 6600, 2160, 2168, 2178, 2250, 0, 809 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 811 /* 126 - 5120x2160@60Hz 64:27 */ 812 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 813 5372, 5500, 2160, 2168, 2178, 2250, 0, 814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 815 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 816 /* 127 - 5120x2160@100Hz 64:27 */ 817 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 818 6304, 6600, 2160, 2168, 2178, 2250, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 821 }; 822 823 static const struct drm_display_mode edid_cea_modes_193[] = { 824 /* 193 - 5120x2160@120Hz 64:27 */ 825 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 826 5372, 5500, 2160, 2168, 2178, 2250, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 829 /* 194 - 7680x4320@24Hz 16:9 */ 830 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 831 10408, 11000, 4320, 4336, 4356, 4500, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 833 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 195 - 7680x4320@25Hz 16:9 */ 835 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 836 10208, 10800, 4320, 4336, 4356, 4400, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 838 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 196 - 7680x4320@30Hz 16:9 */ 840 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 841 8408, 9000, 4320, 4336, 4356, 4400, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 843 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 844 /* 197 - 7680x4320@48Hz 16:9 */ 845 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 846 10408, 11000, 4320, 4336, 4356, 4500, 0, 847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 848 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 198 - 7680x4320@50Hz 16:9 */ 850 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 851 10208, 10800, 4320, 4336, 4356, 4400, 0, 852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 854 /* 199 - 7680x4320@60Hz 16:9 */ 855 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 856 8408, 9000, 4320, 4336, 4356, 4400, 0, 857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 858 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 200 - 7680x4320@100Hz 16:9 */ 860 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 861 9968, 10560, 4320, 4336, 4356, 4500, 0, 862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 863 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 201 - 7680x4320@120Hz 16:9 */ 865 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 866 8208, 8800, 4320, 4336, 4356, 4500, 0, 867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 868 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 202 - 7680x4320@24Hz 64:27 */ 870 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 871 10408, 11000, 4320, 4336, 4356, 4500, 0, 872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 873 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 874 /* 203 - 7680x4320@25Hz 64:27 */ 875 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 876 10208, 10800, 4320, 4336, 4356, 4400, 0, 877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 878 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 879 /* 204 - 7680x4320@30Hz 64:27 */ 880 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 881 8408, 9000, 4320, 4336, 4356, 4400, 0, 882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 883 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 884 /* 205 - 7680x4320@48Hz 64:27 */ 885 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 886 10408, 11000, 4320, 4336, 4356, 4500, 0, 887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 888 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 889 /* 206 - 7680x4320@50Hz 64:27 */ 890 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 891 10208, 10800, 4320, 4336, 4356, 4400, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 893 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 894 /* 207 - 7680x4320@60Hz 64:27 */ 895 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 896 8408, 9000, 4320, 4336, 4356, 4400, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 899 /* 208 - 7680x4320@100Hz 64:27 */ 900 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 901 9968, 10560, 4320, 4336, 4356, 4500, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 904 /* 209 - 7680x4320@120Hz 64:27 */ 905 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 906 8208, 8800, 4320, 4336, 4356, 4500, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 909 /* 210 - 10240x4320@24Hz 64:27 */ 910 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 911 11908, 12500, 4320, 4336, 4356, 4950, 0, 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 913 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 914 /* 211 - 10240x4320@25Hz 64:27 */ 915 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 916 12908, 13500, 4320, 4336, 4356, 4400, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 919 /* 212 - 10240x4320@30Hz 64:27 */ 920 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 921 10704, 11000, 4320, 4336, 4356, 4500, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 923 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 924 /* 213 - 10240x4320@48Hz 64:27 */ 925 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 926 11908, 12500, 4320, 4336, 4356, 4950, 0, 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 928 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 929 /* 214 - 10240x4320@50Hz 64:27 */ 930 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 931 12908, 13500, 4320, 4336, 4356, 4400, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 933 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 934 /* 215 - 10240x4320@60Hz 64:27 */ 935 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 936 10704, 11000, 4320, 4336, 4356, 4500, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 939 /* 216 - 10240x4320@100Hz 64:27 */ 940 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 941 12608, 13200, 4320, 4336, 4356, 4500, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 944 /* 217 - 10240x4320@120Hz 64:27 */ 945 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 946 10704, 11000, 4320, 4336, 4356, 4500, 0, 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 949 /* 218 - 4096x2160@100Hz 256:135 */ 950 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 951 4984, 5280, 2160, 2168, 2178, 2250, 0, 952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 953 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 954 /* 219 - 4096x2160@120Hz 256:135 */ 955 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 956 4272, 4400, 2160, 2168, 2178, 2250, 0, 957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 958 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 959 }; 960 961 /* 962 * HDMI 1.4 4k modes. Index using the VIC. 963 */ 964 static const struct drm_display_mode edid_4k_modes[] = { 965 /* 0 - dummy, VICs start at 1 */ 966 { }, 967 /* 1 - 3840x2160@30Hz */ 968 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 969 3840, 4016, 4104, 4400, 970 2160, 2168, 2178, 2250, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .vrefresh = 30, }, 973 /* 2 - 3840x2160@25Hz */ 974 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 975 3840, 4896, 4984, 5280, 976 2160, 2168, 2178, 2250, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 978 .vrefresh = 25, }, 979 /* 3 - 3840x2160@24Hz */ 980 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 981 3840, 5116, 5204, 5500, 982 2160, 2168, 2178, 2250, 0, 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 984 .vrefresh = 24, }, 985 /* 4 - 4096x2160@24Hz (SMPTE) */ 986 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 987 4096, 5116, 5204, 5500, 988 2160, 2168, 2178, 2250, 0, 989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 990 .vrefresh = 24, }, 991 }; 992 993 /* 994 * Autogenerated from the DMT spec. 995 * This table is copied from xfree86/modes/xf86EdidModes.c. 996 */ 997 static const struct drm_display_mode drm_dmt_modes[] = { 998 /* 0x01 - 640x350@85Hz */ 999 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1000 736, 832, 350, 382, 385, 445, 0, 1001 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1002 /* 0x02 - 640x400@85Hz */ 1003 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1004 736, 832, 400, 401, 404, 445, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1006 /* 0x03 - 720x400@85Hz */ 1007 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 1008 828, 936, 400, 401, 404, 446, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1010 /* 0x04 - 640x480@60Hz */ 1011 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1012 752, 800, 480, 490, 492, 525, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1014 /* 0x05 - 640x480@72Hz */ 1015 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1016 704, 832, 480, 489, 492, 520, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1018 /* 0x06 - 640x480@75Hz */ 1019 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1020 720, 840, 480, 481, 484, 500, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1022 /* 0x07 - 640x480@85Hz */ 1023 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 1024 752, 832, 480, 481, 484, 509, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1026 /* 0x08 - 800x600@56Hz */ 1027 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1028 896, 1024, 600, 601, 603, 625, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1030 /* 0x09 - 800x600@60Hz */ 1031 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1032 968, 1056, 600, 601, 605, 628, 0, 1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1034 /* 0x0a - 800x600@72Hz */ 1035 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1036 976, 1040, 600, 637, 643, 666, 0, 1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1038 /* 0x0b - 800x600@75Hz */ 1039 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1040 896, 1056, 600, 601, 604, 625, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1042 /* 0x0c - 800x600@85Hz */ 1043 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 1044 896, 1048, 600, 601, 604, 631, 0, 1045 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1046 /* 0x0d - 800x600@120Hz RB */ 1047 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 1048 880, 960, 600, 603, 607, 636, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1050 /* 0x0e - 848x480@60Hz */ 1051 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 1052 976, 1088, 480, 486, 494, 517, 0, 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1054 /* 0x0f - 1024x768@43Hz, interlace */ 1055 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1056 1208, 1264, 768, 768, 772, 817, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1058 DRM_MODE_FLAG_INTERLACE) }, 1059 /* 0x10 - 1024x768@60Hz */ 1060 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1061 1184, 1344, 768, 771, 777, 806, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1063 /* 0x11 - 1024x768@70Hz */ 1064 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1065 1184, 1328, 768, 771, 777, 806, 0, 1066 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1067 /* 0x12 - 1024x768@75Hz */ 1068 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1069 1136, 1312, 768, 769, 772, 800, 0, 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1071 /* 0x13 - 1024x768@85Hz */ 1072 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 1073 1168, 1376, 768, 769, 772, 808, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1075 /* 0x14 - 1024x768@120Hz RB */ 1076 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 1077 1104, 1184, 768, 771, 775, 813, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1079 /* 0x15 - 1152x864@75Hz */ 1080 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1081 1344, 1600, 864, 865, 868, 900, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1083 /* 0x55 - 1280x720@60Hz */ 1084 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1085 1430, 1650, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1087 /* 0x16 - 1280x768@60Hz RB */ 1088 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 1089 1360, 1440, 768, 771, 778, 790, 0, 1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1091 /* 0x17 - 1280x768@60Hz */ 1092 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 1093 1472, 1664, 768, 771, 778, 798, 0, 1094 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1095 /* 0x18 - 1280x768@75Hz */ 1096 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 1097 1488, 1696, 768, 771, 778, 805, 0, 1098 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1099 /* 0x19 - 1280x768@85Hz */ 1100 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 1101 1496, 1712, 768, 771, 778, 809, 0, 1102 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1103 /* 0x1a - 1280x768@120Hz RB */ 1104 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 1105 1360, 1440, 768, 771, 778, 813, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1107 /* 0x1b - 1280x800@60Hz RB */ 1108 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 1109 1360, 1440, 800, 803, 809, 823, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1111 /* 0x1c - 1280x800@60Hz */ 1112 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 1113 1480, 1680, 800, 803, 809, 831, 0, 1114 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1115 /* 0x1d - 1280x800@75Hz */ 1116 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 1117 1488, 1696, 800, 803, 809, 838, 0, 1118 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1119 /* 0x1e - 1280x800@85Hz */ 1120 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 1121 1496, 1712, 800, 803, 809, 843, 0, 1122 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1123 /* 0x1f - 1280x800@120Hz RB */ 1124 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 1125 1360, 1440, 800, 803, 809, 847, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1127 /* 0x20 - 1280x960@60Hz */ 1128 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 1129 1488, 1800, 960, 961, 964, 1000, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1131 /* 0x21 - 1280x960@85Hz */ 1132 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 1133 1504, 1728, 960, 961, 964, 1011, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1135 /* 0x22 - 1280x960@120Hz RB */ 1136 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 1137 1360, 1440, 960, 963, 967, 1017, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1139 /* 0x23 - 1280x1024@60Hz */ 1140 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 1141 1440, 1688, 1024, 1025, 1028, 1066, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1143 /* 0x24 - 1280x1024@75Hz */ 1144 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1145 1440, 1688, 1024, 1025, 1028, 1066, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1147 /* 0x25 - 1280x1024@85Hz */ 1148 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 1149 1504, 1728, 1024, 1025, 1028, 1072, 0, 1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1151 /* 0x26 - 1280x1024@120Hz RB */ 1152 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 1153 1360, 1440, 1024, 1027, 1034, 1084, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1155 /* 0x27 - 1360x768@60Hz */ 1156 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 1157 1536, 1792, 768, 771, 777, 795, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1159 /* 0x28 - 1360x768@120Hz RB */ 1160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 1161 1440, 1520, 768, 771, 776, 813, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1163 /* 0x51 - 1366x768@60Hz */ 1164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 1165 1579, 1792, 768, 771, 774, 798, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1167 /* 0x56 - 1366x768@60Hz */ 1168 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 1169 1436, 1500, 768, 769, 772, 800, 0, 1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1171 /* 0x29 - 1400x1050@60Hz RB */ 1172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 1173 1480, 1560, 1050, 1053, 1057, 1080, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1175 /* 0x2a - 1400x1050@60Hz */ 1176 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 1177 1632, 1864, 1050, 1053, 1057, 1089, 0, 1178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1179 /* 0x2b - 1400x1050@75Hz */ 1180 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 1181 1648, 1896, 1050, 1053, 1057, 1099, 0, 1182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1183 /* 0x2c - 1400x1050@85Hz */ 1184 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 1185 1656, 1912, 1050, 1053, 1057, 1105, 0, 1186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1187 /* 0x2d - 1400x1050@120Hz RB */ 1188 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 1189 1480, 1560, 1050, 1053, 1057, 1112, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1191 /* 0x2e - 1440x900@60Hz RB */ 1192 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 1193 1520, 1600, 900, 903, 909, 926, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1195 /* 0x2f - 1440x900@60Hz */ 1196 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 1197 1672, 1904, 900, 903, 909, 934, 0, 1198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1199 /* 0x30 - 1440x900@75Hz */ 1200 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 1201 1688, 1936, 900, 903, 909, 942, 0, 1202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1203 /* 0x31 - 1440x900@85Hz */ 1204 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 1205 1696, 1952, 900, 903, 909, 948, 0, 1206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1207 /* 0x32 - 1440x900@120Hz RB */ 1208 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 1209 1520, 1600, 900, 903, 909, 953, 0, 1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1211 /* 0x53 - 1600x900@60Hz */ 1212 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 1213 1704, 1800, 900, 901, 904, 1000, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1215 /* 0x33 - 1600x1200@60Hz */ 1216 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 1217 1856, 2160, 1200, 1201, 1204, 1250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1219 /* 0x34 - 1600x1200@65Hz */ 1220 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 1221 1856, 2160, 1200, 1201, 1204, 1250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1223 /* 0x35 - 1600x1200@70Hz */ 1224 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 1225 1856, 2160, 1200, 1201, 1204, 1250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1227 /* 0x36 - 1600x1200@75Hz */ 1228 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 1229 1856, 2160, 1200, 1201, 1204, 1250, 0, 1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1231 /* 0x37 - 1600x1200@85Hz */ 1232 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 1233 1856, 2160, 1200, 1201, 1204, 1250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1235 /* 0x38 - 1600x1200@120Hz RB */ 1236 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 1237 1680, 1760, 1200, 1203, 1207, 1271, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1239 /* 0x39 - 1680x1050@60Hz RB */ 1240 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1241 1760, 1840, 1050, 1053, 1059, 1080, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1243 /* 0x3a - 1680x1050@60Hz */ 1244 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1245 1960, 2240, 1050, 1053, 1059, 1089, 0, 1246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1247 /* 0x3b - 1680x1050@75Hz */ 1248 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1249 1976, 2272, 1050, 1053, 1059, 1099, 0, 1250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1251 /* 0x3c - 1680x1050@85Hz */ 1252 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1253 1984, 2288, 1050, 1053, 1059, 1105, 0, 1254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1255 /* 0x3d - 1680x1050@120Hz RB */ 1256 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1257 1760, 1840, 1050, 1053, 1059, 1112, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1259 /* 0x3e - 1792x1344@60Hz */ 1260 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1261 2120, 2448, 1344, 1345, 1348, 1394, 0, 1262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1263 /* 0x3f - 1792x1344@75Hz */ 1264 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1265 2104, 2456, 1344, 1345, 1348, 1417, 0, 1266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1267 /* 0x40 - 1792x1344@120Hz RB */ 1268 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1269 1872, 1952, 1344, 1347, 1351, 1423, 0, 1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1271 /* 0x41 - 1856x1392@60Hz */ 1272 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1273 2176, 2528, 1392, 1393, 1396, 1439, 0, 1274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1275 /* 0x42 - 1856x1392@75Hz */ 1276 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1277 2208, 2560, 1392, 1393, 1396, 1500, 0, 1278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1279 /* 0x43 - 1856x1392@120Hz RB */ 1280 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1281 1936, 2016, 1392, 1395, 1399, 1474, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1283 /* 0x52 - 1920x1080@60Hz */ 1284 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1285 2052, 2200, 1080, 1084, 1089, 1125, 0, 1286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1287 /* 0x44 - 1920x1200@60Hz RB */ 1288 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1289 2000, 2080, 1200, 1203, 1209, 1235, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1291 /* 0x45 - 1920x1200@60Hz */ 1292 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1293 2256, 2592, 1200, 1203, 1209, 1245, 0, 1294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1295 /* 0x46 - 1920x1200@75Hz */ 1296 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1297 2264, 2608, 1200, 1203, 1209, 1255, 0, 1298 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1299 /* 0x47 - 1920x1200@85Hz */ 1300 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1301 2272, 2624, 1200, 1203, 1209, 1262, 0, 1302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1303 /* 0x48 - 1920x1200@120Hz RB */ 1304 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1305 2000, 2080, 1200, 1203, 1209, 1271, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1307 /* 0x49 - 1920x1440@60Hz */ 1308 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1309 2256, 2600, 1440, 1441, 1444, 1500, 0, 1310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1311 /* 0x4a - 1920x1440@75Hz */ 1312 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1313 2288, 2640, 1440, 1441, 1444, 1500, 0, 1314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1315 /* 0x4b - 1920x1440@120Hz RB */ 1316 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1317 2000, 2080, 1440, 1443, 1447, 1525, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1319 /* 0x54 - 2048x1152@60Hz */ 1320 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1321 2154, 2250, 1152, 1153, 1156, 1200, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1323 /* 0x4c - 2560x1600@60Hz RB */ 1324 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1325 2640, 2720, 1600, 1603, 1609, 1646, 0, 1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1327 /* 0x4d - 2560x1600@60Hz */ 1328 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1329 3032, 3504, 1600, 1603, 1609, 1658, 0, 1330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1331 /* 0x4e - 2560x1600@75Hz */ 1332 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1333 3048, 3536, 1600, 1603, 1609, 1672, 0, 1334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1335 /* 0x4f - 2560x1600@85Hz */ 1336 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1337 3048, 3536, 1600, 1603, 1609, 1682, 0, 1338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1339 /* 0x50 - 2560x1600@120Hz RB */ 1340 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1341 2640, 2720, 1600, 1603, 1609, 1694, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1343 /* 0x57 - 4096x2160@60Hz RB */ 1344 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1345 4136, 4176, 2160, 2208, 2216, 2222, 0, 1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1347 /* 0x58 - 4096x2160@59.94Hz RB */ 1348 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1349 4136, 4176, 2160, 2208, 2216, 2222, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1351 }; 1352 1353 /* 1354 * These more or less come from the DMT spec. The 720x400 modes are 1355 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1356 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1357 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1358 * mode. 1359 * 1360 * The DMT modes have been fact-checked; the rest are mild guesses. 1361 */ 1362 static const struct drm_display_mode edid_est_modes[] = { 1363 /* 800x600@60Hz */ 1364 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1365 968, 1056, 600, 601, 605, 628, 0, 1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1367 /* 800x600@56Hz */ 1368 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1369 896, 1024, 600, 601, 603, 625, 0, 1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1371 /* 640x480@75Hz */ 1372 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1373 720, 840, 480, 481, 484, 500, 0, 1374 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1375 /* 640x480@72Hz */ 1376 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1377 704, 832, 480, 489, 492, 520, 0, 1378 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1379 /* 640x480@67Hz */ 1380 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1381 768, 864, 480, 483, 486, 525, 0, 1382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1383 /* 640x480@60Hz */ 1384 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1385 752, 800, 480, 490, 492, 525, 0, 1386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1387 /* 720x400@88Hz */ 1388 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1389 846, 900, 400, 421, 423, 449, 0, 1390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1391 /* 720x400@70Hz */ 1392 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1393 846, 900, 400, 412, 414, 449, 0, 1394 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1395 /* 1280x1024@75Hz */ 1396 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1397 1440, 1688, 1024, 1025, 1028, 1066, 0, 1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1399 /* 1024x768@75Hz */ 1400 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1401 1136, 1312, 768, 769, 772, 800, 0, 1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1403 /* 1024x768@70Hz */ 1404 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1405 1184, 1328, 768, 771, 777, 806, 0, 1406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1407 /* 1024x768@60Hz */ 1408 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1409 1184, 1344, 768, 771, 777, 806, 0, 1410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1411 /* 1024x768@43Hz */ 1412 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1413 1208, 1264, 768, 768, 776, 817, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1415 DRM_MODE_FLAG_INTERLACE) }, 1416 /* 832x624@75Hz */ 1417 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1418 928, 1152, 624, 625, 628, 667, 0, 1419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1420 /* 800x600@75Hz */ 1421 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1422 896, 1056, 600, 601, 604, 625, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1424 /* 800x600@72Hz */ 1425 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1426 976, 1040, 600, 637, 643, 666, 0, 1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1428 /* 1152x864@75Hz */ 1429 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1430 1344, 1600, 864, 865, 868, 900, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1432 }; 1433 1434 #define DRM_BASE_MODE(c, hd, hss, hse, ht, vd, vss, vse, vt, vs, f) \ 1435 .clock = (c), \ 1436 .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ 1437 .htotal = (ht), .vdisplay = (vd), \ 1438 .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ 1439 .vscan = (vs), .flags = (f) 1440 1441 static const struct base_drm_display_mode resolution_white[] = { 1442 /* 0. vic:2 - 720x480@60Hz */ 1443 { DRM_BASE_MODE(27000, 720, 736, 1444 798, 858, 480, 489, 495, 525, 0, 1445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1446 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1447 /* 1. vic:3 - 720x480@60Hz */ 1448 { DRM_BASE_MODE(27000, 720, 736, 1449 798, 858, 480, 489, 495, 525, 0, 1450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1451 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1452 /* 1024x768@60Hz */ 1453 { DRM_BASE_MODE(65000, 1024, 1048, 1454 1184, 1344, 768, 771, 777, 806, 0, 1455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1456 /* 2. vic:4 - 1280x720@60Hz */ 1457 { DRM_BASE_MODE(74250, 1280, 1390, 1458 1430, 1650, 720, 725, 730, 750, 0, 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1460 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1461 /* 3. vic:5 - 1920x1080i@60Hz */ 1462 { DRM_BASE_MODE(74250, 1920, 2008, 1463 2052, 2200, 1080, 1084, 1094, 1125, 0, 1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1465 DRM_MODE_FLAG_INTERLACE), 1466 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1467 /* 4. vic:6 - 720(1440)x480i@60Hz */ 1468 { DRM_BASE_MODE(13500, 720, 739, 1469 801, 858, 480, 488, 494, 525, 0, 1470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1471 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1472 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1473 /* 5. vic:16 - 1920x1080@60Hz */ 1474 { DRM_BASE_MODE(148500, 1920, 2008, 1475 2052, 2200, 1080, 1084, 1089, 1125, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1478 /* 6. vic:17 - 720x576@50Hz */ 1479 { DRM_BASE_MODE(27000, 720, 732, 1480 796, 864, 576, 581, 586, 625, 0, 1481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1482 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1483 /* 7. vic:18 - 720x576@50Hz */ 1484 { DRM_BASE_MODE(27000, 720, 732, 1485 796, 864, 576, 581, 586, 625, 0, 1486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1487 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1488 /* 8. vic:19 - 1280x720@50Hz */ 1489 { DRM_BASE_MODE(74250, 1280, 1720, 1490 1760, 1980, 720, 725, 730, 750, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1493 /* 9. vic:20 - 1920x1080i@50Hz */ 1494 { DRM_BASE_MODE(74250, 1920, 2448, 1495 2492, 2640, 1080, 1084, 1094, 1125, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1497 DRM_MODE_FLAG_INTERLACE), 1498 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1499 /* 10. vic:21 - 720(1440)x576i@50Hz */ 1500 { DRM_BASE_MODE(13500, 720, 732, 1501 795, 864, 576, 580, 586, 625, 0, 1502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1503 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1504 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1505 /* 11. vic:31 - 1920x1080@50Hz */ 1506 { DRM_BASE_MODE(148500, 1920, 2448, 1507 2492, 2640, 1080, 1084, 1089, 1125, 0, 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1509 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1510 /* 12. vic:32 - 1920x1080@24Hz */ 1511 { DRM_BASE_MODE(74250, 1920, 2558, 1512 2602, 2750, 1080, 1084, 1089, 1125, 0, 1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1514 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1515 /* 13. vic:33 - 1920x1080@25Hz */ 1516 { DRM_BASE_MODE(74250, 1920, 2448, 1517 2492, 2640, 1080, 1084, 1089, 1125, 0, 1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1519 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1520 /* 14. vic:34 - 1920x1080@30Hz */ 1521 { DRM_BASE_MODE(74250, 1920, 2008, 1522 2052, 2200, 1080, 1084, 1089, 1125, 0, 1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1524 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1525 /* 15. vic:39 - 1920x1080i@50Hz */ 1526 { DRM_BASE_MODE(72000, 1920, 1952, 1527 2120, 2304, 1080, 1126, 1136, 1250, 0, 1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 1529 DRM_MODE_FLAG_INTERLACE), 1530 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1531 /* 16. vic:60 - 1280x720@24Hz */ 1532 { DRM_BASE_MODE(59400, 1280, 3040, 1533 3080, 3300, 720, 725, 730, 750, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1536 /* 17. vic:61 - 1280x720@25Hz */ 1537 { DRM_BASE_MODE(74250, 1280, 3700, 1538 3740, 3960, 720, 725, 730, 750, 0, 1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1540 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1541 /* 18. vic:62 - 1280x720@30Hz */ 1542 { DRM_BASE_MODE(74250, 1280, 3040, 1543 3080, 3300, 720, 725, 730, 750, 0, 1544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1545 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1546 /* 19. vic:93 - 3840x2160p@24Hz 16:9 */ 1547 { DRM_BASE_MODE(297000, 3840, 5116, 1548 5204, 5500, 2160, 2168, 2178, 2250, 0, 1549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1550 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1551 /* 20. vic:94 - 3840x2160p@25Hz 16:9 */ 1552 { DRM_BASE_MODE(297000, 3840, 4896, 1553 4984, 5280, 2160, 2168, 2178, 2250, 0, 1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1555 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1556 /* 21. vic:95 - 3840x2160p@30Hz 16:9 */ 1557 { DRM_BASE_MODE(297000, 3840, 4016, 1558 4104, 4400, 2160, 2168, 2178, 2250, 0, 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1560 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1561 /* 22. vic:96 - 3840x2160p@50Hz 16:9 */ 1562 { DRM_BASE_MODE(594000, 3840, 4896, 1563 4984, 5280, 2160, 2168, 2178, 2250, 0, 1564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1565 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1566 /* 23. vic:97 - 3840x2160p@60Hz 16:9 */ 1567 { DRM_BASE_MODE(594000, 3840, 4016, 1568 4104, 4400, 2160, 2168, 2178, 2250, 0, 1569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1570 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1571 /* 24. vic:98 - 4096x2160p@24Hz 256:135 */ 1572 { DRM_BASE_MODE(297000, 4096, 5116, 1573 5204, 5500, 2160, 2168, 2178, 2250, 0, 1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1575 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1576 /* 25. vic:99 - 4096x2160p@25Hz 256:135 */ 1577 { DRM_BASE_MODE(297000, 4096, 5064, 1578 5152, 5280, 2160, 2168, 2178, 2250, 0, 1579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1580 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1581 /* 26. vic:100 - 4096x2160p@30Hz 256:135 */ 1582 { DRM_BASE_MODE(297000, 4096, 4184, 1583 4272, 4400, 2160, 2168, 2178, 2250, 0, 1584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1585 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1586 /* 27. vic:101 - 4096x2160p@50Hz 256:135 */ 1587 { DRM_BASE_MODE(594000, 4096, 5064, 1588 5152, 5280, 2160, 2168, 2178, 2250, 0, 1589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1590 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1591 /* 28. vic:102 - 4096x2160p@60Hz 256:135 */ 1592 { DRM_BASE_MODE(594000, 4096, 4184, 1593 4272, 4400, 2160, 2168, 2178, 2250, 0, 1594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1595 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1596 /* 29. vic:118 - 3840x2160@120Hz 16:9 */ 1597 { DRM_BASE_MODE(1188000, 3840, 4016, 1598 4104, 4400, 2160, 2168, 2178, 2250, 0, 1599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1600 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1601 /* 30. vic:196 - 7680x4320@30Hz 16:9 */ 1602 { DRM_BASE_MODE(1188000, 7680, 8232, 1603 8408, 9000, 4320, 4336, 4356, 4400, 0, 1604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1605 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1606 /* 31. vic:198 - 7680x4320@50Hz 16:9 */ 1607 { DRM_BASE_MODE(2376000, 7680, 10032, 1608 10208, 10800, 4320, 4336, 4356, 4400, 0, 1609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1610 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1611 /* 32. vic:199 - 7680x4320@60Hz 16:9 */ 1612 { DRM_BASE_MODE(2376000, 7680, 8232, 1613 8408, 9000, 4320, 4336, 4356, 4400, 0, 1614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1615 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1616 }; 1617 1618 struct minimode { 1619 short w; 1620 short h; 1621 short r; 1622 short rb; 1623 }; 1624 1625 static const struct minimode est3_modes[] = { 1626 /* byte 6 */ 1627 { 640, 350, 85, 0 }, 1628 { 640, 400, 85, 0 }, 1629 { 720, 400, 85, 0 }, 1630 { 640, 480, 85, 0 }, 1631 { 848, 480, 60, 0 }, 1632 { 800, 600, 85, 0 }, 1633 { 1024, 768, 85, 0 }, 1634 { 1152, 864, 75, 0 }, 1635 /* byte 7 */ 1636 { 1280, 768, 60, 1 }, 1637 { 1280, 768, 60, 0 }, 1638 { 1280, 768, 75, 0 }, 1639 { 1280, 768, 85, 0 }, 1640 { 1280, 960, 60, 0 }, 1641 { 1280, 960, 85, 0 }, 1642 { 1280, 1024, 60, 0 }, 1643 { 1280, 1024, 85, 0 }, 1644 /* byte 8 */ 1645 { 1360, 768, 60, 0 }, 1646 { 1440, 900, 60, 1 }, 1647 { 1440, 900, 60, 0 }, 1648 { 1440, 900, 75, 0 }, 1649 { 1440, 900, 85, 0 }, 1650 { 1400, 1050, 60, 1 }, 1651 { 1400, 1050, 60, 0 }, 1652 { 1400, 1050, 75, 0 }, 1653 /* byte 9 */ 1654 { 1400, 1050, 85, 0 }, 1655 { 1680, 1050, 60, 1 }, 1656 { 1680, 1050, 60, 0 }, 1657 { 1680, 1050, 75, 0 }, 1658 { 1680, 1050, 85, 0 }, 1659 { 1600, 1200, 60, 0 }, 1660 { 1600, 1200, 65, 0 }, 1661 { 1600, 1200, 70, 0 }, 1662 /* byte 10 */ 1663 { 1600, 1200, 75, 0 }, 1664 { 1600, 1200, 85, 0 }, 1665 { 1792, 1344, 60, 0 }, 1666 { 1792, 1344, 75, 0 }, 1667 { 1856, 1392, 60, 0 }, 1668 { 1856, 1392, 75, 0 }, 1669 { 1920, 1200, 60, 1 }, 1670 { 1920, 1200, 60, 0 }, 1671 /* byte 11 */ 1672 { 1920, 1200, 75, 0 }, 1673 { 1920, 1200, 85, 0 }, 1674 { 1920, 1440, 60, 0 }, 1675 { 1920, 1440, 75, 0 }, 1676 }; 1677 1678 static const struct minimode extra_modes[] = { 1679 { 1024, 576, 60, 0 }, 1680 { 1366, 768, 60, 0 }, 1681 { 1600, 900, 60, 0 }, 1682 { 1680, 945, 60, 0 }, 1683 { 1920, 1080, 60, 0 }, 1684 { 2048, 1152, 60, 0 }, 1685 { 2048, 1536, 60, 0 }, 1686 }; 1687 1688 static const struct drm_display_mode *cea_mode_for_vic(u8 vic) 1689 { 1690 if (!vic) 1691 return NULL; 1692 else if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 1693 return &edid_cea_modes_1[vic - 1]; 1694 else if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 1695 return &edid_cea_modes_193[vic - 193]; 1696 1697 return NULL; 1698 } 1699 1700 static u8 cea_num_vics(void) 1701 { 1702 return 193 + ARRAY_SIZE(edid_cea_modes_193); 1703 } 1704 1705 static u8 cea_next_vic(u8 vic) 1706 { 1707 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 1708 vic = 193; 1709 1710 return vic; 1711 } 1712 1713 int edid_check_info(struct edid1_info *edid_info) 1714 { 1715 if ((edid_info == NULL) || (edid_info->version == 0)) 1716 return -1; 1717 1718 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1719 return -1; 1720 1721 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1722 return -1; 1723 1724 return 0; 1725 } 1726 1727 int edid_check_checksum(u8 *edid_block) 1728 { 1729 u8 checksum = 0; 1730 int i; 1731 1732 for (i = 0; i < 128; i++) 1733 checksum += edid_block[i]; 1734 1735 return (checksum == 0) ? 0 : -EINVAL; 1736 } 1737 1738 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1739 unsigned int *hmax, unsigned int *vmin, 1740 unsigned int *vmax) 1741 { 1742 int i; 1743 struct edid_monitor_descriptor *monitor; 1744 1745 *hmin = *hmax = *vmin = *vmax = 0; 1746 if (edid_check_info(edid)) 1747 return -1; 1748 1749 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1750 monitor = &edid->monitor_details.descriptor[i]; 1751 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1752 *hmin = monitor->data.range_data.horizontal_min; 1753 *hmax = monitor->data.range_data.horizontal_max; 1754 *vmin = monitor->data.range_data.vertical_min; 1755 *vmax = monitor->data.range_data.vertical_max; 1756 return 0; 1757 } 1758 } 1759 return -1; 1760 } 1761 1762 /* Set all parts of a timing entry to the same value */ 1763 static void set_entry(struct timing_entry *entry, u32 value) 1764 { 1765 entry->min = value; 1766 entry->typ = value; 1767 entry->max = value; 1768 } 1769 1770 /** 1771 * decode_timing() - Decoding an 18-byte detailed timing record 1772 * 1773 * @buf: Pointer to EDID detailed timing record 1774 * @timing: Place to put timing 1775 */ 1776 static void decode_timing(u8 *buf, struct display_timing *timing) 1777 { 1778 uint x_mm, y_mm; 1779 unsigned int ha, hbl, hso, hspw, hborder; 1780 unsigned int va, vbl, vso, vspw, vborder; 1781 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1782 1783 /* Edid contains pixel clock in terms of 10KHz */ 1784 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1785 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1786 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1787 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1788 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1789 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1790 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1791 hborder = buf[15]; 1792 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1793 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1794 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1795 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1796 vborder = buf[16]; 1797 1798 set_entry(&timing->hactive, ha); 1799 set_entry(&timing->hfront_porch, hso); 1800 set_entry(&timing->hback_porch, hbl - hso - hspw); 1801 set_entry(&timing->hsync_len, hspw); 1802 1803 set_entry(&timing->vactive, va); 1804 set_entry(&timing->vfront_porch, vso); 1805 set_entry(&timing->vback_porch, vbl - vso - vspw); 1806 set_entry(&timing->vsync_len, vspw); 1807 1808 timing->flags = 0; 1809 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1810 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1811 else 1812 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1813 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1814 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1815 else 1816 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1817 1818 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1819 timing->flags = DISPLAY_FLAGS_INTERLACED; 1820 1821 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1822 " %04x %04x %04x %04x hborder %x\n" 1823 " %04x %04x %04x %04x vborder %x\n", 1824 timing->pixelclock.typ, 1825 x_mm, y_mm, 1826 ha, ha + hso, ha + hso + hspw, 1827 ha + hbl, hborder, 1828 va, va + vso, va + vso + vspw, 1829 va + vbl, vborder); 1830 } 1831 1832 /** 1833 * decode_mode() - Decoding an 18-byte detailed timing record 1834 * 1835 * @buf: Pointer to EDID detailed timing record 1836 * @timing: Place to put timing 1837 */ 1838 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1839 { 1840 uint x_mm, y_mm; 1841 unsigned int ha, hbl, hso, hspw, hborder; 1842 unsigned int va, vbl, vso, vspw, vborder; 1843 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1844 1845 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1846 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1847 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1848 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1849 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1850 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1851 hborder = buf[15]; 1852 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1853 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1854 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1855 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1856 vborder = buf[16]; 1857 1858 /* Edid contains pixel clock in terms of 10KHz */ 1859 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1860 mode->hdisplay = ha; 1861 mode->hsync_start = ha + hso; 1862 mode->hsync_end = ha + hso + hspw; 1863 mode->htotal = ha + hbl; 1864 mode->vdisplay = va; 1865 mode->vsync_start = va + vso; 1866 mode->vsync_end = va + vso + vspw; 1867 mode->vtotal = va + vbl; 1868 1869 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1870 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1871 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1872 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1873 1874 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1875 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1876 1877 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1878 " %04d %04d %04d %04d hborder %d\n" 1879 " %04d %04d %04d %04d vborder %d\n", 1880 mode->clock, 1881 x_mm, y_mm, mode->flags, 1882 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1883 mode->htotal, hborder, 1884 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1885 mode->vtotal, vborder); 1886 } 1887 1888 /** 1889 * edid_vendor - match a string against EDID's obfuscated vendor field 1890 * @edid: EDID to match 1891 * @vendor: vendor string 1892 * 1893 * Returns true if @vendor is in @edid, false otherwise 1894 */ 1895 static bool edid_vendor(struct edid *edid, char *vendor) 1896 { 1897 char edid_vendor[3]; 1898 1899 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1900 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1901 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1902 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1903 1904 return !strncmp(edid_vendor, vendor, 3); 1905 } 1906 1907 /** 1908 * Check if HDMI vendor specific data block is present in CEA block 1909 * @param info CEA extension block 1910 * @return true if block is found 1911 */ 1912 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1913 { 1914 u8 end, i = 0; 1915 1916 /* check for end of data block */ 1917 end = info->dtd_offset; 1918 if (end == 0) 1919 end = sizeof(info->data); 1920 if (end < 4 || end > sizeof(info->data)) 1921 return false; 1922 end -= 4; 1923 1924 while (i < end) { 1925 /* Look for vendor specific data block of appropriate size */ 1926 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1927 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1928 u8 *db = &info->data[i + 1]; 1929 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1930 1931 if (oui == HDMI_IEEE_OUI) 1932 return true; 1933 } 1934 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1935 } 1936 1937 return false; 1938 } 1939 1940 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1941 { 1942 int refresh = 0; 1943 unsigned int calc_val; 1944 1945 if (mode->vrefresh > 0) { 1946 refresh = mode->vrefresh; 1947 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1948 int vtotal; 1949 1950 vtotal = mode->vtotal; 1951 /* work out vrefresh the value will be x1000 */ 1952 calc_val = (mode->clock * 1000); 1953 calc_val /= mode->htotal; 1954 refresh = (calc_val + vtotal / 2) / vtotal; 1955 1956 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1957 refresh *= 2; 1958 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1959 refresh /= 2; 1960 if (mode->vscan > 1) 1961 refresh /= mode->vscan; 1962 } 1963 return refresh; 1964 } 1965 1966 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1967 int *panel_bits_per_colourp) 1968 { 1969 struct edid1_info *edid = (struct edid1_info *)buf; 1970 bool timing_done; 1971 int i; 1972 1973 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1974 debug("%s: Invalid buffer\n", __func__); 1975 return -EINVAL; 1976 } 1977 1978 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1979 debug("%s: No preferred timing\n", __func__); 1980 return -ENOENT; 1981 } 1982 1983 /* Look for detailed timing */ 1984 timing_done = false; 1985 for (i = 0; i < 4; i++) { 1986 struct edid_monitor_descriptor *desc; 1987 1988 desc = &edid->monitor_details.descriptor[i]; 1989 if (desc->zero_flag_1 != 0) { 1990 decode_mode((u8 *)desc, mode); 1991 timing_done = true; 1992 break; 1993 } 1994 } 1995 if (!timing_done) 1996 return -EINVAL; 1997 1998 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1999 debug("%s: Not a digital display\n", __func__); 2000 return -ENOSYS; 2001 } 2002 if (edid->version != 1 || edid->revision < 4) { 2003 debug("%s: EDID version %d.%d does not have required info\n", 2004 __func__, edid->version, edid->revision); 2005 *panel_bits_per_colourp = -1; 2006 } else { 2007 *panel_bits_per_colourp = 2008 ((edid->video_input_definition & 0x70) >> 3) + 4; 2009 } 2010 2011 return 0; 2012 } 2013 2014 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 2015 int *panel_bits_per_colourp) 2016 { 2017 struct edid1_info *edid = (struct edid1_info *)buf; 2018 bool timing_done; 2019 int i; 2020 2021 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 2022 debug("%s: Invalid buffer\n", __func__); 2023 return -EINVAL; 2024 } 2025 2026 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 2027 debug("%s: No preferred timing\n", __func__); 2028 return -ENOENT; 2029 } 2030 2031 /* Look for detailed timing */ 2032 timing_done = false; 2033 for (i = 0; i < 4; i++) { 2034 struct edid_monitor_descriptor *desc; 2035 2036 desc = &edid->monitor_details.descriptor[i]; 2037 if (desc->zero_flag_1 != 0) { 2038 decode_timing((u8 *)desc, timing); 2039 timing_done = true; 2040 break; 2041 } 2042 } 2043 if (!timing_done) 2044 return -EINVAL; 2045 2046 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 2047 debug("%s: Not a digital display\n", __func__); 2048 return -ENOSYS; 2049 } 2050 if (edid->version != 1 || edid->revision < 4) { 2051 debug("%s: EDID version %d.%d does not have required info\n", 2052 __func__, edid->version, edid->revision); 2053 *panel_bits_per_colourp = -1; 2054 } else { 2055 *panel_bits_per_colourp = 2056 ((edid->video_input_definition & 0x70) >> 3) + 4; 2057 } 2058 2059 timing->hdmi_monitor = false; 2060 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 2061 struct edid_cea861_info *info = 2062 (struct edid_cea861_info *)(buf + sizeof(*edid)); 2063 2064 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 2065 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 2066 } 2067 2068 return 0; 2069 } 2070 2071 /** 2072 * Snip the tailing whitespace/return of a string. 2073 * 2074 * @param string The string to be snipped 2075 * @return the snipped string 2076 */ 2077 static char *snip(char *string) 2078 { 2079 char *s; 2080 2081 /* 2082 * This is always a 13 character buffer 2083 * and it's not always terminated. 2084 */ 2085 string[12] = '\0'; 2086 s = &string[strlen(string) - 1]; 2087 2088 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 2089 *s == '\0')) 2090 *(s--) = '\0'; 2091 2092 return string; 2093 } 2094 2095 /** 2096 * Print an EDID monitor descriptor block 2097 * 2098 * @param monitor The EDID monitor descriptor block 2099 * @have_timing Modifies to 1 if the desciptor contains timing info 2100 */ 2101 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 2102 unsigned int *have_timing) 2103 { 2104 unsigned char *bytes = (unsigned char *)monitor; 2105 struct edid_detailed_timing *timing = 2106 (struct edid_detailed_timing *)monitor; 2107 2108 if (bytes[0] == 0 && bytes[1] == 0) { 2109 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 2110 printf("Monitor serial number: %s\n", 2111 snip(monitor->data.string)); 2112 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 2113 printf("Monitor ID: %s\n", 2114 snip(monitor->data.string)); 2115 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 2116 printf("Monitor name: %s\n", 2117 snip(monitor->data.string)); 2118 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 2119 printf("Monitor range limits, horizontal sync: " 2120 "%d-%d kHz, vertical refresh: " 2121 "%d-%d Hz, max pixel clock: " 2122 "%d MHz\n", 2123 monitor->data.range_data.horizontal_min, 2124 monitor->data.range_data.horizontal_max, 2125 monitor->data.range_data.vertical_min, 2126 monitor->data.range_data.vertical_max, 2127 monitor->data.range_data.pixel_clock_max * 10); 2128 } else { 2129 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 2130 u32 h_total, v_total, vfreq; 2131 2132 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 2133 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 2134 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 2135 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 2136 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 2137 2138 h_total = h_active + h_blanking; 2139 v_total = v_active + v_blanking; 2140 if (v_total > 0 && h_total > 0) 2141 vfreq = pixclock / (v_total * h_total); 2142 else 2143 vfreq = 1; /* Error case */ 2144 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 2145 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 2146 *have_timing = 1; 2147 } 2148 } 2149 2150 /** 2151 * Get the manufacturer name from an EDID info. 2152 * 2153 * @param edid_info The EDID info to be printed 2154 * @param name Returns the string of the manufacturer name 2155 */ 2156 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 2157 { 2158 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 2159 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 2160 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 2161 name[3] = '\0'; 2162 } 2163 2164 void edid_print_info(struct edid1_info *edid_info) 2165 { 2166 int i; 2167 char manufacturer[4]; 2168 unsigned int have_timing = 0; 2169 u32 serial_number; 2170 2171 if (edid_check_info(edid_info)) { 2172 printf("Not a valid EDID\n"); 2173 return; 2174 } 2175 2176 printf("EDID version: %d.%d\n", 2177 edid_info->version, edid_info->revision); 2178 2179 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 2180 2181 edid_get_manufacturer_name(edid_info, manufacturer); 2182 printf("Manufacturer: %s\n", manufacturer); 2183 2184 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 2185 if (serial_number != 0xffffffff) { 2186 if (strcmp(manufacturer, "MAG") == 0) 2187 serial_number -= 0x7000000; 2188 if (strcmp(manufacturer, "OQI") == 0) 2189 serial_number -= 456150000; 2190 if (strcmp(manufacturer, "VSC") == 0) 2191 serial_number -= 640000000; 2192 } 2193 printf("Serial number: %08x\n", serial_number); 2194 printf("Manufactured in week: %d year: %d\n", 2195 edid_info->week, edid_info->year + 1990); 2196 2197 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 2198 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 2199 "digital signal, " : "analog signal, ", 2200 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 2201 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 2202 ", blank to black" : "", 2203 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 2204 ", separate sync" : "", 2205 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 2206 ", composite sync" : "", 2207 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 2208 ", sync on green" : "", 2209 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 2210 ", serration v" : ""); 2211 2212 printf("Monitor is %s\n", 2213 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 2214 2215 printf("Maximum visible display size: %d cm x %d cm\n", 2216 edid_info->max_size_horizontal, 2217 edid_info->max_size_vertical); 2218 2219 printf("Power management features: %s%s, %s%s, %s%s\n", 2220 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 2221 "" : "no ", "active off", 2222 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 2223 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 2224 2225 printf("Estabilished timings:\n"); 2226 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 2227 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 2228 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 2229 printf("\t720x400\t\t88 Hz (XGA2)\n"); 2230 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 2231 printf("\t640x480\t\t60 Hz (VGA)\n"); 2232 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 2233 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 2234 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 2235 printf("\t640x480\t\t72 Hz (VESA)\n"); 2236 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 2237 printf("\t640x480\t\t75 Hz (VESA)\n"); 2238 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 2239 printf("\t800x600\t\t56 Hz (VESA)\n"); 2240 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 2241 printf("\t800x600\t\t60 Hz (VESA)\n"); 2242 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 2243 printf("\t800x600\t\t72 Hz (VESA)\n"); 2244 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 2245 printf("\t800x600\t\t75 Hz (VESA)\n"); 2246 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 2247 printf("\t832x624\t\t75 Hz (Mac II)\n"); 2248 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 2249 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 2250 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 2251 printf("\t1024x768\t60 Hz (VESA)\n"); 2252 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 2253 printf("\t1024x768\t70 Hz (VESA)\n"); 2254 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 2255 printf("\t1024x768\t75 Hz (VESA)\n"); 2256 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 2257 printf("\t1280x1024\t75 (VESA)\n"); 2258 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 2259 printf("\t1152x870\t75 (Mac II)\n"); 2260 2261 /* Standard timings. */ 2262 printf("Standard timings:\n"); 2263 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 2264 unsigned int aspect = 10000; 2265 unsigned int x, y; 2266 unsigned char xres, vfreq; 2267 2268 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 2269 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 2270 if ((xres != vfreq) || 2271 ((xres != 0) && (xres != 1)) || 2272 ((vfreq != 0) && (vfreq != 1))) { 2273 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 2274 i)) { 2275 case ASPECT_625: 2276 aspect = 6250; 2277 break; 2278 case ASPECT_75: 2279 aspect = 7500; 2280 break; 2281 case ASPECT_8: 2282 aspect = 8000; 2283 break; 2284 case ASPECT_5625: 2285 aspect = 5625; 2286 break; 2287 } 2288 x = (xres + 31) * 8; 2289 y = x * aspect / 10000; 2290 printf("\t%dx%d%c\t%d Hz\n", x, y, 2291 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 2292 have_timing = 1; 2293 } 2294 } 2295 2296 /* Detailed timing information. */ 2297 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 2298 i++) { 2299 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 2300 &have_timing); 2301 } 2302 2303 if (!have_timing) 2304 printf("\tNone\n"); 2305 } 2306 2307 /** 2308 * drm_mode_create - create a new display mode 2309 * 2310 * Create a new, cleared drm_display_mode. 2311 * 2312 * Returns: 2313 * Pointer to new mode on success, NULL on error. 2314 */ 2315 static struct drm_display_mode *drm_mode_create(void) 2316 { 2317 struct drm_display_mode *nmode; 2318 2319 nmode = malloc(sizeof(struct drm_display_mode)); 2320 memset(nmode, 0, sizeof(struct drm_display_mode)); 2321 if (!nmode) 2322 return NULL; 2323 2324 return nmode; 2325 } 2326 2327 /** 2328 * drm_mode_destroy - remove a mode 2329 * @mode: mode to remove 2330 * 2331 */ 2332 static void drm_mode_destroy(struct drm_display_mode *mode) 2333 { 2334 if (!mode) 2335 return; 2336 2337 kfree(mode); 2338 } 2339 2340 /** 2341 * drm_cvt_mode -create a modeline based on the CVT algorithm 2342 * @hdisplay: hdisplay size 2343 * @vdisplay: vdisplay size 2344 * @vrefresh: vrefresh rate 2345 * @reduced: whether to use reduced blanking 2346 * @interlaced: whether to compute an interlaced mode 2347 * @margins: whether to add margins (borders) 2348 * 2349 * This function is called to generate the modeline based on CVT algorithm 2350 * according to the hdisplay, vdisplay, vrefresh. 2351 * It is based from the VESA(TM) Coordinated Video Timing Generator by 2352 * Graham Loveridge April 9, 2003 available at 2353 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 2354 * 2355 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 2356 * What I have done is to translate it by using integer calculation. 2357 * 2358 * Returns: 2359 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 2360 * The display mode object is allocated with drm_mode_create(). Returns NULL 2361 * when no mode could be allocated. 2362 */ 2363 static 2364 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 2365 bool reduced, bool interlaced, 2366 bool margins) 2367 { 2368 #define HV_FACTOR 1000 2369 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 2370 #define CVT_MARGIN_PERCENTAGE 18 2371 /* 2) character cell horizontal granularity (pixels) - default 8 */ 2372 #define CVT_H_GRANULARITY 8 2373 /* 3) Minimum vertical porch (lines) - default 3 */ 2374 #define CVT_MIN_V_PORCH 3 2375 /* 4) Minimum number of vertical back porch lines - default 6 */ 2376 #define CVT_MIN_V_BPORCH 6 2377 /* Pixel Clock step (kHz) */ 2378 #define CVT_CLOCK_STEP 250 2379 struct drm_display_mode *drm_mode; 2380 unsigned int vfieldrate, hperiod; 2381 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 2382 int interlace; 2383 2384 /* allocate the drm_display_mode structure. If failure, we will 2385 * return directly 2386 */ 2387 drm_mode = drm_mode_create(); 2388 if (!drm_mode) 2389 return NULL; 2390 2391 /* the CVT default refresh rate is 60Hz */ 2392 if (!vrefresh) 2393 vrefresh = 60; 2394 2395 /* the required field fresh rate */ 2396 if (interlaced) 2397 vfieldrate = vrefresh * 2; 2398 else 2399 vfieldrate = vrefresh; 2400 2401 /* horizontal pixels */ 2402 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 2403 2404 /* determine the left&right borders */ 2405 hmargin = 0; 2406 if (margins) { 2407 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2408 hmargin -= hmargin % CVT_H_GRANULARITY; 2409 } 2410 /* find the total active pixels */ 2411 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 2412 2413 /* find the number of lines per field */ 2414 if (interlaced) 2415 vdisplay_rnd = vdisplay / 2; 2416 else 2417 vdisplay_rnd = vdisplay; 2418 2419 /* find the top & bottom borders */ 2420 vmargin = 0; 2421 if (margins) 2422 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2423 2424 drm_mode->vdisplay = vdisplay + 2 * vmargin; 2425 2426 /* Interlaced */ 2427 if (interlaced) 2428 interlace = 1; 2429 else 2430 interlace = 0; 2431 2432 /* Determine VSync Width from aspect ratio */ 2433 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 2434 vsync = 4; 2435 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 2436 vsync = 5; 2437 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 2438 vsync = 6; 2439 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 2440 vsync = 7; 2441 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 2442 vsync = 7; 2443 else /* custom */ 2444 vsync = 10; 2445 2446 if (!reduced) { 2447 /* simplify the GTF calculation */ 2448 /* 4) Minimum time of vertical sync + back porch interval 2449 * default 550.0 2450 */ 2451 int tmp1, tmp2; 2452 #define CVT_MIN_VSYNC_BP 550 2453 /* 3) Nominal HSync width (% of line period) - default 8 */ 2454 #define CVT_HSYNC_PERCENTAGE 8 2455 unsigned int hblank_percentage; 2456 int vsyncandback_porch, hblank; 2457 2458 /* estimated the horizontal period */ 2459 tmp1 = HV_FACTOR * 1000000 - 2460 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2461 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2462 interlace; 2463 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2464 2465 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2466 /* 9. Find number of lines in sync + backporch */ 2467 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2468 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2469 else 2470 vsyncandback_porch = tmp1; 2471 /* 10. Find number of lines in back porch 2472 * vback_porch = vsyncandback_porch - vsync; 2473 */ 2474 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2475 vsyncandback_porch + CVT_MIN_V_PORCH; 2476 /* 5) Definition of Horizontal blanking time limitation */ 2477 /* Gradient (%/kHz) - default 600 */ 2478 #define CVT_M_FACTOR 600 2479 /* Offset (%) - default 40 */ 2480 #define CVT_C_FACTOR 40 2481 /* Blanking time scaling factor - default 128 */ 2482 #define CVT_K_FACTOR 128 2483 /* Scaling factor weighting - default 20 */ 2484 #define CVT_J_FACTOR 20 2485 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2486 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2487 CVT_J_FACTOR) 2488 /* 12. Find ideal blanking duty cycle from formula */ 2489 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2490 hperiod / 1000; 2491 /* 13. Blanking time */ 2492 if (hblank_percentage < 20 * HV_FACTOR) 2493 hblank_percentage = 20 * HV_FACTOR; 2494 hblank = drm_mode->hdisplay * hblank_percentage / 2495 (100 * HV_FACTOR - hblank_percentage); 2496 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2497 /* 14. find the total pixels per line */ 2498 drm_mode->htotal = drm_mode->hdisplay + hblank; 2499 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2500 drm_mode->hsync_start = drm_mode->hsync_end - 2501 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2502 drm_mode->hsync_start += CVT_H_GRANULARITY - 2503 drm_mode->hsync_start % CVT_H_GRANULARITY; 2504 /* fill the Vsync values */ 2505 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2506 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2507 } else { 2508 /* Reduced blanking */ 2509 /* Minimum vertical blanking interval time - default 460 */ 2510 #define CVT_RB_MIN_VBLANK 460 2511 /* Fixed number of clocks for horizontal sync */ 2512 #define CVT_RB_H_SYNC 32 2513 /* Fixed number of clocks for horizontal blanking */ 2514 #define CVT_RB_H_BLANK 160 2515 /* Fixed number of lines for vertical front porch - default 3*/ 2516 #define CVT_RB_VFPORCH 3 2517 int vbilines; 2518 int tmp1, tmp2; 2519 /* 8. Estimate Horizontal period. */ 2520 tmp1 = HV_FACTOR * 1000000 - 2521 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2522 tmp2 = vdisplay_rnd + 2 * vmargin; 2523 hperiod = tmp1 / (tmp2 * vfieldrate); 2524 /* 9. Find number of lines in vertical blanking */ 2525 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2526 /* 10. Check if vertical blanking is sufficient */ 2527 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2528 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2529 /* 11. Find total number of lines in vertical field */ 2530 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2531 /* 12. Find total number of pixels in a line */ 2532 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2533 /* Fill in HSync values */ 2534 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2535 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2536 /* Fill in VSync values */ 2537 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2538 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2539 } 2540 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2541 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2542 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2543 /* 18/16. Find actual vertical frame frequency */ 2544 /* ignore - just set the mode flag for interlaced */ 2545 if (interlaced) { 2546 drm_mode->vtotal *= 2; 2547 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2548 } 2549 2550 if (reduced) 2551 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2552 DRM_MODE_FLAG_NVSYNC); 2553 else 2554 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2555 DRM_MODE_FLAG_NHSYNC); 2556 2557 return drm_mode; 2558 } 2559 2560 static int 2561 cea_db_payload_len(const u8 *db) 2562 { 2563 return db[0] & 0x1f; 2564 } 2565 2566 static int 2567 cea_db_extended_tag(const u8 *db) 2568 { 2569 return db[1]; 2570 } 2571 2572 static int 2573 cea_db_tag(const u8 *db) 2574 { 2575 return db[0] >> 5; 2576 } 2577 2578 #define for_each_cea_db(cea, i, start, end) \ 2579 for ((i) = (start); (i) < (end) && (i) + \ 2580 cea_db_payload_len(&(cea)[(i)]) < \ 2581 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2582 2583 static int 2584 cea_revision(const u8 *cea) 2585 { 2586 return cea[1]; 2587 } 2588 2589 static int 2590 cea_db_offsets(const u8 *cea, int *start, int *end) 2591 { 2592 /* Data block offset in CEA extension block */ 2593 *start = 4; 2594 *end = cea[2]; 2595 if (*end == 0) 2596 *end = 127; 2597 if (*end < 4 || *end > 127) 2598 return -ERANGE; 2599 2600 /* 2601 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2602 */ 2603 if (*end != 4) { 2604 int i; 2605 2606 i = *start; 2607 while (i < (*end) && 2608 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2609 i += cea_db_payload_len(&(cea)[i]) + 1; 2610 2611 if (cea_db_payload_len(&(cea)[i]) && 2612 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2613 (*end)++; 2614 } 2615 2616 return 0; 2617 } 2618 2619 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2620 { 2621 int hdmi_id; 2622 2623 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2624 return false; 2625 2626 if (cea_db_payload_len(db) < 5) 2627 return false; 2628 2629 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2630 2631 return hdmi_id == HDMI_IEEE_OUI; 2632 } 2633 2634 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2635 { 2636 unsigned int oui; 2637 2638 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2639 return false; 2640 2641 if (cea_db_payload_len(db) < 7) 2642 return false; 2643 2644 oui = db[3] << 16 | db[2] << 8 | db[1]; 2645 2646 return oui == HDMI_FORUM_IEEE_OUI; 2647 } 2648 2649 static bool cea_db_is_y420cmdb(const u8 *db) 2650 { 2651 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2652 return false; 2653 2654 if (!cea_db_payload_len(db)) 2655 return false; 2656 2657 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2658 return false; 2659 2660 return true; 2661 } 2662 2663 static bool cea_db_is_y420vdb(const u8 *db) 2664 { 2665 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2666 return false; 2667 2668 if (!cea_db_payload_len(db)) 2669 return false; 2670 2671 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2672 return false; 2673 2674 return true; 2675 } 2676 2677 static bool drm_valid_hdmi_vic(u8 vic) 2678 { 2679 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2680 } 2681 2682 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2683 const struct drm_display_mode *mode) 2684 { 2685 struct drm_display_mode *mode_buf = data->mode_buf; 2686 2687 if (data->modes >= MODE_LEN) 2688 return; 2689 mode_buf[(data->modes)++] = *mode; 2690 } 2691 2692 static bool drm_valid_cea_vic(u8 vic) 2693 { 2694 return cea_mode_for_vic(vic) ? true : false; 2695 } 2696 2697 static u8 svd_to_vic(u8 svd) 2698 { 2699 /* 0-6 bit vic, 7th bit native mode indicator */ 2700 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2701 return svd & 127; 2702 2703 return svd; 2704 } 2705 2706 static struct drm_display_mode * 2707 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2708 u8 video_index) 2709 { 2710 struct drm_display_mode *newmode; 2711 u8 vic; 2712 2713 if (!video_db || video_index >= video_len) 2714 return NULL; 2715 2716 /* CEA modes are numbered 1..127 */ 2717 vic = svd_to_vic(video_db[video_index]); 2718 if (!drm_valid_cea_vic(vic)) 2719 return NULL; 2720 2721 newmode = drm_mode_create(); 2722 if (!newmode) 2723 return NULL; 2724 2725 *newmode = *cea_mode_for_vic(vic); 2726 newmode->vrefresh = 0; 2727 2728 return newmode; 2729 } 2730 2731 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2732 { 2733 unsigned long *p = map + BIT_WORD(start); 2734 const unsigned int size = start + len; 2735 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2736 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2737 2738 while (len - bits_to_set >= 0) { 2739 *p |= mask_to_set; 2740 len -= bits_to_set; 2741 bits_to_set = BITS_PER_LONG; 2742 mask_to_set = ~0UL; 2743 p++; 2744 } 2745 if (len) { 2746 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2747 *p |= mask_to_set; 2748 } 2749 } 2750 2751 static void 2752 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2753 { 2754 u8 vic = svd_to_vic(svd); 2755 2756 if (!drm_valid_cea_vic(vic)) 2757 return; 2758 2759 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2760 } 2761 2762 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2763 { 2764 int i, modes = 0; 2765 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2766 2767 for (i = 0; i < len; i++) { 2768 struct drm_display_mode *mode; 2769 2770 mode = drm_display_mode_from_vic_index(db, len, i); 2771 if (mode) { 2772 /* 2773 * YCBCR420 capability block contains a bitmap which 2774 * gives the index of CEA modes from CEA VDB, which 2775 * can support YCBCR 420 sampling output also (apart 2776 * from RGB/YCBCR444 etc). 2777 * For example, if the bit 0 in bitmap is set, 2778 * first mode in VDB can support YCBCR420 output too. 2779 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2780 */ 2781 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2782 drm_add_cmdb_modes(db[i], hdmi); 2783 drm_add_hdmi_modes(data, mode); 2784 drm_mode_destroy(mode); 2785 modes++; 2786 } 2787 } 2788 2789 return modes; 2790 } 2791 2792 /* 2793 * do_y420vdb_modes - Parse YCBCR 420 only modes 2794 * @data: the structure that save parsed hdmi edid data 2795 * @svds: start of the data block of CEA YCBCR 420 VDB 2796 * @svds_len: length of the CEA YCBCR 420 VDB 2797 * @hdmi: runtime information about the connected HDMI sink 2798 * 2799 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2800 * which contains modes which can be supported in YCBCR 420 2801 * output format only. 2802 */ 2803 static int 2804 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2805 { 2806 int modes = 0, i; 2807 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2808 2809 for (i = 0; i < svds_len; i++) { 2810 u8 vic = svd_to_vic(svds[i]); 2811 2812 if (!drm_valid_cea_vic(vic)) 2813 continue; 2814 2815 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2816 drm_add_hdmi_modes(data, cea_mode_for_vic(vic)); 2817 modes++; 2818 } 2819 2820 return modes; 2821 } 2822 2823 struct stereo_mandatory_mode { 2824 int width, height, vrefresh; 2825 unsigned int flags; 2826 }; 2827 2828 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2829 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2830 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2831 { 1920, 1080, 50, 2832 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2833 { 1920, 1080, 60, 2834 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2835 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2836 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2837 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2838 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2839 }; 2840 2841 static bool 2842 stereo_match_mandatory(const struct drm_display_mode *mode, 2843 const struct stereo_mandatory_mode *stereo_mode) 2844 { 2845 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2846 2847 return mode->hdisplay == stereo_mode->width && 2848 mode->vdisplay == stereo_mode->height && 2849 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2850 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2851 } 2852 2853 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2854 { 2855 const struct drm_display_mode *mode; 2856 int num = data->modes, modes = 0, i, k; 2857 2858 for (k = 0; k < num; k++) { 2859 mode = &data->mode_buf[k]; 2860 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2861 const struct stereo_mandatory_mode *mandatory; 2862 struct drm_display_mode *new_mode; 2863 2864 if (!stereo_match_mandatory(mode, 2865 &stereo_mandatory_modes[i])) 2866 continue; 2867 2868 mandatory = &stereo_mandatory_modes[i]; 2869 new_mode = drm_mode_create(); 2870 if (!new_mode) 2871 continue; 2872 2873 *new_mode = *mode; 2874 new_mode->flags |= mandatory->flags; 2875 drm_add_hdmi_modes(data, new_mode); 2876 drm_mode_destroy(new_mode); 2877 modes++; 2878 } 2879 } 2880 2881 return modes; 2882 } 2883 2884 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2885 const u8 *video_db, u8 video_len, u8 video_index) 2886 { 2887 struct drm_display_mode *newmode; 2888 int modes = 0; 2889 2890 if (structure & (1 << 0)) { 2891 newmode = drm_display_mode_from_vic_index(video_db, 2892 video_len, 2893 video_index); 2894 if (newmode) { 2895 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2896 drm_add_hdmi_modes(data, newmode); 2897 modes++; 2898 drm_mode_destroy(newmode); 2899 } 2900 } 2901 if (structure & (1 << 6)) { 2902 newmode = drm_display_mode_from_vic_index(video_db, 2903 video_len, 2904 video_index); 2905 if (newmode) { 2906 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2907 drm_add_hdmi_modes(data, newmode); 2908 modes++; 2909 drm_mode_destroy(newmode); 2910 } 2911 } 2912 if (structure & (1 << 8)) { 2913 newmode = drm_display_mode_from_vic_index(video_db, 2914 video_len, 2915 video_index); 2916 if (newmode) { 2917 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2918 drm_add_hdmi_modes(data, newmode); 2919 modes++; 2920 drm_mode_destroy(newmode); 2921 } 2922 } 2923 2924 return modes; 2925 } 2926 2927 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2928 { 2929 if (!drm_valid_hdmi_vic(vic)) { 2930 debug("Unknown HDMI VIC: %d\n", vic); 2931 return 0; 2932 } 2933 2934 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2935 2936 return 1; 2937 } 2938 2939 /* 2940 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2941 * @db: start of the CEA vendor specific block 2942 * @len: length of the CEA block payload, ie. one can access up to db[len] 2943 * 2944 * Parses the HDMI VSDB looking for modes to add to @data. This function 2945 * also adds the stereo 3d modes when applicable. 2946 */ 2947 static int 2948 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2949 struct hdmi_edid_data *data) 2950 { 2951 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2952 u8 vic_len, hdmi_3d_len = 0; 2953 u16 mask; 2954 u16 structure_all; 2955 2956 if (len < 8) 2957 goto out; 2958 2959 /* no HDMI_Video_Present */ 2960 if (!(db[8] & (1 << 5))) 2961 goto out; 2962 2963 /* Latency_Fields_Present */ 2964 if (db[8] & (1 << 7)) 2965 offset += 2; 2966 2967 /* I_Latency_Fields_Present */ 2968 if (db[8] & (1 << 6)) 2969 offset += 2; 2970 2971 /* the declared length is not long enough for the 2 first bytes 2972 * of additional video format capabilities 2973 */ 2974 if (len < (8 + offset + 2)) 2975 goto out; 2976 2977 /* 3D_Present */ 2978 offset++; 2979 if (db[8 + offset] & (1 << 7)) { 2980 modes += add_hdmi_mandatory_stereo_modes(data); 2981 2982 /* 3D_Multi_present */ 2983 multi_present = (db[8 + offset] & 0x60) >> 5; 2984 } 2985 2986 offset++; 2987 vic_len = db[8 + offset] >> 5; 2988 hdmi_3d_len = db[8 + offset] & 0x1f; 2989 2990 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2991 u8 vic; 2992 2993 vic = db[9 + offset + i]; 2994 modes += add_hdmi_mode(data, vic); 2995 } 2996 2997 offset += 1 + vic_len; 2998 2999 if (multi_present == 1) 3000 multi_len = 2; 3001 else if (multi_present == 2) 3002 multi_len = 4; 3003 else 3004 multi_len = 0; 3005 3006 if (len < (8 + offset + hdmi_3d_len - 1)) 3007 goto out; 3008 3009 if (hdmi_3d_len < multi_len) 3010 goto out; 3011 3012 if (multi_present == 1 || multi_present == 2) { 3013 /* 3D_Structure_ALL */ 3014 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3015 3016 /* check if 3D_MASK is present */ 3017 if (multi_present == 2) 3018 mask = (db[10 + offset] << 8) | db[11 + offset]; 3019 else 3020 mask = 0xffff; 3021 3022 for (i = 0; i < 16; i++) { 3023 if (mask & (1 << i)) 3024 modes += add_3d_struct_modes(data, 3025 structure_all, 3026 video_db, 3027 video_len, i); 3028 } 3029 } 3030 3031 offset += multi_len; 3032 3033 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3034 int vic_index; 3035 struct drm_display_mode *newmode = NULL; 3036 unsigned int newflag = 0; 3037 bool detail_present; 3038 3039 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3040 3041 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3042 break; 3043 3044 /* 2D_VIC_order_X */ 3045 vic_index = db[8 + offset + i] >> 4; 3046 3047 /* 3D_Structure_X */ 3048 switch (db[8 + offset + i] & 0x0f) { 3049 case 0: 3050 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3051 break; 3052 case 6: 3053 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3054 break; 3055 case 8: 3056 /* 3D_Detail_X */ 3057 if ((db[9 + offset + i] >> 4) == 1) 3058 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3059 break; 3060 } 3061 3062 if (newflag != 0) { 3063 newmode = drm_display_mode_from_vic_index( 3064 video_db, 3065 video_len, 3066 vic_index); 3067 3068 if (newmode) { 3069 newmode->flags |= newflag; 3070 drm_add_hdmi_modes(data, newmode); 3071 modes++; 3072 drm_mode_destroy(newmode); 3073 } 3074 } 3075 3076 if (detail_present) 3077 i++; 3078 } 3079 3080 out: 3081 return modes; 3082 } 3083 3084 /** 3085 * edid_get_quirks - return quirk flags for a given EDID 3086 * @edid: EDID to process 3087 * 3088 * This tells subsequent routines what fixes they need to apply. 3089 */ 3090 static u32 edid_get_quirks(struct edid *edid) 3091 { 3092 struct edid_quirk *quirk; 3093 int i; 3094 3095 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 3096 quirk = &edid_quirk_list[i]; 3097 3098 if (edid_vendor(edid, quirk->vendor) && 3099 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 3100 return quirk->quirks; 3101 } 3102 3103 return 0; 3104 } 3105 3106 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 3107 const u8 *db) 3108 { 3109 struct drm_display_info *info = &data->display_info; 3110 struct drm_hdmi_info *hdmi = &info->hdmi; 3111 u8 map_len = cea_db_payload_len(db) - 1; 3112 u8 count; 3113 u64 map = 0; 3114 3115 if (map_len == 0) { 3116 /* All CEA modes support ycbcr420 sampling also.*/ 3117 hdmi->y420_cmdb_map = U64_MAX; 3118 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3119 return; 3120 } 3121 3122 /* 3123 * This map indicates which of the existing CEA block modes 3124 * from VDB can support YCBCR420 output too. So if bit=0 is 3125 * set, first mode from VDB can support YCBCR420 output too. 3126 * We will parse and keep this map, before parsing VDB itself 3127 * to avoid going through the same block again and again. 3128 * 3129 * Spec is not clear about max possible size of this block. 3130 * Clamping max bitmap block size at 8 bytes. Every byte can 3131 * address 8 CEA modes, in this way this map can address 3132 * 8*8 = first 64 SVDs. 3133 */ 3134 if (map_len > 8) 3135 map_len = 8; 3136 3137 for (count = 0; count < map_len; count++) 3138 map |= (u64)db[2 + count] << (8 * count); 3139 3140 if (map) 3141 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3142 3143 hdmi->y420_cmdb_map = map; 3144 } 3145 3146 static 3147 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 3148 { 3149 switch (max_frl_rate) { 3150 case 1: 3151 *max_lanes = 3; 3152 *max_rate_per_lane = 3; 3153 break; 3154 case 2: 3155 *max_lanes = 3; 3156 *max_rate_per_lane = 6; 3157 break; 3158 case 3: 3159 *max_lanes = 4; 3160 *max_rate_per_lane = 6; 3161 break; 3162 case 4: 3163 *max_lanes = 4; 3164 *max_rate_per_lane = 8; 3165 break; 3166 case 5: 3167 *max_lanes = 4; 3168 *max_rate_per_lane = 10; 3169 break; 3170 case 6: 3171 *max_lanes = 4; 3172 *max_rate_per_lane = 12; 3173 break; 3174 case 0: 3175 default: 3176 *max_lanes = 0; 3177 *max_rate_per_lane = 0; 3178 } 3179 } 3180 3181 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 3182 const u8 *db) 3183 { 3184 u8 dc_mask; 3185 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 3186 3187 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 3188 hdmi->y420_dc_modes |= dc_mask; 3189 } 3190 3191 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 3192 const u8 *hf_vsdb) 3193 { 3194 struct drm_display_info *display = &data->display_info; 3195 struct drm_hdmi_info *hdmi = &display->hdmi; 3196 3197 if (hf_vsdb[6] & 0x80) { 3198 hdmi->scdc.supported = true; 3199 if (hf_vsdb[6] & 0x40) 3200 hdmi->scdc.read_request = true; 3201 } 3202 3203 /* 3204 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 3205 * And as per the spec, three factors confirm this: 3206 * * Availability of a HF-VSDB block in EDID (check) 3207 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 3208 * * SCDC support available (let's check) 3209 * Lets check it out. 3210 */ 3211 3212 if (hf_vsdb[5]) { 3213 /* max clock is 5000 KHz times block value */ 3214 u32 max_tmds_clock = hf_vsdb[5] * 5000; 3215 struct drm_scdc *scdc = &hdmi->scdc; 3216 3217 if (max_tmds_clock > 340000) { 3218 display->max_tmds_clock = max_tmds_clock; 3219 debug("HF-VSDB: max TMDS clock %d kHz\n", 3220 display->max_tmds_clock); 3221 } 3222 3223 if (scdc->supported) { 3224 scdc->scrambling.supported = true; 3225 3226 /* Few sinks support scrambling for cloks < 340M */ 3227 if ((hf_vsdb[6] & 0x8)) 3228 scdc->scrambling.low_rates = true; 3229 } 3230 } 3231 3232 if (hf_vsdb[7]) { 3233 u8 max_frl_rate; 3234 u8 dsc_max_frl_rate; 3235 u8 dsc_max_slices; 3236 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 3237 3238 debug("hdmi_21 sink detected. parsing edid\n"); 3239 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 3240 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 3241 &hdmi->max_frl_rate_per_lane); 3242 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 3243 3244 if (hdmi_dsc->v_1p2) { 3245 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 3246 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 3247 3248 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 3249 hdmi_dsc->bpc_supported = 16; 3250 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 3251 hdmi_dsc->bpc_supported = 12; 3252 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 3253 hdmi_dsc->bpc_supported = 10; 3254 else 3255 hdmi_dsc->bpc_supported = 0; 3256 3257 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 3258 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 3259 &hdmi_dsc->max_frl_rate_per_lane); 3260 hdmi_dsc->total_chunk_kbytes = 3261 hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 3262 3263 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 3264 switch (dsc_max_slices) { 3265 case 1: 3266 hdmi_dsc->max_slices = 1; 3267 hdmi_dsc->clk_per_slice = 340; 3268 break; 3269 case 2: 3270 hdmi_dsc->max_slices = 2; 3271 hdmi_dsc->clk_per_slice = 340; 3272 break; 3273 case 3: 3274 hdmi_dsc->max_slices = 4; 3275 hdmi_dsc->clk_per_slice = 340; 3276 break; 3277 case 4: 3278 hdmi_dsc->max_slices = 8; 3279 hdmi_dsc->clk_per_slice = 340; 3280 break; 3281 case 5: 3282 hdmi_dsc->max_slices = 8; 3283 hdmi_dsc->clk_per_slice = 400; 3284 break; 3285 case 6: 3286 hdmi_dsc->max_slices = 12; 3287 hdmi_dsc->clk_per_slice = 400; 3288 break; 3289 case 7: 3290 hdmi_dsc->max_slices = 16; 3291 hdmi_dsc->clk_per_slice = 400; 3292 break; 3293 case 0: 3294 default: 3295 hdmi_dsc->max_slices = 0; 3296 hdmi_dsc->clk_per_slice = 0; 3297 } 3298 } 3299 } 3300 3301 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 3302 } 3303 3304 /** 3305 * drm_default_rgb_quant_range - default RGB quantization range 3306 * @mode: display mode 3307 * 3308 * Determine the default RGB quantization range for the mode, 3309 * as specified in CEA-861. 3310 * 3311 * Return: The default RGB quantization range for the mode 3312 */ 3313 enum hdmi_quantization_range 3314 drm_default_rgb_quant_range(struct drm_display_mode *mode) 3315 { 3316 /* All CEA modes other than VIC 1 use limited quantization range. */ 3317 return drm_match_cea_mode(mode) > 1 ? 3318 HDMI_QUANTIZATION_RANGE_LIMITED : 3319 HDMI_QUANTIZATION_RANGE_FULL; 3320 } 3321 3322 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 3323 const u8 *hdmi) 3324 { 3325 struct drm_display_info *info = &data->display_info; 3326 unsigned int dc_bpc = 0; 3327 3328 /* HDMI supports at least 8 bpc */ 3329 info->bpc = 8; 3330 3331 if (cea_db_payload_len(hdmi) < 6) 3332 return; 3333 3334 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3335 dc_bpc = 10; 3336 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3337 debug("HDMI sink does deep color 30.\n"); 3338 } 3339 3340 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3341 dc_bpc = 12; 3342 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3343 debug("HDMI sink does deep color 36.\n"); 3344 } 3345 3346 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3347 dc_bpc = 16; 3348 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3349 debug("HDMI sink does deep color 48.\n"); 3350 } 3351 3352 if (dc_bpc == 0) { 3353 debug("No deep color support on this HDMI sink.\n"); 3354 return; 3355 } 3356 3357 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 3358 info->bpc = dc_bpc; 3359 3360 /* YCRCB444 is optional according to spec. */ 3361 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3362 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 3363 debug("HDMI sink does YCRCB444 in deep color.\n"); 3364 } 3365 3366 /* 3367 * Spec says that if any deep color mode is supported at all, 3368 * then deep color 36 bit must be supported. 3369 */ 3370 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 3371 debug("HDMI sink should do DC_36, but does not!\n"); 3372 } 3373 3374 /* 3375 * Search EDID for CEA extension block. 3376 */ 3377 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 3378 { 3379 u8 *edid_ext = NULL; 3380 int i; 3381 3382 /* No EDID or EDID extensions */ 3383 if (!edid || !edid->extensions) 3384 return NULL; 3385 3386 /* Find CEA extension */ 3387 for (i = 0; i < edid->extensions; i++) { 3388 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 3389 if (edid_ext[0] == ext_id) 3390 break; 3391 } 3392 3393 if (i == edid->extensions) 3394 return NULL; 3395 3396 return edid_ext; 3397 } 3398 3399 static u8 *drm_find_cea_extension(struct edid *edid) 3400 { 3401 return drm_find_edid_extension(edid, 0x02); 3402 } 3403 3404 #define AUDIO_BLOCK 0x01 3405 #define VIDEO_BLOCK 0x02 3406 #define VENDOR_BLOCK 0x03 3407 #define SPEAKER_BLOCK 0x04 3408 #define EDID_BASIC_AUDIO BIT(6) 3409 3410 /** 3411 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3412 * @edid: monitor EDID information 3413 * 3414 * Parse the CEA extension according to CEA-861-B. 3415 * 3416 * Return: True if the monitor is HDMI, false if not or unknown. 3417 */ 3418 bool drm_detect_hdmi_monitor(struct edid *edid) 3419 { 3420 u8 *edid_ext; 3421 int i; 3422 int start_offset, end_offset; 3423 3424 edid_ext = drm_find_cea_extension(edid); 3425 if (!edid_ext) 3426 return false; 3427 3428 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3429 return false; 3430 3431 /* 3432 * Because HDMI identifier is in Vendor Specific Block, 3433 * search it from all data blocks of CEA extension. 3434 */ 3435 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3436 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3437 return true; 3438 } 3439 3440 return false; 3441 } 3442 3443 /** 3444 * drm_detect_monitor_audio - check monitor audio capability 3445 * @edid: EDID block to scan 3446 * 3447 * Monitor should have CEA extension block. 3448 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3449 * audio' only. If there is any audio extension block and supported 3450 * audio format, assume at least 'basic audio' support, even if 'basic 3451 * audio' is not defined in EDID. 3452 * 3453 * Return: True if the monitor supports audio, false otherwise. 3454 */ 3455 bool drm_detect_monitor_audio(struct edid *edid) 3456 { 3457 u8 *edid_ext; 3458 int i, j; 3459 bool has_audio = false; 3460 int start_offset, end_offset; 3461 3462 edid_ext = drm_find_cea_extension(edid); 3463 if (!edid_ext) 3464 goto end; 3465 3466 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3467 3468 if (has_audio) { 3469 printf("Monitor has basic audio support\n"); 3470 goto end; 3471 } 3472 3473 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3474 goto end; 3475 3476 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3477 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3478 has_audio = true; 3479 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 3480 j += 3) 3481 debug("CEA audio format %d\n", 3482 (edid_ext[i + j] >> 3) & 0xf); 3483 goto end; 3484 } 3485 } 3486 end: 3487 return has_audio; 3488 } 3489 3490 static void 3491 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 3492 { 3493 struct drm_display_info *info = &data->display_info; 3494 u8 len = cea_db_payload_len(db); 3495 3496 if (len >= 6) 3497 info->dvi_dual = db[6] & 1; 3498 if (len >= 7) 3499 info->max_tmds_clock = db[7] * 5000; 3500 3501 drm_parse_hdmi_deep_color_info(data, db); 3502 } 3503 3504 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 3505 struct edid *edid) 3506 { 3507 struct drm_display_info *info = &data->display_info; 3508 const u8 *edid_ext; 3509 int i, start, end; 3510 3511 edid_ext = drm_find_cea_extension(edid); 3512 if (!edid_ext) 3513 return; 3514 3515 info->cea_rev = edid_ext[1]; 3516 3517 /* The existence of a CEA block should imply RGB support */ 3518 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3519 if (edid_ext[3] & EDID_CEA_YCRCB444) 3520 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3521 if (edid_ext[3] & EDID_CEA_YCRCB422) 3522 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3523 3524 if (cea_db_offsets(edid_ext, &start, &end)) 3525 return; 3526 3527 for_each_cea_db(edid_ext, i, start, end) { 3528 const u8 *db = &edid_ext[i]; 3529 3530 if (cea_db_is_hdmi_vsdb(db)) 3531 drm_parse_hdmi_vsdb_video(data, db); 3532 if (cea_db_is_hdmi_forum_vsdb(db)) 3533 drm_parse_hdmi_forum_vsdb(data, db); 3534 if (cea_db_is_y420cmdb(db)) 3535 drm_parse_y420cmdb_bitmap(data, db); 3536 } 3537 } 3538 3539 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 3540 { 3541 struct drm_display_info *info = &data->display_info; 3542 3543 info->width_mm = edid->width_cm * 10; 3544 info->height_mm = edid->height_cm * 10; 3545 3546 /* driver figures it out in this case */ 3547 info->bpc = 0; 3548 info->color_formats = 0; 3549 info->cea_rev = 0; 3550 info->max_tmds_clock = 0; 3551 info->dvi_dual = false; 3552 info->edid_hdmi_dc_modes = 0; 3553 3554 memset(&info->hdmi, 0, sizeof(info->hdmi)); 3555 3556 if (edid->revision < 3) 3557 return; 3558 3559 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3560 return; 3561 3562 drm_parse_cea_ext(data, edid); 3563 3564 /* 3565 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3566 * 3567 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3568 * tells us to assume 8 bpc color depth if the EDID doesn't have 3569 * extensions which tell otherwise. 3570 */ 3571 if ((info->bpc == 0) && (edid->revision < 4) && 3572 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3573 info->bpc = 8; 3574 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3575 } 3576 3577 /* Only defined for 1.4 with digital displays */ 3578 if (edid->revision < 4) 3579 return; 3580 3581 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3582 case DRM_EDID_DIGITAL_DEPTH_6: 3583 info->bpc = 6; 3584 break; 3585 case DRM_EDID_DIGITAL_DEPTH_8: 3586 info->bpc = 8; 3587 break; 3588 case DRM_EDID_DIGITAL_DEPTH_10: 3589 info->bpc = 10; 3590 break; 3591 case DRM_EDID_DIGITAL_DEPTH_12: 3592 info->bpc = 12; 3593 break; 3594 case DRM_EDID_DIGITAL_DEPTH_14: 3595 info->bpc = 14; 3596 break; 3597 case DRM_EDID_DIGITAL_DEPTH_16: 3598 info->bpc = 16; 3599 break; 3600 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3601 default: 3602 info->bpc = 0; 3603 break; 3604 } 3605 3606 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3607 info->bpc); 3608 3609 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3610 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3611 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3612 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3613 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3614 } 3615 3616 static 3617 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3618 { 3619 const u8 *cea = drm_find_cea_extension(edid); 3620 const u8 *db, *hdmi = NULL, *video = NULL; 3621 u8 dbl, hdmi_len, video_len = 0; 3622 int modes = 0; 3623 3624 if (cea && cea_revision(cea) >= 3) { 3625 int i, start, end; 3626 3627 if (cea_db_offsets(cea, &start, &end)) 3628 return 0; 3629 3630 for_each_cea_db(cea, i, start, end) { 3631 db = &cea[i]; 3632 dbl = cea_db_payload_len(db); 3633 3634 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3635 video = db + 1; 3636 video_len = dbl; 3637 modes += do_cea_modes(data, video, dbl); 3638 } else if (cea_db_is_hdmi_vsdb(db)) { 3639 hdmi = db; 3640 hdmi_len = dbl; 3641 } else if (cea_db_is_y420vdb(db)) { 3642 const u8 *vdb420 = &db[2]; 3643 3644 /* Add 4:2:0(only) modes present in EDID */ 3645 modes += do_y420vdb_modes(data, vdb420, 3646 dbl - 1); 3647 } 3648 } 3649 } 3650 3651 /* 3652 * We parse the HDMI VSDB after having added the cea modes as we will 3653 * be patching their flags when the sink supports stereo 3D. 3654 */ 3655 if (hdmi) 3656 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3657 video_len, data); 3658 3659 return modes; 3660 } 3661 3662 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3663 3664 static void 3665 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3666 { 3667 int i, n = 0; 3668 u8 d = ext[0x02]; 3669 u8 *det_base = ext + d; 3670 3671 if (d < 4 || d > 127) 3672 return; 3673 3674 n = (127 - d) / 18; 3675 for (i = 0; i < n; i++) 3676 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3677 } 3678 3679 static void 3680 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3681 { 3682 unsigned int i, n = min((int)ext[0x02], 6); 3683 u8 *det_base = ext + 5; 3684 3685 if (ext[0x01] != 1) 3686 return; /* unknown version */ 3687 3688 for (i = 0; i < n; i++) 3689 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3690 } 3691 3692 static void 3693 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3694 { 3695 int i; 3696 struct edid *edid = (struct edid *)raw_edid; 3697 3698 if (!edid) 3699 return; 3700 3701 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3702 cb(&edid->detailed_timings[i], closure); 3703 3704 for (i = 1; i <= raw_edid[0x7e]; i++) { 3705 u8 *ext = raw_edid + (i * EDID_SIZE); 3706 3707 switch (*ext) { 3708 case CEA_EXT: 3709 cea_for_each_detailed_block(ext, cb, closure); 3710 break; 3711 case VTB_EXT: 3712 vtb_for_each_detailed_block(ext, cb, closure); 3713 break; 3714 default: 3715 break; 3716 } 3717 } 3718 } 3719 3720 /* 3721 * EDID is delightfully ambiguous about how interlaced modes are to be 3722 * encoded. Our internal representation is of frame height, but some 3723 * HDTV detailed timings are encoded as field height. 3724 * 3725 * The format list here is from CEA, in frame size. Technically we 3726 * should be checking refresh rate too. Whatever. 3727 */ 3728 static void 3729 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3730 struct detailed_pixel_timing *pt) 3731 { 3732 int i; 3733 3734 static const struct { 3735 int w, h; 3736 } cea_interlaced[] = { 3737 { 1920, 1080 }, 3738 { 720, 480 }, 3739 { 1440, 480 }, 3740 { 2880, 480 }, 3741 { 720, 576 }, 3742 { 1440, 576 }, 3743 { 2880, 576 }, 3744 }; 3745 3746 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3747 return; 3748 3749 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3750 if ((mode->hdisplay == cea_interlaced[i].w) && 3751 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3752 mode->vdisplay *= 2; 3753 mode->vsync_start *= 2; 3754 mode->vsync_end *= 2; 3755 mode->vtotal *= 2; 3756 mode->vtotal |= 1; 3757 } 3758 } 3759 3760 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3761 } 3762 3763 /** 3764 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3765 * @edid: EDID block 3766 * @timing: EDID detailed timing info 3767 * @quirks: quirks to apply 3768 * 3769 * An EDID detailed timing block contains enough info for us to create and 3770 * return a new struct drm_display_mode. 3771 */ 3772 static 3773 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3774 struct detailed_timing *timing, 3775 u32 quirks) 3776 { 3777 struct drm_display_mode *mode; 3778 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3779 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3780 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3781 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3782 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3783 unsigned hsync_offset = 3784 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3785 pt->hsync_offset_lo; 3786 unsigned hsync_pulse_width = 3787 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3788 pt->hsync_pulse_width_lo; 3789 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3790 2 | pt->vsync_offset_pulse_width_lo >> 4; 3791 unsigned vsync_pulse_width = 3792 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3793 (pt->vsync_offset_pulse_width_lo & 0xf); 3794 3795 /* ignore tiny modes */ 3796 if (hactive < 64 || vactive < 64) 3797 return NULL; 3798 3799 if (pt->misc & DRM_EDID_PT_STEREO) { 3800 debug("stereo mode not supported\n"); 3801 return NULL; 3802 } 3803 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3804 debug("composite sync not supported\n"); 3805 3806 /* it is incorrect if hsync/vsync width is zero */ 3807 if (!hsync_pulse_width || !vsync_pulse_width) { 3808 debug("Incorrect Detailed timing. "); 3809 debug("Wrong Hsync/Vsync pulse width\n"); 3810 return NULL; 3811 } 3812 3813 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3814 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3815 if (!mode) 3816 return NULL; 3817 3818 goto set_refresh; 3819 } 3820 3821 mode = drm_mode_create(); 3822 if (!mode) 3823 return NULL; 3824 3825 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3826 timing->pixel_clock = cpu_to_le16(1088); 3827 3828 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3829 3830 mode->hdisplay = hactive; 3831 mode->hsync_start = mode->hdisplay + hsync_offset; 3832 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3833 mode->htotal = mode->hdisplay + hblank; 3834 3835 mode->vdisplay = vactive; 3836 mode->vsync_start = mode->vdisplay + vsync_offset; 3837 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3838 mode->vtotal = mode->vdisplay + vblank; 3839 3840 /* Some EDIDs have bogus h/vtotal values */ 3841 if (mode->hsync_end > mode->htotal) 3842 mode->htotal = mode->hsync_end + 1; 3843 if (mode->vsync_end > mode->vtotal) 3844 mode->vtotal = mode->vsync_end + 1; 3845 3846 drm_mode_do_interlace_quirk(mode, pt); 3847 3848 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3849 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3850 DRM_EDID_PT_VSYNC_POSITIVE; 3851 3852 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3853 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3854 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3855 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3856 3857 set_refresh: 3858 3859 mode->type = DRM_MODE_TYPE_DRIVER; 3860 mode->vrefresh = drm_get_vrefresh(mode); 3861 3862 return mode; 3863 } 3864 3865 /* 3866 * Calculate the alternate clock for the CEA mode 3867 * (60Hz vs. 59.94Hz etc.) 3868 */ 3869 static unsigned int 3870 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3871 { 3872 unsigned int clock = cea_mode->clock; 3873 3874 if (cea_mode->vrefresh % 6 != 0) 3875 return clock; 3876 3877 /* 3878 * edid_cea_modes contains the 59.94Hz 3879 * variant for 240 and 480 line modes, 3880 * and the 60Hz variant otherwise. 3881 */ 3882 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3883 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3884 else 3885 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3886 3887 return clock; 3888 } 3889 3890 /** 3891 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3892 * @mode1: first mode 3893 * @mode2: second mode 3894 * 3895 * Check to see if @mode1 and @mode2 are equivalent, but 3896 * don't check the pixel clocks nor the stereo layout. 3897 * 3898 * Returns: 3899 * True if the modes are equal, false otherwise. 3900 */ 3901 3902 static 3903 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3904 const struct drm_display_mode *mode2) 3905 { 3906 unsigned int flags_mask = 3907 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3908 3909 if (mode1->hdisplay == mode2->hdisplay && 3910 mode1->hsync_start == mode2->hsync_start && 3911 mode1->hsync_end == mode2->hsync_end && 3912 mode1->htotal == mode2->htotal && 3913 mode1->vdisplay == mode2->vdisplay && 3914 mode1->vsync_start == mode2->vsync_start && 3915 mode1->vsync_end == mode2->vsync_end && 3916 mode1->vtotal == mode2->vtotal && 3917 mode1->vscan == mode2->vscan && 3918 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3919 return true; 3920 3921 return false; 3922 } 3923 3924 /** 3925 * drm_mode_equal_no_clocks - test modes for equality 3926 * @mode1: first mode 3927 * @mode2: second mode 3928 * 3929 * Check to see if @mode1 and @mode2 are equivalent, but 3930 * don't check the pixel clocks. 3931 * 3932 * Returns: 3933 * True if the modes are equal, false otherwise. 3934 */ 3935 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3936 const struct drm_display_mode *mode2) 3937 { 3938 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3939 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3940 return false; 3941 3942 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3943 } 3944 3945 static 3946 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3947 unsigned int clock_tolerance) 3948 { 3949 u8 vic; 3950 3951 if (!to_match->clock) 3952 return 0; 3953 3954 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3955 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 3956 unsigned int clock1, clock2; 3957 3958 /* Check both 60Hz and 59.94Hz */ 3959 clock1 = cea_mode->clock; 3960 clock2 = cea_mode_alternate_clock(cea_mode); 3961 3962 if (abs(to_match->clock - clock1) > clock_tolerance && 3963 abs(to_match->clock - clock2) > clock_tolerance) 3964 continue; 3965 3966 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3967 return vic; 3968 } 3969 3970 return 0; 3971 } 3972 3973 static unsigned int 3974 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3975 { 3976 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3977 return hdmi_mode->clock; 3978 3979 return cea_mode_alternate_clock(hdmi_mode); 3980 } 3981 3982 static 3983 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3984 unsigned int clock_tolerance) 3985 { 3986 u8 vic; 3987 3988 if (!to_match->clock) 3989 return 0; 3990 3991 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3992 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3993 unsigned int clock1, clock2; 3994 3995 /* Make sure to also match alternate clocks */ 3996 clock1 = hdmi_mode->clock; 3997 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3998 3999 if (abs(to_match->clock - clock1) > clock_tolerance && 4000 abs(to_match->clock - clock2) > clock_tolerance) 4001 continue; 4002 4003 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 4004 return vic; 4005 } 4006 4007 return 0; 4008 } 4009 4010 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4011 { 4012 const struct drm_display_mode *cea_mode; 4013 int clock1, clock2, clock; 4014 u8 vic; 4015 const char *type; 4016 4017 /* 4018 * allow 5kHz clock difference either way to account for 4019 * the 10kHz clock resolution limit of detailed timings. 4020 */ 4021 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4022 if (drm_valid_cea_vic(vic)) { 4023 type = "CEA"; 4024 cea_mode = cea_mode_for_vic(vic); 4025 clock1 = cea_mode->clock; 4026 clock2 = cea_mode_alternate_clock(cea_mode); 4027 } else { 4028 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4029 if (drm_valid_hdmi_vic(vic)) { 4030 type = "HDMI"; 4031 cea_mode = &edid_4k_modes[vic]; 4032 clock1 = cea_mode->clock; 4033 clock2 = hdmi_mode_alternate_clock(cea_mode); 4034 } else { 4035 return; 4036 } 4037 } 4038 4039 /* pick whichever is closest */ 4040 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4041 clock = clock1; 4042 else 4043 clock = clock2; 4044 4045 if (mode->clock == clock) 4046 return; 4047 4048 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4049 type, vic, mode->clock, clock); 4050 mode->clock = clock; 4051 } 4052 4053 static void 4054 do_detailed_mode(struct detailed_timing *timing, void *c) 4055 { 4056 struct detailed_mode_closure *closure = c; 4057 struct drm_display_mode *newmode; 4058 4059 if (timing->pixel_clock) { 4060 newmode = drm_mode_detailed( 4061 closure->edid, timing, 4062 closure->quirks); 4063 if (!newmode) 4064 return; 4065 4066 if (closure->preferred) 4067 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4068 4069 /* 4070 * Detailed modes are limited to 10kHz pixel clock resolution, 4071 * so fix up anything that looks like CEA/HDMI mode, 4072 * but the clock is just slightly off. 4073 */ 4074 fixup_detailed_cea_mode_clock(newmode); 4075 drm_add_hdmi_modes(closure->data, newmode); 4076 drm_mode_destroy(newmode); 4077 closure->modes++; 4078 closure->preferred = 0; 4079 } 4080 } 4081 4082 /* 4083 * add_detailed_modes - Add modes from detailed timings 4084 * @data: attached data 4085 * @edid: EDID block to scan 4086 * @quirks: quirks to apply 4087 */ 4088 static int 4089 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 4090 u32 quirks) 4091 { 4092 struct detailed_mode_closure closure = { 4093 .data = data, 4094 .edid = edid, 4095 .preferred = 1, 4096 .quirks = quirks, 4097 }; 4098 4099 if (closure.preferred && !version_greater(edid, 1, 3)) 4100 closure.preferred = 4101 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 4102 4103 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 4104 4105 return closure.modes; 4106 } 4107 4108 static int drm_cvt_modes(struct hdmi_edid_data *data, 4109 struct detailed_timing *timing) 4110 { 4111 int i, j, modes = 0; 4112 struct drm_display_mode *newmode; 4113 struct cvt_timing *cvt; 4114 const int rates[] = { 60, 85, 75, 60, 50 }; 4115 const u8 empty[3] = { 0, 0, 0 }; 4116 4117 for (i = 0; i < 4; i++) { 4118 int uninitialized_var(width), height; 4119 4120 cvt = &timing->data.other_data.data.cvt[i]; 4121 4122 if (!memcmp(cvt->code, empty, 3)) 4123 continue; 4124 4125 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4126 switch (cvt->code[1] & 0x0c) { 4127 case 0x00: 4128 width = height * 4 / 3; 4129 break; 4130 case 0x04: 4131 width = height * 16 / 9; 4132 break; 4133 case 0x08: 4134 width = height * 16 / 10; 4135 break; 4136 case 0x0c: 4137 width = height * 15 / 9; 4138 break; 4139 } 4140 4141 for (j = 1; j < 5; j++) { 4142 if (cvt->code[2] & (1 << j)) { 4143 newmode = drm_cvt_mode(width, height, 4144 rates[j], j == 0, 4145 false, false); 4146 if (newmode) { 4147 drm_add_hdmi_modes(data, newmode); 4148 modes++; 4149 drm_mode_destroy(newmode); 4150 } 4151 } 4152 } 4153 } 4154 4155 return modes; 4156 } 4157 4158 static void 4159 do_cvt_mode(struct detailed_timing *timing, void *c) 4160 { 4161 struct detailed_mode_closure *closure = c; 4162 struct detailed_non_pixel *data = &timing->data.other_data; 4163 4164 if (data->type == EDID_DETAIL_CVT_3BYTE) 4165 closure->modes += drm_cvt_modes(closure->data, timing); 4166 } 4167 4168 static int 4169 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 4170 { 4171 struct detailed_mode_closure closure = { 4172 .data = data, 4173 .edid = edid, 4174 }; 4175 4176 if (version_greater(edid, 1, 2)) 4177 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 4178 4179 /* XXX should also look for CVT codes in VTB blocks */ 4180 4181 return closure.modes; 4182 } 4183 4184 static void 4185 find_gtf2(struct detailed_timing *t, void *data) 4186 { 4187 u8 *r = (u8 *)t; 4188 4189 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 4190 *(u8 **)data = r; 4191 } 4192 4193 /* Secondary GTF curve kicks in above some break frequency */ 4194 static int 4195 drm_gtf2_hbreak(struct edid *edid) 4196 { 4197 u8 *r = NULL; 4198 4199 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4200 return r ? (r[12] * 2) : 0; 4201 } 4202 4203 static int 4204 drm_gtf2_2c(struct edid *edid) 4205 { 4206 u8 *r = NULL; 4207 4208 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4209 return r ? r[13] : 0; 4210 } 4211 4212 static int 4213 drm_gtf2_m(struct edid *edid) 4214 { 4215 u8 *r = NULL; 4216 4217 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4218 return r ? (r[15] << 8) + r[14] : 0; 4219 } 4220 4221 static int 4222 drm_gtf2_k(struct edid *edid) 4223 { 4224 u8 *r = NULL; 4225 4226 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4227 return r ? r[16] : 0; 4228 } 4229 4230 static int 4231 drm_gtf2_2j(struct edid *edid) 4232 { 4233 u8 *r = NULL; 4234 4235 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4236 return r ? r[17] : 0; 4237 } 4238 4239 /** 4240 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 4241 * @edid: EDID block to scan 4242 */ 4243 static int standard_timing_level(struct edid *edid) 4244 { 4245 if (edid->revision >= 2) { 4246 if (edid->revision >= 4 && 4247 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 4248 return LEVEL_CVT; 4249 if (drm_gtf2_hbreak(edid)) 4250 return LEVEL_GTF2; 4251 return LEVEL_GTF; 4252 } 4253 return LEVEL_DMT; 4254 } 4255 4256 /* 4257 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 4258 * monitors fill with ascii space (0x20) instead. 4259 */ 4260 static int 4261 bad_std_timing(u8 a, u8 b) 4262 { 4263 return (a == 0x00 && b == 0x00) || 4264 (a == 0x01 && b == 0x01) || 4265 (a == 0x20 && b == 0x20); 4266 } 4267 4268 static void 4269 is_rb(struct detailed_timing *t, void *data) 4270 { 4271 u8 *r = (u8 *)t; 4272 4273 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 4274 if (r[15] & 0x10) 4275 *(bool *)data = true; 4276 } 4277 4278 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 4279 static bool 4280 drm_monitor_supports_rb(struct edid *edid) 4281 { 4282 if (edid->revision >= 4) { 4283 bool ret = false; 4284 4285 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 4286 return ret; 4287 } 4288 4289 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 4290 } 4291 4292 static bool 4293 mode_is_rb(const struct drm_display_mode *mode) 4294 { 4295 return (mode->htotal - mode->hdisplay == 160) && 4296 (mode->hsync_end - mode->hdisplay == 80) && 4297 (mode->hsync_end - mode->hsync_start == 32) && 4298 (mode->vsync_start - mode->vdisplay == 3); 4299 } 4300 4301 /* 4302 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 4303 * @hsize: Mode width 4304 * @vsize: Mode height 4305 * @fresh: Mode refresh rate 4306 * @rb: Mode reduced-blanking-ness 4307 * 4308 * Walk the DMT mode list looking for a match for the given parameters. 4309 * 4310 * Return: A newly allocated copy of the mode, or NULL if not found. 4311 */ 4312 static struct drm_display_mode *drm_mode_find_dmt( 4313 int hsize, int vsize, int fresh, 4314 bool rb) 4315 { 4316 int i; 4317 struct drm_display_mode *newmode; 4318 4319 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4320 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4321 4322 if (hsize != ptr->hdisplay) 4323 continue; 4324 if (vsize != ptr->vdisplay) 4325 continue; 4326 if (fresh != drm_get_vrefresh(ptr)) 4327 continue; 4328 if (rb != mode_is_rb(ptr)) 4329 continue; 4330 4331 newmode = drm_mode_create(); 4332 *newmode = *ptr; 4333 return newmode; 4334 } 4335 4336 return NULL; 4337 } 4338 4339 static struct drm_display_mode * 4340 drm_gtf_mode_complex(int hdisplay, int vdisplay, 4341 int vrefresh, bool interlaced, int margins, 4342 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 4343 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 4344 #define GTF_MARGIN_PERCENTAGE 18 4345 /* 2) character cell horizontal granularity (pixels) - default 8 */ 4346 #define GTF_CELL_GRAN 8 4347 /* 3) Minimum vertical porch (lines) - default 3 */ 4348 #define GTF_MIN_V_PORCH 1 4349 /* width of vsync in lines */ 4350 #define V_SYNC_RQD 3 4351 /* width of hsync as % of total line */ 4352 #define H_SYNC_PERCENT 8 4353 /* min time of vsync + back porch (microsec) */ 4354 #define MIN_VSYNC_PLUS_BP 550 4355 /* C' and M' are part of the Blanking Duty Cycle computation */ 4356 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 4357 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 4358 struct drm_display_mode *drm_mode; 4359 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 4360 int top_margin, bottom_margin; 4361 int interlace; 4362 unsigned int hfreq_est; 4363 int vsync_plus_bp; 4364 unsigned int vtotal_lines; 4365 int left_margin, right_margin; 4366 unsigned int total_active_pixels, ideal_duty_cycle; 4367 unsigned int hblank, total_pixels, pixel_freq; 4368 int hsync, hfront_porch, vodd_front_porch_lines; 4369 unsigned int tmp1, tmp2; 4370 4371 drm_mode = drm_mode_create(); 4372 if (!drm_mode) 4373 return NULL; 4374 4375 /* 1. In order to give correct results, the number of horizontal 4376 * pixels requested is first processed to ensure that it is divisible 4377 * by the character size, by rounding it to the nearest character 4378 * cell boundary: 4379 */ 4380 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4381 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 4382 4383 /* 2. If interlace is requested, the number of vertical lines assumed 4384 * by the calculation must be halved, as the computation calculates 4385 * the number of vertical lines per field. 4386 */ 4387 if (interlaced) 4388 vdisplay_rnd = vdisplay / 2; 4389 else 4390 vdisplay_rnd = vdisplay; 4391 4392 /* 3. Find the frame rate required: */ 4393 if (interlaced) 4394 vfieldrate_rqd = vrefresh * 2; 4395 else 4396 vfieldrate_rqd = vrefresh; 4397 4398 /* 4. Find number of lines in Top margin: */ 4399 top_margin = 0; 4400 if (margins) 4401 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4402 1000; 4403 /* 5. Find number of lines in bottom margin: */ 4404 bottom_margin = top_margin; 4405 4406 /* 6. If interlace is required, then set variable interlace: */ 4407 if (interlaced) 4408 interlace = 1; 4409 else 4410 interlace = 0; 4411 4412 /* 7. Estimate the Horizontal frequency */ 4413 { 4414 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 4415 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 4416 2 + interlace; 4417 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 4418 } 4419 4420 /* 8. Find the number of lines in V sync + back porch */ 4421 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 4422 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 4423 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 4424 /* 9. Find the number of lines in V back porch alone: 4425 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 4426 */ 4427 /* 10. Find the total number of lines in Vertical field period: */ 4428 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 4429 vsync_plus_bp + GTF_MIN_V_PORCH; 4430 /* 11. Estimate the Vertical field frequency: 4431 * vfieldrate_est = hfreq_est / vtotal_lines; 4432 */ 4433 4434 /* 12. Find the actual horizontal period: 4435 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 4436 */ 4437 /* 13. Find the actual Vertical field frequency: 4438 * vfield_rate = hfreq_est / vtotal_lines; 4439 */ 4440 /* 14. Find the Vertical frame frequency: 4441 * if (interlaced) 4442 * vframe_rate = vfield_rate / 2; 4443 * else 4444 * vframe_rate = vfield_rate; 4445 */ 4446 /* 15. Find number of pixels in left margin: */ 4447 if (margins) 4448 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4449 1000; 4450 else 4451 left_margin = 0; 4452 4453 /* 16.Find number of pixels in right margin: */ 4454 right_margin = left_margin; 4455 /* 17.Find total number of active pixels in image and left and right */ 4456 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 4457 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 4458 ideal_duty_cycle = GTF_C_PRIME * 1000 - 4459 (GTF_M_PRIME * 1000000 / hfreq_est); 4460 /* 19.Find the number of pixels in the blanking time to the nearest 4461 * double character cell: 4462 */ 4463 hblank = total_active_pixels * ideal_duty_cycle / 4464 (100000 - ideal_duty_cycle); 4465 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 4466 hblank = hblank * 2 * GTF_CELL_GRAN; 4467 /* 20.Find total number of pixels: */ 4468 total_pixels = total_active_pixels + hblank; 4469 /* 21.Find pixel clock frequency: */ 4470 pixel_freq = total_pixels * hfreq_est / 1000; 4471 /* Stage 1 computations are now complete; I should really pass 4472 * the results to another function and do the Stage 2 computations, 4473 * but I only need a few more values so I'll just append the 4474 * computations here for now 4475 */ 4476 4477 /* 17. Find the number of pixels in the horizontal sync period: */ 4478 hsync = H_SYNC_PERCENT * total_pixels / 100; 4479 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4480 hsync = hsync * GTF_CELL_GRAN; 4481 /* 18. Find the number of pixels in horizontal front porch period */ 4482 hfront_porch = hblank / 2 - hsync; 4483 /* 36. Find the number of lines in the odd front porch period: */ 4484 vodd_front_porch_lines = GTF_MIN_V_PORCH; 4485 4486 /* finally, pack the results in the mode struct */ 4487 drm_mode->hdisplay = hdisplay_rnd; 4488 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 4489 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 4490 drm_mode->htotal = total_pixels; 4491 drm_mode->vdisplay = vdisplay_rnd; 4492 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 4493 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 4494 drm_mode->vtotal = vtotal_lines; 4495 4496 drm_mode->clock = pixel_freq; 4497 4498 if (interlaced) { 4499 drm_mode->vtotal *= 2; 4500 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 4501 } 4502 4503 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 4504 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 4505 else 4506 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 4507 4508 return drm_mode; 4509 } 4510 4511 /** 4512 * drm_gtf_mode - create the mode based on the GTF algorithm 4513 * @hdisplay: hdisplay size 4514 * @vdisplay: vdisplay size 4515 * @vrefresh: vrefresh rate. 4516 * @interlaced: whether to compute an interlaced mode 4517 * @margins: desired margin (borders) size 4518 * 4519 * return the mode based on GTF algorithm 4520 * 4521 * This function is to create the mode based on the GTF algorithm. 4522 * Generalized Timing Formula is derived from: 4523 * GTF Spreadsheet by Andy Morrish (1/5/97) 4524 * available at http://www.vesa.org 4525 * 4526 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 4527 * What I have done is to translate it by using integer calculation. 4528 * I also refer to the function of fb_get_mode in the file of 4529 * drivers/video/fbmon.c 4530 * 4531 * Standard GTF parameters: 4532 * M = 600 4533 * C = 40 4534 * K = 128 4535 * J = 20 4536 * 4537 * Returns: 4538 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 4539 * The display mode object is allocated with drm_mode_create(). Returns NULL 4540 * when no mode could be allocated. 4541 */ 4542 static struct drm_display_mode * 4543 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 4544 bool interlaced, int margins) 4545 { 4546 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 4547 interlaced, margins, 4548 600, 40 * 2, 128, 20 * 2); 4549 } 4550 4551 /** drm_mode_hsync - get the hsync of a mode 4552 * @mode: mode 4553 * 4554 * Returns: 4555 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 4556 * value first if it is not yet set. 4557 */ 4558 static int drm_mode_hsync(const struct drm_display_mode *mode) 4559 { 4560 unsigned int calc_val; 4561 4562 if (mode->htotal < 0) 4563 return 0; 4564 4565 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 4566 calc_val += 500; /* round to 1000Hz */ 4567 calc_val /= 1000; /* truncate to kHz */ 4568 4569 return calc_val; 4570 } 4571 4572 /** 4573 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 4574 * @data: the structure that save parsed hdmi edid data 4575 * @edid: EDID block to scan 4576 * @t: standard timing params 4577 * 4578 * Take the standard timing params (in this case width, aspect, and refresh) 4579 * and convert them into a real mode using CVT/GTF/DMT. 4580 */ 4581 static struct drm_display_mode * 4582 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4583 struct std_timing *t) 4584 { 4585 struct drm_display_mode *mode = NULL; 4586 int i, hsize, vsize; 4587 int vrefresh_rate; 4588 int num = data->modes; 4589 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4590 >> EDID_TIMING_ASPECT_SHIFT; 4591 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4592 >> EDID_TIMING_VFREQ_SHIFT; 4593 int timing_level = standard_timing_level(edid); 4594 4595 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4596 return NULL; 4597 4598 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4599 hsize = t->hsize * 8 + 248; 4600 /* vrefresh_rate = vfreq + 60 */ 4601 vrefresh_rate = vfreq + 60; 4602 /* the vdisplay is calculated based on the aspect ratio */ 4603 if (aspect_ratio == 0) { 4604 if (edid->revision < 3) 4605 vsize = hsize; 4606 else 4607 vsize = (hsize * 10) / 16; 4608 } else if (aspect_ratio == 1) { 4609 vsize = (hsize * 3) / 4; 4610 } else if (aspect_ratio == 2) { 4611 vsize = (hsize * 4) / 5; 4612 } else { 4613 vsize = (hsize * 9) / 16; 4614 } 4615 4616 /* HDTV hack, part 1 */ 4617 if (vrefresh_rate == 60 && 4618 ((hsize == 1360 && vsize == 765) || 4619 (hsize == 1368 && vsize == 769))) { 4620 hsize = 1366; 4621 vsize = 768; 4622 } 4623 4624 /* 4625 * If we already has a mode for this size and refresh 4626 * rate (because it came from detailed or CVT info), use that 4627 * instead. This way we don't have to guess at interlace or 4628 * reduced blanking. 4629 */ 4630 for (i = 0; i < num; i++) 4631 if (data->mode_buf[i].hdisplay == hsize && 4632 data->mode_buf[i].vdisplay == vsize && 4633 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4634 return NULL; 4635 4636 /* HDTV hack, part 2 */ 4637 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4638 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4639 false); 4640 mode->hdisplay = 1366; 4641 mode->hsync_start = mode->hsync_start - 1; 4642 mode->hsync_end = mode->hsync_end - 1; 4643 return mode; 4644 } 4645 4646 /* check whether it can be found in default mode table */ 4647 if (drm_monitor_supports_rb(edid)) { 4648 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4649 true); 4650 if (mode) 4651 return mode; 4652 } 4653 4654 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4655 if (mode) 4656 return mode; 4657 4658 /* okay, generate it */ 4659 switch (timing_level) { 4660 case LEVEL_DMT: 4661 break; 4662 case LEVEL_GTF: 4663 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4664 break; 4665 case LEVEL_GTF2: 4666 /* 4667 * This is potentially wrong if there's ever a monitor with 4668 * more than one ranges section, each claiming a different 4669 * secondary GTF curve. Please don't do that. 4670 */ 4671 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4672 if (!mode) 4673 return NULL; 4674 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4675 drm_mode_destroy(mode); 4676 mode = drm_gtf_mode_complex(hsize, vsize, 4677 vrefresh_rate, 0, 0, 4678 drm_gtf2_m(edid), 4679 drm_gtf2_2c(edid), 4680 drm_gtf2_k(edid), 4681 drm_gtf2_2j(edid)); 4682 } 4683 break; 4684 case LEVEL_CVT: 4685 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4686 false); 4687 break; 4688 } 4689 4690 return mode; 4691 } 4692 4693 static void 4694 do_standard_modes(struct detailed_timing *timing, void *c) 4695 { 4696 struct detailed_mode_closure *closure = c; 4697 struct detailed_non_pixel *data = &timing->data.other_data; 4698 struct edid *edid = closure->edid; 4699 4700 if (data->type == EDID_DETAIL_STD_MODES) { 4701 int i; 4702 4703 for (i = 0; i < 6; i++) { 4704 struct std_timing *std; 4705 struct drm_display_mode *newmode; 4706 4707 std = &data->data.timings[i]; 4708 newmode = drm_mode_std(closure->data, edid, std); 4709 if (newmode) { 4710 drm_add_hdmi_modes(closure->data, newmode); 4711 closure->modes++; 4712 drm_mode_destroy(newmode); 4713 } 4714 } 4715 } 4716 } 4717 4718 /** 4719 * add_standard_modes - get std. modes from EDID and add them 4720 * @data: data to add mode(s) to 4721 * @edid: EDID block to scan 4722 * 4723 * Standard modes can be calculated using the appropriate standard (DMT, 4724 * GTF or CVT. Grab them from @edid and add them to the list. 4725 */ 4726 static int 4727 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4728 { 4729 int i, modes = 0; 4730 struct detailed_mode_closure closure = { 4731 .data = data, 4732 .edid = edid, 4733 }; 4734 4735 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4736 struct drm_display_mode *newmode; 4737 4738 newmode = drm_mode_std(data, edid, 4739 &edid->standard_timings[i]); 4740 if (newmode) { 4741 drm_add_hdmi_modes(data, newmode); 4742 modes++; 4743 drm_mode_destroy(newmode); 4744 } 4745 } 4746 4747 if (version_greater(edid, 1, 0)) 4748 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4749 &closure); 4750 4751 /* XXX should also look for standard codes in VTB blocks */ 4752 4753 return modes + closure.modes; 4754 } 4755 4756 static int 4757 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4758 { 4759 int i, j, m, modes = 0; 4760 struct drm_display_mode *mode; 4761 u8 *est = ((u8 *)timing) + 6; 4762 4763 for (i = 0; i < 6; i++) { 4764 for (j = 7; j >= 0; j--) { 4765 m = (i * 8) + (7 - j); 4766 if (m >= ARRAY_SIZE(est3_modes)) 4767 break; 4768 if (est[i] & (1 << j)) { 4769 mode = drm_mode_find_dmt( 4770 est3_modes[m].w, 4771 est3_modes[m].h, 4772 est3_modes[m].r, 4773 est3_modes[m].rb); 4774 if (mode) { 4775 drm_add_hdmi_modes(data, mode); 4776 modes++; 4777 drm_mode_destroy(mode); 4778 } 4779 } 4780 } 4781 } 4782 4783 return modes; 4784 } 4785 4786 static void 4787 do_established_modes(struct detailed_timing *timing, void *c) 4788 { 4789 struct detailed_mode_closure *closure = c; 4790 struct detailed_non_pixel *data = &timing->data.other_data; 4791 4792 if (data->type == EDID_DETAIL_EST_TIMINGS) 4793 closure->modes += drm_est3_modes(closure->data, timing); 4794 } 4795 4796 /** 4797 * add_established_modes - get est. modes from EDID and add them 4798 * @data: data to add mode(s) to 4799 * @edid: EDID block to scan 4800 * 4801 * Each EDID block contains a bitmap of the supported "established modes" list 4802 * (defined above). Tease them out and add them to the modes list. 4803 */ 4804 static int 4805 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4806 { 4807 unsigned long est_bits = edid->established_timings.t1 | 4808 (edid->established_timings.t2 << 8) | 4809 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4810 int i, modes = 0; 4811 struct detailed_mode_closure closure = { 4812 .data = data, 4813 .edid = edid, 4814 }; 4815 4816 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4817 if (est_bits & (1 << i)) { 4818 struct drm_display_mode *newmode = drm_mode_create(); 4819 *newmode = edid_est_modes[i]; 4820 if (newmode) { 4821 drm_add_hdmi_modes(data, newmode); 4822 modes++; 4823 drm_mode_destroy(newmode); 4824 } 4825 } 4826 } 4827 4828 if (version_greater(edid, 1, 0)) 4829 drm_for_each_detailed_block((u8 *)edid, 4830 do_established_modes, &closure); 4831 4832 return modes + closure.modes; 4833 } 4834 4835 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4836 { 4837 u8 vic; 4838 4839 if (!to_match->clock) 4840 return 0; 4841 4842 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4843 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4844 unsigned int clock1, clock2; 4845 4846 /* Make sure to also match alternate clocks */ 4847 clock1 = hdmi_mode->clock; 4848 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4849 4850 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4851 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4852 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4853 return vic; 4854 } 4855 return 0; 4856 } 4857 4858 static int 4859 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4860 { 4861 struct drm_display_mode *mode; 4862 int i, num, modes = 0; 4863 4864 /* Don't add CEA modes if the CEA extension block is missing */ 4865 if (!drm_find_cea_extension(edid)) 4866 return 0; 4867 4868 /* 4869 * Go through all probed modes and create a new mode 4870 * with the alternate clock for certain CEA modes. 4871 */ 4872 num = data->modes; 4873 4874 for (i = 0; i < num; i++) { 4875 const struct drm_display_mode *cea_mode = NULL; 4876 struct drm_display_mode *newmode; 4877 u8 vic; 4878 unsigned int clock1, clock2; 4879 4880 mode = &data->mode_buf[i]; 4881 vic = drm_match_cea_mode(mode); 4882 4883 if (drm_valid_cea_vic(vic)) { 4884 cea_mode = cea_mode_for_vic(vic); 4885 clock2 = cea_mode_alternate_clock(cea_mode); 4886 } else { 4887 vic = drm_match_hdmi_mode(mode); 4888 if (drm_valid_hdmi_vic(vic)) { 4889 cea_mode = &edid_4k_modes[vic]; 4890 clock2 = hdmi_mode_alternate_clock(cea_mode); 4891 } 4892 } 4893 4894 if (!cea_mode) 4895 continue; 4896 4897 clock1 = cea_mode->clock; 4898 4899 if (clock1 == clock2) 4900 continue; 4901 4902 if (mode->clock != clock1 && mode->clock != clock2) 4903 continue; 4904 4905 newmode = drm_mode_create(); 4906 *newmode = *cea_mode; 4907 if (!newmode) 4908 continue; 4909 4910 /* Carry over the stereo flags */ 4911 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4912 4913 /* 4914 * The current mode could be either variant. Make 4915 * sure to pick the "other" clock for the new mode. 4916 */ 4917 if (mode->clock != clock1) 4918 newmode->clock = clock1; 4919 else 4920 newmode->clock = clock2; 4921 4922 drm_add_hdmi_modes(data, newmode); 4923 modes++; 4924 drm_mode_destroy(newmode); 4925 } 4926 4927 return modes; 4928 } 4929 4930 static u8 *drm_find_displayid_extension(struct edid *edid) 4931 { 4932 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4933 } 4934 4935 static int validate_displayid(u8 *displayid, int length, int idx) 4936 { 4937 int i; 4938 u8 csum = 0; 4939 struct displayid_hdr *base; 4940 4941 base = (struct displayid_hdr *)&displayid[idx]; 4942 4943 debug("base revision 0x%x, length %d, %d %d\n", 4944 base->rev, base->bytes, base->prod_id, base->ext_count); 4945 4946 if (base->bytes + 5 > length - idx) 4947 return -EINVAL; 4948 for (i = idx; i <= base->bytes + 5; i++) 4949 csum += displayid[i]; 4950 if (csum) { 4951 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4952 return -EINVAL; 4953 } 4954 return 0; 4955 } 4956 4957 static struct 4958 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4959 *timings) 4960 { 4961 struct drm_display_mode *mode; 4962 unsigned pixel_clock = (timings->pixel_clock[0] | 4963 (timings->pixel_clock[1] << 8) | 4964 (timings->pixel_clock[2] << 16)); 4965 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4966 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4967 unsigned hsync = (timings->hsync[0] | 4968 (timings->hsync[1] & 0x7f) << 8) + 1; 4969 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4970 unsigned vactive = (timings->vactive[0] | 4971 timings->vactive[1] << 8) + 1; 4972 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4973 unsigned vsync = (timings->vsync[0] | 4974 (timings->vsync[1] & 0x7f) << 8) + 1; 4975 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4976 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4977 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4978 4979 mode = drm_mode_create(); 4980 if (!mode) 4981 return NULL; 4982 4983 mode->clock = pixel_clock * 10; 4984 mode->hdisplay = hactive; 4985 mode->hsync_start = mode->hdisplay + hsync; 4986 mode->hsync_end = mode->hsync_start + hsync_width; 4987 mode->htotal = mode->hdisplay + hblank; 4988 4989 mode->vdisplay = vactive; 4990 mode->vsync_start = mode->vdisplay + vsync; 4991 mode->vsync_end = mode->vsync_start + vsync_width; 4992 mode->vtotal = mode->vdisplay + vblank; 4993 4994 mode->flags = 0; 4995 mode->flags |= 4996 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4997 mode->flags |= 4998 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4999 mode->type = DRM_MODE_TYPE_DRIVER; 5000 5001 if (timings->flags & 0x80) 5002 mode->type |= DRM_MODE_TYPE_PREFERRED; 5003 mode->vrefresh = drm_get_vrefresh(mode); 5004 5005 return mode; 5006 } 5007 5008 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 5009 struct displayid_block *block) 5010 { 5011 struct displayid_detailed_timing_block *det; 5012 int i; 5013 int num_timings; 5014 struct drm_display_mode *newmode; 5015 int num_modes = 0; 5016 5017 det = (struct displayid_detailed_timing_block *)block; 5018 /* blocks must be multiple of 20 bytes length */ 5019 if (block->num_bytes % 20) 5020 return 0; 5021 5022 num_timings = block->num_bytes / 20; 5023 for (i = 0; i < num_timings; i++) { 5024 struct displayid_detailed_timings_1 *timings = 5025 &det->timings[i]; 5026 5027 newmode = drm_displayid_detailed(timings); 5028 if (!newmode) 5029 continue; 5030 5031 drm_add_hdmi_modes(data, newmode); 5032 num_modes++; 5033 drm_mode_destroy(newmode); 5034 } 5035 return num_modes; 5036 } 5037 5038 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 5039 struct edid *edid) 5040 { 5041 u8 *displayid; 5042 int ret; 5043 int idx = 1; 5044 int length = EDID_SIZE; 5045 struct displayid_block *block; 5046 int num_modes = 0; 5047 5048 displayid = drm_find_displayid_extension(edid); 5049 if (!displayid) 5050 return 0; 5051 5052 ret = validate_displayid(displayid, length, idx); 5053 if (ret) 5054 return 0; 5055 5056 idx += sizeof(struct displayid_hdr); 5057 while (block = (struct displayid_block *)&displayid[idx], 5058 idx + sizeof(struct displayid_block) <= length && 5059 idx + sizeof(struct displayid_block) + block->num_bytes <= 5060 length && block->num_bytes > 0) { 5061 idx += block->num_bytes + sizeof(struct displayid_block); 5062 switch (block->tag) { 5063 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5064 num_modes += 5065 add_displayid_detailed_1_modes(data, block); 5066 break; 5067 } 5068 } 5069 return num_modes; 5070 } 5071 5072 static bool 5073 mode_in_hsync_range(const struct drm_display_mode *mode, 5074 struct edid *edid, u8 *t) 5075 { 5076 int hsync, hmin, hmax; 5077 5078 hmin = t[7]; 5079 if (edid->revision >= 4) 5080 hmin += ((t[4] & 0x04) ? 255 : 0); 5081 hmax = t[8]; 5082 if (edid->revision >= 4) 5083 hmax += ((t[4] & 0x08) ? 255 : 0); 5084 hsync = drm_mode_hsync(mode); 5085 5086 return (hsync <= hmax && hsync >= hmin); 5087 } 5088 5089 static bool 5090 mode_in_vsync_range(const struct drm_display_mode *mode, 5091 struct edid *edid, u8 *t) 5092 { 5093 int vsync, vmin, vmax; 5094 5095 vmin = t[5]; 5096 if (edid->revision >= 4) 5097 vmin += ((t[4] & 0x01) ? 255 : 0); 5098 vmax = t[6]; 5099 if (edid->revision >= 4) 5100 vmax += ((t[4] & 0x02) ? 255 : 0); 5101 vsync = drm_get_vrefresh(mode); 5102 5103 return (vsync <= vmax && vsync >= vmin); 5104 } 5105 5106 static u32 5107 range_pixel_clock(struct edid *edid, u8 *t) 5108 { 5109 /* unspecified */ 5110 if (t[9] == 0 || t[9] == 255) 5111 return 0; 5112 5113 /* 1.4 with CVT support gives us real precision, yay */ 5114 if (edid->revision >= 4 && t[10] == 0x04) 5115 return (t[9] * 10000) - ((t[12] >> 2) * 250); 5116 5117 /* 1.3 is pathetic, so fuzz up a bit */ 5118 return t[9] * 10000 + 5001; 5119 } 5120 5121 static bool 5122 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 5123 struct detailed_timing *timing) 5124 { 5125 u32 max_clock; 5126 u8 *t = (u8 *)timing; 5127 5128 if (!mode_in_hsync_range(mode, edid, t)) 5129 return false; 5130 5131 if (!mode_in_vsync_range(mode, edid, t)) 5132 return false; 5133 5134 max_clock = range_pixel_clock(edid, t); 5135 if (max_clock) 5136 if (mode->clock > max_clock) 5137 return false; 5138 5139 /* 1.4 max horizontal check */ 5140 if (edid->revision >= 4 && t[10] == 0x04) 5141 if (t[13] && mode->hdisplay > 8 * 5142 (t[13] + (256 * (t[12] & 0x3)))) 5143 return false; 5144 5145 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 5146 return false; 5147 5148 return true; 5149 } 5150 5151 static bool valid_inferred_mode(struct hdmi_edid_data *data, 5152 const struct drm_display_mode *mode) 5153 { 5154 const struct drm_display_mode *m; 5155 bool ok = false; 5156 int i; 5157 5158 for (i = 0; i < data->modes; i++) { 5159 m = &data->mode_buf[i]; 5160 if (mode->hdisplay == m->hdisplay && 5161 mode->vdisplay == m->vdisplay && 5162 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 5163 return false; /* duplicated */ 5164 if (mode->hdisplay <= m->hdisplay && 5165 mode->vdisplay <= m->vdisplay) 5166 ok = true; 5167 } 5168 return ok; 5169 } 5170 5171 static int 5172 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5173 struct detailed_timing *timing) 5174 { 5175 int i, modes = 0; 5176 5177 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 5178 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 5179 valid_inferred_mode(data, drm_dmt_modes + i)) { 5180 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 5181 modes++; 5182 } 5183 } 5184 5185 return modes; 5186 } 5187 5188 /* fix up 1366x768 mode from 1368x768; 5189 * GFT/CVT can't express 1366 width which isn't dividable by 8 5190 */ 5191 static void fixup_mode_1366x768(struct drm_display_mode *mode) 5192 { 5193 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 5194 mode->hdisplay = 1366; 5195 mode->hsync_start--; 5196 mode->hsync_end--; 5197 } 5198 } 5199 5200 static int 5201 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5202 struct detailed_timing *timing) 5203 { 5204 int i, modes = 0; 5205 struct drm_display_mode *newmode; 5206 5207 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5208 const struct minimode *m = &extra_modes[i]; 5209 5210 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 5211 if (!newmode) 5212 return modes; 5213 5214 fixup_mode_1366x768(newmode); 5215 if (!mode_in_range(newmode, edid, timing) || 5216 !valid_inferred_mode(data, newmode)) { 5217 drm_mode_destroy(newmode); 5218 continue; 5219 } 5220 5221 drm_add_hdmi_modes(data, newmode); 5222 modes++; 5223 drm_mode_destroy(newmode); 5224 } 5225 5226 return modes; 5227 } 5228 5229 static int 5230 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5231 struct detailed_timing *timing) 5232 { 5233 int i, modes = 0; 5234 struct drm_display_mode *newmode; 5235 bool rb = drm_monitor_supports_rb(edid); 5236 5237 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5238 const struct minimode *m = &extra_modes[i]; 5239 5240 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 5241 if (!newmode) 5242 return modes; 5243 5244 fixup_mode_1366x768(newmode); 5245 if (!mode_in_range(newmode, edid, timing) || 5246 !valid_inferred_mode(data, newmode)) { 5247 drm_mode_destroy(newmode); 5248 continue; 5249 } 5250 5251 drm_add_hdmi_modes(data, newmode); 5252 modes++; 5253 drm_mode_destroy(newmode); 5254 } 5255 5256 return modes; 5257 } 5258 5259 static void 5260 do_inferred_modes(struct detailed_timing *timing, void *c) 5261 { 5262 struct detailed_mode_closure *closure = c; 5263 struct detailed_non_pixel *data = &timing->data.other_data; 5264 struct detailed_data_monitor_range *range = &data->data.range; 5265 5266 if (data->type != EDID_DETAIL_MONITOR_RANGE) 5267 return; 5268 5269 closure->modes += drm_dmt_modes_for_range(closure->data, 5270 closure->edid, 5271 timing); 5272 5273 if (!version_greater(closure->edid, 1, 1)) 5274 return; /* GTF not defined yet */ 5275 5276 switch (range->flags) { 5277 case 0x02: /* secondary gtf, XXX could do more */ 5278 case 0x00: /* default gtf */ 5279 closure->modes += drm_gtf_modes_for_range(closure->data, 5280 closure->edid, 5281 timing); 5282 break; 5283 case 0x04: /* cvt, only in 1.4+ */ 5284 if (!version_greater(closure->edid, 1, 3)) 5285 break; 5286 5287 closure->modes += drm_cvt_modes_for_range(closure->data, 5288 closure->edid, 5289 timing); 5290 break; 5291 case 0x01: /* just the ranges, no formula */ 5292 default: 5293 break; 5294 } 5295 } 5296 5297 static int 5298 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 5299 { 5300 struct detailed_mode_closure closure = { 5301 .data = data, 5302 .edid = edid, 5303 }; 5304 5305 if (version_greater(edid, 1, 0)) 5306 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 5307 &closure); 5308 5309 return closure.modes; 5310 } 5311 5312 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 5313 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 5314 5315 /** 5316 * edid_fixup_preferred - set preferred modes based on quirk list 5317 * @data: the structure that save parsed hdmi edid data 5318 * @quirks: quirks list 5319 * 5320 * Walk the mode list, clearing the preferred status 5321 * on existing modes and setting it anew for the right mode ala @quirks. 5322 */ 5323 static void edid_fixup_preferred(struct hdmi_edid_data *data, 5324 u32 quirks) 5325 { 5326 struct drm_display_mode *cur_mode, *preferred_mode; 5327 int i, target_refresh = 0; 5328 int num = data->modes; 5329 int cur_vrefresh, preferred_vrefresh; 5330 5331 if (!num) 5332 return; 5333 5334 preferred_mode = data->preferred_mode; 5335 5336 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 5337 target_refresh = 60; 5338 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 5339 target_refresh = 75; 5340 5341 for (i = 0; i < num; i++) { 5342 cur_mode = &data->mode_buf[i]; 5343 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 5344 5345 if (cur_mode == preferred_mode) 5346 continue; 5347 5348 /* Largest mode is preferred */ 5349 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 5350 preferred_mode = cur_mode; 5351 5352 cur_vrefresh = cur_mode->vrefresh ? 5353 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 5354 preferred_vrefresh = preferred_mode->vrefresh ? 5355 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 5356 /* At a given size, try to get closest to target refresh */ 5357 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 5358 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 5359 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 5360 preferred_mode = cur_mode; 5361 } 5362 } 5363 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 5364 data->preferred_mode = preferred_mode; 5365 } 5366 5367 static const u8 edid_header[] = { 5368 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 5369 }; 5370 5371 /** 5372 * drm_edid_header_is_valid - sanity check the header of the base EDID block 5373 * @raw_edid: pointer to raw base EDID block 5374 * 5375 * Sanity check the header of the base EDID block. 5376 * 5377 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 5378 */ 5379 static int drm_edid_header_is_valid(const u8 *raw_edid) 5380 { 5381 int i, score = 0; 5382 5383 for (i = 0; i < sizeof(edid_header); i++) 5384 if (raw_edid[i] == edid_header[i]) 5385 score++; 5386 5387 return score; 5388 } 5389 5390 static int drm_edid_block_checksum(const u8 *raw_edid) 5391 { 5392 int i; 5393 u8 csum = 0; 5394 5395 for (i = 0; i < EDID_SIZE; i++) 5396 csum += raw_edid[i]; 5397 5398 return csum; 5399 } 5400 5401 static bool drm_edid_is_zero(const u8 *in_edid, int length) 5402 { 5403 if (memchr_inv(in_edid, 0, length)) 5404 return false; 5405 5406 return true; 5407 } 5408 5409 /** 5410 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 5411 * @raw_edid: pointer to raw EDID block 5412 * @block: type of block to validate (0 for base, extension otherwise) 5413 * @print_bad_edid: if true, dump bad EDID blocks to the console 5414 * @edid_corrupt: if true, the header or checksum is invalid 5415 * 5416 * Validate a base or extension EDID block and optionally dump bad blocks to 5417 * the console. 5418 * 5419 * Return: True if the block is valid, false otherwise. 5420 */ 5421 static 5422 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 5423 bool *edid_corrupt) 5424 { 5425 u8 csum; 5426 int edid_fixup = 6; 5427 struct edid *edid = (struct edid *)raw_edid; 5428 5429 if ((!raw_edid)) 5430 return false; 5431 5432 if (block == 0) { 5433 int score = drm_edid_header_is_valid(raw_edid); 5434 5435 if (score == 8) { 5436 if (edid_corrupt) 5437 *edid_corrupt = false; 5438 } else if (score >= edid_fixup) { 5439 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 5440 * The corrupt flag needs to be set here otherwise, the 5441 * fix-up code here will correct the problem, the 5442 * checksum is correct and the test fails 5443 */ 5444 if (edid_corrupt) 5445 *edid_corrupt = true; 5446 debug("Fixing header, your hardware may be failing\n"); 5447 memcpy(raw_edid, edid_header, sizeof(edid_header)); 5448 } else { 5449 if (edid_corrupt) 5450 *edid_corrupt = true; 5451 goto bad; 5452 } 5453 } 5454 5455 csum = drm_edid_block_checksum(raw_edid); 5456 if (csum) { 5457 if (print_bad_edid) { 5458 debug("EDID checksum is invalid, remainder is %d\n", 5459 csum); 5460 } 5461 5462 if (edid_corrupt) 5463 *edid_corrupt = true; 5464 5465 /* allow CEA to slide through, switches mangle this */ 5466 if (raw_edid[0] != 0x02) 5467 goto bad; 5468 } 5469 5470 /* per-block-type checks */ 5471 switch (raw_edid[0]) { 5472 case 0: /* base */ 5473 if (edid->version != 1) { 5474 debug("EDID has major version %d, instead of 1\n", 5475 edid->version); 5476 goto bad; 5477 } 5478 5479 if (edid->revision > 4) 5480 debug("minor > 4, assuming backward compatibility\n"); 5481 break; 5482 5483 default: 5484 break; 5485 } 5486 5487 return true; 5488 5489 bad: 5490 if (print_bad_edid) { 5491 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 5492 debug("EDID block is all zeroes\n"); 5493 } else { 5494 debug("Raw EDID:\n"); 5495 print_hex_dump("", DUMP_PREFIX_NONE, 16, 1, 5496 raw_edid, EDID_SIZE, false); 5497 } 5498 } 5499 return false; 5500 } 5501 5502 /** 5503 * drm_edid_is_valid - sanity check EDID data 5504 * @edid: EDID data 5505 * 5506 * Sanity-check an entire EDID record (including extensions) 5507 * 5508 * Return: True if the EDID data is valid, false otherwise. 5509 */ 5510 static bool drm_edid_is_valid(struct edid *edid) 5511 { 5512 int i; 5513 u8 *raw = (u8 *)edid; 5514 5515 if (!edid) 5516 return false; 5517 5518 for (i = 0; i <= edid->extensions; i++) 5519 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 5520 return false; 5521 5522 return true; 5523 } 5524 5525 /** 5526 * drm_add_edid_modes - add modes from EDID data, if available 5527 * @data: data we're probing 5528 * @edid: EDID data 5529 * 5530 * Add the specified modes to the data's mode list. 5531 * 5532 * Return: The number of modes added or 0 if we couldn't find any. 5533 */ 5534 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 5535 { 5536 int num_modes = 0; 5537 u32 quirks; 5538 struct edid *edid = (struct edid *)raw_edid; 5539 5540 if (!edid) { 5541 debug("no edid\n"); 5542 return 0; 5543 } 5544 5545 if (!drm_edid_is_valid(edid)) { 5546 debug("EDID invalid\n"); 5547 return 0; 5548 } 5549 5550 if (!data->mode_buf) { 5551 debug("mode buff is null\n"); 5552 return 0; 5553 } 5554 5555 quirks = edid_get_quirks(edid); 5556 /* 5557 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5558 * To avoid multiple parsing of same block, lets parse that map 5559 * from sink info, before parsing CEA modes. 5560 */ 5561 drm_add_display_info(data, edid); 5562 5563 /* 5564 * EDID spec says modes should be preferred in this order: 5565 * - preferred detailed mode 5566 * - other detailed modes from base block 5567 * - detailed modes from extension blocks 5568 * - CVT 3-byte code modes 5569 * - standard timing codes 5570 * - established timing codes 5571 * - modes inferred from GTF or CVT range information 5572 * 5573 * We get this pretty much right. 5574 * 5575 * XXX order for additional mode types in extension blocks? 5576 */ 5577 num_modes += add_detailed_modes(data, edid, quirks); 5578 num_modes += add_cvt_modes(data, edid); 5579 num_modes += add_standard_modes(data, edid); 5580 num_modes += add_established_modes(data, edid); 5581 num_modes += add_cea_modes(data, edid); 5582 num_modes += add_alternate_cea_modes(data, edid); 5583 num_modes += add_displayid_detailed_modes(data, edid); 5584 5585 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5586 num_modes += add_inferred_modes(data, edid); 5587 5588 if (num_modes > 0) 5589 data->preferred_mode = &data->mode_buf[0]; 5590 5591 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5592 edid_fixup_preferred(data, quirks); 5593 5594 if (quirks & EDID_QUIRK_FORCE_6BPC) 5595 data->display_info.bpc = 6; 5596 5597 if (quirks & EDID_QUIRK_FORCE_8BPC) 5598 data->display_info.bpc = 8; 5599 5600 if (quirks & EDID_QUIRK_FORCE_10BPC) 5601 data->display_info.bpc = 10; 5602 5603 if (quirks & EDID_QUIRK_FORCE_12BPC) 5604 data->display_info.bpc = 12; 5605 5606 return num_modes; 5607 } 5608 5609 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5610 { 5611 u8 vic; 5612 5613 if (!to_match->clock) { 5614 printf("can't find to match\n"); 5615 return 0; 5616 } 5617 5618 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 5619 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 5620 unsigned int clock1, clock2; 5621 5622 /* Check both 60Hz and 59.94Hz */ 5623 clock1 = cea_mode->clock; 5624 clock2 = cea_mode_alternate_clock(cea_mode); 5625 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5626 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5627 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5628 return vic; 5629 } 5630 5631 return 0; 5632 } 5633 5634 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5635 { 5636 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 5637 5638 if (mode) 5639 return mode->picture_aspect_ratio; 5640 5641 return HDMI_PICTURE_ASPECT_NONE; 5642 } 5643 5644 int 5645 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5646 struct drm_display_mode *mode, 5647 bool is_hdmi2_sink) 5648 { 5649 int err; 5650 5651 if (!frame || !mode) 5652 return -EINVAL; 5653 5654 err = hdmi_avi_infoframe_init(frame); 5655 if (err < 0) 5656 return err; 5657 5658 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5659 frame->pixel_repeat = 1; 5660 5661 frame->video_code = drm_match_cea_mode(mode); 5662 5663 /* 5664 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5665 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5666 * have to make sure we dont break HDMI 1.4 sinks. 5667 */ 5668 if (!is_hdmi2_sink && frame->video_code > 64) 5669 frame->video_code = 0; 5670 5671 /* 5672 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5673 * we should send its VIC in vendor infoframes, else send the 5674 * VIC in AVI infoframes. Lets check if this mode is present in 5675 * HDMI 1.4b 4K modes 5676 */ 5677 if (frame->video_code) { 5678 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5679 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5680 5681 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5682 frame->video_code = 0; 5683 } 5684 5685 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5686 5687 /* 5688 * Populate picture aspect ratio from either 5689 * user input (if specified) or from the CEA mode list. 5690 */ 5691 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5692 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5693 frame->picture_aspect = mode->picture_aspect_ratio; 5694 else if (frame->video_code > 0) 5695 frame->picture_aspect = drm_get_cea_aspect_ratio( 5696 frame->video_code); 5697 5698 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5699 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5700 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5701 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5702 5703 return 0; 5704 } 5705 5706 /** 5707 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5708 * @frame: HDMI vendor infoframe 5709 * 5710 * Returns 0 on success or a negative error code on failure. 5711 */ 5712 int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5713 { 5714 memset(frame, 0, sizeof(*frame)); 5715 5716 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5717 frame->version = 1; 5718 5719 frame->oui = HDMI_IEEE_OUI; 5720 5721 /* 5722 * 0 is a valid value for s3d_struct, so we use a special "not set" 5723 * value 5724 */ 5725 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5726 5727 return 0; 5728 } 5729 5730 /** 5731 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5732 * quantization range information 5733 * @frame: HDMI AVI infoframe 5734 * @rgb_quant_range: RGB quantization range (Q) 5735 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 5736 */ 5737 void 5738 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5739 struct drm_display_mode *mode, 5740 enum hdmi_quantization_range rgb_quant_range, 5741 bool rgb_quant_range_selectable) 5742 { 5743 /* 5744 * CEA-861: 5745 * "A Source shall not send a non-zero Q value that does not correspond 5746 * to the default RGB Quantization Range for the transmitted Picture 5747 * unless the Sink indicates support for the Q bit in a Video 5748 * Capabilities Data Block." 5749 * 5750 * HDMI 2.0 recommends sending non-zero Q when it does match the 5751 * default RGB quantization range for the mode, even when QS=0. 5752 */ 5753 if (rgb_quant_range_selectable || 5754 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5755 frame->quantization_range = rgb_quant_range; 5756 else 5757 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5758 5759 /* 5760 * CEA-861-F: 5761 * "When transmitting any RGB colorimetry, the Source should set the 5762 * YQ-field to match the RGB Quantization Range being transmitted 5763 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5764 * set YQ=1) and the Sink shall ignore the YQ-field." 5765 */ 5766 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5767 frame->ycc_quantization_range = 5768 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5769 else 5770 frame->ycc_quantization_range = 5771 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5772 } 5773 5774 static enum hdmi_3d_structure 5775 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5776 { 5777 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5778 5779 switch (layout) { 5780 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5781 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5782 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5783 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5784 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5785 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5786 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5787 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5788 case DRM_MODE_FLAG_3D_L_DEPTH: 5789 return HDMI_3D_STRUCTURE_L_DEPTH; 5790 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5791 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5792 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5793 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5794 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5795 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5796 default: 5797 return HDMI_3D_STRUCTURE_INVALID; 5798 } 5799 } 5800 5801 int 5802 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5803 struct drm_display_mode *mode) 5804 { 5805 int err; 5806 u32 s3d_flags; 5807 u8 vic; 5808 5809 if (!frame || !mode) 5810 return -EINVAL; 5811 5812 vic = drm_match_hdmi_mode(mode); 5813 5814 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5815 5816 if (!vic && !s3d_flags) 5817 return -EINVAL; 5818 5819 if (vic && s3d_flags) 5820 return -EINVAL; 5821 5822 err = hdmi_vendor_infoframe_init(frame); 5823 if (err < 0) 5824 return err; 5825 5826 if (vic) 5827 frame->vic = vic; 5828 else 5829 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5830 5831 return 0; 5832 } 5833 5834 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5835 { 5836 u8 csum = 0; 5837 size_t i; 5838 5839 /* compute checksum */ 5840 for (i = 0; i < size; i++) 5841 csum += ptr[i]; 5842 5843 return 256 - csum; 5844 } 5845 5846 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5847 { 5848 u8 *ptr = buffer; 5849 5850 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5851 } 5852 5853 /** 5854 * hdmi_avi_infoframe_init() - initialize an HDMI AVI infoframe 5855 * @frame: HDMI AVI infoframe 5856 * 5857 * Returns 0 on success or a negative error code on failure. 5858 */ 5859 int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5860 { 5861 memset(frame, 0, sizeof(*frame)); 5862 5863 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5864 frame->version = 2; 5865 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5866 5867 return 0; 5868 } 5869 EXPORT_SYMBOL(hdmi_avi_infoframe_init); 5870 5871 /** 5872 * hdmi_avi_infoframe_pack() - write HDMI AVI infoframe to binary buffer 5873 * @frame: HDMI AVI infoframe 5874 * @buffer: destination buffer 5875 * @size: size of buffer 5876 * 5877 * Packs the information contained in the @frame structure into a binary 5878 * representation that can be written into the corresponding controller 5879 * registers. Also computes the checksum as required by section 5.3.5 of 5880 * the HDMI 1.4 specification. 5881 * 5882 * Returns the number of bytes packed into the binary buffer or a negative 5883 * error code on failure. 5884 */ 5885 ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, 5886 size_t size) 5887 { 5888 u8 *ptr = buffer; 5889 size_t length; 5890 5891 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5892 5893 if (size < length) 5894 return -ENOSPC; 5895 5896 memset(buffer, 0, size); 5897 5898 ptr[0] = frame->type; 5899 ptr[1] = frame->version; 5900 ptr[2] = frame->length; 5901 ptr[3] = 0; /* checksum */ 5902 5903 /* start infoframe payload */ 5904 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5905 5906 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 5907 5908 /* 5909 * Data byte 1, bit 4 has to be set if we provide the active format 5910 * aspect ratio 5911 */ 5912 if (frame->active_aspect & 0xf) 5913 ptr[0] |= BIT(4); 5914 5915 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 5916 if (frame->top_bar || frame->bottom_bar) 5917 ptr[0] |= BIT(3); 5918 5919 if (frame->left_bar || frame->right_bar) 5920 ptr[0] |= BIT(2); 5921 5922 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 5923 ((frame->picture_aspect & 0x3) << 4) | 5924 (frame->active_aspect & 0xf); 5925 5926 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 5927 ((frame->quantization_range & 0x3) << 2) | 5928 (frame->nups & 0x3); 5929 5930 if (frame->itc) 5931 ptr[2] |= BIT(7); 5932 5933 ptr[3] = frame->video_code & 0x7f; 5934 5935 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 5936 ((frame->content_type & 0x3) << 4) | 5937 (frame->pixel_repeat & 0xf); 5938 5939 ptr[5] = frame->top_bar & 0xff; 5940 ptr[6] = (frame->top_bar >> 8) & 0xff; 5941 ptr[7] = frame->bottom_bar & 0xff; 5942 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 5943 ptr[9] = frame->left_bar & 0xff; 5944 ptr[10] = (frame->left_bar >> 8) & 0xff; 5945 ptr[11] = frame->right_bar & 0xff; 5946 ptr[12] = (frame->right_bar >> 8) & 0xff; 5947 5948 hdmi_infoframe_set_checksum(buffer, length); 5949 5950 return length; 5951 } 5952 EXPORT_SYMBOL(hdmi_avi_infoframe_pack); 5953 5954 static int hdmi_avi_infoframe_check_only(const struct hdmi_avi_infoframe *frame) 5955 { 5956 if (frame->type != HDMI_INFOFRAME_TYPE_AVI || 5957 frame->version != 2 || 5958 frame->length != HDMI_AVI_INFOFRAME_SIZE) 5959 return -EINVAL; 5960 5961 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5962 return -EINVAL; 5963 5964 return 0; 5965 } 5966 5967 /** 5968 * hdmi_avi_infoframe_check() - check a HDMI AVI infoframe 5969 * @frame: HDMI AVI infoframe 5970 * 5971 * Validates that the infoframe is consistent and updates derived fields 5972 * (eg. length) based on other fields. 5973 * 5974 * Returns 0 on success or a negative error code on failure. 5975 */ 5976 int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame) 5977 { 5978 return hdmi_avi_infoframe_check_only(frame); 5979 } 5980 EXPORT_SYMBOL(hdmi_avi_infoframe_check); 5981 5982 /** 5983 * hdmi_avi_infoframe_pack_only() - write HDMI AVI infoframe to binary buffer 5984 * @frame: HDMI AVI infoframe 5985 * @buffer: destination buffer 5986 * @size: size of buffer 5987 * 5988 * Packs the information contained in the @frame structure into a binary 5989 * representation that can be written into the corresponding controller 5990 * registers. Also computes the checksum as required by section 5.3.5 of 5991 * the HDMI 1.4 specification. 5992 * 5993 * Returns the number of bytes packed into the binary buffer or a negative 5994 * error code on failure. 5995 */ 5996 ssize_t hdmi_avi_infoframe_pack_only(const struct hdmi_avi_infoframe *frame, 5997 void *buffer, size_t size) 5998 { 5999 u8 *ptr = buffer; 6000 size_t length; 6001 int ret; 6002 6003 ret = hdmi_avi_infoframe_check_only(frame); 6004 if (ret) 6005 return ret; 6006 6007 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6008 6009 if (size < length) 6010 return -ENOSPC; 6011 6012 memset(buffer, 0, size); 6013 6014 ptr[0] = frame->type; 6015 ptr[1] = frame->version; 6016 ptr[2] = frame->length; 6017 ptr[3] = 0; /* checksum */ 6018 6019 /* start infoframe payload */ 6020 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6021 6022 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 6023 6024 /* 6025 * Data byte 1, bit 4 has to be set if we provide the active format 6026 * aspect ratio 6027 */ 6028 if (frame->active_aspect & 0xf) 6029 ptr[0] |= BIT(4); 6030 6031 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 6032 if (frame->top_bar || frame->bottom_bar) 6033 ptr[0] |= BIT(3); 6034 6035 if (frame->left_bar || frame->right_bar) 6036 ptr[0] |= BIT(2); 6037 6038 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 6039 ((frame->picture_aspect & 0x3) << 4) | 6040 (frame->active_aspect & 0xf); 6041 6042 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 6043 ((frame->quantization_range & 0x3) << 2) | 6044 (frame->nups & 0x3); 6045 6046 if (frame->itc) 6047 ptr[2] |= BIT(7); 6048 6049 ptr[3] = frame->video_code & 0xff; 6050 6051 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 6052 ((frame->content_type & 0x3) << 4) | 6053 (frame->pixel_repeat & 0xf); 6054 6055 ptr[5] = frame->top_bar & 0xff; 6056 ptr[6] = (frame->top_bar >> 8) & 0xff; 6057 ptr[7] = frame->bottom_bar & 0xff; 6058 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 6059 ptr[9] = frame->left_bar & 0xff; 6060 ptr[10] = (frame->left_bar >> 8) & 0xff; 6061 ptr[11] = frame->right_bar & 0xff; 6062 ptr[12] = (frame->right_bar >> 8) & 0xff; 6063 6064 hdmi_infoframe_set_checksum(buffer, length); 6065 6066 return length; 6067 } 6068 EXPORT_SYMBOL(hdmi_avi_infoframe_pack_only); 6069 6070 /** 6071 * hdmi_spd_infoframe_init() - initialize an HDMI SPD infoframe 6072 * @frame: HDMI SPD infoframe 6073 * @vendor: vendor string 6074 * @product: product string 6075 * 6076 * Returns 0 on success or a negative error code on failure. 6077 */ 6078 int hdmi_spd_infoframe_init(struct hdmi_spd_infoframe *frame, 6079 const char *vendor, const char *product) 6080 { 6081 memset(frame, 0, sizeof(*frame)); 6082 6083 frame->type = HDMI_INFOFRAME_TYPE_SPD; 6084 frame->version = 1; 6085 frame->length = HDMI_SPD_INFOFRAME_SIZE; 6086 6087 strncpy(frame->vendor, vendor, sizeof(frame->vendor)); 6088 strncpy(frame->product, product, sizeof(frame->product)); 6089 6090 return 0; 6091 } 6092 EXPORT_SYMBOL(hdmi_spd_infoframe_init); 6093 6094 /** 6095 * hdmi_spd_infoframe_pack() - write HDMI SPD infoframe to binary buffer 6096 * @frame: HDMI SPD infoframe 6097 * @buffer: destination buffer 6098 * @size: size of buffer 6099 * 6100 * Packs the information contained in the @frame structure into a binary 6101 * representation that can be written into the corresponding controller 6102 * registers. Also computes the checksum as required by section 5.3.5 of 6103 * the HDMI 1.4 specification. 6104 * 6105 * Returns the number of bytes packed into the binary buffer or a negative 6106 * error code on failure. 6107 */ 6108 ssize_t hdmi_spd_infoframe_pack(struct hdmi_spd_infoframe *frame, void *buffer, 6109 size_t size) 6110 { 6111 u8 *ptr = buffer; 6112 size_t length; 6113 6114 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6115 6116 if (size < length) 6117 return -ENOSPC; 6118 6119 memset(buffer, 0, size); 6120 6121 ptr[0] = frame->type; 6122 ptr[1] = frame->version; 6123 ptr[2] = frame->length; 6124 ptr[3] = 0; /* checksum */ 6125 6126 /* start infoframe payload */ 6127 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6128 6129 memcpy(ptr, frame->vendor, sizeof(frame->vendor)); 6130 memcpy(ptr + 8, frame->product, sizeof(frame->product)); 6131 6132 ptr[24] = frame->sdi; 6133 6134 hdmi_infoframe_set_checksum(buffer, length); 6135 6136 return length; 6137 } 6138 EXPORT_SYMBOL(hdmi_spd_infoframe_pack); 6139 6140 /** 6141 * hdmi_audio_infoframe_init() - initialize an HDMI audio infoframe 6142 * @frame: HDMI audio infoframe 6143 * 6144 * Returns 0 on success or a negative error code on failure. 6145 */ 6146 int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame) 6147 { 6148 memset(frame, 0, sizeof(*frame)); 6149 6150 frame->type = HDMI_INFOFRAME_TYPE_AUDIO; 6151 frame->version = 1; 6152 frame->length = HDMI_AUDIO_INFOFRAME_SIZE; 6153 6154 return 0; 6155 } 6156 6157 /** 6158 * hdmi_audio_infoframe_pack() - write HDMI audio infoframe to binary buffer 6159 * @frame: HDMI audio infoframe 6160 * @buffer: destination buffer 6161 * @size: size of buffer 6162 * 6163 * Packs the information contained in the @frame structure into a binary 6164 * representation that can be written into the corresponding controller 6165 * registers. Also computes the checksum as required by section 5.3.5 of 6166 * the HDMI 1.4 specification. 6167 * 6168 * Returns the number of bytes packed into the binary buffer or a negative 6169 * error code on failure. 6170 */ 6171 ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame, 6172 void *buffer, size_t size) 6173 { 6174 unsigned char channels; 6175 char *ptr = buffer; 6176 size_t length; 6177 6178 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6179 6180 if (size < length) 6181 return -ENOSPC; 6182 6183 memset(buffer, 0, size); 6184 6185 if (frame->channels >= 2) 6186 channels = frame->channels - 1; 6187 else 6188 channels = 0; 6189 6190 ptr[0] = frame->type; 6191 ptr[1] = frame->version; 6192 ptr[2] = frame->length; 6193 ptr[3] = 0; /* checksum */ 6194 6195 /* start infoframe payload */ 6196 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6197 6198 ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7); 6199 ptr[1] = ((frame->sample_frequency & 0x7) << 2) | 6200 (frame->sample_size & 0x3); 6201 ptr[2] = frame->coding_type_ext & 0x1f; 6202 ptr[3] = frame->channel_allocation; 6203 ptr[4] = (frame->level_shift_value & 0xf) << 3; 6204 6205 if (frame->downmix_inhibit) 6206 ptr[4] |= BIT(7); 6207 6208 hdmi_infoframe_set_checksum(buffer, length); 6209 6210 return length; 6211 } 6212 6213 /** 6214 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 6215 * @frame: HDMI infoframe 6216 * @buffer: destination buffer 6217 * @size: size of buffer 6218 * 6219 * Packs the information contained in the @frame structure into a binary 6220 * representation that can be written into the corresponding controller 6221 * registers. Also computes the checksum as required by section 5.3.5 of 6222 * the HDMI 1.4 specification. 6223 * 6224 * Returns the number of bytes packed into the binary buffer or a negative 6225 * error code on failure. 6226 */ 6227 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 6228 void *buffer, size_t size) 6229 { 6230 char *ptr = buffer; 6231 size_t length; 6232 6233 /* empty info frame */ 6234 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 6235 return -EINVAL; 6236 6237 /* only one of those can be supplied */ 6238 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 6239 return -EINVAL; 6240 6241 /* for side by side (half) we also need to provide 3D_Ext_Data */ 6242 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6243 frame->length = 6; 6244 else 6245 frame->length = 5; 6246 6247 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6248 6249 if (size < length) 6250 return -ENOSPC; 6251 6252 memset(buffer, 0, size); 6253 6254 ptr[0] = frame->type; 6255 ptr[1] = frame->version; 6256 ptr[2] = frame->length; 6257 ptr[3] = 0; /* checksum */ 6258 6259 /* HDMI OUI */ 6260 ptr[4] = 0x03; 6261 ptr[5] = 0x0c; 6262 ptr[6] = 0x00; 6263 6264 if (frame->vic) { 6265 ptr[7] = 0x1 << 5; /* video format */ 6266 ptr[8] = frame->vic; 6267 } else { 6268 ptr[7] = 0x2 << 5; /* video format */ 6269 ptr[8] = (frame->s3d_struct & 0xf) << 4; 6270 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6271 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 6272 } 6273 6274 hdmi_infoframe_set_checksum(buffer, length); 6275 6276 return length; 6277 } 6278 6279 /** 6280 * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and 6281 * mastering infoframe 6282 * @frame: HDMI DRM infoframe 6283 * 6284 * Returns 0 on success or a negative error code on failure. 6285 */ 6286 int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame) 6287 { 6288 memset(frame, 0, sizeof(*frame)); 6289 6290 frame->type = HDMI_INFOFRAME_TYPE_DRM; 6291 frame->version = 1; 6292 6293 return 0; 6294 } 6295 6296 /** 6297 * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer 6298 * @frame: HDMI DRM infoframe 6299 * @buffer: destination buffer 6300 * @size: size of buffer 6301 * 6302 * Packs the information contained in the @frame structure into a binary 6303 * representation that can be written into the corresponding controller 6304 * registers. Also computes the checksum as required by section 5.3.5 of 6305 * the HDMI 1.4 specification. 6306 * 6307 * Returns the number of bytes packed into the binary buffer or a negative 6308 * error code on failure. 6309 */ 6310 ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer, 6311 size_t size) 6312 { 6313 u8 *ptr = buffer; 6314 size_t length; 6315 6316 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6317 6318 if (size < length) 6319 return -ENOSPC; 6320 6321 memset(buffer, 0, size); 6322 6323 ptr[0] = frame->type; 6324 ptr[1] = frame->version; 6325 ptr[2] = frame->length; 6326 ptr[3] = 0; /* checksum */ 6327 6328 /* start infoframe payload */ 6329 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6330 6331 ptr[0] = frame->eotf; 6332 ptr[1] = frame->metadata_type; 6333 6334 ptr[2] = frame->display_primaries_x[0] & 0xff; 6335 ptr[3] = frame->display_primaries_x[0] >> 8; 6336 6337 ptr[4] = frame->display_primaries_x[1] & 0xff; 6338 ptr[5] = frame->display_primaries_x[1] >> 8; 6339 6340 ptr[6] = frame->display_primaries_x[2] & 0xff; 6341 ptr[7] = frame->display_primaries_x[2] >> 8; 6342 6343 ptr[9] = frame->display_primaries_y[0] & 0xff; 6344 ptr[10] = frame->display_primaries_y[0] >> 8; 6345 6346 ptr[11] = frame->display_primaries_y[1] & 0xff; 6347 ptr[12] = frame->display_primaries_y[1] >> 8; 6348 6349 ptr[13] = frame->display_primaries_y[2] & 0xff; 6350 ptr[14] = frame->display_primaries_y[2] >> 8; 6351 6352 ptr[15] = frame->white_point_x & 0xff; 6353 ptr[16] = frame->white_point_x >> 8; 6354 6355 ptr[17] = frame->white_point_y & 0xff; 6356 ptr[18] = frame->white_point_y >> 8; 6357 6358 ptr[19] = frame->max_mastering_display_luminance & 0xff; 6359 ptr[20] = frame->max_mastering_display_luminance >> 8; 6360 6361 ptr[21] = frame->min_mastering_display_luminance & 0xff; 6362 ptr[22] = frame->min_mastering_display_luminance >> 8; 6363 6364 ptr[23] = frame->max_cll & 0xff; 6365 ptr[24] = frame->max_cll >> 8; 6366 6367 ptr[25] = frame->max_fall & 0xff; 6368 ptr[26] = frame->max_fall >> 8; 6369 6370 hdmi_infoframe_set_checksum(buffer, length); 6371 6372 return length; 6373 } 6374 6375 /* 6376 * hdmi_vendor_any_infoframe_pack() - write a vendor infoframe to binary buffer 6377 */ 6378 static ssize_t 6379 hdmi_vendor_any_infoframe_pack(union hdmi_vendor_any_infoframe *frame, 6380 void *buffer, size_t size) 6381 { 6382 /* we only know about HDMI vendor infoframes */ 6383 if (frame->any.oui != HDMI_IEEE_OUI) 6384 return -EINVAL; 6385 6386 return hdmi_vendor_infoframe_pack(&frame->hdmi, buffer, size); 6387 } 6388 6389 /** 6390 * hdmi_infoframe_pack() - write a HDMI infoframe to binary buffer 6391 * @frame: HDMI infoframe 6392 * @buffer: destination buffer 6393 * @size: size of buffer 6394 * 6395 * Packs the information contained in the @frame structure into a binary 6396 * representation that can be written into the corresponding controller 6397 * registers. Also computes the checksum as required by section 5.3.5 of 6398 * the HDMI 1.4 specification. 6399 * 6400 * Returns the number of bytes packed into the binary buffer or a negative 6401 * error code on failure. 6402 */ 6403 ssize_t 6404 hdmi_infoframe_pack(union hdmi_infoframe *frame, void *buffer, size_t size) 6405 { 6406 ssize_t length; 6407 6408 switch (frame->any.type) { 6409 case HDMI_INFOFRAME_TYPE_AVI: 6410 length = hdmi_avi_infoframe_pack(&frame->avi, buffer, size); 6411 break; 6412 case HDMI_INFOFRAME_TYPE_DRM: 6413 length = hdmi_drm_infoframe_pack(&frame->drm, buffer, size); 6414 break; 6415 case HDMI_INFOFRAME_TYPE_SPD: 6416 length = hdmi_spd_infoframe_pack(&frame->spd, buffer, size); 6417 break; 6418 case HDMI_INFOFRAME_TYPE_AUDIO: 6419 length = hdmi_audio_infoframe_pack(&frame->audio, buffer, size); 6420 break; 6421 case HDMI_INFOFRAME_TYPE_VENDOR: 6422 length = hdmi_vendor_any_infoframe_pack(&frame->vendor, 6423 buffer, size); 6424 break; 6425 default: 6426 printf("Bad infoframe type %d\n", frame->any.type); 6427 length = -EINVAL; 6428 } 6429 6430 return length; 6431 } 6432 6433 /** 6434 * hdmi_avi_infoframe_unpack() - unpack binary buffer to a HDMI AVI infoframe 6435 * @buffer: source buffer 6436 * @frame: HDMI AVI infoframe 6437 * 6438 * Unpacks the information contained in binary @buffer into a structured 6439 * @frame of the HDMI Auxiliary Video (AVI) information frame. 6440 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6441 * specification. 6442 * 6443 * Returns 0 on success or a negative error code on failure. 6444 */ 6445 static int hdmi_avi_infoframe_unpack(struct hdmi_avi_infoframe *frame, 6446 void *buffer) 6447 { 6448 u8 *ptr = buffer; 6449 int ret; 6450 6451 if (ptr[0] != HDMI_INFOFRAME_TYPE_AVI || 6452 ptr[1] != 2 || 6453 ptr[2] != HDMI_AVI_INFOFRAME_SIZE) 6454 return -EINVAL; 6455 6456 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AVI)) != 0) 6457 return -EINVAL; 6458 6459 ret = hdmi_avi_infoframe_init(frame); 6460 if (ret) 6461 return ret; 6462 6463 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6464 6465 frame->colorspace = (ptr[0] >> 5) & 0x3; 6466 if (ptr[0] & 0x10) 6467 frame->active_aspect = ptr[1] & 0xf; 6468 if (ptr[0] & 0x8) { 6469 frame->top_bar = (ptr[5] << 8) + ptr[6]; 6470 frame->bottom_bar = (ptr[7] << 8) + ptr[8]; 6471 } 6472 if (ptr[0] & 0x4) { 6473 frame->left_bar = (ptr[9] << 8) + ptr[10]; 6474 frame->right_bar = (ptr[11] << 8) + ptr[12]; 6475 } 6476 frame->scan_mode = ptr[0] & 0x3; 6477 6478 frame->colorimetry = (ptr[1] >> 6) & 0x3; 6479 frame->picture_aspect = (ptr[1] >> 4) & 0x3; 6480 frame->active_aspect = ptr[1] & 0xf; 6481 6482 frame->itc = ptr[2] & 0x80 ? true : false; 6483 frame->extended_colorimetry = (ptr[2] >> 4) & 0x7; 6484 frame->quantization_range = (ptr[2] >> 2) & 0x3; 6485 frame->nups = ptr[2] & 0x3; 6486 6487 frame->video_code = ptr[3] & 0x7f; 6488 frame->ycc_quantization_range = (ptr[4] >> 6) & 0x3; 6489 frame->content_type = (ptr[4] >> 4) & 0x3; 6490 6491 frame->pixel_repeat = ptr[4] & 0xf; 6492 6493 return 0; 6494 } 6495 6496 /** 6497 * hdmi_spd_infoframe_unpack() - unpack binary buffer to a HDMI SPD infoframe 6498 * @buffer: source buffer 6499 * @frame: HDMI SPD infoframe 6500 * 6501 * Unpacks the information contained in binary @buffer into a structured 6502 * @frame of the HDMI Source Product Description (SPD) information frame. 6503 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6504 * specification. 6505 * 6506 * Returns 0 on success or a negative error code on failure. 6507 */ 6508 static int hdmi_spd_infoframe_unpack(struct hdmi_spd_infoframe *frame, 6509 void *buffer) 6510 { 6511 char *ptr = buffer; 6512 int ret; 6513 6514 if (ptr[0] != HDMI_INFOFRAME_TYPE_SPD || 6515 ptr[1] != 1 || 6516 ptr[2] != HDMI_SPD_INFOFRAME_SIZE) { 6517 return -EINVAL; 6518 } 6519 6520 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(SPD)) != 0) 6521 return -EINVAL; 6522 6523 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6524 6525 ret = hdmi_spd_infoframe_init(frame, ptr, ptr + 8); 6526 if (ret) 6527 return ret; 6528 6529 frame->sdi = ptr[24]; 6530 6531 return 0; 6532 } 6533 6534 /** 6535 * hdmi_audio_infoframe_unpack() - unpack binary buffer to a HDMI AUDIO infoframe 6536 * @buffer: source buffer 6537 * @frame: HDMI Audio infoframe 6538 * 6539 * Unpacks the information contained in binary @buffer into a structured 6540 * @frame of the HDMI Audio information frame. 6541 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6542 * specification. 6543 * 6544 * Returns 0 on success or a negative error code on failure. 6545 */ 6546 static int hdmi_audio_infoframe_unpack(struct hdmi_audio_infoframe *frame, 6547 void *buffer) 6548 { 6549 u8 *ptr = buffer; 6550 int ret; 6551 6552 if (ptr[0] != HDMI_INFOFRAME_TYPE_AUDIO || 6553 ptr[1] != 1 || 6554 ptr[2] != HDMI_AUDIO_INFOFRAME_SIZE) { 6555 return -EINVAL; 6556 } 6557 6558 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AUDIO)) != 0) 6559 return -EINVAL; 6560 6561 ret = hdmi_audio_infoframe_init(frame); 6562 if (ret) 6563 return ret; 6564 6565 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6566 6567 frame->channels = ptr[0] & 0x7; 6568 frame->coding_type = (ptr[0] >> 4) & 0xf; 6569 frame->sample_size = ptr[1] & 0x3; 6570 frame->sample_frequency = (ptr[1] >> 2) & 0x7; 6571 frame->coding_type_ext = ptr[2] & 0x1f; 6572 frame->channel_allocation = ptr[3]; 6573 frame->level_shift_value = (ptr[4] >> 3) & 0xf; 6574 frame->downmix_inhibit = ptr[4] & 0x80 ? true : false; 6575 6576 return 0; 6577 } 6578 6579 /** 6580 * hdmi_vendor_infoframe_unpack() - unpack binary buffer to a HDMI vendor infoframe 6581 * @buffer: source buffer 6582 * @frame: HDMI Vendor infoframe 6583 * 6584 * Unpacks the information contained in binary @buffer into a structured 6585 * @frame of the HDMI Vendor information frame. 6586 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6587 * specification. 6588 * 6589 * Returns 0 on success or a negative error code on failure. 6590 */ 6591 static int 6592 hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame, 6593 void *buffer) 6594 { 6595 u8 *ptr = buffer; 6596 size_t length; 6597 int ret; 6598 u8 hdmi_video_format; 6599 struct hdmi_vendor_infoframe *hvf = &frame->hdmi; 6600 6601 if (ptr[0] != HDMI_INFOFRAME_TYPE_VENDOR || 6602 ptr[1] != 1 || 6603 (ptr[2] != 4 && ptr[2] != 5 && ptr[2] != 6)) 6604 return -EINVAL; 6605 6606 length = ptr[2]; 6607 6608 if (hdmi_infoframe_checksum(buffer, 6609 HDMI_INFOFRAME_HEADER_SIZE + length) != 0) 6610 return -EINVAL; 6611 6612 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6613 6614 /* HDMI OUI */ 6615 if (ptr[0] != 0x03 || 6616 ptr[1] != 0x0c || 6617 ptr[2] != 0x00) 6618 return -EINVAL; 6619 6620 hdmi_video_format = ptr[3] >> 5; 6621 6622 if (hdmi_video_format > 0x2) 6623 return -EINVAL; 6624 6625 ret = hdmi_vendor_infoframe_init(hvf); 6626 if (ret) 6627 return ret; 6628 6629 hvf->length = length; 6630 6631 if (hdmi_video_format == 0x2) { 6632 if (length != 5 && length != 6) 6633 return -EINVAL; 6634 hvf->s3d_struct = ptr[4] >> 4; 6635 if (hvf->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) { 6636 if (length != 6) 6637 return -EINVAL; 6638 hvf->s3d_ext_data = ptr[5] >> 4; 6639 } 6640 } else if (hdmi_video_format == 0x1) { 6641 if (length != 5) 6642 return -EINVAL; 6643 hvf->vic = ptr[4]; 6644 } else { 6645 if (length != 4) 6646 return -EINVAL; 6647 } 6648 6649 return 0; 6650 } 6651 6652 /** 6653 * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe 6654 * @buffer: source buffer 6655 * @frame: HDMI infoframe 6656 * 6657 * Unpacks the information contained in binary buffer @buffer into a structured 6658 * @frame of a HDMI infoframe. 6659 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6660 * specification. 6661 * 6662 * Returns 0 on success or a negative error code on failure. 6663 */ 6664 int hdmi_infoframe_unpack(union hdmi_infoframe *frame, void *buffer) 6665 { 6666 int ret; 6667 u8 *ptr = buffer; 6668 6669 switch (ptr[0]) { 6670 case HDMI_INFOFRAME_TYPE_AVI: 6671 ret = hdmi_avi_infoframe_unpack(&frame->avi, buffer); 6672 break; 6673 case HDMI_INFOFRAME_TYPE_SPD: 6674 ret = hdmi_spd_infoframe_unpack(&frame->spd, buffer); 6675 break; 6676 case HDMI_INFOFRAME_TYPE_AUDIO: 6677 ret = hdmi_audio_infoframe_unpack(&frame->audio, buffer); 6678 break; 6679 case HDMI_INFOFRAME_TYPE_VENDOR: 6680 ret = hdmi_vendor_any_infoframe_unpack(&frame->vendor, buffer); 6681 break; 6682 default: 6683 ret = -EINVAL; 6684 break; 6685 } 6686 6687 return ret; 6688 } 6689 6690 bool drm_mode_equal(const struct base_drm_display_mode *mode1, 6691 const struct drm_display_mode *mode2) 6692 { 6693 if (mode1->clock == mode2->clock && 6694 mode1->hdisplay == mode2->hdisplay && 6695 mode1->hsync_start == mode2->hsync_start && 6696 mode1->hsync_end == mode2->hsync_end && 6697 mode1->htotal == mode2->htotal && 6698 mode1->vdisplay == mode2->vdisplay && 6699 mode1->vsync_start == mode2->vsync_start && 6700 mode1->vsync_end == mode2->vsync_end && 6701 mode1->vtotal == mode2->vtotal && 6702 mode1->flags == mode2->flags) 6703 return true; 6704 6705 return false; 6706 } 6707 6708 /** 6709 * drm_mode_sort - sort mode list 6710 * @edid_data: modes structures to sort 6711 * 6712 * Sort @edid_data by favorability, moving good modes to the head of the list. 6713 */ 6714 void drm_mode_sort(struct hdmi_edid_data *edid_data) 6715 { 6716 struct drm_display_mode *a, *b; 6717 struct drm_display_mode c; 6718 int diff, i, j; 6719 6720 for (i = 0; i < (edid_data->modes - 1); i++) { 6721 a = &edid_data->mode_buf[i]; 6722 for (j = i + 1; j < edid_data->modes; j++) { 6723 b = &edid_data->mode_buf[j]; 6724 diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) - 6725 ((a->type & DRM_MODE_TYPE_PREFERRED) != 0); 6726 if (diff) { 6727 if (diff > 0) { 6728 c = *a; 6729 *a = *b; 6730 *b = c; 6731 } 6732 continue; 6733 } 6734 6735 diff = b->hdisplay * b->vdisplay 6736 - a->hdisplay * a->vdisplay; 6737 if (diff) { 6738 if (diff > 0) { 6739 c = *a; 6740 *a = *b; 6741 *b = c; 6742 } 6743 continue; 6744 } 6745 6746 diff = b->vrefresh - a->vrefresh; 6747 if (diff) { 6748 if (diff > 0) { 6749 c = *a; 6750 *a = *b; 6751 *b = c; 6752 } 6753 continue; 6754 } 6755 6756 diff = b->clock - a->clock; 6757 if (diff > 0) { 6758 c = *a; 6759 *a = *b; 6760 *b = c; 6761 } 6762 } 6763 } 6764 edid_data->preferred_mode = &edid_data->mode_buf[0]; 6765 } 6766 6767 /** 6768 * drm_mode_prune_invalid - remove invalid modes from mode list 6769 * @edid_data: structure store mode list 6770 * Returns: 6771 * Number of valid modes. 6772 */ 6773 int drm_mode_prune_invalid(struct hdmi_edid_data *edid_data) 6774 { 6775 int i, j; 6776 int num = edid_data->modes; 6777 int len = sizeof(struct drm_display_mode); 6778 struct drm_display_mode *mode_buf = edid_data->mode_buf; 6779 6780 for (i = 0; i < num; i++) { 6781 if (mode_buf[i].invalid) { 6782 /* If mode is invalid, delete it. */ 6783 for (j = i; j < num - 1; j++) 6784 memcpy(&mode_buf[j], &mode_buf[j + 1], len); 6785 6786 num--; 6787 i--; 6788 } 6789 } 6790 /* Clear redundant modes of mode_buf. */ 6791 memset(&mode_buf[num], 0, len * (edid_data->modes - num)); 6792 6793 edid_data->modes = num; 6794 return num; 6795 } 6796 6797 /** 6798 * drm_rk_filter_whitelist - mark modes out of white list from mode list 6799 * @edid_data: structure store mode list 6800 */ 6801 void drm_rk_filter_whitelist(struct hdmi_edid_data *edid_data) 6802 { 6803 int i, j, white_len; 6804 6805 if (sizeof(resolution_white)) { 6806 white_len = sizeof(resolution_white) / 6807 sizeof(resolution_white[0]); 6808 for (i = 0; i < edid_data->modes; i++) { 6809 for (j = 0; j < white_len; j++) { 6810 if (drm_mode_equal(&resolution_white[j], 6811 &edid_data->mode_buf[i])) 6812 break; 6813 } 6814 6815 if (j == white_len) 6816 edid_data->mode_buf[i].invalid = true; 6817 } 6818 } 6819 } 6820 6821 void drm_rk_select_mode(struct hdmi_edid_data *edid_data, 6822 struct base_screen_info *screen_info) 6823 { 6824 int i; 6825 const struct base_drm_display_mode *base_mode; 6826 6827 if (!screen_info) { 6828 /* define init resolution here */ 6829 } else { 6830 base_mode = &screen_info->mode; 6831 for (i = 0; i < edid_data->modes; i++) { 6832 if (drm_mode_equal(base_mode, 6833 &edid_data->mode_buf[i])) { 6834 edid_data->preferred_mode = 6835 &edid_data->mode_buf[i]; 6836 6837 if (edid_data->mode_buf[i].picture_aspect_ratio) 6838 break; 6839 } 6840 } 6841 } 6842 } 6843 6844 /** 6845 * drm_do_probe_ddc_edid() - get EDID information via I2C 6846 * @adap: ddc adapter 6847 * @buf: EDID data buffer to be filled 6848 * @block: 128 byte EDID block to start fetching from 6849 * @len: EDID data buffer length to fetch 6850 * 6851 * Try to fetch EDID information by calling I2C driver functions. 6852 * 6853 * Return: 0 on success or -1 on failure. 6854 */ 6855 static int 6856 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 6857 size_t len) 6858 { 6859 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 6860 unsigned char segment = block >> 1; 6861 unsigned char xfers = segment ? 3 : 2; 6862 int ret, retries = 5; 6863 6864 do { 6865 struct i2c_msg msgs[] = { 6866 { 6867 .addr = DDC_SEGMENT_ADDR, 6868 .flags = 0, 6869 .len = 1, 6870 .buf = &segment, 6871 }, { 6872 .addr = DDC_ADDR, 6873 .flags = 0, 6874 .len = 1, 6875 .buf = &start, 6876 }, { 6877 .addr = DDC_ADDR, 6878 .flags = I2C_M_RD, 6879 .len = len, 6880 .buf = buf, 6881 } 6882 }; 6883 6884 if (adap->ops) { 6885 ret = adap->ops->xfer(adap->i2c_bus, &msgs[3 - xfers], 6886 xfers); 6887 if (!ret) 6888 ret = xfers; 6889 } else { 6890 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 6891 } 6892 } while (ret != xfers && --retries); 6893 6894 /* All msg transfer successfully. */ 6895 return ret == xfers ? 0 : -1; 6896 } 6897 6898 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid) 6899 { 6900 int i, j, block_num, block = 0; 6901 bool edid_corrupt; 6902 #ifdef DEBUG 6903 u8 *buff; 6904 #endif 6905 6906 /* base block fetch */ 6907 for (i = 0; i < 4; i++) { 6908 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 6909 goto err; 6910 if (drm_edid_block_valid(edid, 0, true, 6911 &edid_corrupt)) 6912 break; 6913 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 6914 printf("edid base block is 0, get edid failed\n"); 6915 goto err; 6916 } 6917 } 6918 6919 if (i == 4) 6920 goto err; 6921 6922 block++; 6923 /* get the number of extensions */ 6924 block_num = edid[0x7e]; 6925 6926 for (j = 1; j <= block_num; j++) { 6927 for (i = 0; i < 4; i++) { 6928 if (drm_do_probe_ddc_edid(adap, &edid[0x80 * j], j, 6929 HDMI_EDID_BLOCK_SIZE)) 6930 goto err; 6931 if (drm_edid_block_valid(&edid[0x80 * j], j, 6932 true, NULL)) 6933 break; 6934 } 6935 6936 if (i == 4) 6937 goto err; 6938 block++; 6939 } 6940 6941 #ifdef DEBUG 6942 printf("RAW EDID:\n"); 6943 for (i = 0; i < block_num + 1; i++) { 6944 buff = &edid[0x80 * i]; 6945 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 6946 if (j % 16 == 0) 6947 printf("\n"); 6948 printf("0x%02x, ", buff[j]); 6949 } 6950 printf("\n"); 6951 } 6952 #endif 6953 6954 return 0; 6955 6956 err: 6957 printf("can't get edid block:%d\n", block); 6958 /* clear all read edid block, include invalid block */ 6959 memset(edid, 0, HDMI_EDID_BLOCK_SIZE * (block + 1)); 6960 return -EFAULT; 6961 } 6962 6963 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 6964 void *buffer, size_t size) 6965 { 6966 struct i2c_msg msgs[2] = { 6967 { 6968 .addr = addr, 6969 .flags = 0, 6970 .len = 1, 6971 .buf = &offset, 6972 }, { 6973 .addr = addr, 6974 .flags = I2C_M_RD, 6975 .len = size, 6976 .buf = buffer, 6977 } 6978 }; 6979 6980 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 6981 } 6982 6983 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 6984 const void *buffer, size_t size) 6985 { 6986 struct i2c_msg msg = { 6987 .addr = addr, 6988 .flags = 0, 6989 .len = 1 + size, 6990 .buf = NULL, 6991 }; 6992 void *data; 6993 int err; 6994 6995 data = malloc(1 + size); 6996 if (!data) 6997 return -ENOMEM; 6998 6999 msg.buf = data; 7000 7001 memcpy(data, &offset, sizeof(offset)); 7002 memcpy(data + 1, buffer, size); 7003 7004 err = adap->ddc_xfer(adap, &msg, 1); 7005 7006 free(data); 7007 7008 return err; 7009 } 7010 7011 /** 7012 * drm_scdc_readb - read a single byte from SCDC 7013 * @adap: ddc adapter 7014 * @offset: offset of register to read 7015 * @value: return location for the register value 7016 * 7017 * Reads a single byte from SCDC. This is a convenience wrapper around the 7018 * drm_scdc_read() function. 7019 * 7020 * Returns: 7021 * 0 on success or a negative error code on failure. 7022 */ 7023 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 7024 u8 *value) 7025 { 7026 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 7027 sizeof(*value)); 7028 } 7029 7030 /** 7031 * drm_scdc_writeb - write a single byte to SCDC 7032 * @adap: ddc adapter 7033 * @offset: offset of register to read 7034 * @value: return location for the register value 7035 * 7036 * Writes a single byte to SCDC. This is a convenience wrapper around the 7037 * drm_scdc_write() function. 7038 * 7039 * Returns: 7040 * 0 on success or a negative error code on failure. 7041 */ 7042 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 7043 u8 value) 7044 { 7045 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 7046 sizeof(value)); 7047 } 7048 7049