1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <hexdump.h> 22 #include <malloc.h> 23 #include <linux/compat.h> 24 #include <linux/ctype.h> 25 #include <linux/fb.h> 26 #include <linux/hdmi.h> 27 #include <linux/string.h> 28 29 #define EDID_EST_TIMINGS 16 30 #define EDID_STD_TIMINGS 8 31 #define EDID_DETAILED_TIMINGS 4 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 bool preferred; 78 u32 quirks; 79 int modes; 80 }; 81 82 #define LEVEL_DMT 0 83 #define LEVEL_GTF 1 84 #define LEVEL_GTF2 2 85 #define LEVEL_CVT 3 86 87 static struct edid_quirk { 88 char vendor[4]; 89 int product_id; 90 u32 quirks; 91 } edid_quirk_list[] = { 92 /* Acer AL1706 */ 93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Acer F51 */ 95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Unknown Acer */ 97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 98 99 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 100 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 116 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 146 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 147 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Probably taken from CEA-861 spec. 152 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 153 * 154 * Index using the VIC. 155 */ 156 static const struct drm_display_mode edid_cea_modes[] = { 157 /* 0 - dummy, VICs start at 1 */ 158 { }, 159 /* 1 - 640x480@60Hz */ 160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 161 752, 800, 480, 490, 492, 525, 0, 162 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 163 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 164 /* 2 - 720x480@60Hz */ 165 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 166 798, 858, 480, 489, 495, 525, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 168 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 169 /* 3 - 720x480@60Hz */ 170 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 171 798, 858, 480, 489, 495, 525, 0, 172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 173 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 174 /* 4 - 1280x720@60Hz */ 175 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 176 1430, 1650, 720, 725, 730, 750, 0, 177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 178 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 179 /* 5 - 1920x1080i@60Hz */ 180 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 181 2052, 2200, 1080, 1084, 1094, 1125, 0, 182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 183 DRM_MODE_FLAG_INTERLACE), 184 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 185 /* 6 - 720(1440)x480i@60Hz */ 186 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 187 801, 858, 480, 488, 494, 525, 0, 188 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 189 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 190 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 191 /* 7 - 720(1440)x480i@60Hz */ 192 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 193 801, 858, 480, 488, 494, 525, 0, 194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 195 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 196 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 197 /* 8 - 720(1440)x240@60Hz */ 198 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 199 801, 858, 240, 244, 247, 262, 0, 200 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 201 DRM_MODE_FLAG_DBLCLK), 202 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 203 /* 9 - 720(1440)x240@60Hz */ 204 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 205 801, 858, 240, 244, 247, 262, 0, 206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 207 DRM_MODE_FLAG_DBLCLK), 208 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 209 /* 10 - 2880x480i@60Hz */ 210 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 211 3204, 3432, 480, 488, 494, 525, 0, 212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 213 DRM_MODE_FLAG_INTERLACE), 214 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 215 /* 11 - 2880x480i@60Hz */ 216 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 217 3204, 3432, 480, 488, 494, 525, 0, 218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 219 DRM_MODE_FLAG_INTERLACE), 220 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 221 /* 12 - 2880x240@60Hz */ 222 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 223 3204, 3432, 240, 244, 247, 262, 0, 224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 225 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 226 /* 13 - 2880x240@60Hz */ 227 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 228 3204, 3432, 240, 244, 247, 262, 0, 229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 230 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 231 /* 14 - 1440x480@60Hz */ 232 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 233 1596, 1716, 480, 489, 495, 525, 0, 234 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 235 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 236 /* 15 - 1440x480@60Hz */ 237 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 238 1596, 1716, 480, 489, 495, 525, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 240 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 241 /* 16 - 1920x1080@60Hz */ 242 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 243 2052, 2200, 1080, 1084, 1089, 1125, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 245 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 246 /* 17 - 720x576@50Hz */ 247 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 248 796, 864, 576, 581, 586, 625, 0, 249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 250 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 251 /* 18 - 720x576@50Hz */ 252 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 253 796, 864, 576, 581, 586, 625, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 255 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 256 /* 19 - 1280x720@50Hz */ 257 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 258 1760, 1980, 720, 725, 730, 750, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 260 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 261 /* 20 - 1920x1080i@50Hz */ 262 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 263 2492, 2640, 1080, 1084, 1094, 1125, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 265 DRM_MODE_FLAG_INTERLACE), 266 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 267 /* 21 - 720(1440)x576i@50Hz */ 268 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 269 795, 864, 576, 580, 586, 625, 0, 270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 271 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 273 /* 22 - 720(1440)x576i@50Hz */ 274 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 275 795, 864, 576, 580, 586, 625, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 277 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 278 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 279 /* 23 - 720(1440)x288@50Hz */ 280 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 281 795, 864, 288, 290, 293, 312, 0, 282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 283 DRM_MODE_FLAG_DBLCLK), 284 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 285 /* 24 - 720(1440)x288@50Hz */ 286 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 287 795, 864, 288, 290, 293, 312, 0, 288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 289 DRM_MODE_FLAG_DBLCLK), 290 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 291 /* 25 - 2880x576i@50Hz */ 292 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 293 3180, 3456, 576, 580, 586, 625, 0, 294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 295 DRM_MODE_FLAG_INTERLACE), 296 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 297 /* 26 - 2880x576i@50Hz */ 298 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 299 3180, 3456, 576, 580, 586, 625, 0, 300 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 301 DRM_MODE_FLAG_INTERLACE), 302 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 303 /* 27 - 2880x288@50Hz */ 304 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 305 3180, 3456, 288, 290, 293, 312, 0, 306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 307 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 308 /* 28 - 2880x288@50Hz */ 309 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 310 3180, 3456, 288, 290, 293, 312, 0, 311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 312 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 313 /* 29 - 1440x576@50Hz */ 314 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 315 1592, 1728, 576, 581, 586, 625, 0, 316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 317 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 318 /* 30 - 1440x576@50Hz */ 319 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 320 1592, 1728, 576, 581, 586, 625, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 322 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 323 /* 31 - 1920x1080@50Hz */ 324 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 325 2492, 2640, 1080, 1084, 1089, 1125, 0, 326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 327 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 328 /* 32 - 1920x1080@24Hz */ 329 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 330 2602, 2750, 1080, 1084, 1089, 1125, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 332 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 333 /* 33 - 1920x1080@25Hz */ 334 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 335 2492, 2640, 1080, 1084, 1089, 1125, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 337 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 338 /* 34 - 1920x1080@30Hz */ 339 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 340 2052, 2200, 1080, 1084, 1089, 1125, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 342 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 343 /* 35 - 2880x480@60Hz */ 344 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 345 3192, 3432, 480, 489, 495, 525, 0, 346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 347 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 348 /* 36 - 2880x480@60Hz */ 349 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 350 3192, 3432, 480, 489, 495, 525, 0, 351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 352 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 353 /* 37 - 2880x576@50Hz */ 354 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 355 3184, 3456, 576, 581, 586, 625, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 357 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 358 /* 38 - 2880x576@50Hz */ 359 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 360 3184, 3456, 576, 581, 586, 625, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 362 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 363 /* 39 - 1920x1080i@50Hz */ 364 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 365 2120, 2304, 1080, 1126, 1136, 1250, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 367 DRM_MODE_FLAG_INTERLACE), 368 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 369 /* 40 - 1920x1080i@100Hz */ 370 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 371 2492, 2640, 1080, 1084, 1094, 1125, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 373 DRM_MODE_FLAG_INTERLACE), 374 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 375 /* 41 - 1280x720@100Hz */ 376 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 377 1760, 1980, 720, 725, 730, 750, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 379 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 380 /* 42 - 720x576@100Hz */ 381 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 382 796, 864, 576, 581, 586, 625, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 384 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 385 /* 43 - 720x576@100Hz */ 386 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 387 796, 864, 576, 581, 586, 625, 0, 388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 389 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 390 /* 44 - 720(1440)x576i@100Hz */ 391 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 392 795, 864, 576, 580, 586, 625, 0, 393 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 394 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 395 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 396 /* 45 - 720(1440)x576i@100Hz */ 397 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 398 795, 864, 576, 580, 586, 625, 0, 399 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 400 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 401 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 402 /* 46 - 1920x1080i@120Hz */ 403 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 404 2052, 2200, 1080, 1084, 1094, 1125, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 406 DRM_MODE_FLAG_INTERLACE), 407 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 408 /* 47 - 1280x720@120Hz */ 409 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 410 1430, 1650, 720, 725, 730, 750, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 412 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 413 /* 48 - 720x480@120Hz */ 414 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 415 798, 858, 480, 489, 495, 525, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 417 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 418 /* 49 - 720x480@120Hz */ 419 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 420 798, 858, 480, 489, 495, 525, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 422 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 423 /* 50 - 720(1440)x480i@120Hz */ 424 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 425 801, 858, 480, 488, 494, 525, 0, 426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 427 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 428 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 429 /* 51 - 720(1440)x480i@120Hz */ 430 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 431 801, 858, 480, 488, 494, 525, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 433 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 434 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 435 /* 52 - 720x576@200Hz */ 436 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 437 796, 864, 576, 581, 586, 625, 0, 438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 439 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 440 /* 53 - 720x576@200Hz */ 441 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 442 796, 864, 576, 581, 586, 625, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 444 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 445 /* 54 - 720(1440)x576i@200Hz */ 446 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 447 795, 864, 576, 580, 586, 625, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 449 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 450 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 451 /* 55 - 720(1440)x576i@200Hz */ 452 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 453 795, 864, 576, 580, 586, 625, 0, 454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 455 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 456 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 457 /* 56 - 720x480@240Hz */ 458 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 459 798, 858, 480, 489, 495, 525, 0, 460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 461 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 462 /* 57 - 720x480@240Hz */ 463 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 464 798, 858, 480, 489, 495, 525, 0, 465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 466 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 467 /* 58 - 720(1440)x480i@240 */ 468 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 469 801, 858, 480, 488, 494, 525, 0, 470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 471 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 472 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 473 /* 59 - 720(1440)x480i@240 */ 474 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 475 801, 858, 480, 488, 494, 525, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 477 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 478 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 479 /* 60 - 1280x720@24Hz */ 480 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 481 3080, 3300, 720, 725, 730, 750, 0, 482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 483 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 484 /* 61 - 1280x720@25Hz */ 485 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 486 3740, 3960, 720, 725, 730, 750, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 488 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 489 /* 62 - 1280x720@30Hz */ 490 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 491 3080, 3300, 720, 725, 730, 750, 0, 492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 493 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 494 /* 63 - 1920x1080@120Hz */ 495 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 496 2052, 2200, 1080, 1084, 1089, 1125, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 498 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 499 /* 64 - 1920x1080@100Hz */ 500 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 501 2492, 2640, 1080, 1084, 1089, 1125, 0, 502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 503 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 504 /* 65 - 1280x720@24Hz */ 505 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 506 3080, 3300, 720, 725, 730, 750, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 508 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 509 /* 66 - 1280x720@25Hz */ 510 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 511 3740, 3960, 720, 725, 730, 750, 0, 512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 513 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 514 /* 67 - 1280x720@30Hz */ 515 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 516 3080, 3300, 720, 725, 730, 750, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 518 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 519 /* 68 - 1280x720@50Hz */ 520 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 521 1760, 1980, 720, 725, 730, 750, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 523 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 524 /* 69 - 1280x720@60Hz */ 525 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 526 1430, 1650, 720, 725, 730, 750, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 528 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 529 /* 70 - 1280x720@100Hz */ 530 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 531 1760, 1980, 720, 725, 730, 750, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 533 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 534 /* 71 - 1280x720@120Hz */ 535 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 536 1430, 1650, 720, 725, 730, 750, 0, 537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 538 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 539 /* 72 - 1920x1080@24Hz */ 540 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 541 2602, 2750, 1080, 1084, 1089, 1125, 0, 542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 543 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 544 /* 73 - 1920x1080@25Hz */ 545 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 546 2492, 2640, 1080, 1084, 1089, 1125, 0, 547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 548 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 549 /* 74 - 1920x1080@30Hz */ 550 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 551 2052, 2200, 1080, 1084, 1089, 1125, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 553 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 554 /* 75 - 1920x1080@50Hz */ 555 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 556 2492, 2640, 1080, 1084, 1089, 1125, 0, 557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 558 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 559 /* 76 - 1920x1080@60Hz */ 560 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 561 2052, 2200, 1080, 1084, 1089, 1125, 0, 562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 563 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 564 /* 77 - 1920x1080@100Hz */ 565 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 566 2492, 2640, 1080, 1084, 1089, 1125, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 568 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 569 /* 78 - 1920x1080@120Hz */ 570 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 571 2052, 2200, 1080, 1084, 1089, 1125, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 573 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 574 /* 79 - 1680x720@24Hz */ 575 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 576 3080, 3300, 720, 725, 730, 750, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 578 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 579 /* 80 - 1680x720@25Hz */ 580 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 581 2948, 3168, 720, 725, 730, 750, 0, 582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 583 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 584 /* 81 - 1680x720@30Hz */ 585 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 586 2420, 2640, 720, 725, 730, 750, 0, 587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 588 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 589 /* 82 - 1680x720@50Hz */ 590 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 591 1980, 2200, 720, 725, 730, 750, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 593 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 594 /* 83 - 1680x720@60Hz */ 595 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 596 1980, 2200, 720, 725, 730, 750, 0, 597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 598 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 599 /* 84 - 1680x720@100Hz */ 600 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 601 1780, 2000, 720, 725, 730, 825, 0, 602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 603 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 604 /* 85 - 1680x720@120Hz */ 605 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 606 1780, 2000, 720, 725, 730, 825, 0, 607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 608 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 609 /* 86 - 2560x1080@24Hz */ 610 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 611 3602, 3750, 1080, 1084, 1089, 1100, 0, 612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 613 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 614 /* 87 - 2560x1080@25Hz */ 615 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 616 3052, 3200, 1080, 1084, 1089, 1125, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 618 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 619 /* 88 - 2560x1080@30Hz */ 620 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 621 3372, 3520, 1080, 1084, 1089, 1125, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 623 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 624 /* 89 - 2560x1080@50Hz */ 625 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 626 3152, 3300, 1080, 1084, 1089, 1125, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 628 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 629 /* 90 - 2560x1080@60Hz */ 630 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 631 2852, 3000, 1080, 1084, 1089, 1100, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 633 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 634 /* 91 - 2560x1080@100Hz */ 635 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 636 2822, 2970, 1080, 1084, 1089, 1250, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 638 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 639 /* 92 - 2560x1080@120Hz */ 640 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 641 3152, 3300, 1080, 1084, 1089, 1250, 0, 642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 643 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 644 /* 93 - 3840x2160p@24Hz 16:9 */ 645 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 646 5204, 5500, 2160, 2168, 2178, 2250, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 648 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 649 /* 94 - 3840x2160p@25Hz 16:9 */ 650 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 651 4984, 5280, 2160, 2168, 2178, 2250, 0, 652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 653 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 654 /* 95 - 3840x2160p@30Hz 16:9 */ 655 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 656 4104, 4400, 2160, 2168, 2178, 2250, 0, 657 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 658 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 659 /* 96 - 3840x2160p@50Hz 16:9 */ 660 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 661 4984, 5280, 2160, 2168, 2178, 2250, 0, 662 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 663 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 664 /* 97 - 3840x2160p@60Hz 16:9 */ 665 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 666 4104, 4400, 2160, 2168, 2178, 2250, 0, 667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 669 /* 98 - 4096x2160p@24Hz 256:135 */ 670 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 671 5204, 5500, 2160, 2168, 2178, 2250, 0, 672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 673 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 674 /* 99 - 4096x2160p@25Hz 256:135 */ 675 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 676 5152, 5280, 2160, 2168, 2178, 2250, 0, 677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 678 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 679 /* 100 - 4096x2160p@30Hz 256:135 */ 680 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 681 4272, 4400, 2160, 2168, 2178, 2250, 0, 682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 683 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 684 /* 101 - 4096x2160p@50Hz 256:135 */ 685 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 686 5152, 5280, 2160, 2168, 2178, 2250, 0, 687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 688 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 689 /* 102 - 4096x2160p@60Hz 256:135 */ 690 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 691 4272, 4400, 2160, 2168, 2178, 2250, 0, 692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 693 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 694 /* 103 - 3840x2160p@24Hz 64:27 */ 695 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 696 5204, 5500, 2160, 2168, 2178, 2250, 0, 697 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 698 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 699 /* 104 - 3840x2160p@25Hz 64:27 */ 700 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 701 4104, 4400, 2160, 2168, 2178, 2250, 0, 702 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 703 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 704 /* 105 - 3840x2160p@30Hz 64:27 */ 705 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 706 4104, 4400, 2160, 2168, 2178, 2250, 0, 707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 708 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 709 /* 106 - 3840x2160p@50Hz 64:27 */ 710 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 711 4984, 5280, 2160, 2168, 2178, 2250, 0, 712 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 713 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 714 /* 107 - 3840x2160p@60Hz 64:27 */ 715 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 716 4104, 4400, 2160, 2168, 2178, 2250, 0, 717 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 718 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 719 }; 720 721 /* 722 * HDMI 1.4 4k modes. Index using the VIC. 723 */ 724 static const struct drm_display_mode edid_4k_modes[] = { 725 /* 0 - dummy, VICs start at 1 */ 726 { }, 727 /* 1 - 3840x2160@30Hz */ 728 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 729 3840, 4016, 4104, 4400, 730 2160, 2168, 2178, 2250, 0, 731 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 732 .vrefresh = 30, }, 733 /* 2 - 3840x2160@25Hz */ 734 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 735 3840, 4896, 4984, 5280, 736 2160, 2168, 2178, 2250, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .vrefresh = 25, }, 739 /* 3 - 3840x2160@24Hz */ 740 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 741 3840, 5116, 5204, 5500, 742 2160, 2168, 2178, 2250, 0, 743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 744 .vrefresh = 24, }, 745 /* 4 - 4096x2160@24Hz (SMPTE) */ 746 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 747 4096, 5116, 5204, 5500, 748 2160, 2168, 2178, 2250, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 24, }, 751 }; 752 753 /* 754 * Autogenerated from the DMT spec. 755 * This table is copied from xfree86/modes/xf86EdidModes.c. 756 */ 757 static const struct drm_display_mode drm_dmt_modes[] = { 758 /* 0x01 - 640x350@85Hz */ 759 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 760 736, 832, 350, 382, 385, 445, 0, 761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 762 /* 0x02 - 640x400@85Hz */ 763 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 764 736, 832, 400, 401, 404, 445, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 766 /* 0x03 - 720x400@85Hz */ 767 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 768 828, 936, 400, 401, 404, 446, 0, 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 770 /* 0x04 - 640x480@60Hz */ 771 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 772 752, 800, 480, 490, 492, 525, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 774 /* 0x05 - 640x480@72Hz */ 775 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 776 704, 832, 480, 489, 492, 520, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 778 /* 0x06 - 640x480@75Hz */ 779 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 780 720, 840, 480, 481, 484, 500, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 782 /* 0x07 - 640x480@85Hz */ 783 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 784 752, 832, 480, 481, 484, 509, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 786 /* 0x08 - 800x600@56Hz */ 787 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 788 896, 1024, 600, 601, 603, 625, 0, 789 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 790 /* 0x09 - 800x600@60Hz */ 791 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 792 968, 1056, 600, 601, 605, 628, 0, 793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 794 /* 0x0a - 800x600@72Hz */ 795 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 796 976, 1040, 600, 637, 643, 666, 0, 797 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 798 /* 0x0b - 800x600@75Hz */ 799 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 800 896, 1056, 600, 601, 604, 625, 0, 801 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 802 /* 0x0c - 800x600@85Hz */ 803 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 804 896, 1048, 600, 601, 604, 631, 0, 805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 806 /* 0x0d - 800x600@120Hz RB */ 807 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 808 880, 960, 600, 603, 607, 636, 0, 809 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 810 /* 0x0e - 848x480@60Hz */ 811 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 812 976, 1088, 480, 486, 494, 517, 0, 813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 814 /* 0x0f - 1024x768@43Hz, interlace */ 815 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 816 1208, 1264, 768, 768, 772, 817, 0, 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 818 DRM_MODE_FLAG_INTERLACE) }, 819 /* 0x10 - 1024x768@60Hz */ 820 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 821 1184, 1344, 768, 771, 777, 806, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 823 /* 0x11 - 1024x768@70Hz */ 824 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 825 1184, 1328, 768, 771, 777, 806, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 827 /* 0x12 - 1024x768@75Hz */ 828 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 829 1136, 1312, 768, 769, 772, 800, 0, 830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 831 /* 0x13 - 1024x768@85Hz */ 832 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 833 1168, 1376, 768, 769, 772, 808, 0, 834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 835 /* 0x14 - 1024x768@120Hz RB */ 836 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 837 1104, 1184, 768, 771, 775, 813, 0, 838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 839 /* 0x15 - 1152x864@75Hz */ 840 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 841 1344, 1600, 864, 865, 868, 900, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 843 /* 0x55 - 1280x720@60Hz */ 844 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 845 1430, 1650, 720, 725, 730, 750, 0, 846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 847 /* 0x16 - 1280x768@60Hz RB */ 848 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 849 1360, 1440, 768, 771, 778, 790, 0, 850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 851 /* 0x17 - 1280x768@60Hz */ 852 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 853 1472, 1664, 768, 771, 778, 798, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 855 /* 0x18 - 1280x768@75Hz */ 856 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 857 1488, 1696, 768, 771, 778, 805, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 859 /* 0x19 - 1280x768@85Hz */ 860 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 861 1496, 1712, 768, 771, 778, 809, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 863 /* 0x1a - 1280x768@120Hz RB */ 864 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 865 1360, 1440, 768, 771, 778, 813, 0, 866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 867 /* 0x1b - 1280x800@60Hz RB */ 868 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 869 1360, 1440, 800, 803, 809, 823, 0, 870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 871 /* 0x1c - 1280x800@60Hz */ 872 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 873 1480, 1680, 800, 803, 809, 831, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 875 /* 0x1d - 1280x800@75Hz */ 876 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 877 1488, 1696, 800, 803, 809, 838, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 879 /* 0x1e - 1280x800@85Hz */ 880 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 881 1496, 1712, 800, 803, 809, 843, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 883 /* 0x1f - 1280x800@120Hz RB */ 884 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 885 1360, 1440, 800, 803, 809, 847, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 887 /* 0x20 - 1280x960@60Hz */ 888 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 889 1488, 1800, 960, 961, 964, 1000, 0, 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 891 /* 0x21 - 1280x960@85Hz */ 892 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 893 1504, 1728, 960, 961, 964, 1011, 0, 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 895 /* 0x22 - 1280x960@120Hz RB */ 896 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 897 1360, 1440, 960, 963, 967, 1017, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 899 /* 0x23 - 1280x1024@60Hz */ 900 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 901 1440, 1688, 1024, 1025, 1028, 1066, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 903 /* 0x24 - 1280x1024@75Hz */ 904 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 905 1440, 1688, 1024, 1025, 1028, 1066, 0, 906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 907 /* 0x25 - 1280x1024@85Hz */ 908 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 909 1504, 1728, 1024, 1025, 1028, 1072, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 911 /* 0x26 - 1280x1024@120Hz RB */ 912 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 913 1360, 1440, 1024, 1027, 1034, 1084, 0, 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 915 /* 0x27 - 1360x768@60Hz */ 916 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 917 1536, 1792, 768, 771, 777, 795, 0, 918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 919 /* 0x28 - 1360x768@120Hz RB */ 920 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 921 1440, 1520, 768, 771, 776, 813, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 923 /* 0x51 - 1366x768@60Hz */ 924 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 925 1579, 1792, 768, 771, 774, 798, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 927 /* 0x56 - 1366x768@60Hz */ 928 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 929 1436, 1500, 768, 769, 772, 800, 0, 930 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 931 /* 0x29 - 1400x1050@60Hz RB */ 932 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 933 1480, 1560, 1050, 1053, 1057, 1080, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 935 /* 0x2a - 1400x1050@60Hz */ 936 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 937 1632, 1864, 1050, 1053, 1057, 1089, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 939 /* 0x2b - 1400x1050@75Hz */ 940 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 941 1648, 1896, 1050, 1053, 1057, 1099, 0, 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 943 /* 0x2c - 1400x1050@85Hz */ 944 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 945 1656, 1912, 1050, 1053, 1057, 1105, 0, 946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 947 /* 0x2d - 1400x1050@120Hz RB */ 948 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 949 1480, 1560, 1050, 1053, 1057, 1112, 0, 950 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 951 /* 0x2e - 1440x900@60Hz RB */ 952 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 953 1520, 1600, 900, 903, 909, 926, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 955 /* 0x2f - 1440x900@60Hz */ 956 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 957 1672, 1904, 900, 903, 909, 934, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 959 /* 0x30 - 1440x900@75Hz */ 960 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 961 1688, 1936, 900, 903, 909, 942, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 963 /* 0x31 - 1440x900@85Hz */ 964 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 965 1696, 1952, 900, 903, 909, 948, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 967 /* 0x32 - 1440x900@120Hz RB */ 968 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 969 1520, 1600, 900, 903, 909, 953, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 971 /* 0x53 - 1600x900@60Hz */ 972 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 973 1704, 1800, 900, 901, 904, 1000, 0, 974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 975 /* 0x33 - 1600x1200@60Hz */ 976 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 977 1856, 2160, 1200, 1201, 1204, 1250, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 979 /* 0x34 - 1600x1200@65Hz */ 980 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 981 1856, 2160, 1200, 1201, 1204, 1250, 0, 982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 983 /* 0x35 - 1600x1200@70Hz */ 984 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 985 1856, 2160, 1200, 1201, 1204, 1250, 0, 986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 987 /* 0x36 - 1600x1200@75Hz */ 988 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 989 1856, 2160, 1200, 1201, 1204, 1250, 0, 990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 991 /* 0x37 - 1600x1200@85Hz */ 992 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 993 1856, 2160, 1200, 1201, 1204, 1250, 0, 994 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 995 /* 0x38 - 1600x1200@120Hz RB */ 996 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 997 1680, 1760, 1200, 1203, 1207, 1271, 0, 998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 999 /* 0x39 - 1680x1050@60Hz RB */ 1000 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1001 1760, 1840, 1050, 1053, 1059, 1080, 0, 1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1003 /* 0x3a - 1680x1050@60Hz */ 1004 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1005 1960, 2240, 1050, 1053, 1059, 1089, 0, 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1007 /* 0x3b - 1680x1050@75Hz */ 1008 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1009 1976, 2272, 1050, 1053, 1059, 1099, 0, 1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1011 /* 0x3c - 1680x1050@85Hz */ 1012 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1013 1984, 2288, 1050, 1053, 1059, 1105, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1015 /* 0x3d - 1680x1050@120Hz RB */ 1016 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1017 1760, 1840, 1050, 1053, 1059, 1112, 0, 1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1019 /* 0x3e - 1792x1344@60Hz */ 1020 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1021 2120, 2448, 1344, 1345, 1348, 1394, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1023 /* 0x3f - 1792x1344@75Hz */ 1024 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1025 2104, 2456, 1344, 1345, 1348, 1417, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1027 /* 0x40 - 1792x1344@120Hz RB */ 1028 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1029 1872, 1952, 1344, 1347, 1351, 1423, 0, 1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1031 /* 0x41 - 1856x1392@60Hz */ 1032 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1033 2176, 2528, 1392, 1393, 1396, 1439, 0, 1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1035 /* 0x42 - 1856x1392@75Hz */ 1036 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1037 2208, 2560, 1392, 1393, 1396, 1500, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1039 /* 0x43 - 1856x1392@120Hz RB */ 1040 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1041 1936, 2016, 1392, 1395, 1399, 1474, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1043 /* 0x52 - 1920x1080@60Hz */ 1044 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1045 2052, 2200, 1080, 1084, 1089, 1125, 0, 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1047 /* 0x44 - 1920x1200@60Hz RB */ 1048 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1049 2000, 2080, 1200, 1203, 1209, 1235, 0, 1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1051 /* 0x45 - 1920x1200@60Hz */ 1052 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1053 2256, 2592, 1200, 1203, 1209, 1245, 0, 1054 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1055 /* 0x46 - 1920x1200@75Hz */ 1056 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1057 2264, 2608, 1200, 1203, 1209, 1255, 0, 1058 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1059 /* 0x47 - 1920x1200@85Hz */ 1060 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1061 2272, 2624, 1200, 1203, 1209, 1262, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1063 /* 0x48 - 1920x1200@120Hz RB */ 1064 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1065 2000, 2080, 1200, 1203, 1209, 1271, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1067 /* 0x49 - 1920x1440@60Hz */ 1068 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1069 2256, 2600, 1440, 1441, 1444, 1500, 0, 1070 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1071 /* 0x4a - 1920x1440@75Hz */ 1072 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1073 2288, 2640, 1440, 1441, 1444, 1500, 0, 1074 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1075 /* 0x4b - 1920x1440@120Hz RB */ 1076 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1077 2000, 2080, 1440, 1443, 1447, 1525, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1079 /* 0x54 - 2048x1152@60Hz */ 1080 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1081 2154, 2250, 1152, 1153, 1156, 1200, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1083 /* 0x4c - 2560x1600@60Hz RB */ 1084 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1085 2640, 2720, 1600, 1603, 1609, 1646, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1087 /* 0x4d - 2560x1600@60Hz */ 1088 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1089 3032, 3504, 1600, 1603, 1609, 1658, 0, 1090 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1091 /* 0x4e - 2560x1600@75Hz */ 1092 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1093 3048, 3536, 1600, 1603, 1609, 1672, 0, 1094 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1095 /* 0x4f - 2560x1600@85Hz */ 1096 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1097 3048, 3536, 1600, 1603, 1609, 1682, 0, 1098 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1099 /* 0x50 - 2560x1600@120Hz RB */ 1100 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1101 2640, 2720, 1600, 1603, 1609, 1694, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1103 /* 0x57 - 4096x2160@60Hz RB */ 1104 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1105 4136, 4176, 2160, 2208, 2216, 2222, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1107 /* 0x58 - 4096x2160@59.94Hz RB */ 1108 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1109 4136, 4176, 2160, 2208, 2216, 2222, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1111 }; 1112 1113 /* 1114 * These more or less come from the DMT spec. The 720x400 modes are 1115 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1116 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1117 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1118 * mode. 1119 * 1120 * The DMT modes have been fact-checked; the rest are mild guesses. 1121 */ 1122 static const struct drm_display_mode edid_est_modes[] = { 1123 /* 800x600@60Hz */ 1124 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1125 968, 1056, 600, 601, 605, 628, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1127 /* 800x600@56Hz */ 1128 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1129 896, 1024, 600, 601, 603, 625, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1131 /* 640x480@75Hz */ 1132 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1133 720, 840, 480, 481, 484, 500, 0, 1134 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1135 /* 640x480@72Hz */ 1136 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1137 704, 832, 480, 489, 492, 520, 0, 1138 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1139 /* 640x480@67Hz */ 1140 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1141 768, 864, 480, 483, 486, 525, 0, 1142 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1143 /* 640x480@60Hz */ 1144 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1145 752, 800, 480, 490, 492, 525, 0, 1146 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1147 /* 720x400@88Hz */ 1148 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1149 846, 900, 400, 421, 423, 449, 0, 1150 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1151 /* 720x400@70Hz */ 1152 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1153 846, 900, 400, 412, 414, 449, 0, 1154 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1155 /* 1280x1024@75Hz */ 1156 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1157 1440, 1688, 1024, 1025, 1028, 1066, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1159 /* 1024x768@75Hz */ 1160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1161 1136, 1312, 768, 769, 772, 800, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1163 /* 1024x768@70Hz */ 1164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1165 1184, 1328, 768, 771, 777, 806, 0, 1166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1167 /* 1024x768@60Hz */ 1168 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1169 1184, 1344, 768, 771, 777, 806, 0, 1170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1171 /* 1024x768@43Hz */ 1172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1173 1208, 1264, 768, 768, 776, 817, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1175 DRM_MODE_FLAG_INTERLACE) }, 1176 /* 832x624@75Hz */ 1177 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1178 928, 1152, 624, 625, 628, 667, 0, 1179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1180 /* 800x600@75Hz */ 1181 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1182 896, 1056, 600, 601, 604, 625, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1184 /* 800x600@72Hz */ 1185 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1186 976, 1040, 600, 637, 643, 666, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1188 /* 1152x864@75Hz */ 1189 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1190 1344, 1600, 864, 865, 868, 900, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1192 }; 1193 1194 #define DRM_BASE_MODE(c, hd, hss, hse, ht, vd, vss, vse, vt, vs, f) \ 1195 .clock = (c), \ 1196 .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ 1197 .htotal = (ht), .vdisplay = (vd), \ 1198 .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ 1199 .vscan = (vs), .flags = (f) 1200 1201 static const struct base_drm_display_mode resolution_white[] = { 1202 /* 0. vic:2 - 720x480@60Hz */ 1203 { DRM_BASE_MODE(27000, 720, 736, 1204 798, 858, 480, 489, 495, 525, 0, 1205 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1206 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1207 /* 1. vic:3 - 720x480@60Hz */ 1208 { DRM_BASE_MODE(27000, 720, 736, 1209 798, 858, 480, 489, 495, 525, 0, 1210 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1211 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1212 /* 2. vic:4 - 1280x720@60Hz */ 1213 { DRM_BASE_MODE(74250, 1280, 1390, 1214 1430, 1650, 720, 725, 730, 750, 0, 1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1216 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1217 /* 3. vic:5 - 1920x1080i@60Hz */ 1218 { DRM_BASE_MODE(74250, 1920, 2008, 1219 2052, 2200, 1080, 1084, 1094, 1125, 0, 1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1221 DRM_MODE_FLAG_INTERLACE), 1222 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1223 /* 4. vic:6 - 720(1440)x480i@60Hz */ 1224 { DRM_BASE_MODE(13500, 720, 739, 1225 801, 858, 480, 488, 494, 525, 0, 1226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1227 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1228 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1229 /* 5. vic:16 - 1920x1080@60Hz */ 1230 { DRM_BASE_MODE(148500, 1920, 2008, 1231 2052, 2200, 1080, 1084, 1089, 1125, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1234 /* 6. vic:17 - 720x576@50Hz */ 1235 { DRM_BASE_MODE(27000, 720, 732, 1236 796, 864, 576, 581, 586, 625, 0, 1237 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1238 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1239 /* 7. vic:18 - 720x576@50Hz */ 1240 { DRM_BASE_MODE(27000, 720, 732, 1241 796, 864, 576, 581, 586, 625, 0, 1242 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1243 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1244 /* 8. vic:19 - 1280x720@50Hz */ 1245 { DRM_BASE_MODE(74250, 1280, 1720, 1246 1760, 1980, 720, 725, 730, 750, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1249 /* 9. vic:20 - 1920x1080i@50Hz */ 1250 { DRM_BASE_MODE(74250, 1920, 2448, 1251 2492, 2640, 1080, 1084, 1094, 1125, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1253 DRM_MODE_FLAG_INTERLACE), 1254 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1255 /* 10. vic:21 - 720(1440)x576i@50Hz */ 1256 { DRM_BASE_MODE(13500, 720, 732, 1257 795, 864, 576, 580, 586, 625, 0, 1258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1259 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1260 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1261 /* 11. vic:31 - 1920x1080@50Hz */ 1262 { DRM_BASE_MODE(148500, 1920, 2448, 1263 2492, 2640, 1080, 1084, 1089, 1125, 0, 1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1265 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1266 /* 12. vic:32 - 1920x1080@24Hz */ 1267 { DRM_BASE_MODE(74250, 1920, 2558, 1268 2602, 2750, 1080, 1084, 1089, 1125, 0, 1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1270 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1271 /* 13. vic:33 - 1920x1080@25Hz */ 1272 { DRM_BASE_MODE(74250, 1920, 2448, 1273 2492, 2640, 1080, 1084, 1089, 1125, 0, 1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1275 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1276 /* 14. vic:34 - 1920x1080@30Hz */ 1277 { DRM_BASE_MODE(74250, 1920, 2008, 1278 2052, 2200, 1080, 1084, 1089, 1125, 0, 1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1280 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1281 /* 15. vic:39 - 1920x1080i@50Hz */ 1282 { DRM_BASE_MODE(72000, 1920, 1952, 1283 2120, 2304, 1080, 1126, 1136, 1250, 0, 1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 1285 DRM_MODE_FLAG_INTERLACE), 1286 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1287 /* 16. vic:60 - 1280x720@24Hz */ 1288 { DRM_BASE_MODE(59400, 1280, 3040, 1289 3080, 3300, 720, 725, 730, 750, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1291 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1292 /* 17. vic:61 - 1280x720@25Hz */ 1293 { DRM_BASE_MODE(74250, 1280, 3700, 1294 3740, 3960, 720, 725, 730, 750, 0, 1295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1296 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1297 /* 18. vic:62 - 1280x720@30Hz */ 1298 { DRM_BASE_MODE(74250, 1280, 3040, 1299 3080, 3300, 720, 725, 730, 750, 0, 1300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1301 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1302 /* 19. vic:93 - 3840x2160p@24Hz 16:9 */ 1303 { DRM_BASE_MODE(297000, 3840, 5116, 1304 5204, 5500, 2160, 2168, 2178, 2250, 0, 1305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1306 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1307 /* 20. vic:94 - 3840x2160p@25Hz 16:9 */ 1308 { DRM_BASE_MODE(297000, 3840, 4896, 1309 4984, 5280, 2160, 2168, 2178, 2250, 0, 1310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1311 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1312 /* 21. vic:95 - 3840x2160p@30Hz 16:9 */ 1313 { DRM_BASE_MODE(297000, 3840, 4016, 1314 4104, 4400, 2160, 2168, 2178, 2250, 0, 1315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1316 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1317 /* 22. vic:96 - 3840x2160p@50Hz 16:9 */ 1318 { DRM_BASE_MODE(594000, 3840, 4896, 1319 4984, 5280, 2160, 2168, 2178, 2250, 0, 1320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1321 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1322 /* 23. vic:97 - 3840x2160p@60Hz 16:9 */ 1323 { DRM_BASE_MODE(594000, 3840, 4016, 1324 4104, 4400, 2160, 2168, 2178, 2250, 0, 1325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1326 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1327 /* 24. vic:98 - 4096x2160p@24Hz 256:135 */ 1328 { DRM_BASE_MODE(297000, 4096, 5116, 1329 5204, 5500, 2160, 2168, 2178, 2250, 0, 1330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1331 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1332 /* 25. vic:99 - 4096x2160p@25Hz 256:135 */ 1333 { DRM_BASE_MODE(297000, 4096, 5064, 1334 5152, 5280, 2160, 2168, 2178, 2250, 0, 1335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1336 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1337 /* 26. vic:100 - 4096x2160p@30Hz 256:135 */ 1338 { DRM_BASE_MODE(297000, 4096, 4184, 1339 4272, 4400, 2160, 2168, 2178, 2250, 0, 1340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1341 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1342 /* 27. vic:101 - 4096x2160p@50Hz 256:135 */ 1343 { DRM_BASE_MODE(594000, 4096, 5064, 1344 5152, 5280, 2160, 2168, 2178, 2250, 0, 1345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1346 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1347 /* 28. vic:102 - 4096x2160p@60Hz 256:135 */ 1348 { DRM_BASE_MODE(594000, 4096, 4184, 1349 4272, 4400, 2160, 2168, 2178, 2250, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1351 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1352 }; 1353 1354 struct minimode { 1355 short w; 1356 short h; 1357 short r; 1358 short rb; 1359 }; 1360 1361 static const struct minimode est3_modes[] = { 1362 /* byte 6 */ 1363 { 640, 350, 85, 0 }, 1364 { 640, 400, 85, 0 }, 1365 { 720, 400, 85, 0 }, 1366 { 640, 480, 85, 0 }, 1367 { 848, 480, 60, 0 }, 1368 { 800, 600, 85, 0 }, 1369 { 1024, 768, 85, 0 }, 1370 { 1152, 864, 75, 0 }, 1371 /* byte 7 */ 1372 { 1280, 768, 60, 1 }, 1373 { 1280, 768, 60, 0 }, 1374 { 1280, 768, 75, 0 }, 1375 { 1280, 768, 85, 0 }, 1376 { 1280, 960, 60, 0 }, 1377 { 1280, 960, 85, 0 }, 1378 { 1280, 1024, 60, 0 }, 1379 { 1280, 1024, 85, 0 }, 1380 /* byte 8 */ 1381 { 1360, 768, 60, 0 }, 1382 { 1440, 900, 60, 1 }, 1383 { 1440, 900, 60, 0 }, 1384 { 1440, 900, 75, 0 }, 1385 { 1440, 900, 85, 0 }, 1386 { 1400, 1050, 60, 1 }, 1387 { 1400, 1050, 60, 0 }, 1388 { 1400, 1050, 75, 0 }, 1389 /* byte 9 */ 1390 { 1400, 1050, 85, 0 }, 1391 { 1680, 1050, 60, 1 }, 1392 { 1680, 1050, 60, 0 }, 1393 { 1680, 1050, 75, 0 }, 1394 { 1680, 1050, 85, 0 }, 1395 { 1600, 1200, 60, 0 }, 1396 { 1600, 1200, 65, 0 }, 1397 { 1600, 1200, 70, 0 }, 1398 /* byte 10 */ 1399 { 1600, 1200, 75, 0 }, 1400 { 1600, 1200, 85, 0 }, 1401 { 1792, 1344, 60, 0 }, 1402 { 1792, 1344, 75, 0 }, 1403 { 1856, 1392, 60, 0 }, 1404 { 1856, 1392, 75, 0 }, 1405 { 1920, 1200, 60, 1 }, 1406 { 1920, 1200, 60, 0 }, 1407 /* byte 11 */ 1408 { 1920, 1200, 75, 0 }, 1409 { 1920, 1200, 85, 0 }, 1410 { 1920, 1440, 60, 0 }, 1411 { 1920, 1440, 75, 0 }, 1412 }; 1413 1414 static const struct minimode extra_modes[] = { 1415 { 1024, 576, 60, 0 }, 1416 { 1366, 768, 60, 0 }, 1417 { 1600, 900, 60, 0 }, 1418 { 1680, 945, 60, 0 }, 1419 { 1920, 1080, 60, 0 }, 1420 { 2048, 1152, 60, 0 }, 1421 { 2048, 1536, 60, 0 }, 1422 }; 1423 1424 int edid_check_info(struct edid1_info *edid_info) 1425 { 1426 if ((edid_info == NULL) || (edid_info->version == 0)) 1427 return -1; 1428 1429 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1430 return -1; 1431 1432 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1433 return -1; 1434 1435 return 0; 1436 } 1437 1438 int edid_check_checksum(u8 *edid_block) 1439 { 1440 u8 checksum = 0; 1441 int i; 1442 1443 for (i = 0; i < 128; i++) 1444 checksum += edid_block[i]; 1445 1446 return (checksum == 0) ? 0 : -EINVAL; 1447 } 1448 1449 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1450 unsigned int *hmax, unsigned int *vmin, 1451 unsigned int *vmax) 1452 { 1453 int i; 1454 struct edid_monitor_descriptor *monitor; 1455 1456 *hmin = *hmax = *vmin = *vmax = 0; 1457 if (edid_check_info(edid)) 1458 return -1; 1459 1460 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1461 monitor = &edid->monitor_details.descriptor[i]; 1462 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1463 *hmin = monitor->data.range_data.horizontal_min; 1464 *hmax = monitor->data.range_data.horizontal_max; 1465 *vmin = monitor->data.range_data.vertical_min; 1466 *vmax = monitor->data.range_data.vertical_max; 1467 return 0; 1468 } 1469 } 1470 return -1; 1471 } 1472 1473 /* Set all parts of a timing entry to the same value */ 1474 static void set_entry(struct timing_entry *entry, u32 value) 1475 { 1476 entry->min = value; 1477 entry->typ = value; 1478 entry->max = value; 1479 } 1480 1481 /** 1482 * decode_timing() - Decoding an 18-byte detailed timing record 1483 * 1484 * @buf: Pointer to EDID detailed timing record 1485 * @timing: Place to put timing 1486 */ 1487 static void decode_timing(u8 *buf, struct display_timing *timing) 1488 { 1489 uint x_mm, y_mm; 1490 unsigned int ha, hbl, hso, hspw, hborder; 1491 unsigned int va, vbl, vso, vspw, vborder; 1492 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1493 1494 /* Edid contains pixel clock in terms of 10KHz */ 1495 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1496 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1497 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1498 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1499 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1500 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1501 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1502 hborder = buf[15]; 1503 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1504 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1505 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1506 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1507 vborder = buf[16]; 1508 1509 set_entry(&timing->hactive, ha); 1510 set_entry(&timing->hfront_porch, hso); 1511 set_entry(&timing->hback_porch, hbl - hso - hspw); 1512 set_entry(&timing->hsync_len, hspw); 1513 1514 set_entry(&timing->vactive, va); 1515 set_entry(&timing->vfront_porch, vso); 1516 set_entry(&timing->vback_porch, vbl - vso - vspw); 1517 set_entry(&timing->vsync_len, vspw); 1518 1519 timing->flags = 0; 1520 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1521 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1522 else 1523 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1524 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1525 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1526 else 1527 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1528 1529 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1530 timing->flags = DISPLAY_FLAGS_INTERLACED; 1531 1532 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1533 " %04x %04x %04x %04x hborder %x\n" 1534 " %04x %04x %04x %04x vborder %x\n", 1535 timing->pixelclock.typ, 1536 x_mm, y_mm, 1537 ha, ha + hso, ha + hso + hspw, 1538 ha + hbl, hborder, 1539 va, va + vso, va + vso + vspw, 1540 va + vbl, vborder); 1541 } 1542 1543 /** 1544 * decode_mode() - Decoding an 18-byte detailed timing record 1545 * 1546 * @buf: Pointer to EDID detailed timing record 1547 * @timing: Place to put timing 1548 */ 1549 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1550 { 1551 uint x_mm, y_mm; 1552 unsigned int ha, hbl, hso, hspw, hborder; 1553 unsigned int va, vbl, vso, vspw, vborder; 1554 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1555 1556 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1557 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1558 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1559 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1560 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1561 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1562 hborder = buf[15]; 1563 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1564 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1565 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1566 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1567 vborder = buf[16]; 1568 1569 /* Edid contains pixel clock in terms of 10KHz */ 1570 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1571 mode->hdisplay = ha; 1572 mode->hsync_start = ha + hso; 1573 mode->hsync_end = ha + hso + hspw; 1574 mode->htotal = ha + hbl; 1575 mode->vdisplay = va; 1576 mode->vsync_start = va + vso; 1577 mode->vsync_end = va + vso + vspw; 1578 mode->vtotal = va + vbl; 1579 1580 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1581 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1582 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1583 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1584 1585 if (EDID_DETAILED_TIMING_FLAG_INTERLEAVED(*t)) 1586 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1587 1588 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1589 " %04d %04d %04d %04d hborder %d\n" 1590 " %04d %04d %04d %04d vborder %d\n", 1591 mode->clock, 1592 x_mm, y_mm, mode->flags, 1593 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1594 mode->htotal, hborder, 1595 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1596 mode->vtotal, vborder); 1597 } 1598 1599 /** 1600 * edid_vendor - match a string against EDID's obfuscated vendor field 1601 * @edid: EDID to match 1602 * @vendor: vendor string 1603 * 1604 * Returns true if @vendor is in @edid, false otherwise 1605 */ 1606 static bool edid_vendor(struct edid *edid, char *vendor) 1607 { 1608 char edid_vendor[3]; 1609 1610 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1611 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1612 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1613 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1614 1615 return !strncmp(edid_vendor, vendor, 3); 1616 } 1617 1618 /** 1619 * Check if HDMI vendor specific data block is present in CEA block 1620 * @param info CEA extension block 1621 * @return true if block is found 1622 */ 1623 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1624 { 1625 u8 end, i = 0; 1626 1627 /* check for end of data block */ 1628 end = info->dtd_offset; 1629 if (end == 0) 1630 end = sizeof(info->data); 1631 if (end < 4 || end > sizeof(info->data)) 1632 return false; 1633 end -= 4; 1634 1635 while (i < end) { 1636 /* Look for vendor specific data block of appropriate size */ 1637 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1638 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1639 u8 *db = &info->data[i + 1]; 1640 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1641 1642 if (oui == HDMI_IEEE_OUI) 1643 return true; 1644 } 1645 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1646 } 1647 1648 return false; 1649 } 1650 1651 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1652 { 1653 int refresh = 0; 1654 unsigned int calc_val; 1655 1656 if (mode->vrefresh > 0) { 1657 refresh = mode->vrefresh; 1658 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1659 int vtotal; 1660 1661 vtotal = mode->vtotal; 1662 /* work out vrefresh the value will be x1000 */ 1663 calc_val = (mode->clock * 1000); 1664 calc_val /= mode->htotal; 1665 refresh = (calc_val + vtotal / 2) / vtotal; 1666 1667 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1668 refresh *= 2; 1669 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1670 refresh /= 2; 1671 if (mode->vscan > 1) 1672 refresh /= mode->vscan; 1673 } 1674 return refresh; 1675 } 1676 1677 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1678 int *panel_bits_per_colourp) 1679 { 1680 struct edid1_info *edid = (struct edid1_info *)buf; 1681 bool timing_done; 1682 int i; 1683 1684 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1685 debug("%s: Invalid buffer\n", __func__); 1686 return -EINVAL; 1687 } 1688 1689 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1690 debug("%s: No preferred timing\n", __func__); 1691 return -ENOENT; 1692 } 1693 1694 /* Look for detailed timing */ 1695 timing_done = false; 1696 for (i = 0; i < 4; i++) { 1697 struct edid_monitor_descriptor *desc; 1698 1699 desc = &edid->monitor_details.descriptor[i]; 1700 if (desc->zero_flag_1 != 0) { 1701 decode_mode((u8 *)desc, mode); 1702 timing_done = true; 1703 break; 1704 } 1705 } 1706 if (!timing_done) 1707 return -EINVAL; 1708 1709 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1710 debug("%s: Not a digital display\n", __func__); 1711 return -ENOSYS; 1712 } 1713 if (edid->version != 1 || edid->revision < 4) { 1714 debug("%s: EDID version %d.%d does not have required info\n", 1715 __func__, edid->version, edid->revision); 1716 *panel_bits_per_colourp = -1; 1717 } else { 1718 *panel_bits_per_colourp = 1719 ((edid->video_input_definition & 0x70) >> 3) + 4; 1720 } 1721 1722 return 0; 1723 } 1724 1725 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 1726 int *panel_bits_per_colourp) 1727 { 1728 struct edid1_info *edid = (struct edid1_info *)buf; 1729 bool timing_done; 1730 int i; 1731 1732 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1733 debug("%s: Invalid buffer\n", __func__); 1734 return -EINVAL; 1735 } 1736 1737 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1738 debug("%s: No preferred timing\n", __func__); 1739 return -ENOENT; 1740 } 1741 1742 /* Look for detailed timing */ 1743 timing_done = false; 1744 for (i = 0; i < 4; i++) { 1745 struct edid_monitor_descriptor *desc; 1746 1747 desc = &edid->monitor_details.descriptor[i]; 1748 if (desc->zero_flag_1 != 0) { 1749 decode_timing((u8 *)desc, timing); 1750 timing_done = true; 1751 break; 1752 } 1753 } 1754 if (!timing_done) 1755 return -EINVAL; 1756 1757 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1758 debug("%s: Not a digital display\n", __func__); 1759 return -ENOSYS; 1760 } 1761 if (edid->version != 1 || edid->revision < 4) { 1762 debug("%s: EDID version %d.%d does not have required info\n", 1763 __func__, edid->version, edid->revision); 1764 *panel_bits_per_colourp = -1; 1765 } else { 1766 *panel_bits_per_colourp = 1767 ((edid->video_input_definition & 0x70) >> 3) + 4; 1768 } 1769 1770 timing->hdmi_monitor = false; 1771 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 1772 struct edid_cea861_info *info = 1773 (struct edid_cea861_info *)(buf + sizeof(*edid)); 1774 1775 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 1776 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 1777 } 1778 1779 return 0; 1780 } 1781 1782 /** 1783 * Snip the tailing whitespace/return of a string. 1784 * 1785 * @param string The string to be snipped 1786 * @return the snipped string 1787 */ 1788 static char *snip(char *string) 1789 { 1790 char *s; 1791 1792 /* 1793 * This is always a 13 character buffer 1794 * and it's not always terminated. 1795 */ 1796 string[12] = '\0'; 1797 s = &string[strlen(string) - 1]; 1798 1799 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 1800 *s == '\0')) 1801 *(s--) = '\0'; 1802 1803 return string; 1804 } 1805 1806 /** 1807 * Print an EDID monitor descriptor block 1808 * 1809 * @param monitor The EDID monitor descriptor block 1810 * @have_timing Modifies to 1 if the desciptor contains timing info 1811 */ 1812 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 1813 unsigned int *have_timing) 1814 { 1815 unsigned char *bytes = (unsigned char *)monitor; 1816 struct edid_detailed_timing *timing = 1817 (struct edid_detailed_timing *)monitor; 1818 1819 if (bytes[0] == 0 && bytes[1] == 0) { 1820 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 1821 printf("Monitor serial number: %s\n", 1822 snip(monitor->data.string)); 1823 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 1824 printf("Monitor ID: %s\n", 1825 snip(monitor->data.string)); 1826 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 1827 printf("Monitor name: %s\n", 1828 snip(monitor->data.string)); 1829 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 1830 printf("Monitor range limits, horizontal sync: " 1831 "%d-%d kHz, vertical refresh: " 1832 "%d-%d Hz, max pixel clock: " 1833 "%d MHz\n", 1834 monitor->data.range_data.horizontal_min, 1835 monitor->data.range_data.horizontal_max, 1836 monitor->data.range_data.vertical_min, 1837 monitor->data.range_data.vertical_max, 1838 monitor->data.range_data.pixel_clock_max * 10); 1839 } else { 1840 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 1841 u32 h_total, v_total, vfreq; 1842 1843 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 1844 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 1845 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 1846 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 1847 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 1848 1849 h_total = h_active + h_blanking; 1850 v_total = v_active + v_blanking; 1851 if (v_total > 0 && h_total > 0) 1852 vfreq = pixclock / (v_total * h_total); 1853 else 1854 vfreq = 1; /* Error case */ 1855 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 1856 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 1857 *have_timing = 1; 1858 } 1859 } 1860 1861 /** 1862 * Get the manufacturer name from an EDID info. 1863 * 1864 * @param edid_info The EDID info to be printed 1865 * @param name Returns the string of the manufacturer name 1866 */ 1867 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 1868 { 1869 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 1870 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 1871 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 1872 name[3] = '\0'; 1873 } 1874 1875 void edid_print_info(struct edid1_info *edid_info) 1876 { 1877 int i; 1878 char manufacturer[4]; 1879 unsigned int have_timing = 0; 1880 u32 serial_number; 1881 1882 if (edid_check_info(edid_info)) { 1883 printf("Not a valid EDID\n"); 1884 return; 1885 } 1886 1887 printf("EDID version: %d.%d\n", 1888 edid_info->version, edid_info->revision); 1889 1890 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 1891 1892 edid_get_manufacturer_name(edid_info, manufacturer); 1893 printf("Manufacturer: %s\n", manufacturer); 1894 1895 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 1896 if (serial_number != 0xffffffff) { 1897 if (strcmp(manufacturer, "MAG") == 0) 1898 serial_number -= 0x7000000; 1899 if (strcmp(manufacturer, "OQI") == 0) 1900 serial_number -= 456150000; 1901 if (strcmp(manufacturer, "VSC") == 0) 1902 serial_number -= 640000000; 1903 } 1904 printf("Serial number: %08x\n", serial_number); 1905 printf("Manufactured in week: %d year: %d\n", 1906 edid_info->week, edid_info->year + 1990); 1907 1908 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 1909 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 1910 "digital signal, " : "analog signal, ", 1911 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 1912 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 1913 ", blank to black" : "", 1914 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 1915 ", separate sync" : "", 1916 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 1917 ", composite sync" : "", 1918 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 1919 ", sync on green" : "", 1920 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 1921 ", serration v" : ""); 1922 1923 printf("Monitor is %s\n", 1924 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 1925 1926 printf("Maximum visible display size: %d cm x %d cm\n", 1927 edid_info->max_size_horizontal, 1928 edid_info->max_size_vertical); 1929 1930 printf("Power management features: %s%s, %s%s, %s%s\n", 1931 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 1932 "" : "no ", "active off", 1933 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 1934 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 1935 1936 printf("Estabilished timings:\n"); 1937 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 1938 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 1939 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 1940 printf("\t720x400\t\t88 Hz (XGA2)\n"); 1941 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 1942 printf("\t640x480\t\t60 Hz (VGA)\n"); 1943 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 1944 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 1945 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 1946 printf("\t640x480\t\t72 Hz (VESA)\n"); 1947 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 1948 printf("\t640x480\t\t75 Hz (VESA)\n"); 1949 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 1950 printf("\t800x600\t\t56 Hz (VESA)\n"); 1951 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 1952 printf("\t800x600\t\t60 Hz (VESA)\n"); 1953 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 1954 printf("\t800x600\t\t72 Hz (VESA)\n"); 1955 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 1956 printf("\t800x600\t\t75 Hz (VESA)\n"); 1957 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 1958 printf("\t832x624\t\t75 Hz (Mac II)\n"); 1959 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 1960 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 1961 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 1962 printf("\t1024x768\t60 Hz (VESA)\n"); 1963 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 1964 printf("\t1024x768\t70 Hz (VESA)\n"); 1965 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 1966 printf("\t1024x768\t75 Hz (VESA)\n"); 1967 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 1968 printf("\t1280x1024\t75 (VESA)\n"); 1969 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 1970 printf("\t1152x870\t75 (Mac II)\n"); 1971 1972 /* Standard timings. */ 1973 printf("Standard timings:\n"); 1974 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 1975 unsigned int aspect = 10000; 1976 unsigned int x, y; 1977 unsigned char xres, vfreq; 1978 1979 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 1980 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 1981 if ((xres != vfreq) || 1982 ((xres != 0) && (xres != 1)) || 1983 ((vfreq != 0) && (vfreq != 1))) { 1984 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 1985 i)) { 1986 case ASPECT_625: 1987 aspect = 6250; 1988 break; 1989 case ASPECT_75: 1990 aspect = 7500; 1991 break; 1992 case ASPECT_8: 1993 aspect = 8000; 1994 break; 1995 case ASPECT_5625: 1996 aspect = 5625; 1997 break; 1998 } 1999 x = (xres + 31) * 8; 2000 y = x * aspect / 10000; 2001 printf("\t%dx%d%c\t%d Hz\n", x, y, 2002 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 2003 have_timing = 1; 2004 } 2005 } 2006 2007 /* Detailed timing information. */ 2008 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 2009 i++) { 2010 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 2011 &have_timing); 2012 } 2013 2014 if (!have_timing) 2015 printf("\tNone\n"); 2016 } 2017 2018 /** 2019 * drm_mode_create - create a new display mode 2020 * 2021 * Create a new, cleared drm_display_mode. 2022 * 2023 * Returns: 2024 * Pointer to new mode on success, NULL on error. 2025 */ 2026 static struct drm_display_mode *drm_mode_create(void) 2027 { 2028 struct drm_display_mode *nmode; 2029 2030 nmode = malloc(sizeof(struct drm_display_mode)); 2031 memset(nmode, 0, sizeof(struct drm_display_mode)); 2032 if (!nmode) 2033 return NULL; 2034 2035 return nmode; 2036 } 2037 2038 /** 2039 * drm_mode_destroy - remove a mode 2040 * @mode: mode to remove 2041 * 2042 */ 2043 static void drm_mode_destroy(struct drm_display_mode *mode) 2044 { 2045 if (!mode) 2046 return; 2047 2048 kfree(mode); 2049 } 2050 2051 /** 2052 * drm_cvt_mode -create a modeline based on the CVT algorithm 2053 * @hdisplay: hdisplay size 2054 * @vdisplay: vdisplay size 2055 * @vrefresh: vrefresh rate 2056 * @reduced: whether to use reduced blanking 2057 * @interlaced: whether to compute an interlaced mode 2058 * @margins: whether to add margins (borders) 2059 * 2060 * This function is called to generate the modeline based on CVT algorithm 2061 * according to the hdisplay, vdisplay, vrefresh. 2062 * It is based from the VESA(TM) Coordinated Video Timing Generator by 2063 * Graham Loveridge April 9, 2003 available at 2064 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 2065 * 2066 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 2067 * What I have done is to translate it by using integer calculation. 2068 * 2069 * Returns: 2070 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 2071 * The display mode object is allocated with drm_mode_create(). Returns NULL 2072 * when no mode could be allocated. 2073 */ 2074 static 2075 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 2076 bool reduced, bool interlaced, 2077 bool margins) 2078 { 2079 #define HV_FACTOR 1000 2080 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 2081 #define CVT_MARGIN_PERCENTAGE 18 2082 /* 2) character cell horizontal granularity (pixels) - default 8 */ 2083 #define CVT_H_GRANULARITY 8 2084 /* 3) Minimum vertical porch (lines) - default 3 */ 2085 #define CVT_MIN_V_PORCH 3 2086 /* 4) Minimum number of vertical back porch lines - default 6 */ 2087 #define CVT_MIN_V_BPORCH 6 2088 /* Pixel Clock step (kHz) */ 2089 #define CVT_CLOCK_STEP 250 2090 struct drm_display_mode *drm_mode; 2091 unsigned int vfieldrate, hperiod; 2092 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 2093 int interlace; 2094 2095 /* allocate the drm_display_mode structure. If failure, we will 2096 * return directly 2097 */ 2098 drm_mode = drm_mode_create(); 2099 if (!drm_mode) 2100 return NULL; 2101 2102 /* the CVT default refresh rate is 60Hz */ 2103 if (!vrefresh) 2104 vrefresh = 60; 2105 2106 /* the required field fresh rate */ 2107 if (interlaced) 2108 vfieldrate = vrefresh * 2; 2109 else 2110 vfieldrate = vrefresh; 2111 2112 /* horizontal pixels */ 2113 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 2114 2115 /* determine the left&right borders */ 2116 hmargin = 0; 2117 if (margins) { 2118 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2119 hmargin -= hmargin % CVT_H_GRANULARITY; 2120 } 2121 /* find the total active pixels */ 2122 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 2123 2124 /* find the number of lines per field */ 2125 if (interlaced) 2126 vdisplay_rnd = vdisplay / 2; 2127 else 2128 vdisplay_rnd = vdisplay; 2129 2130 /* find the top & bottom borders */ 2131 vmargin = 0; 2132 if (margins) 2133 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2134 2135 drm_mode->vdisplay = vdisplay + 2 * vmargin; 2136 2137 /* Interlaced */ 2138 if (interlaced) 2139 interlace = 1; 2140 else 2141 interlace = 0; 2142 2143 /* Determine VSync Width from aspect ratio */ 2144 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 2145 vsync = 4; 2146 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 2147 vsync = 5; 2148 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 2149 vsync = 6; 2150 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 2151 vsync = 7; 2152 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 2153 vsync = 7; 2154 else /* custom */ 2155 vsync = 10; 2156 2157 if (!reduced) { 2158 /* simplify the GTF calculation */ 2159 /* 4) Minimum time of vertical sync + back porch interval 2160 * default 550.0 2161 */ 2162 int tmp1, tmp2; 2163 #define CVT_MIN_VSYNC_BP 550 2164 /* 3) Nominal HSync width (% of line period) - default 8 */ 2165 #define CVT_HSYNC_PERCENTAGE 8 2166 unsigned int hblank_percentage; 2167 int vsyncandback_porch, hblank; 2168 2169 /* estimated the horizontal period */ 2170 tmp1 = HV_FACTOR * 1000000 - 2171 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2172 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2173 interlace; 2174 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2175 2176 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2177 /* 9. Find number of lines in sync + backporch */ 2178 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2179 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2180 else 2181 vsyncandback_porch = tmp1; 2182 /* 10. Find number of lines in back porch 2183 * vback_porch = vsyncandback_porch - vsync; 2184 */ 2185 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2186 vsyncandback_porch + CVT_MIN_V_PORCH; 2187 /* 5) Definition of Horizontal blanking time limitation */ 2188 /* Gradient (%/kHz) - default 600 */ 2189 #define CVT_M_FACTOR 600 2190 /* Offset (%) - default 40 */ 2191 #define CVT_C_FACTOR 40 2192 /* Blanking time scaling factor - default 128 */ 2193 #define CVT_K_FACTOR 128 2194 /* Scaling factor weighting - default 20 */ 2195 #define CVT_J_FACTOR 20 2196 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2197 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2198 CVT_J_FACTOR) 2199 /* 12. Find ideal blanking duty cycle from formula */ 2200 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2201 hperiod / 1000; 2202 /* 13. Blanking time */ 2203 if (hblank_percentage < 20 * HV_FACTOR) 2204 hblank_percentage = 20 * HV_FACTOR; 2205 hblank = drm_mode->hdisplay * hblank_percentage / 2206 (100 * HV_FACTOR - hblank_percentage); 2207 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2208 /* 14. find the total pixels per line */ 2209 drm_mode->htotal = drm_mode->hdisplay + hblank; 2210 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2211 drm_mode->hsync_start = drm_mode->hsync_end - 2212 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2213 drm_mode->hsync_start += CVT_H_GRANULARITY - 2214 drm_mode->hsync_start % CVT_H_GRANULARITY; 2215 /* fill the Vsync values */ 2216 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2217 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2218 } else { 2219 /* Reduced blanking */ 2220 /* Minimum vertical blanking interval time - default 460 */ 2221 #define CVT_RB_MIN_VBLANK 460 2222 /* Fixed number of clocks for horizontal sync */ 2223 #define CVT_RB_H_SYNC 32 2224 /* Fixed number of clocks for horizontal blanking */ 2225 #define CVT_RB_H_BLANK 160 2226 /* Fixed number of lines for vertical front porch - default 3*/ 2227 #define CVT_RB_VFPORCH 3 2228 int vbilines; 2229 int tmp1, tmp2; 2230 /* 8. Estimate Horizontal period. */ 2231 tmp1 = HV_FACTOR * 1000000 - 2232 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2233 tmp2 = vdisplay_rnd + 2 * vmargin; 2234 hperiod = tmp1 / (tmp2 * vfieldrate); 2235 /* 9. Find number of lines in vertical blanking */ 2236 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2237 /* 10. Check if vertical blanking is sufficient */ 2238 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2239 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2240 /* 11. Find total number of lines in vertical field */ 2241 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2242 /* 12. Find total number of pixels in a line */ 2243 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2244 /* Fill in HSync values */ 2245 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2246 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2247 /* Fill in VSync values */ 2248 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2249 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2250 } 2251 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2252 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2253 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2254 /* 18/16. Find actual vertical frame frequency */ 2255 /* ignore - just set the mode flag for interlaced */ 2256 if (interlaced) { 2257 drm_mode->vtotal *= 2; 2258 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2259 } 2260 2261 if (reduced) 2262 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2263 DRM_MODE_FLAG_NVSYNC); 2264 else 2265 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2266 DRM_MODE_FLAG_NHSYNC); 2267 2268 return drm_mode; 2269 } 2270 2271 static int 2272 cea_db_payload_len(const u8 *db) 2273 { 2274 return db[0] & 0x1f; 2275 } 2276 2277 static int 2278 cea_db_extended_tag(const u8 *db) 2279 { 2280 return db[1]; 2281 } 2282 2283 static int 2284 cea_db_tag(const u8 *db) 2285 { 2286 return db[0] >> 5; 2287 } 2288 2289 #define for_each_cea_db(cea, i, start, end) \ 2290 for ((i) = (start); (i) < (end) && (i) + \ 2291 cea_db_payload_len(&(cea)[(i)]) < \ 2292 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2293 2294 static int 2295 cea_revision(const u8 *cea) 2296 { 2297 return cea[1]; 2298 } 2299 2300 static int 2301 cea_db_offsets(const u8 *cea, int *start, int *end) 2302 { 2303 /* Data block offset in CEA extension block */ 2304 *start = 4; 2305 *end = cea[2]; 2306 if (*end == 0) 2307 *end = 127; 2308 if (*end < 4 || *end > 127) 2309 return -ERANGE; 2310 2311 /* 2312 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2313 */ 2314 if (*end != 4) { 2315 int i; 2316 2317 i = *start; 2318 while (i < (*end) && 2319 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2320 i += cea_db_payload_len(&(cea)[i]) + 1; 2321 2322 if (cea_db_payload_len(&(cea)[i]) && 2323 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2324 (*end)++; 2325 } 2326 2327 return 0; 2328 } 2329 2330 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2331 { 2332 int hdmi_id; 2333 2334 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2335 return false; 2336 2337 if (cea_db_payload_len(db) < 5) 2338 return false; 2339 2340 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2341 2342 return hdmi_id == HDMI_IEEE_OUI; 2343 } 2344 2345 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2346 { 2347 unsigned int oui; 2348 2349 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2350 return false; 2351 2352 if (cea_db_payload_len(db) < 7) 2353 return false; 2354 2355 oui = db[3] << 16 | db[2] << 8 | db[1]; 2356 2357 return oui == HDMI_FORUM_IEEE_OUI; 2358 } 2359 2360 static bool cea_db_is_y420cmdb(const u8 *db) 2361 { 2362 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2363 return false; 2364 2365 if (!cea_db_payload_len(db)) 2366 return false; 2367 2368 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2369 return false; 2370 2371 return true; 2372 } 2373 2374 static bool cea_db_is_y420vdb(const u8 *db) 2375 { 2376 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2377 return false; 2378 2379 if (!cea_db_payload_len(db)) 2380 return false; 2381 2382 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2383 return false; 2384 2385 return true; 2386 } 2387 2388 static bool drm_valid_hdmi_vic(u8 vic) 2389 { 2390 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2391 } 2392 2393 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2394 const struct drm_display_mode *mode) 2395 { 2396 struct drm_display_mode *mode_buf = data->mode_buf; 2397 2398 if (data->modes >= MODE_LEN) 2399 return; 2400 mode_buf[(data->modes)++] = *mode; 2401 } 2402 2403 static bool drm_valid_cea_vic(u8 vic) 2404 { 2405 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2406 } 2407 2408 static u8 svd_to_vic(u8 svd) 2409 { 2410 /* 0-6 bit vic, 7th bit native mode indicator */ 2411 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2412 return svd & 127; 2413 2414 return svd; 2415 } 2416 2417 static struct drm_display_mode * 2418 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2419 u8 video_index) 2420 { 2421 struct drm_display_mode *newmode; 2422 u8 vic; 2423 2424 if (!video_db || video_index >= video_len) 2425 return NULL; 2426 2427 /* CEA modes are numbered 1..127 */ 2428 vic = svd_to_vic(video_db[video_index]); 2429 if (!drm_valid_cea_vic(vic)) 2430 return NULL; 2431 2432 newmode = drm_mode_create(); 2433 if (!newmode) 2434 return NULL; 2435 2436 *newmode = edid_cea_modes[vic]; 2437 newmode->vrefresh = 0; 2438 2439 return newmode; 2440 } 2441 2442 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2443 { 2444 unsigned long *p = map + BIT_WORD(start); 2445 const unsigned int size = start + len; 2446 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2447 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2448 2449 while (len - bits_to_set >= 0) { 2450 *p |= mask_to_set; 2451 len -= bits_to_set; 2452 bits_to_set = BITS_PER_LONG; 2453 mask_to_set = ~0UL; 2454 p++; 2455 } 2456 if (len) { 2457 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2458 *p |= mask_to_set; 2459 } 2460 } 2461 2462 static void 2463 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2464 { 2465 u8 vic = svd_to_vic(svd); 2466 2467 if (!drm_valid_cea_vic(vic)) 2468 return; 2469 2470 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2471 } 2472 2473 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2474 { 2475 int i, modes = 0; 2476 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2477 2478 for (i = 0; i < len; i++) { 2479 struct drm_display_mode *mode; 2480 2481 mode = drm_display_mode_from_vic_index(db, len, i); 2482 if (mode) { 2483 /* 2484 * YCBCR420 capability block contains a bitmap which 2485 * gives the index of CEA modes from CEA VDB, which 2486 * can support YCBCR 420 sampling output also (apart 2487 * from RGB/YCBCR444 etc). 2488 * For example, if the bit 0 in bitmap is set, 2489 * first mode in VDB can support YCBCR420 output too. 2490 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2491 */ 2492 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2493 drm_add_cmdb_modes(db[i], hdmi); 2494 drm_add_hdmi_modes(data, mode); 2495 drm_mode_destroy(mode); 2496 modes++; 2497 } 2498 } 2499 2500 return modes; 2501 } 2502 2503 /* 2504 * do_y420vdb_modes - Parse YCBCR 420 only modes 2505 * @data: the structure that save parsed hdmi edid data 2506 * @svds: start of the data block of CEA YCBCR 420 VDB 2507 * @svds_len: length of the CEA YCBCR 420 VDB 2508 * @hdmi: runtime information about the connected HDMI sink 2509 * 2510 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2511 * which contains modes which can be supported in YCBCR 420 2512 * output format only. 2513 */ 2514 static int 2515 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2516 { 2517 int modes = 0, i; 2518 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2519 2520 for (i = 0; i < svds_len; i++) { 2521 u8 vic = svd_to_vic(svds[i]); 2522 2523 if (!drm_valid_cea_vic(vic)) 2524 continue; 2525 2526 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2527 drm_add_hdmi_modes(data, &edid_cea_modes[vic]); 2528 modes++; 2529 } 2530 2531 return modes; 2532 } 2533 2534 struct stereo_mandatory_mode { 2535 int width, height, vrefresh; 2536 unsigned int flags; 2537 }; 2538 2539 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2540 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2541 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2542 { 1920, 1080, 50, 2543 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2544 { 1920, 1080, 60, 2545 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2546 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2547 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2548 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2549 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2550 }; 2551 2552 static bool 2553 stereo_match_mandatory(const struct drm_display_mode *mode, 2554 const struct stereo_mandatory_mode *stereo_mode) 2555 { 2556 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2557 2558 return mode->hdisplay == stereo_mode->width && 2559 mode->vdisplay == stereo_mode->height && 2560 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2561 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2562 } 2563 2564 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2565 { 2566 const struct drm_display_mode *mode; 2567 int num = data->modes, modes = 0, i, k; 2568 2569 for (k = 0; k < num; k++) { 2570 mode = &data->mode_buf[k]; 2571 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2572 const struct stereo_mandatory_mode *mandatory; 2573 struct drm_display_mode *new_mode; 2574 2575 if (!stereo_match_mandatory(mode, 2576 &stereo_mandatory_modes[i])) 2577 continue; 2578 2579 mandatory = &stereo_mandatory_modes[i]; 2580 new_mode = drm_mode_create(); 2581 if (!new_mode) 2582 continue; 2583 2584 *new_mode = *mode; 2585 new_mode->flags |= mandatory->flags; 2586 drm_add_hdmi_modes(data, new_mode); 2587 drm_mode_destroy(new_mode); 2588 modes++; 2589 } 2590 } 2591 2592 return modes; 2593 } 2594 2595 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2596 const u8 *video_db, u8 video_len, u8 video_index) 2597 { 2598 struct drm_display_mode *newmode; 2599 int modes = 0; 2600 2601 if (structure & (1 << 0)) { 2602 newmode = drm_display_mode_from_vic_index(video_db, 2603 video_len, 2604 video_index); 2605 if (newmode) { 2606 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2607 drm_add_hdmi_modes(data, newmode); 2608 modes++; 2609 drm_mode_destroy(newmode); 2610 } 2611 } 2612 if (structure & (1 << 6)) { 2613 newmode = drm_display_mode_from_vic_index(video_db, 2614 video_len, 2615 video_index); 2616 if (newmode) { 2617 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2618 drm_add_hdmi_modes(data, newmode); 2619 modes++; 2620 drm_mode_destroy(newmode); 2621 } 2622 } 2623 if (structure & (1 << 8)) { 2624 newmode = drm_display_mode_from_vic_index(video_db, 2625 video_len, 2626 video_index); 2627 if (newmode) { 2628 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2629 drm_add_hdmi_modes(data, newmode); 2630 modes++; 2631 drm_mode_destroy(newmode); 2632 } 2633 } 2634 2635 return modes; 2636 } 2637 2638 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2639 { 2640 if (!drm_valid_hdmi_vic(vic)) { 2641 debug("Unknown HDMI VIC: %d\n", vic); 2642 return 0; 2643 } 2644 2645 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2646 2647 return 1; 2648 } 2649 2650 /* 2651 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2652 * @db: start of the CEA vendor specific block 2653 * @len: length of the CEA block payload, ie. one can access up to db[len] 2654 * 2655 * Parses the HDMI VSDB looking for modes to add to @data. This function 2656 * also adds the stereo 3d modes when applicable. 2657 */ 2658 static int 2659 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2660 struct hdmi_edid_data *data) 2661 { 2662 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2663 u8 vic_len, hdmi_3d_len = 0; 2664 u16 mask; 2665 u16 structure_all; 2666 2667 if (len < 8) 2668 goto out; 2669 2670 /* no HDMI_Video_Present */ 2671 if (!(db[8] & (1 << 5))) 2672 goto out; 2673 2674 /* Latency_Fields_Present */ 2675 if (db[8] & (1 << 7)) 2676 offset += 2; 2677 2678 /* I_Latency_Fields_Present */ 2679 if (db[8] & (1 << 6)) 2680 offset += 2; 2681 2682 /* the declared length is not long enough for the 2 first bytes 2683 * of additional video format capabilities 2684 */ 2685 if (len < (8 + offset + 2)) 2686 goto out; 2687 2688 /* 3D_Present */ 2689 offset++; 2690 if (db[8 + offset] & (1 << 7)) { 2691 modes += add_hdmi_mandatory_stereo_modes(data); 2692 2693 /* 3D_Multi_present */ 2694 multi_present = (db[8 + offset] & 0x60) >> 5; 2695 } 2696 2697 offset++; 2698 vic_len = db[8 + offset] >> 5; 2699 hdmi_3d_len = db[8 + offset] & 0x1f; 2700 2701 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2702 u8 vic; 2703 2704 vic = db[9 + offset + i]; 2705 modes += add_hdmi_mode(data, vic); 2706 } 2707 2708 offset += 1 + vic_len; 2709 2710 if (multi_present == 1) 2711 multi_len = 2; 2712 else if (multi_present == 2) 2713 multi_len = 4; 2714 else 2715 multi_len = 0; 2716 2717 if (len < (8 + offset + hdmi_3d_len - 1)) 2718 goto out; 2719 2720 if (hdmi_3d_len < multi_len) 2721 goto out; 2722 2723 if (multi_present == 1 || multi_present == 2) { 2724 /* 3D_Structure_ALL */ 2725 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2726 2727 /* check if 3D_MASK is present */ 2728 if (multi_present == 2) 2729 mask = (db[10 + offset] << 8) | db[11 + offset]; 2730 else 2731 mask = 0xffff; 2732 2733 for (i = 0; i < 16; i++) { 2734 if (mask & (1 << i)) 2735 modes += add_3d_struct_modes(data, 2736 structure_all, 2737 video_db, 2738 video_len, i); 2739 } 2740 } 2741 2742 offset += multi_len; 2743 2744 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2745 int vic_index; 2746 struct drm_display_mode *newmode = NULL; 2747 unsigned int newflag = 0; 2748 bool detail_present; 2749 2750 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2751 2752 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2753 break; 2754 2755 /* 2D_VIC_order_X */ 2756 vic_index = db[8 + offset + i] >> 4; 2757 2758 /* 3D_Structure_X */ 2759 switch (db[8 + offset + i] & 0x0f) { 2760 case 0: 2761 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2762 break; 2763 case 6: 2764 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2765 break; 2766 case 8: 2767 /* 3D_Detail_X */ 2768 if ((db[9 + offset + i] >> 4) == 1) 2769 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2770 break; 2771 } 2772 2773 if (newflag != 0) { 2774 newmode = drm_display_mode_from_vic_index( 2775 video_db, 2776 video_len, 2777 vic_index); 2778 2779 if (newmode) { 2780 newmode->flags |= newflag; 2781 drm_add_hdmi_modes(data, newmode); 2782 modes++; 2783 drm_mode_destroy(newmode); 2784 } 2785 } 2786 2787 if (detail_present) 2788 i++; 2789 } 2790 2791 out: 2792 return modes; 2793 } 2794 2795 /** 2796 * edid_get_quirks - return quirk flags for a given EDID 2797 * @edid: EDID to process 2798 * 2799 * This tells subsequent routines what fixes they need to apply. 2800 */ 2801 static u32 edid_get_quirks(struct edid *edid) 2802 { 2803 struct edid_quirk *quirk; 2804 int i; 2805 2806 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2807 quirk = &edid_quirk_list[i]; 2808 2809 if (edid_vendor(edid, quirk->vendor) && 2810 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2811 return quirk->quirks; 2812 } 2813 2814 return 0; 2815 } 2816 2817 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 2818 const u8 *db) 2819 { 2820 struct drm_display_info *info = &data->display_info; 2821 struct drm_hdmi_info *hdmi = &info->hdmi; 2822 u8 map_len = cea_db_payload_len(db) - 1; 2823 u8 count; 2824 u64 map = 0; 2825 2826 if (map_len == 0) { 2827 /* All CEA modes support ycbcr420 sampling also.*/ 2828 hdmi->y420_cmdb_map = U64_MAX; 2829 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2830 return; 2831 } 2832 2833 /* 2834 * This map indicates which of the existing CEA block modes 2835 * from VDB can support YCBCR420 output too. So if bit=0 is 2836 * set, first mode from VDB can support YCBCR420 output too. 2837 * We will parse and keep this map, before parsing VDB itself 2838 * to avoid going through the same block again and again. 2839 * 2840 * Spec is not clear about max possible size of this block. 2841 * Clamping max bitmap block size at 8 bytes. Every byte can 2842 * address 8 CEA modes, in this way this map can address 2843 * 8*8 = first 64 SVDs. 2844 */ 2845 if (map_len > 8) 2846 map_len = 8; 2847 2848 for (count = 0; count < map_len; count++) 2849 map |= (u64)db[2 + count] << (8 * count); 2850 2851 if (map) 2852 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2853 2854 hdmi->y420_cmdb_map = map; 2855 } 2856 2857 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 2858 const u8 *db) 2859 { 2860 u8 dc_mask; 2861 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2862 2863 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 2864 hdmi->y420_dc_modes |= dc_mask; 2865 } 2866 2867 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 2868 const u8 *hf_vsdb) 2869 { 2870 struct drm_display_info *display = &data->display_info; 2871 struct drm_hdmi_info *hdmi = &display->hdmi; 2872 2873 if (hf_vsdb[6] & 0x80) { 2874 hdmi->scdc.supported = true; 2875 if (hf_vsdb[6] & 0x40) 2876 hdmi->scdc.read_request = true; 2877 } 2878 2879 /* 2880 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 2881 * And as per the spec, three factors confirm this: 2882 * * Availability of a HF-VSDB block in EDID (check) 2883 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 2884 * * SCDC support available (let's check) 2885 * Lets check it out. 2886 */ 2887 2888 if (hf_vsdb[5]) { 2889 /* max clock is 5000 KHz times block value */ 2890 u32 max_tmds_clock = hf_vsdb[5] * 5000; 2891 struct drm_scdc *scdc = &hdmi->scdc; 2892 2893 if (max_tmds_clock > 340000) { 2894 display->max_tmds_clock = max_tmds_clock; 2895 debug("HF-VSDB: max TMDS clock %d kHz\n", 2896 display->max_tmds_clock); 2897 } 2898 2899 if (scdc->supported) { 2900 scdc->scrambling.supported = true; 2901 2902 /* Few sinks support scrambling for cloks < 340M */ 2903 if ((hf_vsdb[6] & 0x8)) 2904 scdc->scrambling.low_rates = true; 2905 } 2906 } 2907 2908 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 2909 } 2910 2911 /** 2912 * drm_default_rgb_quant_range - default RGB quantization range 2913 * @mode: display mode 2914 * 2915 * Determine the default RGB quantization range for the mode, 2916 * as specified in CEA-861. 2917 * 2918 * Return: The default RGB quantization range for the mode 2919 */ 2920 enum hdmi_quantization_range 2921 drm_default_rgb_quant_range(struct drm_display_mode *mode) 2922 { 2923 /* All CEA modes other than VIC 1 use limited quantization range. */ 2924 return drm_match_cea_mode(mode) > 1 ? 2925 HDMI_QUANTIZATION_RANGE_LIMITED : 2926 HDMI_QUANTIZATION_RANGE_FULL; 2927 } 2928 2929 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 2930 const u8 *hdmi) 2931 { 2932 struct drm_display_info *info = &data->display_info; 2933 unsigned int dc_bpc = 0; 2934 2935 /* HDMI supports at least 8 bpc */ 2936 info->bpc = 8; 2937 2938 if (cea_db_payload_len(hdmi) < 6) 2939 return; 2940 2941 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 2942 dc_bpc = 10; 2943 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 2944 debug("HDMI sink does deep color 30.\n"); 2945 } 2946 2947 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 2948 dc_bpc = 12; 2949 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 2950 debug("HDMI sink does deep color 36.\n"); 2951 } 2952 2953 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 2954 dc_bpc = 16; 2955 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 2956 debug("HDMI sink does deep color 48.\n"); 2957 } 2958 2959 if (dc_bpc == 0) { 2960 debug("No deep color support on this HDMI sink.\n"); 2961 return; 2962 } 2963 2964 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 2965 info->bpc = dc_bpc; 2966 2967 /* YCRCB444 is optional according to spec. */ 2968 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 2969 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 2970 debug("HDMI sink does YCRCB444 in deep color.\n"); 2971 } 2972 2973 /* 2974 * Spec says that if any deep color mode is supported at all, 2975 * then deep color 36 bit must be supported. 2976 */ 2977 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 2978 debug("HDMI sink should do DC_36, but does not!\n"); 2979 } 2980 2981 /* 2982 * Search EDID for CEA extension block. 2983 */ 2984 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2985 { 2986 u8 *edid_ext = NULL; 2987 int i; 2988 2989 /* No EDID or EDID extensions */ 2990 if (!edid || !edid->extensions) 2991 return NULL; 2992 2993 /* Find CEA extension */ 2994 for (i = 0; i < edid->extensions; i++) { 2995 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 2996 if (edid_ext[0] == ext_id) 2997 break; 2998 } 2999 3000 if (i == edid->extensions) 3001 return NULL; 3002 3003 return edid_ext; 3004 } 3005 3006 static u8 *drm_find_cea_extension(struct edid *edid) 3007 { 3008 return drm_find_edid_extension(edid, 0x02); 3009 } 3010 3011 #define AUDIO_BLOCK 0x01 3012 #define VIDEO_BLOCK 0x02 3013 #define VENDOR_BLOCK 0x03 3014 #define SPEAKER_BLOCK 0x04 3015 #define EDID_BASIC_AUDIO BIT(6) 3016 3017 /** 3018 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3019 * @edid: monitor EDID information 3020 * 3021 * Parse the CEA extension according to CEA-861-B. 3022 * 3023 * Return: True if the monitor is HDMI, false if not or unknown. 3024 */ 3025 bool drm_detect_hdmi_monitor(struct edid *edid) 3026 { 3027 u8 *edid_ext; 3028 int i; 3029 int start_offset, end_offset; 3030 3031 edid_ext = drm_find_cea_extension(edid); 3032 if (!edid_ext) 3033 return false; 3034 3035 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3036 return false; 3037 3038 /* 3039 * Because HDMI identifier is in Vendor Specific Block, 3040 * search it from all data blocks of CEA extension. 3041 */ 3042 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3043 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3044 return true; 3045 } 3046 3047 return false; 3048 } 3049 3050 /** 3051 * drm_detect_monitor_audio - check monitor audio capability 3052 * @edid: EDID block to scan 3053 * 3054 * Monitor should have CEA extension block. 3055 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3056 * audio' only. If there is any audio extension block and supported 3057 * audio format, assume at least 'basic audio' support, even if 'basic 3058 * audio' is not defined in EDID. 3059 * 3060 * Return: True if the monitor supports audio, false otherwise. 3061 */ 3062 bool drm_detect_monitor_audio(struct edid *edid) 3063 { 3064 u8 *edid_ext; 3065 int i, j; 3066 bool has_audio = false; 3067 int start_offset, end_offset; 3068 3069 edid_ext = drm_find_cea_extension(edid); 3070 if (!edid_ext) 3071 goto end; 3072 3073 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3074 3075 if (has_audio) { 3076 printf("Monitor has basic audio support\n"); 3077 goto end; 3078 } 3079 3080 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3081 goto end; 3082 3083 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3084 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3085 has_audio = true; 3086 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 3087 j += 3) 3088 debug("CEA audio format %d\n", 3089 (edid_ext[i + j] >> 3) & 0xf); 3090 goto end; 3091 } 3092 } 3093 end: 3094 return has_audio; 3095 } 3096 3097 static void 3098 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 3099 { 3100 struct drm_display_info *info = &data->display_info; 3101 u8 len = cea_db_payload_len(db); 3102 3103 if (len >= 6) 3104 info->dvi_dual = db[6] & 1; 3105 if (len >= 7) 3106 info->max_tmds_clock = db[7] * 5000; 3107 3108 drm_parse_hdmi_deep_color_info(data, db); 3109 } 3110 3111 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 3112 struct edid *edid) 3113 { 3114 struct drm_display_info *info = &data->display_info; 3115 const u8 *edid_ext; 3116 int i, start, end; 3117 3118 edid_ext = drm_find_cea_extension(edid); 3119 if (!edid_ext) 3120 return; 3121 3122 info->cea_rev = edid_ext[1]; 3123 3124 /* The existence of a CEA block should imply RGB support */ 3125 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3126 if (edid_ext[3] & EDID_CEA_YCRCB444) 3127 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3128 if (edid_ext[3] & EDID_CEA_YCRCB422) 3129 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3130 3131 if (cea_db_offsets(edid_ext, &start, &end)) 3132 return; 3133 3134 for_each_cea_db(edid_ext, i, start, end) { 3135 const u8 *db = &edid_ext[i]; 3136 3137 if (cea_db_is_hdmi_vsdb(db)) 3138 drm_parse_hdmi_vsdb_video(data, db); 3139 if (cea_db_is_hdmi_forum_vsdb(db)) 3140 drm_parse_hdmi_forum_vsdb(data, db); 3141 if (cea_db_is_y420cmdb(db)) 3142 drm_parse_y420cmdb_bitmap(data, db); 3143 } 3144 } 3145 3146 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 3147 { 3148 struct drm_display_info *info = &data->display_info; 3149 3150 info->width_mm = edid->width_cm * 10; 3151 info->height_mm = edid->height_cm * 10; 3152 3153 /* driver figures it out in this case */ 3154 info->bpc = 0; 3155 info->color_formats = 0; 3156 info->cea_rev = 0; 3157 info->max_tmds_clock = 0; 3158 info->dvi_dual = false; 3159 info->edid_hdmi_dc_modes = 0; 3160 3161 memset(&info->hdmi, 0, sizeof(info->hdmi)); 3162 3163 if (edid->revision < 3) 3164 return; 3165 3166 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3167 return; 3168 3169 drm_parse_cea_ext(data, edid); 3170 3171 /* 3172 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3173 * 3174 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3175 * tells us to assume 8 bpc color depth if the EDID doesn't have 3176 * extensions which tell otherwise. 3177 */ 3178 if ((info->bpc == 0) && (edid->revision < 4) && 3179 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3180 info->bpc = 8; 3181 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3182 } 3183 3184 /* Only defined for 1.4 with digital displays */ 3185 if (edid->revision < 4) 3186 return; 3187 3188 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3189 case DRM_EDID_DIGITAL_DEPTH_6: 3190 info->bpc = 6; 3191 break; 3192 case DRM_EDID_DIGITAL_DEPTH_8: 3193 info->bpc = 8; 3194 break; 3195 case DRM_EDID_DIGITAL_DEPTH_10: 3196 info->bpc = 10; 3197 break; 3198 case DRM_EDID_DIGITAL_DEPTH_12: 3199 info->bpc = 12; 3200 break; 3201 case DRM_EDID_DIGITAL_DEPTH_14: 3202 info->bpc = 14; 3203 break; 3204 case DRM_EDID_DIGITAL_DEPTH_16: 3205 info->bpc = 16; 3206 break; 3207 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3208 default: 3209 info->bpc = 0; 3210 break; 3211 } 3212 3213 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3214 info->bpc); 3215 3216 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3217 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3218 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3219 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3220 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3221 } 3222 3223 static 3224 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3225 { 3226 const u8 *cea = drm_find_cea_extension(edid); 3227 const u8 *db, *hdmi = NULL, *video = NULL; 3228 u8 dbl, hdmi_len, video_len = 0; 3229 int modes = 0; 3230 3231 if (cea && cea_revision(cea) >= 3) { 3232 int i, start, end; 3233 3234 if (cea_db_offsets(cea, &start, &end)) 3235 return 0; 3236 3237 for_each_cea_db(cea, i, start, end) { 3238 db = &cea[i]; 3239 dbl = cea_db_payload_len(db); 3240 3241 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3242 video = db + 1; 3243 video_len = dbl; 3244 modes += do_cea_modes(data, video, dbl); 3245 } else if (cea_db_is_hdmi_vsdb(db)) { 3246 hdmi = db; 3247 hdmi_len = dbl; 3248 } else if (cea_db_is_y420vdb(db)) { 3249 const u8 *vdb420 = &db[2]; 3250 3251 /* Add 4:2:0(only) modes present in EDID */ 3252 modes += do_y420vdb_modes(data, vdb420, 3253 dbl - 1); 3254 } 3255 } 3256 } 3257 3258 /* 3259 * We parse the HDMI VSDB after having added the cea modes as we will 3260 * be patching their flags when the sink supports stereo 3D. 3261 */ 3262 if (hdmi) 3263 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3264 video_len, data); 3265 3266 return modes; 3267 } 3268 3269 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3270 3271 static void 3272 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3273 { 3274 int i, n = 0; 3275 u8 d = ext[0x02]; 3276 u8 *det_base = ext + d; 3277 3278 n = (127 - d) / 18; 3279 for (i = 0; i < n; i++) 3280 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3281 } 3282 3283 static void 3284 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3285 { 3286 unsigned int i, n = min((int)ext[0x02], 6); 3287 u8 *det_base = ext + 5; 3288 3289 if (ext[0x01] != 1) 3290 return; /* unknown version */ 3291 3292 for (i = 0; i < n; i++) 3293 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3294 } 3295 3296 static void 3297 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3298 { 3299 int i; 3300 struct edid *edid = (struct edid *)raw_edid; 3301 3302 if (!edid) 3303 return; 3304 3305 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3306 cb(&edid->detailed_timings[i], closure); 3307 3308 for (i = 1; i <= raw_edid[0x7e]; i++) { 3309 u8 *ext = raw_edid + (i * EDID_SIZE); 3310 3311 switch (*ext) { 3312 case CEA_EXT: 3313 cea_for_each_detailed_block(ext, cb, closure); 3314 break; 3315 case VTB_EXT: 3316 vtb_for_each_detailed_block(ext, cb, closure); 3317 break; 3318 default: 3319 break; 3320 } 3321 } 3322 } 3323 3324 /* 3325 * EDID is delightfully ambiguous about how interlaced modes are to be 3326 * encoded. Our internal representation is of frame height, but some 3327 * HDTV detailed timings are encoded as field height. 3328 * 3329 * The format list here is from CEA, in frame size. Technically we 3330 * should be checking refresh rate too. Whatever. 3331 */ 3332 static void 3333 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3334 struct detailed_pixel_timing *pt) 3335 { 3336 int i; 3337 3338 static const struct { 3339 int w, h; 3340 } cea_interlaced[] = { 3341 { 1920, 1080 }, 3342 { 720, 480 }, 3343 { 1440, 480 }, 3344 { 2880, 480 }, 3345 { 720, 576 }, 3346 { 1440, 576 }, 3347 { 2880, 576 }, 3348 }; 3349 3350 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3351 return; 3352 3353 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3354 if ((mode->hdisplay == cea_interlaced[i].w) && 3355 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3356 mode->vdisplay *= 2; 3357 mode->vsync_start *= 2; 3358 mode->vsync_end *= 2; 3359 mode->vtotal *= 2; 3360 mode->vtotal |= 1; 3361 } 3362 } 3363 3364 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3365 } 3366 3367 /** 3368 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3369 * @edid: EDID block 3370 * @timing: EDID detailed timing info 3371 * @quirks: quirks to apply 3372 * 3373 * An EDID detailed timing block contains enough info for us to create and 3374 * return a new struct drm_display_mode. 3375 */ 3376 static 3377 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3378 struct detailed_timing *timing, 3379 u32 quirks) 3380 { 3381 struct drm_display_mode *mode; 3382 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3383 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3384 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3385 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3386 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3387 unsigned hsync_offset = 3388 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3389 pt->hsync_offset_lo; 3390 unsigned hsync_pulse_width = 3391 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3392 pt->hsync_pulse_width_lo; 3393 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3394 2 | pt->vsync_offset_pulse_width_lo >> 4; 3395 unsigned vsync_pulse_width = 3396 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3397 (pt->vsync_offset_pulse_width_lo & 0xf); 3398 3399 /* ignore tiny modes */ 3400 if (hactive < 64 || vactive < 64) 3401 return NULL; 3402 3403 if (pt->misc & DRM_EDID_PT_STEREO) { 3404 debug("stereo mode not supported\n"); 3405 return NULL; 3406 } 3407 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3408 debug("composite sync not supported\n"); 3409 3410 /* it is incorrect if hsync/vsync width is zero */ 3411 if (!hsync_pulse_width || !vsync_pulse_width) { 3412 debug("Incorrect Detailed timing. "); 3413 debug("Wrong Hsync/Vsync pulse width\n"); 3414 return NULL; 3415 } 3416 3417 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3418 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3419 if (!mode) 3420 return NULL; 3421 3422 goto set_refresh; 3423 } 3424 3425 mode = drm_mode_create(); 3426 if (!mode) 3427 return NULL; 3428 3429 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3430 timing->pixel_clock = cpu_to_le16(1088); 3431 3432 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3433 3434 mode->hdisplay = hactive; 3435 mode->hsync_start = mode->hdisplay + hsync_offset; 3436 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3437 mode->htotal = mode->hdisplay + hblank; 3438 3439 mode->vdisplay = vactive; 3440 mode->vsync_start = mode->vdisplay + vsync_offset; 3441 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3442 mode->vtotal = mode->vdisplay + vblank; 3443 3444 /* Some EDIDs have bogus h/vtotal values */ 3445 if (mode->hsync_end > mode->htotal) 3446 mode->htotal = mode->hsync_end + 1; 3447 if (mode->vsync_end > mode->vtotal) 3448 mode->vtotal = mode->vsync_end + 1; 3449 3450 drm_mode_do_interlace_quirk(mode, pt); 3451 3452 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3453 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3454 DRM_EDID_PT_VSYNC_POSITIVE; 3455 3456 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3457 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3458 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3459 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3460 3461 set_refresh: 3462 3463 mode->type = DRM_MODE_TYPE_DRIVER; 3464 mode->vrefresh = drm_get_vrefresh(mode); 3465 3466 return mode; 3467 } 3468 3469 /* 3470 * Calculate the alternate clock for the CEA mode 3471 * (60Hz vs. 59.94Hz etc.) 3472 */ 3473 static unsigned int 3474 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3475 { 3476 unsigned int clock = cea_mode->clock; 3477 3478 if (cea_mode->vrefresh % 6 != 0) 3479 return clock; 3480 3481 /* 3482 * edid_cea_modes contains the 59.94Hz 3483 * variant for 240 and 480 line modes, 3484 * and the 60Hz variant otherwise. 3485 */ 3486 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3487 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3488 else 3489 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3490 3491 return clock; 3492 } 3493 3494 /** 3495 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3496 * @mode1: first mode 3497 * @mode2: second mode 3498 * 3499 * Check to see if @mode1 and @mode2 are equivalent, but 3500 * don't check the pixel clocks nor the stereo layout. 3501 * 3502 * Returns: 3503 * True if the modes are equal, false otherwise. 3504 */ 3505 3506 static 3507 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3508 const struct drm_display_mode *mode2) 3509 { 3510 unsigned int flags_mask = 3511 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3512 3513 if (mode1->hdisplay == mode2->hdisplay && 3514 mode1->hsync_start == mode2->hsync_start && 3515 mode1->hsync_end == mode2->hsync_end && 3516 mode1->htotal == mode2->htotal && 3517 mode1->vdisplay == mode2->vdisplay && 3518 mode1->vsync_start == mode2->vsync_start && 3519 mode1->vsync_end == mode2->vsync_end && 3520 mode1->vtotal == mode2->vtotal && 3521 mode1->vscan == mode2->vscan && 3522 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3523 return true; 3524 3525 return false; 3526 } 3527 3528 /** 3529 * drm_mode_equal_no_clocks - test modes for equality 3530 * @mode1: first mode 3531 * @mode2: second mode 3532 * 3533 * Check to see if @mode1 and @mode2 are equivalent, but 3534 * don't check the pixel clocks. 3535 * 3536 * Returns: 3537 * True if the modes are equal, false otherwise. 3538 */ 3539 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3540 const struct drm_display_mode *mode2) 3541 { 3542 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3543 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3544 return false; 3545 3546 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3547 } 3548 3549 static 3550 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3551 unsigned int clock_tolerance) 3552 { 3553 u8 vic; 3554 3555 if (!to_match->clock) 3556 return 0; 3557 3558 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3559 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 3560 unsigned int clock1, clock2; 3561 3562 /* Check both 60Hz and 59.94Hz */ 3563 clock1 = cea_mode->clock; 3564 clock2 = cea_mode_alternate_clock(cea_mode); 3565 3566 if (abs(to_match->clock - clock1) > clock_tolerance && 3567 abs(to_match->clock - clock2) > clock_tolerance) 3568 continue; 3569 3570 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3571 return vic; 3572 } 3573 3574 return 0; 3575 } 3576 3577 static unsigned int 3578 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3579 { 3580 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3581 return hdmi_mode->clock; 3582 3583 return cea_mode_alternate_clock(hdmi_mode); 3584 } 3585 3586 static 3587 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3588 unsigned int clock_tolerance) 3589 { 3590 u8 vic; 3591 3592 if (!to_match->clock) 3593 return 0; 3594 3595 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3596 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3597 unsigned int clock1, clock2; 3598 3599 /* Make sure to also match alternate clocks */ 3600 clock1 = hdmi_mode->clock; 3601 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3602 3603 if (abs(to_match->clock - clock1) > clock_tolerance && 3604 abs(to_match->clock - clock2) > clock_tolerance) 3605 continue; 3606 3607 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3608 return vic; 3609 } 3610 3611 return 0; 3612 } 3613 3614 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3615 { 3616 const struct drm_display_mode *cea_mode; 3617 int clock1, clock2, clock; 3618 u8 vic; 3619 const char *type; 3620 3621 /* 3622 * allow 5kHz clock difference either way to account for 3623 * the 10kHz clock resolution limit of detailed timings. 3624 */ 3625 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3626 if (drm_valid_cea_vic(vic)) { 3627 type = "CEA"; 3628 cea_mode = &edid_cea_modes[vic]; 3629 clock1 = cea_mode->clock; 3630 clock2 = cea_mode_alternate_clock(cea_mode); 3631 } else { 3632 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3633 if (drm_valid_hdmi_vic(vic)) { 3634 type = "HDMI"; 3635 cea_mode = &edid_4k_modes[vic]; 3636 clock1 = cea_mode->clock; 3637 clock2 = hdmi_mode_alternate_clock(cea_mode); 3638 } else { 3639 return; 3640 } 3641 } 3642 3643 /* pick whichever is closest */ 3644 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3645 clock = clock1; 3646 else 3647 clock = clock2; 3648 3649 if (mode->clock == clock) 3650 return; 3651 3652 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3653 type, vic, mode->clock, clock); 3654 mode->clock = clock; 3655 } 3656 3657 static void 3658 do_detailed_mode(struct detailed_timing *timing, void *c) 3659 { 3660 struct detailed_mode_closure *closure = c; 3661 struct drm_display_mode *newmode; 3662 3663 if (timing->pixel_clock) { 3664 newmode = drm_mode_detailed( 3665 closure->edid, timing, 3666 closure->quirks); 3667 if (!newmode) 3668 return; 3669 3670 if (closure->preferred) 3671 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3672 3673 /* 3674 * Detailed modes are limited to 10kHz pixel clock resolution, 3675 * so fix up anything that looks like CEA/HDMI mode, 3676 * but the clock is just slightly off. 3677 */ 3678 fixup_detailed_cea_mode_clock(newmode); 3679 drm_add_hdmi_modes(closure->data, newmode); 3680 drm_mode_destroy(newmode); 3681 closure->modes++; 3682 closure->preferred = 0; 3683 } 3684 } 3685 3686 /* 3687 * add_detailed_modes - Add modes from detailed timings 3688 * @data: attached data 3689 * @edid: EDID block to scan 3690 * @quirks: quirks to apply 3691 */ 3692 static int 3693 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 3694 u32 quirks) 3695 { 3696 struct detailed_mode_closure closure = { 3697 .data = data, 3698 .edid = edid, 3699 .preferred = 1, 3700 .quirks = quirks, 3701 }; 3702 3703 if (closure.preferred && !version_greater(edid, 1, 3)) 3704 closure.preferred = 3705 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3706 3707 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3708 3709 return closure.modes; 3710 } 3711 3712 static int drm_cvt_modes(struct hdmi_edid_data *data, 3713 struct detailed_timing *timing) 3714 { 3715 int i, j, modes = 0; 3716 struct drm_display_mode *newmode; 3717 struct cvt_timing *cvt; 3718 const int rates[] = { 60, 85, 75, 60, 50 }; 3719 const u8 empty[3] = { 0, 0, 0 }; 3720 3721 for (i = 0; i < 4; i++) { 3722 int uninitialized_var(width), height; 3723 3724 cvt = &timing->data.other_data.data.cvt[i]; 3725 3726 if (!memcmp(cvt->code, empty, 3)) 3727 continue; 3728 3729 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3730 switch (cvt->code[1] & 0x0c) { 3731 case 0x00: 3732 width = height * 4 / 3; 3733 break; 3734 case 0x04: 3735 width = height * 16 / 9; 3736 break; 3737 case 0x08: 3738 width = height * 16 / 10; 3739 break; 3740 case 0x0c: 3741 width = height * 15 / 9; 3742 break; 3743 } 3744 3745 for (j = 1; j < 5; j++) { 3746 if (cvt->code[2] & (1 << j)) { 3747 newmode = drm_cvt_mode(width, height, 3748 rates[j], j == 0, 3749 false, false); 3750 if (newmode) { 3751 drm_add_hdmi_modes(data, newmode); 3752 modes++; 3753 drm_mode_destroy(newmode); 3754 } 3755 } 3756 } 3757 } 3758 3759 return modes; 3760 } 3761 3762 static void 3763 do_cvt_mode(struct detailed_timing *timing, void *c) 3764 { 3765 struct detailed_mode_closure *closure = c; 3766 struct detailed_non_pixel *data = &timing->data.other_data; 3767 3768 if (data->type == EDID_DETAIL_CVT_3BYTE) 3769 closure->modes += drm_cvt_modes(closure->data, timing); 3770 } 3771 3772 static int 3773 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 3774 { 3775 struct detailed_mode_closure closure = { 3776 .data = data, 3777 .edid = edid, 3778 }; 3779 3780 if (version_greater(edid, 1, 2)) 3781 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3782 3783 /* XXX should also look for CVT codes in VTB blocks */ 3784 3785 return closure.modes; 3786 } 3787 3788 static void 3789 find_gtf2(struct detailed_timing *t, void *data) 3790 { 3791 u8 *r = (u8 *)t; 3792 3793 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 3794 *(u8 **)data = r; 3795 } 3796 3797 /* Secondary GTF curve kicks in above some break frequency */ 3798 static int 3799 drm_gtf2_hbreak(struct edid *edid) 3800 { 3801 u8 *r = NULL; 3802 3803 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3804 return r ? (r[12] * 2) : 0; 3805 } 3806 3807 static int 3808 drm_gtf2_2c(struct edid *edid) 3809 { 3810 u8 *r = NULL; 3811 3812 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3813 return r ? r[13] : 0; 3814 } 3815 3816 static int 3817 drm_gtf2_m(struct edid *edid) 3818 { 3819 u8 *r = NULL; 3820 3821 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3822 return r ? (r[15] << 8) + r[14] : 0; 3823 } 3824 3825 static int 3826 drm_gtf2_k(struct edid *edid) 3827 { 3828 u8 *r = NULL; 3829 3830 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3831 return r ? r[16] : 0; 3832 } 3833 3834 static int 3835 drm_gtf2_2j(struct edid *edid) 3836 { 3837 u8 *r = NULL; 3838 3839 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3840 return r ? r[17] : 0; 3841 } 3842 3843 /** 3844 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 3845 * @edid: EDID block to scan 3846 */ 3847 static int standard_timing_level(struct edid *edid) 3848 { 3849 if (edid->revision >= 2) { 3850 if (edid->revision >= 4 && 3851 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 3852 return LEVEL_CVT; 3853 if (drm_gtf2_hbreak(edid)) 3854 return LEVEL_GTF2; 3855 return LEVEL_GTF; 3856 } 3857 return LEVEL_DMT; 3858 } 3859 3860 /* 3861 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3862 * monitors fill with ascii space (0x20) instead. 3863 */ 3864 static int 3865 bad_std_timing(u8 a, u8 b) 3866 { 3867 return (a == 0x00 && b == 0x00) || 3868 (a == 0x01 && b == 0x01) || 3869 (a == 0x20 && b == 0x20); 3870 } 3871 3872 static void 3873 is_rb(struct detailed_timing *t, void *data) 3874 { 3875 u8 *r = (u8 *)t; 3876 3877 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 3878 if (r[15] & 0x10) 3879 *(bool *)data = true; 3880 } 3881 3882 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3883 static bool 3884 drm_monitor_supports_rb(struct edid *edid) 3885 { 3886 if (edid->revision >= 4) { 3887 bool ret = false; 3888 3889 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 3890 return ret; 3891 } 3892 3893 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3894 } 3895 3896 static bool 3897 mode_is_rb(const struct drm_display_mode *mode) 3898 { 3899 return (mode->htotal - mode->hdisplay == 160) && 3900 (mode->hsync_end - mode->hdisplay == 80) && 3901 (mode->hsync_end - mode->hsync_start == 32) && 3902 (mode->vsync_start - mode->vdisplay == 3); 3903 } 3904 3905 /* 3906 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3907 * @hsize: Mode width 3908 * @vsize: Mode height 3909 * @fresh: Mode refresh rate 3910 * @rb: Mode reduced-blanking-ness 3911 * 3912 * Walk the DMT mode list looking for a match for the given parameters. 3913 * 3914 * Return: A newly allocated copy of the mode, or NULL if not found. 3915 */ 3916 static struct drm_display_mode *drm_mode_find_dmt( 3917 int hsize, int vsize, int fresh, 3918 bool rb) 3919 { 3920 int i; 3921 struct drm_display_mode *newmode; 3922 3923 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3924 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3925 3926 if (hsize != ptr->hdisplay) 3927 continue; 3928 if (vsize != ptr->vdisplay) 3929 continue; 3930 if (fresh != drm_get_vrefresh(ptr)) 3931 continue; 3932 if (rb != mode_is_rb(ptr)) 3933 continue; 3934 3935 newmode = drm_mode_create(); 3936 *newmode = *ptr; 3937 return newmode; 3938 } 3939 3940 return NULL; 3941 } 3942 3943 static struct drm_display_mode * 3944 drm_gtf_mode_complex(int hdisplay, int vdisplay, 3945 int vrefresh, bool interlaced, int margins, 3946 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 3947 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 3948 #define GTF_MARGIN_PERCENTAGE 18 3949 /* 2) character cell horizontal granularity (pixels) - default 8 */ 3950 #define GTF_CELL_GRAN 8 3951 /* 3) Minimum vertical porch (lines) - default 3 */ 3952 #define GTF_MIN_V_PORCH 1 3953 /* width of vsync in lines */ 3954 #define V_SYNC_RQD 3 3955 /* width of hsync as % of total line */ 3956 #define H_SYNC_PERCENT 8 3957 /* min time of vsync + back porch (microsec) */ 3958 #define MIN_VSYNC_PLUS_BP 550 3959 /* C' and M' are part of the Blanking Duty Cycle computation */ 3960 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 3961 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 3962 struct drm_display_mode *drm_mode; 3963 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 3964 int top_margin, bottom_margin; 3965 int interlace; 3966 unsigned int hfreq_est; 3967 int vsync_plus_bp; 3968 unsigned int vtotal_lines; 3969 int left_margin, right_margin; 3970 unsigned int total_active_pixels, ideal_duty_cycle; 3971 unsigned int hblank, total_pixels, pixel_freq; 3972 int hsync, hfront_porch, vodd_front_porch_lines; 3973 unsigned int tmp1, tmp2; 3974 3975 drm_mode = drm_mode_create(); 3976 if (!drm_mode) 3977 return NULL; 3978 3979 /* 1. In order to give correct results, the number of horizontal 3980 * pixels requested is first processed to ensure that it is divisible 3981 * by the character size, by rounding it to the nearest character 3982 * cell boundary: 3983 */ 3984 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3985 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 3986 3987 /* 2. If interlace is requested, the number of vertical lines assumed 3988 * by the calculation must be halved, as the computation calculates 3989 * the number of vertical lines per field. 3990 */ 3991 if (interlaced) 3992 vdisplay_rnd = vdisplay / 2; 3993 else 3994 vdisplay_rnd = vdisplay; 3995 3996 /* 3. Find the frame rate required: */ 3997 if (interlaced) 3998 vfieldrate_rqd = vrefresh * 2; 3999 else 4000 vfieldrate_rqd = vrefresh; 4001 4002 /* 4. Find number of lines in Top margin: */ 4003 top_margin = 0; 4004 if (margins) 4005 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4006 1000; 4007 /* 5. Find number of lines in bottom margin: */ 4008 bottom_margin = top_margin; 4009 4010 /* 6. If interlace is required, then set variable interlace: */ 4011 if (interlaced) 4012 interlace = 1; 4013 else 4014 interlace = 0; 4015 4016 /* 7. Estimate the Horizontal frequency */ 4017 { 4018 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 4019 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 4020 2 + interlace; 4021 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 4022 } 4023 4024 /* 8. Find the number of lines in V sync + back porch */ 4025 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 4026 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 4027 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 4028 /* 9. Find the number of lines in V back porch alone: 4029 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 4030 */ 4031 /* 10. Find the total number of lines in Vertical field period: */ 4032 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 4033 vsync_plus_bp + GTF_MIN_V_PORCH; 4034 /* 11. Estimate the Vertical field frequency: 4035 * vfieldrate_est = hfreq_est / vtotal_lines; 4036 */ 4037 4038 /* 12. Find the actual horizontal period: 4039 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 4040 */ 4041 /* 13. Find the actual Vertical field frequency: 4042 * vfield_rate = hfreq_est / vtotal_lines; 4043 */ 4044 /* 14. Find the Vertical frame frequency: 4045 * if (interlaced) 4046 * vframe_rate = vfield_rate / 2; 4047 * else 4048 * vframe_rate = vfield_rate; 4049 */ 4050 /* 15. Find number of pixels in left margin: */ 4051 if (margins) 4052 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4053 1000; 4054 else 4055 left_margin = 0; 4056 4057 /* 16.Find number of pixels in right margin: */ 4058 right_margin = left_margin; 4059 /* 17.Find total number of active pixels in image and left and right */ 4060 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 4061 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 4062 ideal_duty_cycle = GTF_C_PRIME * 1000 - 4063 (GTF_M_PRIME * 1000000 / hfreq_est); 4064 /* 19.Find the number of pixels in the blanking time to the nearest 4065 * double character cell: 4066 */ 4067 hblank = total_active_pixels * ideal_duty_cycle / 4068 (100000 - ideal_duty_cycle); 4069 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 4070 hblank = hblank * 2 * GTF_CELL_GRAN; 4071 /* 20.Find total number of pixels: */ 4072 total_pixels = total_active_pixels + hblank; 4073 /* 21.Find pixel clock frequency: */ 4074 pixel_freq = total_pixels * hfreq_est / 1000; 4075 /* Stage 1 computations are now complete; I should really pass 4076 * the results to another function and do the Stage 2 computations, 4077 * but I only need a few more values so I'll just append the 4078 * computations here for now 4079 */ 4080 4081 /* 17. Find the number of pixels in the horizontal sync period: */ 4082 hsync = H_SYNC_PERCENT * total_pixels / 100; 4083 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4084 hsync = hsync * GTF_CELL_GRAN; 4085 /* 18. Find the number of pixels in horizontal front porch period */ 4086 hfront_porch = hblank / 2 - hsync; 4087 /* 36. Find the number of lines in the odd front porch period: */ 4088 vodd_front_porch_lines = GTF_MIN_V_PORCH; 4089 4090 /* finally, pack the results in the mode struct */ 4091 drm_mode->hdisplay = hdisplay_rnd; 4092 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 4093 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 4094 drm_mode->htotal = total_pixels; 4095 drm_mode->vdisplay = vdisplay_rnd; 4096 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 4097 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 4098 drm_mode->vtotal = vtotal_lines; 4099 4100 drm_mode->clock = pixel_freq; 4101 4102 if (interlaced) { 4103 drm_mode->vtotal *= 2; 4104 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 4105 } 4106 4107 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 4108 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 4109 else 4110 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 4111 4112 return drm_mode; 4113 } 4114 4115 /** 4116 * drm_gtf_mode - create the mode based on the GTF algorithm 4117 * @hdisplay: hdisplay size 4118 * @vdisplay: vdisplay size 4119 * @vrefresh: vrefresh rate. 4120 * @interlaced: whether to compute an interlaced mode 4121 * @margins: desired margin (borders) size 4122 * 4123 * return the mode based on GTF algorithm 4124 * 4125 * This function is to create the mode based on the GTF algorithm. 4126 * Generalized Timing Formula is derived from: 4127 * GTF Spreadsheet by Andy Morrish (1/5/97) 4128 * available at http://www.vesa.org 4129 * 4130 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 4131 * What I have done is to translate it by using integer calculation. 4132 * I also refer to the function of fb_get_mode in the file of 4133 * drivers/video/fbmon.c 4134 * 4135 * Standard GTF parameters: 4136 * M = 600 4137 * C = 40 4138 * K = 128 4139 * J = 20 4140 * 4141 * Returns: 4142 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 4143 * The display mode object is allocated with drm_mode_create(). Returns NULL 4144 * when no mode could be allocated. 4145 */ 4146 static struct drm_display_mode * 4147 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 4148 bool interlaced, int margins) 4149 { 4150 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 4151 interlaced, margins, 4152 600, 40 * 2, 128, 20 * 2); 4153 } 4154 4155 /** drm_mode_hsync - get the hsync of a mode 4156 * @mode: mode 4157 * 4158 * Returns: 4159 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 4160 * value first if it is not yet set. 4161 */ 4162 static int drm_mode_hsync(const struct drm_display_mode *mode) 4163 { 4164 unsigned int calc_val; 4165 4166 if (mode->htotal < 0) 4167 return 0; 4168 4169 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 4170 calc_val += 500; /* round to 1000Hz */ 4171 calc_val /= 1000; /* truncate to kHz */ 4172 4173 return calc_val; 4174 } 4175 4176 /** 4177 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 4178 * @data: the structure that save parsed hdmi edid data 4179 * @edid: EDID block to scan 4180 * @t: standard timing params 4181 * 4182 * Take the standard timing params (in this case width, aspect, and refresh) 4183 * and convert them into a real mode using CVT/GTF/DMT. 4184 */ 4185 static struct drm_display_mode * 4186 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4187 struct std_timing *t) 4188 { 4189 struct drm_display_mode *mode = NULL; 4190 int i, hsize, vsize; 4191 int vrefresh_rate; 4192 int num = data->modes; 4193 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4194 >> EDID_TIMING_ASPECT_SHIFT; 4195 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4196 >> EDID_TIMING_VFREQ_SHIFT; 4197 int timing_level = standard_timing_level(edid); 4198 4199 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4200 return NULL; 4201 4202 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4203 hsize = t->hsize * 8 + 248; 4204 /* vrefresh_rate = vfreq + 60 */ 4205 vrefresh_rate = vfreq + 60; 4206 /* the vdisplay is calculated based on the aspect ratio */ 4207 if (aspect_ratio == 0) { 4208 if (edid->revision < 3) 4209 vsize = hsize; 4210 else 4211 vsize = (hsize * 10) / 16; 4212 } else if (aspect_ratio == 1) { 4213 vsize = (hsize * 3) / 4; 4214 } else if (aspect_ratio == 2) { 4215 vsize = (hsize * 4) / 5; 4216 } else { 4217 vsize = (hsize * 9) / 16; 4218 } 4219 4220 /* HDTV hack, part 1 */ 4221 if (vrefresh_rate == 60 && 4222 ((hsize == 1360 && vsize == 765) || 4223 (hsize == 1368 && vsize == 769))) { 4224 hsize = 1366; 4225 vsize = 768; 4226 } 4227 4228 /* 4229 * If we already has a mode for this size and refresh 4230 * rate (because it came from detailed or CVT info), use that 4231 * instead. This way we don't have to guess at interlace or 4232 * reduced blanking. 4233 */ 4234 for (i = 0; i < num; i++) 4235 if (data->mode_buf[i].hdisplay == hsize && 4236 data->mode_buf[i].vdisplay == vsize && 4237 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4238 return NULL; 4239 4240 /* HDTV hack, part 2 */ 4241 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4242 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4243 false); 4244 mode->hdisplay = 1366; 4245 mode->hsync_start = mode->hsync_start - 1; 4246 mode->hsync_end = mode->hsync_end - 1; 4247 return mode; 4248 } 4249 4250 /* check whether it can be found in default mode table */ 4251 if (drm_monitor_supports_rb(edid)) { 4252 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4253 true); 4254 if (mode) 4255 return mode; 4256 } 4257 4258 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4259 if (mode) 4260 return mode; 4261 4262 /* okay, generate it */ 4263 switch (timing_level) { 4264 case LEVEL_DMT: 4265 break; 4266 case LEVEL_GTF: 4267 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4268 break; 4269 case LEVEL_GTF2: 4270 /* 4271 * This is potentially wrong if there's ever a monitor with 4272 * more than one ranges section, each claiming a different 4273 * secondary GTF curve. Please don't do that. 4274 */ 4275 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4276 if (!mode) 4277 return NULL; 4278 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4279 drm_mode_destroy(mode); 4280 mode = drm_gtf_mode_complex(hsize, vsize, 4281 vrefresh_rate, 0, 0, 4282 drm_gtf2_m(edid), 4283 drm_gtf2_2c(edid), 4284 drm_gtf2_k(edid), 4285 drm_gtf2_2j(edid)); 4286 } 4287 break; 4288 case LEVEL_CVT: 4289 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4290 false); 4291 break; 4292 } 4293 4294 return mode; 4295 } 4296 4297 static void 4298 do_standard_modes(struct detailed_timing *timing, void *c) 4299 { 4300 struct detailed_mode_closure *closure = c; 4301 struct detailed_non_pixel *data = &timing->data.other_data; 4302 struct edid *edid = closure->edid; 4303 4304 if (data->type == EDID_DETAIL_STD_MODES) { 4305 int i; 4306 4307 for (i = 0; i < 6; i++) { 4308 struct std_timing *std; 4309 struct drm_display_mode *newmode; 4310 4311 std = &data->data.timings[i]; 4312 newmode = drm_mode_std(closure->data, edid, std); 4313 if (newmode) { 4314 drm_add_hdmi_modes(closure->data, newmode); 4315 closure->modes++; 4316 drm_mode_destroy(newmode); 4317 } 4318 } 4319 } 4320 } 4321 4322 /** 4323 * add_standard_modes - get std. modes from EDID and add them 4324 * @data: data to add mode(s) to 4325 * @edid: EDID block to scan 4326 * 4327 * Standard modes can be calculated using the appropriate standard (DMT, 4328 * GTF or CVT. Grab them from @edid and add them to the list. 4329 */ 4330 static int 4331 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4332 { 4333 int i, modes = 0; 4334 struct detailed_mode_closure closure = { 4335 .data = data, 4336 .edid = edid, 4337 }; 4338 4339 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4340 struct drm_display_mode *newmode; 4341 4342 newmode = drm_mode_std(data, edid, 4343 &edid->standard_timings[i]); 4344 if (newmode) { 4345 drm_add_hdmi_modes(data, newmode); 4346 modes++; 4347 drm_mode_destroy(newmode); 4348 } 4349 } 4350 4351 if (version_greater(edid, 1, 0)) 4352 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4353 &closure); 4354 4355 /* XXX should also look for standard codes in VTB blocks */ 4356 4357 return modes + closure.modes; 4358 } 4359 4360 static int 4361 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4362 { 4363 int i, j, m, modes = 0; 4364 struct drm_display_mode *mode; 4365 u8 *est = ((u8 *)timing) + 6; 4366 4367 for (i = 0; i < 6; i++) { 4368 for (j = 7; j >= 0; j--) { 4369 m = (i * 8) + (7 - j); 4370 if (m >= ARRAY_SIZE(est3_modes)) 4371 break; 4372 if (est[i] & (1 << j)) { 4373 mode = drm_mode_find_dmt( 4374 est3_modes[m].w, 4375 est3_modes[m].h, 4376 est3_modes[m].r, 4377 est3_modes[m].rb); 4378 if (mode) { 4379 drm_add_hdmi_modes(data, mode); 4380 modes++; 4381 drm_mode_destroy(mode); 4382 } 4383 } 4384 } 4385 } 4386 4387 return modes; 4388 } 4389 4390 static void 4391 do_established_modes(struct detailed_timing *timing, void *c) 4392 { 4393 struct detailed_mode_closure *closure = c; 4394 struct detailed_non_pixel *data = &timing->data.other_data; 4395 4396 if (data->type == EDID_DETAIL_EST_TIMINGS) 4397 closure->modes += drm_est3_modes(closure->data, timing); 4398 } 4399 4400 /** 4401 * add_established_modes - get est. modes from EDID and add them 4402 * @data: data to add mode(s) to 4403 * @edid: EDID block to scan 4404 * 4405 * Each EDID block contains a bitmap of the supported "established modes" list 4406 * (defined above). Tease them out and add them to the modes list. 4407 */ 4408 static int 4409 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4410 { 4411 unsigned long est_bits = edid->established_timings.t1 | 4412 (edid->established_timings.t2 << 8) | 4413 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4414 int i, modes = 0; 4415 struct detailed_mode_closure closure = { 4416 .data = data, 4417 .edid = edid, 4418 }; 4419 4420 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4421 if (est_bits & (1 << i)) { 4422 struct drm_display_mode *newmode = drm_mode_create(); 4423 *newmode = edid_est_modes[i]; 4424 if (newmode) { 4425 drm_add_hdmi_modes(data, newmode); 4426 modes++; 4427 drm_mode_destroy(newmode); 4428 } 4429 } 4430 } 4431 4432 if (version_greater(edid, 1, 0)) 4433 drm_for_each_detailed_block((u8 *)edid, 4434 do_established_modes, &closure); 4435 4436 return modes + closure.modes; 4437 } 4438 4439 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4440 { 4441 u8 vic; 4442 4443 if (!to_match->clock) 4444 return 0; 4445 4446 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4447 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4448 unsigned int clock1, clock2; 4449 4450 /* Make sure to also match alternate clocks */ 4451 clock1 = hdmi_mode->clock; 4452 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4453 4454 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4455 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4456 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4457 return vic; 4458 } 4459 return 0; 4460 } 4461 4462 static int 4463 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4464 { 4465 struct drm_display_mode *mode; 4466 int i, num, modes = 0; 4467 4468 /* Don't add CEA modes if the CEA extension block is missing */ 4469 if (!drm_find_cea_extension(edid)) 4470 return 0; 4471 4472 /* 4473 * Go through all probed modes and create a new mode 4474 * with the alternate clock for certain CEA modes. 4475 */ 4476 num = data->modes; 4477 4478 for (i = 0; i < num; i++) { 4479 const struct drm_display_mode *cea_mode = NULL; 4480 struct drm_display_mode *newmode; 4481 u8 vic; 4482 unsigned int clock1, clock2; 4483 4484 mode = &data->mode_buf[i]; 4485 vic = drm_match_cea_mode(mode); 4486 4487 if (drm_valid_cea_vic(vic)) { 4488 cea_mode = &edid_cea_modes[vic]; 4489 clock2 = cea_mode_alternate_clock(cea_mode); 4490 } else { 4491 vic = drm_match_hdmi_mode(mode); 4492 if (drm_valid_hdmi_vic(vic)) { 4493 cea_mode = &edid_4k_modes[vic]; 4494 clock2 = hdmi_mode_alternate_clock(cea_mode); 4495 } 4496 } 4497 4498 if (!cea_mode) 4499 continue; 4500 4501 clock1 = cea_mode->clock; 4502 4503 if (clock1 == clock2) 4504 continue; 4505 4506 if (mode->clock != clock1 && mode->clock != clock2) 4507 continue; 4508 4509 newmode = drm_mode_create(); 4510 *newmode = *cea_mode; 4511 if (!newmode) 4512 continue; 4513 4514 /* Carry over the stereo flags */ 4515 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4516 4517 /* 4518 * The current mode could be either variant. Make 4519 * sure to pick the "other" clock for the new mode. 4520 */ 4521 if (mode->clock != clock1) 4522 newmode->clock = clock1; 4523 else 4524 newmode->clock = clock2; 4525 4526 drm_add_hdmi_modes(data, newmode); 4527 modes++; 4528 drm_mode_destroy(newmode); 4529 } 4530 4531 return modes; 4532 } 4533 4534 static u8 *drm_find_displayid_extension(struct edid *edid) 4535 { 4536 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4537 } 4538 4539 static int validate_displayid(u8 *displayid, int length, int idx) 4540 { 4541 int i; 4542 u8 csum = 0; 4543 struct displayid_hdr *base; 4544 4545 base = (struct displayid_hdr *)&displayid[idx]; 4546 4547 debug("base revision 0x%x, length %d, %d %d\n", 4548 base->rev, base->bytes, base->prod_id, base->ext_count); 4549 4550 if (base->bytes + 5 > length - idx) 4551 return -EINVAL; 4552 for (i = idx; i <= base->bytes + 5; i++) 4553 csum += displayid[i]; 4554 if (csum) { 4555 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4556 return -EINVAL; 4557 } 4558 return 0; 4559 } 4560 4561 static struct 4562 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4563 *timings) 4564 { 4565 struct drm_display_mode *mode; 4566 unsigned pixel_clock = (timings->pixel_clock[0] | 4567 (timings->pixel_clock[1] << 8) | 4568 (timings->pixel_clock[2] << 16)); 4569 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4570 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4571 unsigned hsync = (timings->hsync[0] | 4572 (timings->hsync[1] & 0x7f) << 8) + 1; 4573 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4574 unsigned vactive = (timings->vactive[0] | 4575 timings->vactive[1] << 8) + 1; 4576 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4577 unsigned vsync = (timings->vsync[0] | 4578 (timings->vsync[1] & 0x7f) << 8) + 1; 4579 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4580 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4581 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4582 4583 mode = drm_mode_create(); 4584 if (!mode) 4585 return NULL; 4586 4587 mode->clock = pixel_clock * 10; 4588 mode->hdisplay = hactive; 4589 mode->hsync_start = mode->hdisplay + hsync; 4590 mode->hsync_end = mode->hsync_start + hsync_width; 4591 mode->htotal = mode->hdisplay + hblank; 4592 4593 mode->vdisplay = vactive; 4594 mode->vsync_start = mode->vdisplay + vsync; 4595 mode->vsync_end = mode->vsync_start + vsync_width; 4596 mode->vtotal = mode->vdisplay + vblank; 4597 4598 mode->flags = 0; 4599 mode->flags |= 4600 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4601 mode->flags |= 4602 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4603 mode->type = DRM_MODE_TYPE_DRIVER; 4604 4605 if (timings->flags & 0x80) 4606 mode->type |= DRM_MODE_TYPE_PREFERRED; 4607 mode->vrefresh = drm_get_vrefresh(mode); 4608 4609 return mode; 4610 } 4611 4612 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 4613 struct displayid_block *block) 4614 { 4615 struct displayid_detailed_timing_block *det; 4616 int i; 4617 int num_timings; 4618 struct drm_display_mode *newmode; 4619 int num_modes = 0; 4620 4621 det = (struct displayid_detailed_timing_block *)block; 4622 /* blocks must be multiple of 20 bytes length */ 4623 if (block->num_bytes % 20) 4624 return 0; 4625 4626 num_timings = block->num_bytes / 20; 4627 for (i = 0; i < num_timings; i++) { 4628 struct displayid_detailed_timings_1 *timings = 4629 &det->timings[i]; 4630 4631 newmode = drm_displayid_detailed(timings); 4632 if (!newmode) 4633 continue; 4634 4635 drm_add_hdmi_modes(data, newmode); 4636 num_modes++; 4637 drm_mode_destroy(newmode); 4638 } 4639 return num_modes; 4640 } 4641 4642 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 4643 struct edid *edid) 4644 { 4645 u8 *displayid; 4646 int ret; 4647 int idx = 1; 4648 int length = EDID_SIZE; 4649 struct displayid_block *block; 4650 int num_modes = 0; 4651 4652 displayid = drm_find_displayid_extension(edid); 4653 if (!displayid) 4654 return 0; 4655 4656 ret = validate_displayid(displayid, length, idx); 4657 if (ret) 4658 return 0; 4659 4660 idx += sizeof(struct displayid_hdr); 4661 while (block = (struct displayid_block *)&displayid[idx], 4662 idx + sizeof(struct displayid_block) <= length && 4663 idx + sizeof(struct displayid_block) + block->num_bytes <= 4664 length && block->num_bytes > 0) { 4665 idx += block->num_bytes + sizeof(struct displayid_block); 4666 switch (block->tag) { 4667 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4668 num_modes += 4669 add_displayid_detailed_1_modes(data, block); 4670 break; 4671 } 4672 } 4673 return num_modes; 4674 } 4675 4676 static bool 4677 mode_in_hsync_range(const struct drm_display_mode *mode, 4678 struct edid *edid, u8 *t) 4679 { 4680 int hsync, hmin, hmax; 4681 4682 hmin = t[7]; 4683 if (edid->revision >= 4) 4684 hmin += ((t[4] & 0x04) ? 255 : 0); 4685 hmax = t[8]; 4686 if (edid->revision >= 4) 4687 hmax += ((t[4] & 0x08) ? 255 : 0); 4688 hsync = drm_mode_hsync(mode); 4689 4690 return (hsync <= hmax && hsync >= hmin); 4691 } 4692 4693 static bool 4694 mode_in_vsync_range(const struct drm_display_mode *mode, 4695 struct edid *edid, u8 *t) 4696 { 4697 int vsync, vmin, vmax; 4698 4699 vmin = t[5]; 4700 if (edid->revision >= 4) 4701 vmin += ((t[4] & 0x01) ? 255 : 0); 4702 vmax = t[6]; 4703 if (edid->revision >= 4) 4704 vmax += ((t[4] & 0x02) ? 255 : 0); 4705 vsync = drm_get_vrefresh(mode); 4706 4707 return (vsync <= vmax && vsync >= vmin); 4708 } 4709 4710 static u32 4711 range_pixel_clock(struct edid *edid, u8 *t) 4712 { 4713 /* unspecified */ 4714 if (t[9] == 0 || t[9] == 255) 4715 return 0; 4716 4717 /* 1.4 with CVT support gives us real precision, yay */ 4718 if (edid->revision >= 4 && t[10] == 0x04) 4719 return (t[9] * 10000) - ((t[12] >> 2) * 250); 4720 4721 /* 1.3 is pathetic, so fuzz up a bit */ 4722 return t[9] * 10000 + 5001; 4723 } 4724 4725 static bool 4726 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 4727 struct detailed_timing *timing) 4728 { 4729 u32 max_clock; 4730 u8 *t = (u8 *)timing; 4731 4732 if (!mode_in_hsync_range(mode, edid, t)) 4733 return false; 4734 4735 if (!mode_in_vsync_range(mode, edid, t)) 4736 return false; 4737 4738 max_clock = range_pixel_clock(edid, t); 4739 if (max_clock) 4740 if (mode->clock > max_clock) 4741 return false; 4742 4743 /* 1.4 max horizontal check */ 4744 if (edid->revision >= 4 && t[10] == 0x04) 4745 if (t[13] && mode->hdisplay > 8 * 4746 (t[13] + (256 * (t[12] & 0x3)))) 4747 return false; 4748 4749 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 4750 return false; 4751 4752 return true; 4753 } 4754 4755 static bool valid_inferred_mode(struct hdmi_edid_data *data, 4756 const struct drm_display_mode *mode) 4757 { 4758 const struct drm_display_mode *m; 4759 bool ok = false; 4760 int i; 4761 4762 for (i = 0; i < data->modes; i++) { 4763 m = &data->mode_buf[i]; 4764 if (mode->hdisplay == m->hdisplay && 4765 mode->vdisplay == m->vdisplay && 4766 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 4767 return false; /* duplicated */ 4768 if (mode->hdisplay <= m->hdisplay && 4769 mode->vdisplay <= m->vdisplay) 4770 ok = true; 4771 } 4772 return ok; 4773 } 4774 4775 static int 4776 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4777 struct detailed_timing *timing) 4778 { 4779 int i, modes = 0; 4780 4781 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4782 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 4783 valid_inferred_mode(data, drm_dmt_modes + i)) { 4784 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 4785 modes++; 4786 } 4787 } 4788 4789 return modes; 4790 } 4791 4792 /* fix up 1366x768 mode from 1368x768; 4793 * GFT/CVT can't express 1366 width which isn't dividable by 8 4794 */ 4795 static void fixup_mode_1366x768(struct drm_display_mode *mode) 4796 { 4797 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 4798 mode->hdisplay = 1366; 4799 mode->hsync_start--; 4800 mode->hsync_end--; 4801 } 4802 } 4803 4804 static int 4805 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4806 struct detailed_timing *timing) 4807 { 4808 int i, modes = 0; 4809 struct drm_display_mode *newmode; 4810 4811 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4812 const struct minimode *m = &extra_modes[i]; 4813 4814 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 4815 if (!newmode) 4816 return modes; 4817 4818 fixup_mode_1366x768(newmode); 4819 if (!mode_in_range(newmode, edid, timing) || 4820 !valid_inferred_mode(data, newmode)) { 4821 drm_mode_destroy(newmode); 4822 continue; 4823 } 4824 4825 drm_add_hdmi_modes(data, newmode); 4826 modes++; 4827 drm_mode_destroy(newmode); 4828 } 4829 4830 return modes; 4831 } 4832 4833 static int 4834 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4835 struct detailed_timing *timing) 4836 { 4837 int i, modes = 0; 4838 struct drm_display_mode *newmode; 4839 bool rb = drm_monitor_supports_rb(edid); 4840 4841 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4842 const struct minimode *m = &extra_modes[i]; 4843 4844 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 4845 if (!newmode) 4846 return modes; 4847 4848 fixup_mode_1366x768(newmode); 4849 if (!mode_in_range(newmode, edid, timing) || 4850 !valid_inferred_mode(data, newmode)) { 4851 drm_mode_destroy(newmode); 4852 continue; 4853 } 4854 4855 drm_add_hdmi_modes(data, newmode); 4856 modes++; 4857 drm_mode_destroy(newmode); 4858 } 4859 4860 return modes; 4861 } 4862 4863 static void 4864 do_inferred_modes(struct detailed_timing *timing, void *c) 4865 { 4866 struct detailed_mode_closure *closure = c; 4867 struct detailed_non_pixel *data = &timing->data.other_data; 4868 struct detailed_data_monitor_range *range = &data->data.range; 4869 4870 if (data->type != EDID_DETAIL_MONITOR_RANGE) 4871 return; 4872 4873 closure->modes += drm_dmt_modes_for_range(closure->data, 4874 closure->edid, 4875 timing); 4876 4877 if (!version_greater(closure->edid, 1, 1)) 4878 return; /* GTF not defined yet */ 4879 4880 switch (range->flags) { 4881 case 0x02: /* secondary gtf, XXX could do more */ 4882 case 0x00: /* default gtf */ 4883 closure->modes += drm_gtf_modes_for_range(closure->data, 4884 closure->edid, 4885 timing); 4886 break; 4887 case 0x04: /* cvt, only in 1.4+ */ 4888 if (!version_greater(closure->edid, 1, 3)) 4889 break; 4890 4891 closure->modes += drm_cvt_modes_for_range(closure->data, 4892 closure->edid, 4893 timing); 4894 break; 4895 case 0x01: /* just the ranges, no formula */ 4896 default: 4897 break; 4898 } 4899 } 4900 4901 static int 4902 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 4903 { 4904 struct detailed_mode_closure closure = { 4905 .data = data, 4906 .edid = edid, 4907 }; 4908 4909 if (version_greater(edid, 1, 0)) 4910 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 4911 &closure); 4912 4913 return closure.modes; 4914 } 4915 4916 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 4917 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 4918 4919 /** 4920 * edid_fixup_preferred - set preferred modes based on quirk list 4921 * @data: the structure that save parsed hdmi edid data 4922 * @quirks: quirks list 4923 * 4924 * Walk the mode list, clearing the preferred status 4925 * on existing modes and setting it anew for the right mode ala @quirks. 4926 */ 4927 static void edid_fixup_preferred(struct hdmi_edid_data *data, 4928 u32 quirks) 4929 { 4930 struct drm_display_mode *cur_mode, *preferred_mode; 4931 int i, target_refresh = 0; 4932 int num = data->modes; 4933 int cur_vrefresh, preferred_vrefresh; 4934 4935 if (!num) 4936 return; 4937 4938 preferred_mode = data->preferred_mode; 4939 4940 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 4941 target_refresh = 60; 4942 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 4943 target_refresh = 75; 4944 4945 for (i = 0; i < num; i++) { 4946 cur_mode = &data->mode_buf[i]; 4947 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 4948 4949 if (cur_mode == preferred_mode) 4950 continue; 4951 4952 /* Largest mode is preferred */ 4953 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 4954 preferred_mode = cur_mode; 4955 4956 cur_vrefresh = cur_mode->vrefresh ? 4957 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 4958 preferred_vrefresh = preferred_mode->vrefresh ? 4959 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 4960 /* At a given size, try to get closest to target refresh */ 4961 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 4962 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 4963 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 4964 preferred_mode = cur_mode; 4965 } 4966 } 4967 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 4968 data->preferred_mode = preferred_mode; 4969 } 4970 4971 static const u8 edid_header[] = { 4972 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 4973 }; 4974 4975 /** 4976 * drm_edid_header_is_valid - sanity check the header of the base EDID block 4977 * @raw_edid: pointer to raw base EDID block 4978 * 4979 * Sanity check the header of the base EDID block. 4980 * 4981 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 4982 */ 4983 static int drm_edid_header_is_valid(const u8 *raw_edid) 4984 { 4985 int i, score = 0; 4986 4987 for (i = 0; i < sizeof(edid_header); i++) 4988 if (raw_edid[i] == edid_header[i]) 4989 score++; 4990 4991 return score; 4992 } 4993 4994 static int drm_edid_block_checksum(const u8 *raw_edid) 4995 { 4996 int i; 4997 u8 csum = 0; 4998 4999 for (i = 0; i < EDID_SIZE; i++) 5000 csum += raw_edid[i]; 5001 5002 return csum; 5003 } 5004 5005 static bool drm_edid_is_zero(const u8 *in_edid, int length) 5006 { 5007 if (memchr_inv(in_edid, 0, length)) 5008 return false; 5009 5010 return true; 5011 } 5012 5013 /** 5014 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 5015 * @raw_edid: pointer to raw EDID block 5016 * @block: type of block to validate (0 for base, extension otherwise) 5017 * @print_bad_edid: if true, dump bad EDID blocks to the console 5018 * @edid_corrupt: if true, the header or checksum is invalid 5019 * 5020 * Validate a base or extension EDID block and optionally dump bad blocks to 5021 * the console. 5022 * 5023 * Return: True if the block is valid, false otherwise. 5024 */ 5025 static 5026 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 5027 bool *edid_corrupt) 5028 { 5029 u8 csum; 5030 int edid_fixup = 6; 5031 struct edid *edid = (struct edid *)raw_edid; 5032 5033 if ((!raw_edid)) 5034 return false; 5035 5036 if (block == 0) { 5037 int score = drm_edid_header_is_valid(raw_edid); 5038 5039 if (score == 8) { 5040 if (edid_corrupt) 5041 *edid_corrupt = false; 5042 } else if (score >= edid_fixup) { 5043 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 5044 * The corrupt flag needs to be set here otherwise, the 5045 * fix-up code here will correct the problem, the 5046 * checksum is correct and the test fails 5047 */ 5048 if (edid_corrupt) 5049 *edid_corrupt = true; 5050 debug("Fixing header, your hardware may be failing\n"); 5051 memcpy(raw_edid, edid_header, sizeof(edid_header)); 5052 } else { 5053 if (edid_corrupt) 5054 *edid_corrupt = true; 5055 goto bad; 5056 } 5057 } 5058 5059 csum = drm_edid_block_checksum(raw_edid); 5060 if (csum) { 5061 if (print_bad_edid) { 5062 debug("EDID checksum is invalid, remainder is %d\n", 5063 csum); 5064 } 5065 5066 if (edid_corrupt) 5067 *edid_corrupt = true; 5068 5069 /* allow CEA to slide through, switches mangle this */ 5070 if (raw_edid[0] != 0x02) 5071 goto bad; 5072 } 5073 5074 /* per-block-type checks */ 5075 switch (raw_edid[0]) { 5076 case 0: /* base */ 5077 if (edid->version != 1) { 5078 debug("EDID has major version %d, instead of 1\n", 5079 edid->version); 5080 goto bad; 5081 } 5082 5083 if (edid->revision > 4) 5084 debug("minor > 4, assuming backward compatibility\n"); 5085 break; 5086 5087 default: 5088 break; 5089 } 5090 5091 return true; 5092 5093 bad: 5094 if (print_bad_edid) { 5095 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 5096 debug("EDID block is all zeroes\n"); 5097 } else { 5098 debug("Raw EDID:\n"); 5099 print_hex_dump("", DUMP_PREFIX_NONE, 16, 1, 5100 raw_edid, EDID_SIZE, false); 5101 } 5102 } 5103 return false; 5104 } 5105 5106 /** 5107 * drm_edid_is_valid - sanity check EDID data 5108 * @edid: EDID data 5109 * 5110 * Sanity-check an entire EDID record (including extensions) 5111 * 5112 * Return: True if the EDID data is valid, false otherwise. 5113 */ 5114 static bool drm_edid_is_valid(struct edid *edid) 5115 { 5116 int i; 5117 u8 *raw = (u8 *)edid; 5118 5119 if (!edid) 5120 return false; 5121 5122 for (i = 0; i <= edid->extensions; i++) 5123 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 5124 return false; 5125 5126 return true; 5127 } 5128 5129 /** 5130 * drm_add_edid_modes - add modes from EDID data, if available 5131 * @data: data we're probing 5132 * @edid: EDID data 5133 * 5134 * Add the specified modes to the data's mode list. 5135 * 5136 * Return: The number of modes added or 0 if we couldn't find any. 5137 */ 5138 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 5139 { 5140 int num_modes = 0; 5141 u32 quirks; 5142 struct edid *edid = (struct edid *)raw_edid; 5143 5144 if (!edid) { 5145 debug("no edid\n"); 5146 return 0; 5147 } 5148 5149 if (!drm_edid_is_valid(edid)) { 5150 debug("EDID invalid\n"); 5151 return 0; 5152 } 5153 5154 if (!data->mode_buf) { 5155 debug("mode buff is null\n"); 5156 return 0; 5157 } 5158 5159 quirks = edid_get_quirks(edid); 5160 /* 5161 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5162 * To avoid multiple parsing of same block, lets parse that map 5163 * from sink info, before parsing CEA modes. 5164 */ 5165 drm_add_display_info(data, edid); 5166 5167 /* 5168 * EDID spec says modes should be preferred in this order: 5169 * - preferred detailed mode 5170 * - other detailed modes from base block 5171 * - detailed modes from extension blocks 5172 * - CVT 3-byte code modes 5173 * - standard timing codes 5174 * - established timing codes 5175 * - modes inferred from GTF or CVT range information 5176 * 5177 * We get this pretty much right. 5178 * 5179 * XXX order for additional mode types in extension blocks? 5180 */ 5181 num_modes += add_detailed_modes(data, edid, quirks); 5182 num_modes += add_cvt_modes(data, edid); 5183 num_modes += add_standard_modes(data, edid); 5184 num_modes += add_established_modes(data, edid); 5185 num_modes += add_cea_modes(data, edid); 5186 num_modes += add_alternate_cea_modes(data, edid); 5187 num_modes += add_displayid_detailed_modes(data, edid); 5188 5189 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5190 num_modes += add_inferred_modes(data, edid); 5191 5192 if (num_modes > 0) 5193 data->preferred_mode = &data->mode_buf[0]; 5194 5195 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5196 edid_fixup_preferred(data, quirks); 5197 5198 if (quirks & EDID_QUIRK_FORCE_6BPC) 5199 data->display_info.bpc = 6; 5200 5201 if (quirks & EDID_QUIRK_FORCE_8BPC) 5202 data->display_info.bpc = 8; 5203 5204 if (quirks & EDID_QUIRK_FORCE_10BPC) 5205 data->display_info.bpc = 10; 5206 5207 if (quirks & EDID_QUIRK_FORCE_12BPC) 5208 data->display_info.bpc = 12; 5209 5210 return num_modes; 5211 } 5212 5213 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5214 { 5215 u8 vic; 5216 5217 if (!to_match->clock) { 5218 printf("can't find to match\n"); 5219 return 0; 5220 } 5221 5222 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 5223 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 5224 unsigned int clock1, clock2; 5225 5226 /* Check both 60Hz and 59.94Hz */ 5227 clock1 = cea_mode->clock; 5228 clock2 = cea_mode_alternate_clock(cea_mode); 5229 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5230 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5231 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5232 return vic; 5233 } 5234 5235 return 0; 5236 } 5237 5238 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5239 { 5240 return edid_cea_modes[video_code].picture_aspect_ratio; 5241 } 5242 5243 int 5244 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5245 struct drm_display_mode *mode, 5246 bool is_hdmi2_sink) 5247 { 5248 int err; 5249 5250 if (!frame || !mode) 5251 return -EINVAL; 5252 5253 err = hdmi_avi_infoframe_init(frame); 5254 if (err < 0) 5255 return err; 5256 5257 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5258 frame->pixel_repeat = 1; 5259 5260 frame->video_code = drm_match_cea_mode(mode); 5261 5262 /* 5263 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5264 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5265 * have to make sure we dont break HDMI 1.4 sinks. 5266 */ 5267 if (!is_hdmi2_sink && frame->video_code > 64) 5268 frame->video_code = 0; 5269 5270 /* 5271 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5272 * we should send its VIC in vendor infoframes, else send the 5273 * VIC in AVI infoframes. Lets check if this mode is present in 5274 * HDMI 1.4b 4K modes 5275 */ 5276 if (frame->video_code) { 5277 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5278 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5279 5280 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5281 frame->video_code = 0; 5282 } 5283 5284 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5285 5286 /* 5287 * Populate picture aspect ratio from either 5288 * user input (if specified) or from the CEA mode list. 5289 */ 5290 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5291 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5292 frame->picture_aspect = mode->picture_aspect_ratio; 5293 else if (frame->video_code > 0) 5294 frame->picture_aspect = drm_get_cea_aspect_ratio( 5295 frame->video_code); 5296 5297 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5298 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5299 5300 return 0; 5301 } 5302 5303 /** 5304 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5305 * @frame: HDMI vendor infoframe 5306 * 5307 * Returns 0 on success or a negative error code on failure. 5308 */ 5309 int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5310 { 5311 memset(frame, 0, sizeof(*frame)); 5312 5313 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5314 frame->version = 1; 5315 5316 frame->oui = HDMI_IEEE_OUI; 5317 5318 /* 5319 * 0 is a valid value for s3d_struct, so we use a special "not set" 5320 * value 5321 */ 5322 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5323 5324 return 0; 5325 } 5326 5327 /** 5328 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5329 * quantization range information 5330 * @frame: HDMI AVI infoframe 5331 * @rgb_quant_range: RGB quantization range (Q) 5332 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 5333 */ 5334 void 5335 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5336 struct drm_display_mode *mode, 5337 enum hdmi_quantization_range rgb_quant_range, 5338 bool rgb_quant_range_selectable) 5339 { 5340 /* 5341 * CEA-861: 5342 * "A Source shall not send a non-zero Q value that does not correspond 5343 * to the default RGB Quantization Range for the transmitted Picture 5344 * unless the Sink indicates support for the Q bit in a Video 5345 * Capabilities Data Block." 5346 * 5347 * HDMI 2.0 recommends sending non-zero Q when it does match the 5348 * default RGB quantization range for the mode, even when QS=0. 5349 */ 5350 if (rgb_quant_range_selectable || 5351 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5352 frame->quantization_range = rgb_quant_range; 5353 else 5354 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5355 5356 /* 5357 * CEA-861-F: 5358 * "When transmitting any RGB colorimetry, the Source should set the 5359 * YQ-field to match the RGB Quantization Range being transmitted 5360 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5361 * set YQ=1) and the Sink shall ignore the YQ-field." 5362 */ 5363 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5364 frame->ycc_quantization_range = 5365 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5366 else 5367 frame->ycc_quantization_range = 5368 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5369 } 5370 5371 static enum hdmi_3d_structure 5372 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5373 { 5374 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5375 5376 switch (layout) { 5377 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5378 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5379 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5380 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5381 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5382 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5383 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5384 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5385 case DRM_MODE_FLAG_3D_L_DEPTH: 5386 return HDMI_3D_STRUCTURE_L_DEPTH; 5387 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5388 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5389 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5390 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5391 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5392 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5393 default: 5394 return HDMI_3D_STRUCTURE_INVALID; 5395 } 5396 } 5397 5398 int 5399 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5400 struct drm_display_mode *mode) 5401 { 5402 int err; 5403 u32 s3d_flags; 5404 u8 vic; 5405 5406 if (!frame || !mode) 5407 return -EINVAL; 5408 5409 vic = drm_match_hdmi_mode(mode); 5410 5411 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5412 5413 if (!vic && !s3d_flags) 5414 return -EINVAL; 5415 5416 if (vic && s3d_flags) 5417 return -EINVAL; 5418 5419 err = hdmi_vendor_infoframe_init(frame); 5420 if (err < 0) 5421 return err; 5422 5423 if (vic) 5424 frame->vic = vic; 5425 else 5426 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5427 5428 return 0; 5429 } 5430 5431 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5432 { 5433 u8 csum = 0; 5434 size_t i; 5435 5436 /* compute checksum */ 5437 for (i = 0; i < size; i++) 5438 csum += ptr[i]; 5439 5440 return 256 - csum; 5441 } 5442 5443 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5444 { 5445 u8 *ptr = buffer; 5446 5447 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5448 } 5449 5450 /** 5451 * hdmi_avi_infoframe_init() - initialize an HDMI AVI infoframe 5452 * @frame: HDMI AVI infoframe 5453 * 5454 * Returns 0 on success or a negative error code on failure. 5455 */ 5456 int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5457 { 5458 memset(frame, 0, sizeof(*frame)); 5459 5460 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5461 frame->version = 2; 5462 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5463 5464 return 0; 5465 } 5466 EXPORT_SYMBOL(hdmi_avi_infoframe_init); 5467 5468 /** 5469 * hdmi_avi_infoframe_pack() - write HDMI AVI infoframe to binary buffer 5470 * @frame: HDMI AVI infoframe 5471 * @buffer: destination buffer 5472 * @size: size of buffer 5473 * 5474 * Packs the information contained in the @frame structure into a binary 5475 * representation that can be written into the corresponding controller 5476 * registers. Also computes the checksum as required by section 5.3.5 of 5477 * the HDMI 1.4 specification. 5478 * 5479 * Returns the number of bytes packed into the binary buffer or a negative 5480 * error code on failure. 5481 */ 5482 ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, 5483 size_t size) 5484 { 5485 u8 *ptr = buffer; 5486 size_t length; 5487 5488 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5489 5490 if (size < length) 5491 return -ENOSPC; 5492 5493 memset(buffer, 0, size); 5494 5495 ptr[0] = frame->type; 5496 ptr[1] = frame->version; 5497 ptr[2] = frame->length; 5498 ptr[3] = 0; /* checksum */ 5499 5500 /* start infoframe payload */ 5501 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5502 5503 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 5504 5505 /* 5506 * Data byte 1, bit 4 has to be set if we provide the active format 5507 * aspect ratio 5508 */ 5509 if (frame->active_aspect & 0xf) 5510 ptr[0] |= BIT(4); 5511 5512 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 5513 if (frame->top_bar || frame->bottom_bar) 5514 ptr[0] |= BIT(3); 5515 5516 if (frame->left_bar || frame->right_bar) 5517 ptr[0] |= BIT(2); 5518 5519 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 5520 ((frame->picture_aspect & 0x3) << 4) | 5521 (frame->active_aspect & 0xf); 5522 5523 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 5524 ((frame->quantization_range & 0x3) << 2) | 5525 (frame->nups & 0x3); 5526 5527 if (frame->itc) 5528 ptr[2] |= BIT(7); 5529 5530 ptr[3] = frame->video_code & 0x7f; 5531 5532 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 5533 ((frame->content_type & 0x3) << 4) | 5534 (frame->pixel_repeat & 0xf); 5535 5536 ptr[5] = frame->top_bar & 0xff; 5537 ptr[6] = (frame->top_bar >> 8) & 0xff; 5538 ptr[7] = frame->bottom_bar & 0xff; 5539 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 5540 ptr[9] = frame->left_bar & 0xff; 5541 ptr[10] = (frame->left_bar >> 8) & 0xff; 5542 ptr[11] = frame->right_bar & 0xff; 5543 ptr[12] = (frame->right_bar >> 8) & 0xff; 5544 5545 hdmi_infoframe_set_checksum(buffer, length); 5546 5547 return length; 5548 } 5549 EXPORT_SYMBOL(hdmi_avi_infoframe_pack); 5550 5551 /** 5552 * hdmi_spd_infoframe_init() - initialize an HDMI SPD infoframe 5553 * @frame: HDMI SPD infoframe 5554 * @vendor: vendor string 5555 * @product: product string 5556 * 5557 * Returns 0 on success or a negative error code on failure. 5558 */ 5559 int hdmi_spd_infoframe_init(struct hdmi_spd_infoframe *frame, 5560 const char *vendor, const char *product) 5561 { 5562 memset(frame, 0, sizeof(*frame)); 5563 5564 frame->type = HDMI_INFOFRAME_TYPE_SPD; 5565 frame->version = 1; 5566 frame->length = HDMI_SPD_INFOFRAME_SIZE; 5567 5568 strncpy(frame->vendor, vendor, sizeof(frame->vendor)); 5569 strncpy(frame->product, product, sizeof(frame->product)); 5570 5571 return 0; 5572 } 5573 EXPORT_SYMBOL(hdmi_spd_infoframe_init); 5574 5575 /** 5576 * hdmi_spd_infoframe_pack() - write HDMI SPD infoframe to binary buffer 5577 * @frame: HDMI SPD infoframe 5578 * @buffer: destination buffer 5579 * @size: size of buffer 5580 * 5581 * Packs the information contained in the @frame structure into a binary 5582 * representation that can be written into the corresponding controller 5583 * registers. Also computes the checksum as required by section 5.3.5 of 5584 * the HDMI 1.4 specification. 5585 * 5586 * Returns the number of bytes packed into the binary buffer or a negative 5587 * error code on failure. 5588 */ 5589 ssize_t hdmi_spd_infoframe_pack(struct hdmi_spd_infoframe *frame, void *buffer, 5590 size_t size) 5591 { 5592 u8 *ptr = buffer; 5593 size_t length; 5594 5595 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5596 5597 if (size < length) 5598 return -ENOSPC; 5599 5600 memset(buffer, 0, size); 5601 5602 ptr[0] = frame->type; 5603 ptr[1] = frame->version; 5604 ptr[2] = frame->length; 5605 ptr[3] = 0; /* checksum */ 5606 5607 /* start infoframe payload */ 5608 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5609 5610 memcpy(ptr, frame->vendor, sizeof(frame->vendor)); 5611 memcpy(ptr + 8, frame->product, sizeof(frame->product)); 5612 5613 ptr[24] = frame->sdi; 5614 5615 hdmi_infoframe_set_checksum(buffer, length); 5616 5617 return length; 5618 } 5619 EXPORT_SYMBOL(hdmi_spd_infoframe_pack); 5620 5621 /** 5622 * hdmi_audio_infoframe_init() - initialize an HDMI audio infoframe 5623 * @frame: HDMI audio infoframe 5624 * 5625 * Returns 0 on success or a negative error code on failure. 5626 */ 5627 int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame) 5628 { 5629 memset(frame, 0, sizeof(*frame)); 5630 5631 frame->type = HDMI_INFOFRAME_TYPE_AUDIO; 5632 frame->version = 1; 5633 frame->length = HDMI_AUDIO_INFOFRAME_SIZE; 5634 5635 return 0; 5636 } 5637 5638 /** 5639 * hdmi_audio_infoframe_pack() - write HDMI audio infoframe to binary buffer 5640 * @frame: HDMI audio infoframe 5641 * @buffer: destination buffer 5642 * @size: size of buffer 5643 * 5644 * Packs the information contained in the @frame structure into a binary 5645 * representation that can be written into the corresponding controller 5646 * registers. Also computes the checksum as required by section 5.3.5 of 5647 * the HDMI 1.4 specification. 5648 * 5649 * Returns the number of bytes packed into the binary buffer or a negative 5650 * error code on failure. 5651 */ 5652 ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame, 5653 void *buffer, size_t size) 5654 { 5655 unsigned char channels; 5656 char *ptr = buffer; 5657 size_t length; 5658 5659 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5660 5661 if (size < length) 5662 return -ENOSPC; 5663 5664 memset(buffer, 0, size); 5665 5666 if (frame->channels >= 2) 5667 channels = frame->channels - 1; 5668 else 5669 channels = 0; 5670 5671 ptr[0] = frame->type; 5672 ptr[1] = frame->version; 5673 ptr[2] = frame->length; 5674 ptr[3] = 0; /* checksum */ 5675 5676 /* start infoframe payload */ 5677 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5678 5679 ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7); 5680 ptr[1] = ((frame->sample_frequency & 0x7) << 2) | 5681 (frame->sample_size & 0x3); 5682 ptr[2] = frame->coding_type_ext & 0x1f; 5683 ptr[3] = frame->channel_allocation; 5684 ptr[4] = (frame->level_shift_value & 0xf) << 3; 5685 5686 if (frame->downmix_inhibit) 5687 ptr[4] |= BIT(7); 5688 5689 hdmi_infoframe_set_checksum(buffer, length); 5690 5691 return length; 5692 } 5693 5694 /** 5695 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 5696 * @frame: HDMI infoframe 5697 * @buffer: destination buffer 5698 * @size: size of buffer 5699 * 5700 * Packs the information contained in the @frame structure into a binary 5701 * representation that can be written into the corresponding controller 5702 * registers. Also computes the checksum as required by section 5.3.5 of 5703 * the HDMI 1.4 specification. 5704 * 5705 * Returns the number of bytes packed into the binary buffer or a negative 5706 * error code on failure. 5707 */ 5708 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 5709 void *buffer, size_t size) 5710 { 5711 char *ptr = buffer; 5712 size_t length; 5713 5714 /* empty info frame */ 5715 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 5716 return -EINVAL; 5717 5718 /* only one of those can be supplied */ 5719 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 5720 return -EINVAL; 5721 5722 /* for side by side (half) we also need to provide 3D_Ext_Data */ 5723 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5724 frame->length = 6; 5725 else 5726 frame->length = 5; 5727 5728 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5729 5730 if (size < length) 5731 return -ENOSPC; 5732 5733 memset(buffer, 0, size); 5734 5735 ptr[0] = frame->type; 5736 ptr[1] = frame->version; 5737 ptr[2] = frame->length; 5738 ptr[3] = 0; /* checksum */ 5739 5740 /* HDMI OUI */ 5741 ptr[4] = 0x03; 5742 ptr[5] = 0x0c; 5743 ptr[6] = 0x00; 5744 5745 if (frame->vic) { 5746 ptr[7] = 0x1 << 5; /* video format */ 5747 ptr[8] = frame->vic; 5748 } else { 5749 ptr[7] = 0x2 << 5; /* video format */ 5750 ptr[8] = (frame->s3d_struct & 0xf) << 4; 5751 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5752 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 5753 } 5754 5755 hdmi_infoframe_set_checksum(buffer, length); 5756 5757 return length; 5758 } 5759 5760 /** 5761 * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and 5762 * mastering infoframe 5763 * @frame: HDMI DRM infoframe 5764 * 5765 * Returns 0 on success or a negative error code on failure. 5766 */ 5767 int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame) 5768 { 5769 memset(frame, 0, sizeof(*frame)); 5770 5771 frame->type = HDMI_INFOFRAME_TYPE_DRM; 5772 frame->version = 1; 5773 5774 return 0; 5775 } 5776 5777 /** 5778 * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer 5779 * @frame: HDMI DRM infoframe 5780 * @buffer: destination buffer 5781 * @size: size of buffer 5782 * 5783 * Packs the information contained in the @frame structure into a binary 5784 * representation that can be written into the corresponding controller 5785 * registers. Also computes the checksum as required by section 5.3.5 of 5786 * the HDMI 1.4 specification. 5787 * 5788 * Returns the number of bytes packed into the binary buffer or a negative 5789 * error code on failure. 5790 */ 5791 ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer, 5792 size_t size) 5793 { 5794 u8 *ptr = buffer; 5795 size_t length; 5796 5797 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5798 5799 if (size < length) 5800 return -ENOSPC; 5801 5802 memset(buffer, 0, size); 5803 5804 ptr[0] = frame->type; 5805 ptr[1] = frame->version; 5806 ptr[2] = frame->length; 5807 ptr[3] = 0; /* checksum */ 5808 5809 /* start infoframe payload */ 5810 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5811 5812 ptr[0] = frame->eotf; 5813 ptr[1] = frame->metadata_type; 5814 5815 ptr[2] = frame->display_primaries_x[0] & 0xff; 5816 ptr[3] = frame->display_primaries_x[0] >> 8; 5817 5818 ptr[4] = frame->display_primaries_x[1] & 0xff; 5819 ptr[5] = frame->display_primaries_x[1] >> 8; 5820 5821 ptr[6] = frame->display_primaries_x[2] & 0xff; 5822 ptr[7] = frame->display_primaries_x[2] >> 8; 5823 5824 ptr[9] = frame->display_primaries_y[0] & 0xff; 5825 ptr[10] = frame->display_primaries_y[0] >> 8; 5826 5827 ptr[11] = frame->display_primaries_y[1] & 0xff; 5828 ptr[12] = frame->display_primaries_y[1] >> 8; 5829 5830 ptr[13] = frame->display_primaries_y[2] & 0xff; 5831 ptr[14] = frame->display_primaries_y[2] >> 8; 5832 5833 ptr[15] = frame->white_point_x & 0xff; 5834 ptr[16] = frame->white_point_x >> 8; 5835 5836 ptr[17] = frame->white_point_y & 0xff; 5837 ptr[18] = frame->white_point_y >> 8; 5838 5839 ptr[19] = frame->max_mastering_display_luminance & 0xff; 5840 ptr[20] = frame->max_mastering_display_luminance >> 8; 5841 5842 ptr[21] = frame->min_mastering_display_luminance & 0xff; 5843 ptr[22] = frame->min_mastering_display_luminance >> 8; 5844 5845 ptr[23] = frame->max_cll & 0xff; 5846 ptr[24] = frame->max_cll >> 8; 5847 5848 ptr[25] = frame->max_fall & 0xff; 5849 ptr[26] = frame->max_fall >> 8; 5850 5851 hdmi_infoframe_set_checksum(buffer, length); 5852 5853 return length; 5854 } 5855 5856 /* 5857 * hdmi_vendor_any_infoframe_pack() - write a vendor infoframe to binary buffer 5858 */ 5859 static ssize_t 5860 hdmi_vendor_any_infoframe_pack(union hdmi_vendor_any_infoframe *frame, 5861 void *buffer, size_t size) 5862 { 5863 /* we only know about HDMI vendor infoframes */ 5864 if (frame->any.oui != HDMI_IEEE_OUI) 5865 return -EINVAL; 5866 5867 return hdmi_vendor_infoframe_pack(&frame->hdmi, buffer, size); 5868 } 5869 5870 /** 5871 * hdmi_infoframe_pack() - write a HDMI infoframe to binary buffer 5872 * @frame: HDMI infoframe 5873 * @buffer: destination buffer 5874 * @size: size of buffer 5875 * 5876 * Packs the information contained in the @frame structure into a binary 5877 * representation that can be written into the corresponding controller 5878 * registers. Also computes the checksum as required by section 5.3.5 of 5879 * the HDMI 1.4 specification. 5880 * 5881 * Returns the number of bytes packed into the binary buffer or a negative 5882 * error code on failure. 5883 */ 5884 ssize_t 5885 hdmi_infoframe_pack(union hdmi_infoframe *frame, void *buffer, size_t size) 5886 { 5887 ssize_t length; 5888 5889 switch (frame->any.type) { 5890 case HDMI_INFOFRAME_TYPE_AVI: 5891 length = hdmi_avi_infoframe_pack(&frame->avi, buffer, size); 5892 break; 5893 case HDMI_INFOFRAME_TYPE_DRM: 5894 length = hdmi_drm_infoframe_pack(&frame->drm, buffer, size); 5895 break; 5896 case HDMI_INFOFRAME_TYPE_SPD: 5897 length = hdmi_spd_infoframe_pack(&frame->spd, buffer, size); 5898 break; 5899 case HDMI_INFOFRAME_TYPE_AUDIO: 5900 length = hdmi_audio_infoframe_pack(&frame->audio, buffer, size); 5901 break; 5902 case HDMI_INFOFRAME_TYPE_VENDOR: 5903 length = hdmi_vendor_any_infoframe_pack(&frame->vendor, 5904 buffer, size); 5905 break; 5906 default: 5907 printf("Bad infoframe type %d\n", frame->any.type); 5908 length = -EINVAL; 5909 } 5910 5911 return length; 5912 } 5913 5914 /** 5915 * hdmi_avi_infoframe_unpack() - unpack binary buffer to a HDMI AVI infoframe 5916 * @buffer: source buffer 5917 * @frame: HDMI AVI infoframe 5918 * 5919 * Unpacks the information contained in binary @buffer into a structured 5920 * @frame of the HDMI Auxiliary Video (AVI) information frame. 5921 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 5922 * specification. 5923 * 5924 * Returns 0 on success or a negative error code on failure. 5925 */ 5926 static int hdmi_avi_infoframe_unpack(struct hdmi_avi_infoframe *frame, 5927 void *buffer) 5928 { 5929 u8 *ptr = buffer; 5930 int ret; 5931 5932 if (ptr[0] != HDMI_INFOFRAME_TYPE_AVI || 5933 ptr[1] != 2 || 5934 ptr[2] != HDMI_AVI_INFOFRAME_SIZE) 5935 return -EINVAL; 5936 5937 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AVI)) != 0) 5938 return -EINVAL; 5939 5940 ret = hdmi_avi_infoframe_init(frame); 5941 if (ret) 5942 return ret; 5943 5944 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5945 5946 frame->colorspace = (ptr[0] >> 5) & 0x3; 5947 if (ptr[0] & 0x10) 5948 frame->active_aspect = ptr[1] & 0xf; 5949 if (ptr[0] & 0x8) { 5950 frame->top_bar = (ptr[5] << 8) + ptr[6]; 5951 frame->bottom_bar = (ptr[7] << 8) + ptr[8]; 5952 } 5953 if (ptr[0] & 0x4) { 5954 frame->left_bar = (ptr[9] << 8) + ptr[10]; 5955 frame->right_bar = (ptr[11] << 8) + ptr[12]; 5956 } 5957 frame->scan_mode = ptr[0] & 0x3; 5958 5959 frame->colorimetry = (ptr[1] >> 6) & 0x3; 5960 frame->picture_aspect = (ptr[1] >> 4) & 0x3; 5961 frame->active_aspect = ptr[1] & 0xf; 5962 5963 frame->itc = ptr[2] & 0x80 ? true : false; 5964 frame->extended_colorimetry = (ptr[2] >> 4) & 0x7; 5965 frame->quantization_range = (ptr[2] >> 2) & 0x3; 5966 frame->nups = ptr[2] & 0x3; 5967 5968 frame->video_code = ptr[3] & 0x7f; 5969 frame->ycc_quantization_range = (ptr[4] >> 6) & 0x3; 5970 frame->content_type = (ptr[4] >> 4) & 0x3; 5971 5972 frame->pixel_repeat = ptr[4] & 0xf; 5973 5974 return 0; 5975 } 5976 5977 /** 5978 * hdmi_spd_infoframe_unpack() - unpack binary buffer to a HDMI SPD infoframe 5979 * @buffer: source buffer 5980 * @frame: HDMI SPD infoframe 5981 * 5982 * Unpacks the information contained in binary @buffer into a structured 5983 * @frame of the HDMI Source Product Description (SPD) information frame. 5984 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 5985 * specification. 5986 * 5987 * Returns 0 on success or a negative error code on failure. 5988 */ 5989 static int hdmi_spd_infoframe_unpack(struct hdmi_spd_infoframe *frame, 5990 void *buffer) 5991 { 5992 char *ptr = buffer; 5993 int ret; 5994 5995 if (ptr[0] != HDMI_INFOFRAME_TYPE_SPD || 5996 ptr[1] != 1 || 5997 ptr[2] != HDMI_SPD_INFOFRAME_SIZE) { 5998 return -EINVAL; 5999 } 6000 6001 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(SPD)) != 0) 6002 return -EINVAL; 6003 6004 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6005 6006 ret = hdmi_spd_infoframe_init(frame, ptr, ptr + 8); 6007 if (ret) 6008 return ret; 6009 6010 frame->sdi = ptr[24]; 6011 6012 return 0; 6013 } 6014 6015 /** 6016 * hdmi_audio_infoframe_unpack() - unpack binary buffer to a HDMI AUDIO infoframe 6017 * @buffer: source buffer 6018 * @frame: HDMI Audio infoframe 6019 * 6020 * Unpacks the information contained in binary @buffer into a structured 6021 * @frame of the HDMI Audio information frame. 6022 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6023 * specification. 6024 * 6025 * Returns 0 on success or a negative error code on failure. 6026 */ 6027 static int hdmi_audio_infoframe_unpack(struct hdmi_audio_infoframe *frame, 6028 void *buffer) 6029 { 6030 u8 *ptr = buffer; 6031 int ret; 6032 6033 if (ptr[0] != HDMI_INFOFRAME_TYPE_AUDIO || 6034 ptr[1] != 1 || 6035 ptr[2] != HDMI_AUDIO_INFOFRAME_SIZE) { 6036 return -EINVAL; 6037 } 6038 6039 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AUDIO)) != 0) 6040 return -EINVAL; 6041 6042 ret = hdmi_audio_infoframe_init(frame); 6043 if (ret) 6044 return ret; 6045 6046 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6047 6048 frame->channels = ptr[0] & 0x7; 6049 frame->coding_type = (ptr[0] >> 4) & 0xf; 6050 frame->sample_size = ptr[1] & 0x3; 6051 frame->sample_frequency = (ptr[1] >> 2) & 0x7; 6052 frame->coding_type_ext = ptr[2] & 0x1f; 6053 frame->channel_allocation = ptr[3]; 6054 frame->level_shift_value = (ptr[4] >> 3) & 0xf; 6055 frame->downmix_inhibit = ptr[4] & 0x80 ? true : false; 6056 6057 return 0; 6058 } 6059 6060 /** 6061 * hdmi_vendor_infoframe_unpack() - unpack binary buffer to a HDMI vendor infoframe 6062 * @buffer: source buffer 6063 * @frame: HDMI Vendor infoframe 6064 * 6065 * Unpacks the information contained in binary @buffer into a structured 6066 * @frame of the HDMI Vendor information frame. 6067 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6068 * specification. 6069 * 6070 * Returns 0 on success or a negative error code on failure. 6071 */ 6072 static int 6073 hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame, 6074 void *buffer) 6075 { 6076 u8 *ptr = buffer; 6077 size_t length; 6078 int ret; 6079 u8 hdmi_video_format; 6080 struct hdmi_vendor_infoframe *hvf = &frame->hdmi; 6081 6082 if (ptr[0] != HDMI_INFOFRAME_TYPE_VENDOR || 6083 ptr[1] != 1 || 6084 (ptr[2] != 4 && ptr[2] != 5 && ptr[2] != 6)) 6085 return -EINVAL; 6086 6087 length = ptr[2]; 6088 6089 if (hdmi_infoframe_checksum(buffer, 6090 HDMI_INFOFRAME_HEADER_SIZE + length) != 0) 6091 return -EINVAL; 6092 6093 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6094 6095 /* HDMI OUI */ 6096 if (ptr[0] != 0x03 || 6097 ptr[1] != 0x0c || 6098 ptr[2] != 0x00) 6099 return -EINVAL; 6100 6101 hdmi_video_format = ptr[3] >> 5; 6102 6103 if (hdmi_video_format > 0x2) 6104 return -EINVAL; 6105 6106 ret = hdmi_vendor_infoframe_init(hvf); 6107 if (ret) 6108 return ret; 6109 6110 hvf->length = length; 6111 6112 if (hdmi_video_format == 0x2) { 6113 if (length != 5 && length != 6) 6114 return -EINVAL; 6115 hvf->s3d_struct = ptr[4] >> 4; 6116 if (hvf->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) { 6117 if (length != 6) 6118 return -EINVAL; 6119 hvf->s3d_ext_data = ptr[5] >> 4; 6120 } 6121 } else if (hdmi_video_format == 0x1) { 6122 if (length != 5) 6123 return -EINVAL; 6124 hvf->vic = ptr[4]; 6125 } else { 6126 if (length != 4) 6127 return -EINVAL; 6128 } 6129 6130 return 0; 6131 } 6132 6133 /** 6134 * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe 6135 * @buffer: source buffer 6136 * @frame: HDMI infoframe 6137 * 6138 * Unpacks the information contained in binary buffer @buffer into a structured 6139 * @frame of a HDMI infoframe. 6140 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6141 * specification. 6142 * 6143 * Returns 0 on success or a negative error code on failure. 6144 */ 6145 int hdmi_infoframe_unpack(union hdmi_infoframe *frame, void *buffer) 6146 { 6147 int ret; 6148 u8 *ptr = buffer; 6149 6150 switch (ptr[0]) { 6151 case HDMI_INFOFRAME_TYPE_AVI: 6152 ret = hdmi_avi_infoframe_unpack(&frame->avi, buffer); 6153 break; 6154 case HDMI_INFOFRAME_TYPE_SPD: 6155 ret = hdmi_spd_infoframe_unpack(&frame->spd, buffer); 6156 break; 6157 case HDMI_INFOFRAME_TYPE_AUDIO: 6158 ret = hdmi_audio_infoframe_unpack(&frame->audio, buffer); 6159 break; 6160 case HDMI_INFOFRAME_TYPE_VENDOR: 6161 ret = hdmi_vendor_any_infoframe_unpack(&frame->vendor, buffer); 6162 break; 6163 default: 6164 ret = -EINVAL; 6165 break; 6166 } 6167 6168 return ret; 6169 } 6170 6171 bool drm_mode_equal(const struct base_drm_display_mode *mode1, 6172 const struct drm_display_mode *mode2) 6173 { 6174 unsigned int flags_mask = 6175 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_PHSYNC | 6176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | 6177 DRM_MODE_FLAG_NVSYNC; 6178 6179 if (mode1->clock == mode2->clock && 6180 mode1->hdisplay == mode2->hdisplay && 6181 mode1->hsync_start == mode2->hsync_start && 6182 mode1->hsync_end == mode2->hsync_end && 6183 mode1->htotal == mode2->htotal && 6184 mode1->vdisplay == mode2->vdisplay && 6185 mode1->vsync_start == mode2->vsync_start && 6186 mode1->vsync_end == mode2->vsync_end && 6187 mode1->vtotal == mode2->vtotal && 6188 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) { 6189 return true; 6190 } 6191 6192 return false; 6193 } 6194 6195 /** 6196 * drm_mode_sort - sort mode list 6197 * @edid_data: modes structures to sort 6198 * 6199 * Sort @edid_data by favorability, moving good modes to the head of the list. 6200 */ 6201 void drm_mode_sort(struct hdmi_edid_data *edid_data) 6202 { 6203 struct drm_display_mode *a, *b; 6204 struct drm_display_mode c; 6205 int diff, i, j; 6206 6207 for (i = 0; i < (edid_data->modes - 1); i++) { 6208 a = &edid_data->mode_buf[i]; 6209 for (j = i + 1; j < edid_data->modes; j++) { 6210 b = &edid_data->mode_buf[j]; 6211 diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) - 6212 ((a->type & DRM_MODE_TYPE_PREFERRED) != 0); 6213 if (diff) { 6214 if (diff > 0) { 6215 c = *a; 6216 *a = *b; 6217 *b = c; 6218 } 6219 continue; 6220 } 6221 6222 diff = b->hdisplay * b->vdisplay 6223 - a->hdisplay * a->vdisplay; 6224 if (diff) { 6225 if (diff > 0) { 6226 c = *a; 6227 *a = *b; 6228 *b = c; 6229 } 6230 continue; 6231 } 6232 6233 diff = b->vrefresh - a->vrefresh; 6234 if (diff) { 6235 if (diff > 0) { 6236 c = *a; 6237 *a = *b; 6238 *b = c; 6239 } 6240 continue; 6241 } 6242 6243 diff = b->clock - a->clock; 6244 if (diff > 0) { 6245 c = *a; 6246 *a = *b; 6247 *b = c; 6248 } 6249 } 6250 } 6251 edid_data->preferred_mode = &edid_data->mode_buf[0]; 6252 } 6253 6254 /** 6255 * drm_mode_prune_invalid - remove invalid modes from mode list 6256 * @edid_data: structure store mode list 6257 * Returns: 6258 * Number of valid modes. 6259 */ 6260 int drm_mode_prune_invalid(struct hdmi_edid_data *edid_data) 6261 { 6262 int i, j; 6263 int num = edid_data->modes; 6264 int len = sizeof(struct drm_display_mode); 6265 struct drm_display_mode *mode_buf = edid_data->mode_buf; 6266 6267 for (i = 0; i < num; i++) { 6268 if (mode_buf[i].invalid) { 6269 /* If mode is invalid, delete it. */ 6270 for (j = i; j < num - 1; j++) 6271 memcpy(&mode_buf[j], &mode_buf[j + 1], len); 6272 6273 num--; 6274 i--; 6275 } 6276 } 6277 /* Clear redundant modes of mode_buf. */ 6278 memset(&mode_buf[num], 0, len * (edid_data->modes - num)); 6279 6280 edid_data->modes = num; 6281 return num; 6282 } 6283 6284 /** 6285 * drm_rk_filter_whitelist - mark modes out of white list from mode list 6286 * @edid_data: structure store mode list 6287 */ 6288 void drm_rk_filter_whitelist(struct hdmi_edid_data *edid_data) 6289 { 6290 int i, j, white_len; 6291 6292 if (sizeof(resolution_white)) { 6293 white_len = sizeof(resolution_white) / 6294 sizeof(resolution_white[0]); 6295 for (i = 0; i < edid_data->modes; i++) { 6296 for (j = 0; j < white_len; j++) { 6297 if (drm_mode_equal(&resolution_white[j], 6298 &edid_data->mode_buf[i])) 6299 break; 6300 } 6301 6302 if (j == white_len) 6303 edid_data->mode_buf[i].invalid = true; 6304 } 6305 } 6306 } 6307 6308 void drm_rk_select_mode(struct hdmi_edid_data *edid_data, 6309 struct base_screen_info *screen_info) 6310 { 6311 int i; 6312 const struct base_drm_display_mode *base_mode; 6313 6314 if (!screen_info) { 6315 /* define init resolution here */ 6316 } else { 6317 base_mode = &screen_info->mode; 6318 for (i = 0; i < edid_data->modes; i++) { 6319 if (drm_mode_equal(base_mode, 6320 &edid_data->mode_buf[i])) { 6321 edid_data->preferred_mode = 6322 &edid_data->mode_buf[i]; 6323 break; 6324 } 6325 } 6326 } 6327 } 6328 6329 /** 6330 * drm_do_probe_ddc_edid() - get EDID information via I2C 6331 * @adap: ddc adapter 6332 * @buf: EDID data buffer to be filled 6333 * @block: 128 byte EDID block to start fetching from 6334 * @len: EDID data buffer length to fetch 6335 * 6336 * Try to fetch EDID information by calling I2C driver functions. 6337 * 6338 * Return: 0 on success or -1 on failure. 6339 */ 6340 static int 6341 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 6342 size_t len) 6343 { 6344 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 6345 unsigned char segment = block >> 1; 6346 unsigned char xfers = segment ? 3 : 2; 6347 int ret, retries = 5; 6348 6349 do { 6350 struct i2c_msg msgs[] = { 6351 { 6352 .addr = DDC_SEGMENT_ADDR, 6353 .flags = 0, 6354 .len = 1, 6355 .buf = &segment, 6356 }, { 6357 .addr = DDC_ADDR, 6358 .flags = 0, 6359 .len = 1, 6360 .buf = &start, 6361 }, { 6362 .addr = DDC_ADDR, 6363 .flags = I2C_M_RD, 6364 .len = len, 6365 .buf = buf, 6366 } 6367 }; 6368 6369 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 6370 6371 } while (ret != xfers && --retries); 6372 6373 /* All msg transfer successfully. */ 6374 return ret == xfers ? 0 : -1; 6375 } 6376 6377 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid) 6378 { 6379 int i, j, block_num, block = 0; 6380 bool edid_corrupt; 6381 #ifdef DEBUG 6382 u8 *buff; 6383 #endif 6384 6385 /* base block fetch */ 6386 for (i = 0; i < 4; i++) { 6387 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 6388 goto err; 6389 if (drm_edid_block_valid(edid, 0, true, 6390 &edid_corrupt)) 6391 break; 6392 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 6393 printf("edid base block is 0, get edid failed\n"); 6394 goto err; 6395 } 6396 } 6397 6398 if (i == 4) 6399 goto err; 6400 6401 block++; 6402 /* get the number of extensions */ 6403 block_num = edid[0x7e]; 6404 6405 for (j = 1; j <= block_num; j++) { 6406 for (i = 0; i < 4; i++) { 6407 if (drm_do_probe_ddc_edid(adap, &edid[0x80 * j], j, 6408 HDMI_EDID_BLOCK_SIZE)) 6409 goto err; 6410 if (drm_edid_block_valid(&edid[0x80 * j], j, 6411 true, NULL)) 6412 break; 6413 } 6414 6415 if (i == 4) 6416 goto err; 6417 block++; 6418 } 6419 6420 #ifdef DEBUG 6421 printf("RAW EDID:\n"); 6422 for (i = 0; i < block_num + 1; i++) { 6423 buff = &edid[0x80 * i]; 6424 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 6425 if (j % 16 == 0) 6426 printf("\n"); 6427 printf("0x%02x, ", buff[j]); 6428 } 6429 printf("\n"); 6430 } 6431 #endif 6432 6433 return 0; 6434 6435 err: 6436 printf("can't get edid block:%d\n", block); 6437 /* clear all read edid block, include invalid block */ 6438 memset(edid, 0, HDMI_EDID_BLOCK_SIZE * (block + 1)); 6439 return -EFAULT; 6440 } 6441 6442 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 6443 void *buffer, size_t size) 6444 { 6445 struct i2c_msg msgs[2] = { 6446 { 6447 .addr = addr, 6448 .flags = 0, 6449 .len = 1, 6450 .buf = &offset, 6451 }, { 6452 .addr = addr, 6453 .flags = I2C_M_RD, 6454 .len = size, 6455 .buf = buffer, 6456 } 6457 }; 6458 6459 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 6460 } 6461 6462 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 6463 const void *buffer, size_t size) 6464 { 6465 struct i2c_msg msg = { 6466 .addr = addr, 6467 .flags = 0, 6468 .len = 1 + size, 6469 .buf = NULL, 6470 }; 6471 void *data; 6472 int err; 6473 6474 data = malloc(1 + size); 6475 if (!data) 6476 return -ENOMEM; 6477 6478 msg.buf = data; 6479 6480 memcpy(data, &offset, sizeof(offset)); 6481 memcpy(data + 1, buffer, size); 6482 6483 err = adap->ddc_xfer(adap, &msg, 1); 6484 6485 free(data); 6486 6487 return err; 6488 } 6489 6490 /** 6491 * drm_scdc_readb - read a single byte from SCDC 6492 * @adap: ddc adapter 6493 * @offset: offset of register to read 6494 * @value: return location for the register value 6495 * 6496 * Reads a single byte from SCDC. This is a convenience wrapper around the 6497 * drm_scdc_read() function. 6498 * 6499 * Returns: 6500 * 0 on success or a negative error code on failure. 6501 */ 6502 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 6503 u8 *value) 6504 { 6505 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 6506 sizeof(*value)); 6507 } 6508 6509 /** 6510 * drm_scdc_writeb - write a single byte to SCDC 6511 * @adap: ddc adapter 6512 * @offset: offset of register to read 6513 * @value: return location for the register value 6514 * 6515 * Writes a single byte to SCDC. This is a convenience wrapper around the 6516 * drm_scdc_write() function. 6517 * 6518 * Returns: 6519 * 0 on success or a negative error code on failure. 6520 */ 6521 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 6522 u8 value) 6523 { 6524 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 6525 sizeof(value)); 6526 } 6527 6528