1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <hexdump.h> 22 #include <malloc.h> 23 #include <linux/compat.h> 24 #include <linux/ctype.h> 25 #include <linux/fb.h> 26 #include <linux/hdmi.h> 27 #include <linux/string.h> 28 29 #define EDID_EST_TIMINGS 16 30 #define EDID_STD_TIMINGS 8 31 #define EDID_DETAILED_TIMINGS 4 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 bool preferred; 78 u32 quirks; 79 int modes; 80 }; 81 82 #define LEVEL_DMT 0 83 #define LEVEL_GTF 1 84 #define LEVEL_GTF2 2 85 #define LEVEL_CVT 3 86 87 static struct edid_quirk { 88 char vendor[4]; 89 int product_id; 90 u32 quirks; 91 } edid_quirk_list[] = { 92 /* Acer AL1706 */ 93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Acer F51 */ 95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Unknown Acer */ 97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 98 99 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 100 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 116 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 146 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 147 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Probably taken from CEA-861 spec. 152 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 153 * 154 * Index using the VIC. 155 */ 156 static const struct drm_display_mode edid_cea_modes[] = { 157 /* 0 - dummy, VICs start at 1 */ 158 { }, 159 /* 1 - 640x480@60Hz */ 160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 161 752, 800, 480, 490, 492, 525, 0, 162 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 163 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 164 /* 2 - 720x480@60Hz */ 165 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 166 798, 858, 480, 489, 495, 525, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 168 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 169 /* 3 - 720x480@60Hz */ 170 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 171 798, 858, 480, 489, 495, 525, 0, 172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 173 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 174 /* 4 - 1280x720@60Hz */ 175 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 176 1430, 1650, 720, 725, 730, 750, 0, 177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 178 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 179 /* 5 - 1920x1080i@60Hz */ 180 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 181 2052, 2200, 1080, 1084, 1094, 1125, 0, 182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 183 DRM_MODE_FLAG_INTERLACE), 184 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 185 /* 6 - 720(1440)x480i@60Hz */ 186 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 187 801, 858, 480, 488, 494, 525, 0, 188 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 189 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 190 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 191 /* 7 - 720(1440)x480i@60Hz */ 192 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 193 801, 858, 480, 488, 494, 525, 0, 194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 195 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 196 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 197 /* 8 - 720(1440)x240@60Hz */ 198 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 199 801, 858, 240, 244, 247, 262, 0, 200 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 201 DRM_MODE_FLAG_DBLCLK), 202 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 203 /* 9 - 720(1440)x240@60Hz */ 204 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 205 801, 858, 240, 244, 247, 262, 0, 206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 207 DRM_MODE_FLAG_DBLCLK), 208 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 209 /* 10 - 2880x480i@60Hz */ 210 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 211 3204, 3432, 480, 488, 494, 525, 0, 212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 213 DRM_MODE_FLAG_INTERLACE), 214 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 215 /* 11 - 2880x480i@60Hz */ 216 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 217 3204, 3432, 480, 488, 494, 525, 0, 218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 219 DRM_MODE_FLAG_INTERLACE), 220 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 221 /* 12 - 2880x240@60Hz */ 222 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 223 3204, 3432, 240, 244, 247, 262, 0, 224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 225 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 226 /* 13 - 2880x240@60Hz */ 227 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 228 3204, 3432, 240, 244, 247, 262, 0, 229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 230 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 231 /* 14 - 1440x480@60Hz */ 232 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 233 1596, 1716, 480, 489, 495, 525, 0, 234 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 235 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 236 /* 15 - 1440x480@60Hz */ 237 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 238 1596, 1716, 480, 489, 495, 525, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 240 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 241 /* 16 - 1920x1080@60Hz */ 242 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 243 2052, 2200, 1080, 1084, 1089, 1125, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 245 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 246 /* 17 - 720x576@50Hz */ 247 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 248 796, 864, 576, 581, 586, 625, 0, 249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 250 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 251 /* 18 - 720x576@50Hz */ 252 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 253 796, 864, 576, 581, 586, 625, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 255 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 256 /* 19 - 1280x720@50Hz */ 257 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 258 1760, 1980, 720, 725, 730, 750, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 260 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 261 /* 20 - 1920x1080i@50Hz */ 262 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 263 2492, 2640, 1080, 1084, 1094, 1125, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 265 DRM_MODE_FLAG_INTERLACE), 266 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 267 /* 21 - 720(1440)x576i@50Hz */ 268 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 269 795, 864, 576, 580, 586, 625, 0, 270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 271 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 273 /* 22 - 720(1440)x576i@50Hz */ 274 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 275 795, 864, 576, 580, 586, 625, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 277 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 278 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 279 /* 23 - 720(1440)x288@50Hz */ 280 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 281 795, 864, 288, 290, 293, 312, 0, 282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 283 DRM_MODE_FLAG_DBLCLK), 284 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 285 /* 24 - 720(1440)x288@50Hz */ 286 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 287 795, 864, 288, 290, 293, 312, 0, 288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 289 DRM_MODE_FLAG_DBLCLK), 290 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 291 /* 25 - 2880x576i@50Hz */ 292 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 293 3180, 3456, 576, 580, 586, 625, 0, 294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 295 DRM_MODE_FLAG_INTERLACE), 296 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 297 /* 26 - 2880x576i@50Hz */ 298 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 299 3180, 3456, 576, 580, 586, 625, 0, 300 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 301 DRM_MODE_FLAG_INTERLACE), 302 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 303 /* 27 - 2880x288@50Hz */ 304 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 305 3180, 3456, 288, 290, 293, 312, 0, 306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 307 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 308 /* 28 - 2880x288@50Hz */ 309 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 310 3180, 3456, 288, 290, 293, 312, 0, 311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 312 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 313 /* 29 - 1440x576@50Hz */ 314 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 315 1592, 1728, 576, 581, 586, 625, 0, 316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 317 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 318 /* 30 - 1440x576@50Hz */ 319 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 320 1592, 1728, 576, 581, 586, 625, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 322 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 323 /* 31 - 1920x1080@50Hz */ 324 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 325 2492, 2640, 1080, 1084, 1089, 1125, 0, 326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 327 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 328 /* 32 - 1920x1080@24Hz */ 329 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 330 2602, 2750, 1080, 1084, 1089, 1125, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 332 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 333 /* 33 - 1920x1080@25Hz */ 334 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 335 2492, 2640, 1080, 1084, 1089, 1125, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 337 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 338 /* 34 - 1920x1080@30Hz */ 339 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 340 2052, 2200, 1080, 1084, 1089, 1125, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 342 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 343 /* 35 - 2880x480@60Hz */ 344 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 345 3192, 3432, 480, 489, 495, 525, 0, 346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 347 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 348 /* 36 - 2880x480@60Hz */ 349 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 350 3192, 3432, 480, 489, 495, 525, 0, 351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 352 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 353 /* 37 - 2880x576@50Hz */ 354 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 355 3184, 3456, 576, 581, 586, 625, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 357 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 358 /* 38 - 2880x576@50Hz */ 359 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 360 3184, 3456, 576, 581, 586, 625, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 362 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 363 /* 39 - 1920x1080i@50Hz */ 364 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 365 2120, 2304, 1080, 1126, 1136, 1250, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 367 DRM_MODE_FLAG_INTERLACE), 368 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 369 /* 40 - 1920x1080i@100Hz */ 370 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 371 2492, 2640, 1080, 1084, 1094, 1125, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 373 DRM_MODE_FLAG_INTERLACE), 374 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 375 /* 41 - 1280x720@100Hz */ 376 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 377 1760, 1980, 720, 725, 730, 750, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 379 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 380 /* 42 - 720x576@100Hz */ 381 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 382 796, 864, 576, 581, 586, 625, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 384 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 385 /* 43 - 720x576@100Hz */ 386 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 387 796, 864, 576, 581, 586, 625, 0, 388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 389 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 390 /* 44 - 720(1440)x576i@100Hz */ 391 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 392 795, 864, 576, 580, 586, 625, 0, 393 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 394 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 395 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 396 /* 45 - 720(1440)x576i@100Hz */ 397 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 398 795, 864, 576, 580, 586, 625, 0, 399 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 400 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 401 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 402 /* 46 - 1920x1080i@120Hz */ 403 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 404 2052, 2200, 1080, 1084, 1094, 1125, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 406 DRM_MODE_FLAG_INTERLACE), 407 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 408 /* 47 - 1280x720@120Hz */ 409 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 410 1430, 1650, 720, 725, 730, 750, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 412 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 413 /* 48 - 720x480@120Hz */ 414 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 415 798, 858, 480, 489, 495, 525, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 417 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 418 /* 49 - 720x480@120Hz */ 419 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 420 798, 858, 480, 489, 495, 525, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 422 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 423 /* 50 - 720(1440)x480i@120Hz */ 424 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 425 801, 858, 480, 488, 494, 525, 0, 426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 427 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 428 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 429 /* 51 - 720(1440)x480i@120Hz */ 430 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 431 801, 858, 480, 488, 494, 525, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 433 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 434 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 435 /* 52 - 720x576@200Hz */ 436 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 437 796, 864, 576, 581, 586, 625, 0, 438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 439 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 440 /* 53 - 720x576@200Hz */ 441 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 442 796, 864, 576, 581, 586, 625, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 444 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 445 /* 54 - 720(1440)x576i@200Hz */ 446 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 447 795, 864, 576, 580, 586, 625, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 449 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 450 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 451 /* 55 - 720(1440)x576i@200Hz */ 452 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 453 795, 864, 576, 580, 586, 625, 0, 454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 455 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 456 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 457 /* 56 - 720x480@240Hz */ 458 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 459 798, 858, 480, 489, 495, 525, 0, 460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 461 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 462 /* 57 - 720x480@240Hz */ 463 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 464 798, 858, 480, 489, 495, 525, 0, 465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 466 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 467 /* 58 - 720(1440)x480i@240 */ 468 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 469 801, 858, 480, 488, 494, 525, 0, 470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 471 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 472 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 473 /* 59 - 720(1440)x480i@240 */ 474 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 475 801, 858, 480, 488, 494, 525, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 477 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 478 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 479 /* 60 - 1280x720@24Hz */ 480 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 481 3080, 3300, 720, 725, 730, 750, 0, 482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 483 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 484 /* 61 - 1280x720@25Hz */ 485 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 486 3740, 3960, 720, 725, 730, 750, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 488 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 489 /* 62 - 1280x720@30Hz */ 490 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 491 3080, 3300, 720, 725, 730, 750, 0, 492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 493 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 494 /* 63 - 1920x1080@120Hz */ 495 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 496 2052, 2200, 1080, 1084, 1089, 1125, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 498 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 499 /* 64 - 1920x1080@100Hz */ 500 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 501 2492, 2640, 1080, 1084, 1089, 1125, 0, 502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 503 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 504 /* 65 - 1280x720@24Hz */ 505 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 506 3080, 3300, 720, 725, 730, 750, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 508 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 509 /* 66 - 1280x720@25Hz */ 510 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 511 3740, 3960, 720, 725, 730, 750, 0, 512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 513 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 514 /* 67 - 1280x720@30Hz */ 515 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 516 3080, 3300, 720, 725, 730, 750, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 518 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 519 /* 68 - 1280x720@50Hz */ 520 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 521 1760, 1980, 720, 725, 730, 750, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 523 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 524 /* 69 - 1280x720@60Hz */ 525 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 526 1430, 1650, 720, 725, 730, 750, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 528 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 529 /* 70 - 1280x720@100Hz */ 530 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 531 1760, 1980, 720, 725, 730, 750, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 533 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 534 /* 71 - 1280x720@120Hz */ 535 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 536 1430, 1650, 720, 725, 730, 750, 0, 537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 538 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 539 /* 72 - 1920x1080@24Hz */ 540 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 541 2602, 2750, 1080, 1084, 1089, 1125, 0, 542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 543 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 544 /* 73 - 1920x1080@25Hz */ 545 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 546 2492, 2640, 1080, 1084, 1089, 1125, 0, 547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 548 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 549 /* 74 - 1920x1080@30Hz */ 550 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 551 2052, 2200, 1080, 1084, 1089, 1125, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 553 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 554 /* 75 - 1920x1080@50Hz */ 555 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 556 2492, 2640, 1080, 1084, 1089, 1125, 0, 557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 558 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 559 /* 76 - 1920x1080@60Hz */ 560 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 561 2052, 2200, 1080, 1084, 1089, 1125, 0, 562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 563 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 564 /* 77 - 1920x1080@100Hz */ 565 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 566 2492, 2640, 1080, 1084, 1089, 1125, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 568 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 569 /* 78 - 1920x1080@120Hz */ 570 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 571 2052, 2200, 1080, 1084, 1089, 1125, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 573 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 574 /* 79 - 1680x720@24Hz */ 575 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 576 3080, 3300, 720, 725, 730, 750, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 578 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 579 /* 80 - 1680x720@25Hz */ 580 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 581 2948, 3168, 720, 725, 730, 750, 0, 582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 583 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 584 /* 81 - 1680x720@30Hz */ 585 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 586 2420, 2640, 720, 725, 730, 750, 0, 587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 588 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 589 /* 82 - 1680x720@50Hz */ 590 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 591 1980, 2200, 720, 725, 730, 750, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 593 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 594 /* 83 - 1680x720@60Hz */ 595 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 596 1980, 2200, 720, 725, 730, 750, 0, 597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 598 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 599 /* 84 - 1680x720@100Hz */ 600 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 601 1780, 2000, 720, 725, 730, 825, 0, 602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 603 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 604 /* 85 - 1680x720@120Hz */ 605 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 606 1780, 2000, 720, 725, 730, 825, 0, 607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 608 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 609 /* 86 - 2560x1080@24Hz */ 610 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 611 3602, 3750, 1080, 1084, 1089, 1100, 0, 612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 613 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 614 /* 87 - 2560x1080@25Hz */ 615 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 616 3052, 3200, 1080, 1084, 1089, 1125, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 618 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 619 /* 88 - 2560x1080@30Hz */ 620 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 621 3372, 3520, 1080, 1084, 1089, 1125, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 623 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 624 /* 89 - 2560x1080@50Hz */ 625 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 626 3152, 3300, 1080, 1084, 1089, 1125, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 628 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 629 /* 90 - 2560x1080@60Hz */ 630 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 631 2852, 3000, 1080, 1084, 1089, 1100, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 633 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 634 /* 91 - 2560x1080@100Hz */ 635 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 636 2822, 2970, 1080, 1084, 1089, 1250, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 638 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 639 /* 92 - 2560x1080@120Hz */ 640 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 641 3152, 3300, 1080, 1084, 1089, 1250, 0, 642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 643 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 644 /* 93 - 3840x2160p@24Hz 16:9 */ 645 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 646 5204, 5500, 2160, 2168, 2178, 2250, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 648 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 649 /* 94 - 3840x2160p@25Hz 16:9 */ 650 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 651 4984, 5280, 2160, 2168, 2178, 2250, 0, 652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 653 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 654 /* 95 - 3840x2160p@30Hz 16:9 */ 655 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 656 4104, 4400, 2160, 2168, 2178, 2250, 0, 657 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 658 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 659 /* 96 - 3840x2160p@50Hz 16:9 */ 660 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 661 4984, 5280, 2160, 2168, 2178, 2250, 0, 662 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 663 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 664 /* 97 - 3840x2160p@60Hz 16:9 */ 665 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 666 4104, 4400, 2160, 2168, 2178, 2250, 0, 667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 669 /* 98 - 4096x2160p@24Hz 256:135 */ 670 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 671 5204, 5500, 2160, 2168, 2178, 2250, 0, 672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 673 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 674 /* 99 - 4096x2160p@25Hz 256:135 */ 675 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 676 5152, 5280, 2160, 2168, 2178, 2250, 0, 677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 678 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 679 /* 100 - 4096x2160p@30Hz 256:135 */ 680 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 681 4272, 4400, 2160, 2168, 2178, 2250, 0, 682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 683 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 684 /* 101 - 4096x2160p@50Hz 256:135 */ 685 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 686 5152, 5280, 2160, 2168, 2178, 2250, 0, 687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 688 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 689 /* 102 - 4096x2160p@60Hz 256:135 */ 690 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 691 4272, 4400, 2160, 2168, 2178, 2250, 0, 692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 693 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 694 /* 103 - 3840x2160p@24Hz 64:27 */ 695 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 696 5204, 5500, 2160, 2168, 2178, 2250, 0, 697 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 698 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 699 /* 104 - 3840x2160p@25Hz 64:27 */ 700 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 701 4104, 4400, 2160, 2168, 2178, 2250, 0, 702 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 703 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 704 /* 105 - 3840x2160p@30Hz 64:27 */ 705 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 706 4104, 4400, 2160, 2168, 2178, 2250, 0, 707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 708 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 709 /* 106 - 3840x2160p@50Hz 64:27 */ 710 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 711 4984, 5280, 2160, 2168, 2178, 2250, 0, 712 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 713 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 714 /* 107 - 3840x2160p@60Hz 64:27 */ 715 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 716 4104, 4400, 2160, 2168, 2178, 2250, 0, 717 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 718 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 719 }; 720 721 /* 722 * HDMI 1.4 4k modes. Index using the VIC. 723 */ 724 static const struct drm_display_mode edid_4k_modes[] = { 725 /* 0 - dummy, VICs start at 1 */ 726 { }, 727 /* 1 - 3840x2160@30Hz */ 728 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 729 3840, 4016, 4104, 4400, 730 2160, 2168, 2178, 2250, 0, 731 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 732 .vrefresh = 30, }, 733 /* 2 - 3840x2160@25Hz */ 734 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 735 3840, 4896, 4984, 5280, 736 2160, 2168, 2178, 2250, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .vrefresh = 25, }, 739 /* 3 - 3840x2160@24Hz */ 740 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 741 3840, 5116, 5204, 5500, 742 2160, 2168, 2178, 2250, 0, 743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 744 .vrefresh = 24, }, 745 /* 4 - 4096x2160@24Hz (SMPTE) */ 746 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 747 4096, 5116, 5204, 5500, 748 2160, 2168, 2178, 2250, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 24, }, 751 }; 752 753 /* 754 * Autogenerated from the DMT spec. 755 * This table is copied from xfree86/modes/xf86EdidModes.c. 756 */ 757 static const struct drm_display_mode drm_dmt_modes[] = { 758 /* 0x01 - 640x350@85Hz */ 759 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 760 736, 832, 350, 382, 385, 445, 0, 761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 762 /* 0x02 - 640x400@85Hz */ 763 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 764 736, 832, 400, 401, 404, 445, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 766 /* 0x03 - 720x400@85Hz */ 767 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 768 828, 936, 400, 401, 404, 446, 0, 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 770 /* 0x04 - 640x480@60Hz */ 771 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 772 752, 800, 480, 490, 492, 525, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 774 /* 0x05 - 640x480@72Hz */ 775 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 776 704, 832, 480, 489, 492, 520, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 778 /* 0x06 - 640x480@75Hz */ 779 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 780 720, 840, 480, 481, 484, 500, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 782 /* 0x07 - 640x480@85Hz */ 783 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 784 752, 832, 480, 481, 484, 509, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 786 /* 0x08 - 800x600@56Hz */ 787 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 788 896, 1024, 600, 601, 603, 625, 0, 789 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 790 /* 0x09 - 800x600@60Hz */ 791 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 792 968, 1056, 600, 601, 605, 628, 0, 793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 794 /* 0x0a - 800x600@72Hz */ 795 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 796 976, 1040, 600, 637, 643, 666, 0, 797 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 798 /* 0x0b - 800x600@75Hz */ 799 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 800 896, 1056, 600, 601, 604, 625, 0, 801 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 802 /* 0x0c - 800x600@85Hz */ 803 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 804 896, 1048, 600, 601, 604, 631, 0, 805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 806 /* 0x0d - 800x600@120Hz RB */ 807 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 808 880, 960, 600, 603, 607, 636, 0, 809 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 810 /* 0x0e - 848x480@60Hz */ 811 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 812 976, 1088, 480, 486, 494, 517, 0, 813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 814 /* 0x0f - 1024x768@43Hz, interlace */ 815 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 816 1208, 1264, 768, 768, 772, 817, 0, 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 818 DRM_MODE_FLAG_INTERLACE) }, 819 /* 0x10 - 1024x768@60Hz */ 820 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 821 1184, 1344, 768, 771, 777, 806, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 823 /* 0x11 - 1024x768@70Hz */ 824 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 825 1184, 1328, 768, 771, 777, 806, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 827 /* 0x12 - 1024x768@75Hz */ 828 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 829 1136, 1312, 768, 769, 772, 800, 0, 830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 831 /* 0x13 - 1024x768@85Hz */ 832 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 833 1168, 1376, 768, 769, 772, 808, 0, 834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 835 /* 0x14 - 1024x768@120Hz RB */ 836 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 837 1104, 1184, 768, 771, 775, 813, 0, 838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 839 /* 0x15 - 1152x864@75Hz */ 840 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 841 1344, 1600, 864, 865, 868, 900, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 843 /* 0x55 - 1280x720@60Hz */ 844 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 845 1430, 1650, 720, 725, 730, 750, 0, 846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 847 /* 0x16 - 1280x768@60Hz RB */ 848 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 849 1360, 1440, 768, 771, 778, 790, 0, 850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 851 /* 0x17 - 1280x768@60Hz */ 852 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 853 1472, 1664, 768, 771, 778, 798, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 855 /* 0x18 - 1280x768@75Hz */ 856 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 857 1488, 1696, 768, 771, 778, 805, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 859 /* 0x19 - 1280x768@85Hz */ 860 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 861 1496, 1712, 768, 771, 778, 809, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 863 /* 0x1a - 1280x768@120Hz RB */ 864 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 865 1360, 1440, 768, 771, 778, 813, 0, 866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 867 /* 0x1b - 1280x800@60Hz RB */ 868 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 869 1360, 1440, 800, 803, 809, 823, 0, 870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 871 /* 0x1c - 1280x800@60Hz */ 872 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 873 1480, 1680, 800, 803, 809, 831, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 875 /* 0x1d - 1280x800@75Hz */ 876 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 877 1488, 1696, 800, 803, 809, 838, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 879 /* 0x1e - 1280x800@85Hz */ 880 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 881 1496, 1712, 800, 803, 809, 843, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 883 /* 0x1f - 1280x800@120Hz RB */ 884 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 885 1360, 1440, 800, 803, 809, 847, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 887 /* 0x20 - 1280x960@60Hz */ 888 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 889 1488, 1800, 960, 961, 964, 1000, 0, 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 891 /* 0x21 - 1280x960@85Hz */ 892 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 893 1504, 1728, 960, 961, 964, 1011, 0, 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 895 /* 0x22 - 1280x960@120Hz RB */ 896 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 897 1360, 1440, 960, 963, 967, 1017, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 899 /* 0x23 - 1280x1024@60Hz */ 900 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 901 1440, 1688, 1024, 1025, 1028, 1066, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 903 /* 0x24 - 1280x1024@75Hz */ 904 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 905 1440, 1688, 1024, 1025, 1028, 1066, 0, 906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 907 /* 0x25 - 1280x1024@85Hz */ 908 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 909 1504, 1728, 1024, 1025, 1028, 1072, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 911 /* 0x26 - 1280x1024@120Hz RB */ 912 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 913 1360, 1440, 1024, 1027, 1034, 1084, 0, 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 915 /* 0x27 - 1360x768@60Hz */ 916 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 917 1536, 1792, 768, 771, 777, 795, 0, 918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 919 /* 0x28 - 1360x768@120Hz RB */ 920 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 921 1440, 1520, 768, 771, 776, 813, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 923 /* 0x51 - 1366x768@60Hz */ 924 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 925 1579, 1792, 768, 771, 774, 798, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 927 /* 0x56 - 1366x768@60Hz */ 928 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 929 1436, 1500, 768, 769, 772, 800, 0, 930 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 931 /* 0x29 - 1400x1050@60Hz RB */ 932 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 933 1480, 1560, 1050, 1053, 1057, 1080, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 935 /* 0x2a - 1400x1050@60Hz */ 936 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 937 1632, 1864, 1050, 1053, 1057, 1089, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 939 /* 0x2b - 1400x1050@75Hz */ 940 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 941 1648, 1896, 1050, 1053, 1057, 1099, 0, 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 943 /* 0x2c - 1400x1050@85Hz */ 944 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 945 1656, 1912, 1050, 1053, 1057, 1105, 0, 946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 947 /* 0x2d - 1400x1050@120Hz RB */ 948 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 949 1480, 1560, 1050, 1053, 1057, 1112, 0, 950 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 951 /* 0x2e - 1440x900@60Hz RB */ 952 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 953 1520, 1600, 900, 903, 909, 926, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 955 /* 0x2f - 1440x900@60Hz */ 956 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 957 1672, 1904, 900, 903, 909, 934, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 959 /* 0x30 - 1440x900@75Hz */ 960 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 961 1688, 1936, 900, 903, 909, 942, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 963 /* 0x31 - 1440x900@85Hz */ 964 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 965 1696, 1952, 900, 903, 909, 948, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 967 /* 0x32 - 1440x900@120Hz RB */ 968 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 969 1520, 1600, 900, 903, 909, 953, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 971 /* 0x53 - 1600x900@60Hz */ 972 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 973 1704, 1800, 900, 901, 904, 1000, 0, 974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 975 /* 0x33 - 1600x1200@60Hz */ 976 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 977 1856, 2160, 1200, 1201, 1204, 1250, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 979 /* 0x34 - 1600x1200@65Hz */ 980 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 981 1856, 2160, 1200, 1201, 1204, 1250, 0, 982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 983 /* 0x35 - 1600x1200@70Hz */ 984 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 985 1856, 2160, 1200, 1201, 1204, 1250, 0, 986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 987 /* 0x36 - 1600x1200@75Hz */ 988 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 989 1856, 2160, 1200, 1201, 1204, 1250, 0, 990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 991 /* 0x37 - 1600x1200@85Hz */ 992 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 993 1856, 2160, 1200, 1201, 1204, 1250, 0, 994 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 995 /* 0x38 - 1600x1200@120Hz RB */ 996 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 997 1680, 1760, 1200, 1203, 1207, 1271, 0, 998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 999 /* 0x39 - 1680x1050@60Hz RB */ 1000 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1001 1760, 1840, 1050, 1053, 1059, 1080, 0, 1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1003 /* 0x3a - 1680x1050@60Hz */ 1004 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1005 1960, 2240, 1050, 1053, 1059, 1089, 0, 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1007 /* 0x3b - 1680x1050@75Hz */ 1008 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1009 1976, 2272, 1050, 1053, 1059, 1099, 0, 1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1011 /* 0x3c - 1680x1050@85Hz */ 1012 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1013 1984, 2288, 1050, 1053, 1059, 1105, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1015 /* 0x3d - 1680x1050@120Hz RB */ 1016 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1017 1760, 1840, 1050, 1053, 1059, 1112, 0, 1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1019 /* 0x3e - 1792x1344@60Hz */ 1020 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1021 2120, 2448, 1344, 1345, 1348, 1394, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1023 /* 0x3f - 1792x1344@75Hz */ 1024 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1025 2104, 2456, 1344, 1345, 1348, 1417, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1027 /* 0x40 - 1792x1344@120Hz RB */ 1028 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1029 1872, 1952, 1344, 1347, 1351, 1423, 0, 1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1031 /* 0x41 - 1856x1392@60Hz */ 1032 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1033 2176, 2528, 1392, 1393, 1396, 1439, 0, 1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1035 /* 0x42 - 1856x1392@75Hz */ 1036 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1037 2208, 2560, 1392, 1393, 1396, 1500, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1039 /* 0x43 - 1856x1392@120Hz RB */ 1040 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1041 1936, 2016, 1392, 1395, 1399, 1474, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1043 /* 0x52 - 1920x1080@60Hz */ 1044 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1045 2052, 2200, 1080, 1084, 1089, 1125, 0, 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1047 /* 0x44 - 1920x1200@60Hz RB */ 1048 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1049 2000, 2080, 1200, 1203, 1209, 1235, 0, 1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1051 /* 0x45 - 1920x1200@60Hz */ 1052 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1053 2256, 2592, 1200, 1203, 1209, 1245, 0, 1054 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1055 /* 0x46 - 1920x1200@75Hz */ 1056 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1057 2264, 2608, 1200, 1203, 1209, 1255, 0, 1058 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1059 /* 0x47 - 1920x1200@85Hz */ 1060 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1061 2272, 2624, 1200, 1203, 1209, 1262, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1063 /* 0x48 - 1920x1200@120Hz RB */ 1064 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1065 2000, 2080, 1200, 1203, 1209, 1271, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1067 /* 0x49 - 1920x1440@60Hz */ 1068 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1069 2256, 2600, 1440, 1441, 1444, 1500, 0, 1070 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1071 /* 0x4a - 1920x1440@75Hz */ 1072 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1073 2288, 2640, 1440, 1441, 1444, 1500, 0, 1074 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1075 /* 0x4b - 1920x1440@120Hz RB */ 1076 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1077 2000, 2080, 1440, 1443, 1447, 1525, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1079 /* 0x54 - 2048x1152@60Hz */ 1080 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1081 2154, 2250, 1152, 1153, 1156, 1200, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1083 /* 0x4c - 2560x1600@60Hz RB */ 1084 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1085 2640, 2720, 1600, 1603, 1609, 1646, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1087 /* 0x4d - 2560x1600@60Hz */ 1088 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1089 3032, 3504, 1600, 1603, 1609, 1658, 0, 1090 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1091 /* 0x4e - 2560x1600@75Hz */ 1092 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1093 3048, 3536, 1600, 1603, 1609, 1672, 0, 1094 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1095 /* 0x4f - 2560x1600@85Hz */ 1096 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1097 3048, 3536, 1600, 1603, 1609, 1682, 0, 1098 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1099 /* 0x50 - 2560x1600@120Hz RB */ 1100 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1101 2640, 2720, 1600, 1603, 1609, 1694, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1103 /* 0x57 - 4096x2160@60Hz RB */ 1104 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1105 4136, 4176, 2160, 2208, 2216, 2222, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1107 /* 0x58 - 4096x2160@59.94Hz RB */ 1108 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1109 4136, 4176, 2160, 2208, 2216, 2222, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1111 }; 1112 1113 /* 1114 * These more or less come from the DMT spec. The 720x400 modes are 1115 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1116 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1117 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1118 * mode. 1119 * 1120 * The DMT modes have been fact-checked; the rest are mild guesses. 1121 */ 1122 static const struct drm_display_mode edid_est_modes[] = { 1123 /* 800x600@60Hz */ 1124 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1125 968, 1056, 600, 601, 605, 628, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1127 /* 800x600@56Hz */ 1128 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1129 896, 1024, 600, 601, 603, 625, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1131 /* 640x480@75Hz */ 1132 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1133 720, 840, 480, 481, 484, 500, 0, 1134 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1135 /* 640x480@72Hz */ 1136 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1137 704, 832, 480, 489, 492, 520, 0, 1138 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1139 /* 640x480@67Hz */ 1140 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1141 768, 864, 480, 483, 486, 525, 0, 1142 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1143 /* 640x480@60Hz */ 1144 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1145 752, 800, 480, 490, 492, 525, 0, 1146 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1147 /* 720x400@88Hz */ 1148 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1149 846, 900, 400, 421, 423, 449, 0, 1150 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1151 /* 720x400@70Hz */ 1152 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1153 846, 900, 400, 412, 414, 449, 0, 1154 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1155 /* 1280x1024@75Hz */ 1156 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1157 1440, 1688, 1024, 1025, 1028, 1066, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1159 /* 1024x768@75Hz */ 1160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1161 1136, 1312, 768, 769, 772, 800, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1163 /* 1024x768@70Hz */ 1164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1165 1184, 1328, 768, 771, 777, 806, 0, 1166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1167 /* 1024x768@60Hz */ 1168 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1169 1184, 1344, 768, 771, 777, 806, 0, 1170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1171 /* 1024x768@43Hz */ 1172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1173 1208, 1264, 768, 768, 776, 817, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1175 DRM_MODE_FLAG_INTERLACE) }, 1176 /* 832x624@75Hz */ 1177 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1178 928, 1152, 624, 625, 628, 667, 0, 1179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1180 /* 800x600@75Hz */ 1181 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1182 896, 1056, 600, 601, 604, 625, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1184 /* 800x600@72Hz */ 1185 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1186 976, 1040, 600, 637, 643, 666, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1188 /* 1152x864@75Hz */ 1189 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1190 1344, 1600, 864, 865, 868, 900, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1192 }; 1193 1194 #define DRM_BASE_MODE(c, hd, hss, hse, ht, vd, vss, vse, vt, vs, f) \ 1195 .clock = (c), \ 1196 .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ 1197 .htotal = (ht), .vdisplay = (vd), \ 1198 .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ 1199 .vscan = (vs), .flags = (f) 1200 1201 static const struct base_drm_display_mode resolution_white[] = { 1202 /* 0. vic:2 - 720x480@60Hz */ 1203 { DRM_BASE_MODE(27000, 720, 736, 1204 798, 858, 480, 489, 495, 525, 0, 1205 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1206 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1207 /* 1. vic:3 - 720x480@60Hz */ 1208 { DRM_BASE_MODE(27000, 720, 736, 1209 798, 858, 480, 489, 495, 525, 0, 1210 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1211 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1212 /* 1024x768@60Hz */ 1213 { DRM_BASE_MODE(65000, 1024, 1048, 1214 1184, 1344, 768, 771, 777, 806, 0, 1215 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1216 /* 2. vic:4 - 1280x720@60Hz */ 1217 { DRM_BASE_MODE(74250, 1280, 1390, 1218 1430, 1650, 720, 725, 730, 750, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1221 /* 3. vic:5 - 1920x1080i@60Hz */ 1222 { DRM_BASE_MODE(74250, 1920, 2008, 1223 2052, 2200, 1080, 1084, 1094, 1125, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1225 DRM_MODE_FLAG_INTERLACE), 1226 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1227 /* 4. vic:6 - 720(1440)x480i@60Hz */ 1228 { DRM_BASE_MODE(13500, 720, 739, 1229 801, 858, 480, 488, 494, 525, 0, 1230 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1231 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1232 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1233 /* 5. vic:16 - 1920x1080@60Hz */ 1234 { DRM_BASE_MODE(148500, 1920, 2008, 1235 2052, 2200, 1080, 1084, 1089, 1125, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1238 /* 6. vic:17 - 720x576@50Hz */ 1239 { DRM_BASE_MODE(27000, 720, 732, 1240 796, 864, 576, 581, 586, 625, 0, 1241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1242 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1243 /* 7. vic:18 - 720x576@50Hz */ 1244 { DRM_BASE_MODE(27000, 720, 732, 1245 796, 864, 576, 581, 586, 625, 0, 1246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1247 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1248 /* 8. vic:19 - 1280x720@50Hz */ 1249 { DRM_BASE_MODE(74250, 1280, 1720, 1250 1760, 1980, 720, 725, 730, 750, 0, 1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1252 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1253 /* 9. vic:20 - 1920x1080i@50Hz */ 1254 { DRM_BASE_MODE(74250, 1920, 2448, 1255 2492, 2640, 1080, 1084, 1094, 1125, 0, 1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1257 DRM_MODE_FLAG_INTERLACE), 1258 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1259 /* 10. vic:21 - 720(1440)x576i@50Hz */ 1260 { DRM_BASE_MODE(13500, 720, 732, 1261 795, 864, 576, 580, 586, 625, 0, 1262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1263 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1264 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1265 /* 11. vic:31 - 1920x1080@50Hz */ 1266 { DRM_BASE_MODE(148500, 1920, 2448, 1267 2492, 2640, 1080, 1084, 1089, 1125, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1270 /* 12. vic:32 - 1920x1080@24Hz */ 1271 { DRM_BASE_MODE(74250, 1920, 2558, 1272 2602, 2750, 1080, 1084, 1089, 1125, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1275 /* 13. vic:33 - 1920x1080@25Hz */ 1276 { DRM_BASE_MODE(74250, 1920, 2448, 1277 2492, 2640, 1080, 1084, 1089, 1125, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1280 /* 14. vic:34 - 1920x1080@30Hz */ 1281 { DRM_BASE_MODE(74250, 1920, 2008, 1282 2052, 2200, 1080, 1084, 1089, 1125, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1285 /* 15. vic:39 - 1920x1080i@50Hz */ 1286 { DRM_BASE_MODE(72000, 1920, 1952, 1287 2120, 2304, 1080, 1126, 1136, 1250, 0, 1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 1289 DRM_MODE_FLAG_INTERLACE), 1290 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1291 /* 16. vic:60 - 1280x720@24Hz */ 1292 { DRM_BASE_MODE(59400, 1280, 3040, 1293 3080, 3300, 720, 725, 730, 750, 0, 1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1295 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1296 /* 17. vic:61 - 1280x720@25Hz */ 1297 { DRM_BASE_MODE(74250, 1280, 3700, 1298 3740, 3960, 720, 725, 730, 750, 0, 1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1300 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1301 /* 18. vic:62 - 1280x720@30Hz */ 1302 { DRM_BASE_MODE(74250, 1280, 3040, 1303 3080, 3300, 720, 725, 730, 750, 0, 1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1305 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1306 /* 19. vic:93 - 3840x2160p@24Hz 16:9 */ 1307 { DRM_BASE_MODE(297000, 3840, 5116, 1308 5204, 5500, 2160, 2168, 2178, 2250, 0, 1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1310 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1311 /* 20. vic:94 - 3840x2160p@25Hz 16:9 */ 1312 { DRM_BASE_MODE(297000, 3840, 4896, 1313 4984, 5280, 2160, 2168, 2178, 2250, 0, 1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1315 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1316 /* 21. vic:95 - 3840x2160p@30Hz 16:9 */ 1317 { DRM_BASE_MODE(297000, 3840, 4016, 1318 4104, 4400, 2160, 2168, 2178, 2250, 0, 1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1320 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1321 /* 22. vic:96 - 3840x2160p@50Hz 16:9 */ 1322 { DRM_BASE_MODE(594000, 3840, 4896, 1323 4984, 5280, 2160, 2168, 2178, 2250, 0, 1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1325 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1326 /* 23. vic:97 - 3840x2160p@60Hz 16:9 */ 1327 { DRM_BASE_MODE(594000, 3840, 4016, 1328 4104, 4400, 2160, 2168, 2178, 2250, 0, 1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1330 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1331 /* 24. vic:98 - 4096x2160p@24Hz 256:135 */ 1332 { DRM_BASE_MODE(297000, 4096, 5116, 1333 5204, 5500, 2160, 2168, 2178, 2250, 0, 1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1335 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1336 /* 25. vic:99 - 4096x2160p@25Hz 256:135 */ 1337 { DRM_BASE_MODE(297000, 4096, 5064, 1338 5152, 5280, 2160, 2168, 2178, 2250, 0, 1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1340 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1341 /* 26. vic:100 - 4096x2160p@30Hz 256:135 */ 1342 { DRM_BASE_MODE(297000, 4096, 4184, 1343 4272, 4400, 2160, 2168, 2178, 2250, 0, 1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1345 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1346 /* 27. vic:101 - 4096x2160p@50Hz 256:135 */ 1347 { DRM_BASE_MODE(594000, 4096, 5064, 1348 5152, 5280, 2160, 2168, 2178, 2250, 0, 1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1350 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1351 /* 28. vic:102 - 4096x2160p@60Hz 256:135 */ 1352 { DRM_BASE_MODE(594000, 4096, 4184, 1353 4272, 4400, 2160, 2168, 2178, 2250, 0, 1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1355 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1356 }; 1357 1358 struct minimode { 1359 short w; 1360 short h; 1361 short r; 1362 short rb; 1363 }; 1364 1365 static const struct minimode est3_modes[] = { 1366 /* byte 6 */ 1367 { 640, 350, 85, 0 }, 1368 { 640, 400, 85, 0 }, 1369 { 720, 400, 85, 0 }, 1370 { 640, 480, 85, 0 }, 1371 { 848, 480, 60, 0 }, 1372 { 800, 600, 85, 0 }, 1373 { 1024, 768, 85, 0 }, 1374 { 1152, 864, 75, 0 }, 1375 /* byte 7 */ 1376 { 1280, 768, 60, 1 }, 1377 { 1280, 768, 60, 0 }, 1378 { 1280, 768, 75, 0 }, 1379 { 1280, 768, 85, 0 }, 1380 { 1280, 960, 60, 0 }, 1381 { 1280, 960, 85, 0 }, 1382 { 1280, 1024, 60, 0 }, 1383 { 1280, 1024, 85, 0 }, 1384 /* byte 8 */ 1385 { 1360, 768, 60, 0 }, 1386 { 1440, 900, 60, 1 }, 1387 { 1440, 900, 60, 0 }, 1388 { 1440, 900, 75, 0 }, 1389 { 1440, 900, 85, 0 }, 1390 { 1400, 1050, 60, 1 }, 1391 { 1400, 1050, 60, 0 }, 1392 { 1400, 1050, 75, 0 }, 1393 /* byte 9 */ 1394 { 1400, 1050, 85, 0 }, 1395 { 1680, 1050, 60, 1 }, 1396 { 1680, 1050, 60, 0 }, 1397 { 1680, 1050, 75, 0 }, 1398 { 1680, 1050, 85, 0 }, 1399 { 1600, 1200, 60, 0 }, 1400 { 1600, 1200, 65, 0 }, 1401 { 1600, 1200, 70, 0 }, 1402 /* byte 10 */ 1403 { 1600, 1200, 75, 0 }, 1404 { 1600, 1200, 85, 0 }, 1405 { 1792, 1344, 60, 0 }, 1406 { 1792, 1344, 75, 0 }, 1407 { 1856, 1392, 60, 0 }, 1408 { 1856, 1392, 75, 0 }, 1409 { 1920, 1200, 60, 1 }, 1410 { 1920, 1200, 60, 0 }, 1411 /* byte 11 */ 1412 { 1920, 1200, 75, 0 }, 1413 { 1920, 1200, 85, 0 }, 1414 { 1920, 1440, 60, 0 }, 1415 { 1920, 1440, 75, 0 }, 1416 }; 1417 1418 static const struct minimode extra_modes[] = { 1419 { 1024, 576, 60, 0 }, 1420 { 1366, 768, 60, 0 }, 1421 { 1600, 900, 60, 0 }, 1422 { 1680, 945, 60, 0 }, 1423 { 1920, 1080, 60, 0 }, 1424 { 2048, 1152, 60, 0 }, 1425 { 2048, 1536, 60, 0 }, 1426 }; 1427 1428 int edid_check_info(struct edid1_info *edid_info) 1429 { 1430 if ((edid_info == NULL) || (edid_info->version == 0)) 1431 return -1; 1432 1433 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1434 return -1; 1435 1436 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1437 return -1; 1438 1439 return 0; 1440 } 1441 1442 int edid_check_checksum(u8 *edid_block) 1443 { 1444 u8 checksum = 0; 1445 int i; 1446 1447 for (i = 0; i < 128; i++) 1448 checksum += edid_block[i]; 1449 1450 return (checksum == 0) ? 0 : -EINVAL; 1451 } 1452 1453 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1454 unsigned int *hmax, unsigned int *vmin, 1455 unsigned int *vmax) 1456 { 1457 int i; 1458 struct edid_monitor_descriptor *monitor; 1459 1460 *hmin = *hmax = *vmin = *vmax = 0; 1461 if (edid_check_info(edid)) 1462 return -1; 1463 1464 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1465 monitor = &edid->monitor_details.descriptor[i]; 1466 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1467 *hmin = monitor->data.range_data.horizontal_min; 1468 *hmax = monitor->data.range_data.horizontal_max; 1469 *vmin = monitor->data.range_data.vertical_min; 1470 *vmax = monitor->data.range_data.vertical_max; 1471 return 0; 1472 } 1473 } 1474 return -1; 1475 } 1476 1477 /* Set all parts of a timing entry to the same value */ 1478 static void set_entry(struct timing_entry *entry, u32 value) 1479 { 1480 entry->min = value; 1481 entry->typ = value; 1482 entry->max = value; 1483 } 1484 1485 /** 1486 * decode_timing() - Decoding an 18-byte detailed timing record 1487 * 1488 * @buf: Pointer to EDID detailed timing record 1489 * @timing: Place to put timing 1490 */ 1491 static void decode_timing(u8 *buf, struct display_timing *timing) 1492 { 1493 uint x_mm, y_mm; 1494 unsigned int ha, hbl, hso, hspw, hborder; 1495 unsigned int va, vbl, vso, vspw, vborder; 1496 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1497 1498 /* Edid contains pixel clock in terms of 10KHz */ 1499 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1500 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1501 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1502 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1503 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1504 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1505 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1506 hborder = buf[15]; 1507 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1508 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1509 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1510 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1511 vborder = buf[16]; 1512 1513 set_entry(&timing->hactive, ha); 1514 set_entry(&timing->hfront_porch, hso); 1515 set_entry(&timing->hback_porch, hbl - hso - hspw); 1516 set_entry(&timing->hsync_len, hspw); 1517 1518 set_entry(&timing->vactive, va); 1519 set_entry(&timing->vfront_porch, vso); 1520 set_entry(&timing->vback_porch, vbl - vso - vspw); 1521 set_entry(&timing->vsync_len, vspw); 1522 1523 timing->flags = 0; 1524 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1525 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1526 else 1527 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1528 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1529 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1530 else 1531 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1532 1533 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1534 timing->flags = DISPLAY_FLAGS_INTERLACED; 1535 1536 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1537 " %04x %04x %04x %04x hborder %x\n" 1538 " %04x %04x %04x %04x vborder %x\n", 1539 timing->pixelclock.typ, 1540 x_mm, y_mm, 1541 ha, ha + hso, ha + hso + hspw, 1542 ha + hbl, hborder, 1543 va, va + vso, va + vso + vspw, 1544 va + vbl, vborder); 1545 } 1546 1547 /** 1548 * decode_mode() - Decoding an 18-byte detailed timing record 1549 * 1550 * @buf: Pointer to EDID detailed timing record 1551 * @timing: Place to put timing 1552 */ 1553 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1554 { 1555 uint x_mm, y_mm; 1556 unsigned int ha, hbl, hso, hspw, hborder; 1557 unsigned int va, vbl, vso, vspw, vborder; 1558 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1559 1560 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1561 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1562 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1563 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1564 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1565 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1566 hborder = buf[15]; 1567 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1568 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1569 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1570 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1571 vborder = buf[16]; 1572 1573 /* Edid contains pixel clock in terms of 10KHz */ 1574 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1575 mode->hdisplay = ha; 1576 mode->hsync_start = ha + hso; 1577 mode->hsync_end = ha + hso + hspw; 1578 mode->htotal = ha + hbl; 1579 mode->vdisplay = va; 1580 mode->vsync_start = va + vso; 1581 mode->vsync_end = va + vso + vspw; 1582 mode->vtotal = va + vbl; 1583 1584 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1585 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1586 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1587 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1588 1589 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1590 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1591 1592 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1593 " %04d %04d %04d %04d hborder %d\n" 1594 " %04d %04d %04d %04d vborder %d\n", 1595 mode->clock, 1596 x_mm, y_mm, mode->flags, 1597 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1598 mode->htotal, hborder, 1599 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1600 mode->vtotal, vborder); 1601 } 1602 1603 /** 1604 * edid_vendor - match a string against EDID's obfuscated vendor field 1605 * @edid: EDID to match 1606 * @vendor: vendor string 1607 * 1608 * Returns true if @vendor is in @edid, false otherwise 1609 */ 1610 static bool edid_vendor(struct edid *edid, char *vendor) 1611 { 1612 char edid_vendor[3]; 1613 1614 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1615 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1616 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1617 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1618 1619 return !strncmp(edid_vendor, vendor, 3); 1620 } 1621 1622 /** 1623 * Check if HDMI vendor specific data block is present in CEA block 1624 * @param info CEA extension block 1625 * @return true if block is found 1626 */ 1627 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1628 { 1629 u8 end, i = 0; 1630 1631 /* check for end of data block */ 1632 end = info->dtd_offset; 1633 if (end == 0) 1634 end = sizeof(info->data); 1635 if (end < 4 || end > sizeof(info->data)) 1636 return false; 1637 end -= 4; 1638 1639 while (i < end) { 1640 /* Look for vendor specific data block of appropriate size */ 1641 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1642 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1643 u8 *db = &info->data[i + 1]; 1644 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1645 1646 if (oui == HDMI_IEEE_OUI) 1647 return true; 1648 } 1649 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1650 } 1651 1652 return false; 1653 } 1654 1655 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1656 { 1657 int refresh = 0; 1658 unsigned int calc_val; 1659 1660 if (mode->vrefresh > 0) { 1661 refresh = mode->vrefresh; 1662 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1663 int vtotal; 1664 1665 vtotal = mode->vtotal; 1666 /* work out vrefresh the value will be x1000 */ 1667 calc_val = (mode->clock * 1000); 1668 calc_val /= mode->htotal; 1669 refresh = (calc_val + vtotal / 2) / vtotal; 1670 1671 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1672 refresh *= 2; 1673 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1674 refresh /= 2; 1675 if (mode->vscan > 1) 1676 refresh /= mode->vscan; 1677 } 1678 return refresh; 1679 } 1680 1681 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1682 int *panel_bits_per_colourp) 1683 { 1684 struct edid1_info *edid = (struct edid1_info *)buf; 1685 bool timing_done; 1686 int i; 1687 1688 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1689 debug("%s: Invalid buffer\n", __func__); 1690 return -EINVAL; 1691 } 1692 1693 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1694 debug("%s: No preferred timing\n", __func__); 1695 return -ENOENT; 1696 } 1697 1698 /* Look for detailed timing */ 1699 timing_done = false; 1700 for (i = 0; i < 4; i++) { 1701 struct edid_monitor_descriptor *desc; 1702 1703 desc = &edid->monitor_details.descriptor[i]; 1704 if (desc->zero_flag_1 != 0) { 1705 decode_mode((u8 *)desc, mode); 1706 timing_done = true; 1707 break; 1708 } 1709 } 1710 if (!timing_done) 1711 return -EINVAL; 1712 1713 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1714 debug("%s: Not a digital display\n", __func__); 1715 return -ENOSYS; 1716 } 1717 if (edid->version != 1 || edid->revision < 4) { 1718 debug("%s: EDID version %d.%d does not have required info\n", 1719 __func__, edid->version, edid->revision); 1720 *panel_bits_per_colourp = -1; 1721 } else { 1722 *panel_bits_per_colourp = 1723 ((edid->video_input_definition & 0x70) >> 3) + 4; 1724 } 1725 1726 return 0; 1727 } 1728 1729 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 1730 int *panel_bits_per_colourp) 1731 { 1732 struct edid1_info *edid = (struct edid1_info *)buf; 1733 bool timing_done; 1734 int i; 1735 1736 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1737 debug("%s: Invalid buffer\n", __func__); 1738 return -EINVAL; 1739 } 1740 1741 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1742 debug("%s: No preferred timing\n", __func__); 1743 return -ENOENT; 1744 } 1745 1746 /* Look for detailed timing */ 1747 timing_done = false; 1748 for (i = 0; i < 4; i++) { 1749 struct edid_monitor_descriptor *desc; 1750 1751 desc = &edid->monitor_details.descriptor[i]; 1752 if (desc->zero_flag_1 != 0) { 1753 decode_timing((u8 *)desc, timing); 1754 timing_done = true; 1755 break; 1756 } 1757 } 1758 if (!timing_done) 1759 return -EINVAL; 1760 1761 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1762 debug("%s: Not a digital display\n", __func__); 1763 return -ENOSYS; 1764 } 1765 if (edid->version != 1 || edid->revision < 4) { 1766 debug("%s: EDID version %d.%d does not have required info\n", 1767 __func__, edid->version, edid->revision); 1768 *panel_bits_per_colourp = -1; 1769 } else { 1770 *panel_bits_per_colourp = 1771 ((edid->video_input_definition & 0x70) >> 3) + 4; 1772 } 1773 1774 timing->hdmi_monitor = false; 1775 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 1776 struct edid_cea861_info *info = 1777 (struct edid_cea861_info *)(buf + sizeof(*edid)); 1778 1779 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 1780 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 1781 } 1782 1783 return 0; 1784 } 1785 1786 /** 1787 * Snip the tailing whitespace/return of a string. 1788 * 1789 * @param string The string to be snipped 1790 * @return the snipped string 1791 */ 1792 static char *snip(char *string) 1793 { 1794 char *s; 1795 1796 /* 1797 * This is always a 13 character buffer 1798 * and it's not always terminated. 1799 */ 1800 string[12] = '\0'; 1801 s = &string[strlen(string) - 1]; 1802 1803 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 1804 *s == '\0')) 1805 *(s--) = '\0'; 1806 1807 return string; 1808 } 1809 1810 /** 1811 * Print an EDID monitor descriptor block 1812 * 1813 * @param monitor The EDID monitor descriptor block 1814 * @have_timing Modifies to 1 if the desciptor contains timing info 1815 */ 1816 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 1817 unsigned int *have_timing) 1818 { 1819 unsigned char *bytes = (unsigned char *)monitor; 1820 struct edid_detailed_timing *timing = 1821 (struct edid_detailed_timing *)monitor; 1822 1823 if (bytes[0] == 0 && bytes[1] == 0) { 1824 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 1825 printf("Monitor serial number: %s\n", 1826 snip(monitor->data.string)); 1827 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 1828 printf("Monitor ID: %s\n", 1829 snip(monitor->data.string)); 1830 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 1831 printf("Monitor name: %s\n", 1832 snip(monitor->data.string)); 1833 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 1834 printf("Monitor range limits, horizontal sync: " 1835 "%d-%d kHz, vertical refresh: " 1836 "%d-%d Hz, max pixel clock: " 1837 "%d MHz\n", 1838 monitor->data.range_data.horizontal_min, 1839 monitor->data.range_data.horizontal_max, 1840 monitor->data.range_data.vertical_min, 1841 monitor->data.range_data.vertical_max, 1842 monitor->data.range_data.pixel_clock_max * 10); 1843 } else { 1844 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 1845 u32 h_total, v_total, vfreq; 1846 1847 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 1848 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 1849 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 1850 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 1851 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 1852 1853 h_total = h_active + h_blanking; 1854 v_total = v_active + v_blanking; 1855 if (v_total > 0 && h_total > 0) 1856 vfreq = pixclock / (v_total * h_total); 1857 else 1858 vfreq = 1; /* Error case */ 1859 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 1860 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 1861 *have_timing = 1; 1862 } 1863 } 1864 1865 /** 1866 * Get the manufacturer name from an EDID info. 1867 * 1868 * @param edid_info The EDID info to be printed 1869 * @param name Returns the string of the manufacturer name 1870 */ 1871 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 1872 { 1873 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 1874 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 1875 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 1876 name[3] = '\0'; 1877 } 1878 1879 void edid_print_info(struct edid1_info *edid_info) 1880 { 1881 int i; 1882 char manufacturer[4]; 1883 unsigned int have_timing = 0; 1884 u32 serial_number; 1885 1886 if (edid_check_info(edid_info)) { 1887 printf("Not a valid EDID\n"); 1888 return; 1889 } 1890 1891 printf("EDID version: %d.%d\n", 1892 edid_info->version, edid_info->revision); 1893 1894 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 1895 1896 edid_get_manufacturer_name(edid_info, manufacturer); 1897 printf("Manufacturer: %s\n", manufacturer); 1898 1899 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 1900 if (serial_number != 0xffffffff) { 1901 if (strcmp(manufacturer, "MAG") == 0) 1902 serial_number -= 0x7000000; 1903 if (strcmp(manufacturer, "OQI") == 0) 1904 serial_number -= 456150000; 1905 if (strcmp(manufacturer, "VSC") == 0) 1906 serial_number -= 640000000; 1907 } 1908 printf("Serial number: %08x\n", serial_number); 1909 printf("Manufactured in week: %d year: %d\n", 1910 edid_info->week, edid_info->year + 1990); 1911 1912 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 1913 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 1914 "digital signal, " : "analog signal, ", 1915 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 1916 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 1917 ", blank to black" : "", 1918 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 1919 ", separate sync" : "", 1920 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 1921 ", composite sync" : "", 1922 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 1923 ", sync on green" : "", 1924 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 1925 ", serration v" : ""); 1926 1927 printf("Monitor is %s\n", 1928 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 1929 1930 printf("Maximum visible display size: %d cm x %d cm\n", 1931 edid_info->max_size_horizontal, 1932 edid_info->max_size_vertical); 1933 1934 printf("Power management features: %s%s, %s%s, %s%s\n", 1935 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 1936 "" : "no ", "active off", 1937 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 1938 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 1939 1940 printf("Estabilished timings:\n"); 1941 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 1942 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 1943 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 1944 printf("\t720x400\t\t88 Hz (XGA2)\n"); 1945 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 1946 printf("\t640x480\t\t60 Hz (VGA)\n"); 1947 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 1948 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 1949 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 1950 printf("\t640x480\t\t72 Hz (VESA)\n"); 1951 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 1952 printf("\t640x480\t\t75 Hz (VESA)\n"); 1953 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 1954 printf("\t800x600\t\t56 Hz (VESA)\n"); 1955 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 1956 printf("\t800x600\t\t60 Hz (VESA)\n"); 1957 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 1958 printf("\t800x600\t\t72 Hz (VESA)\n"); 1959 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 1960 printf("\t800x600\t\t75 Hz (VESA)\n"); 1961 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 1962 printf("\t832x624\t\t75 Hz (Mac II)\n"); 1963 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 1964 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 1965 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 1966 printf("\t1024x768\t60 Hz (VESA)\n"); 1967 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 1968 printf("\t1024x768\t70 Hz (VESA)\n"); 1969 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 1970 printf("\t1024x768\t75 Hz (VESA)\n"); 1971 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 1972 printf("\t1280x1024\t75 (VESA)\n"); 1973 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 1974 printf("\t1152x870\t75 (Mac II)\n"); 1975 1976 /* Standard timings. */ 1977 printf("Standard timings:\n"); 1978 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 1979 unsigned int aspect = 10000; 1980 unsigned int x, y; 1981 unsigned char xres, vfreq; 1982 1983 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 1984 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 1985 if ((xres != vfreq) || 1986 ((xres != 0) && (xres != 1)) || 1987 ((vfreq != 0) && (vfreq != 1))) { 1988 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 1989 i)) { 1990 case ASPECT_625: 1991 aspect = 6250; 1992 break; 1993 case ASPECT_75: 1994 aspect = 7500; 1995 break; 1996 case ASPECT_8: 1997 aspect = 8000; 1998 break; 1999 case ASPECT_5625: 2000 aspect = 5625; 2001 break; 2002 } 2003 x = (xres + 31) * 8; 2004 y = x * aspect / 10000; 2005 printf("\t%dx%d%c\t%d Hz\n", x, y, 2006 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 2007 have_timing = 1; 2008 } 2009 } 2010 2011 /* Detailed timing information. */ 2012 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 2013 i++) { 2014 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 2015 &have_timing); 2016 } 2017 2018 if (!have_timing) 2019 printf("\tNone\n"); 2020 } 2021 2022 /** 2023 * drm_mode_create - create a new display mode 2024 * 2025 * Create a new, cleared drm_display_mode. 2026 * 2027 * Returns: 2028 * Pointer to new mode on success, NULL on error. 2029 */ 2030 static struct drm_display_mode *drm_mode_create(void) 2031 { 2032 struct drm_display_mode *nmode; 2033 2034 nmode = malloc(sizeof(struct drm_display_mode)); 2035 memset(nmode, 0, sizeof(struct drm_display_mode)); 2036 if (!nmode) 2037 return NULL; 2038 2039 return nmode; 2040 } 2041 2042 /** 2043 * drm_mode_destroy - remove a mode 2044 * @mode: mode to remove 2045 * 2046 */ 2047 static void drm_mode_destroy(struct drm_display_mode *mode) 2048 { 2049 if (!mode) 2050 return; 2051 2052 kfree(mode); 2053 } 2054 2055 /** 2056 * drm_cvt_mode -create a modeline based on the CVT algorithm 2057 * @hdisplay: hdisplay size 2058 * @vdisplay: vdisplay size 2059 * @vrefresh: vrefresh rate 2060 * @reduced: whether to use reduced blanking 2061 * @interlaced: whether to compute an interlaced mode 2062 * @margins: whether to add margins (borders) 2063 * 2064 * This function is called to generate the modeline based on CVT algorithm 2065 * according to the hdisplay, vdisplay, vrefresh. 2066 * It is based from the VESA(TM) Coordinated Video Timing Generator by 2067 * Graham Loveridge April 9, 2003 available at 2068 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 2069 * 2070 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 2071 * What I have done is to translate it by using integer calculation. 2072 * 2073 * Returns: 2074 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 2075 * The display mode object is allocated with drm_mode_create(). Returns NULL 2076 * when no mode could be allocated. 2077 */ 2078 static 2079 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 2080 bool reduced, bool interlaced, 2081 bool margins) 2082 { 2083 #define HV_FACTOR 1000 2084 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 2085 #define CVT_MARGIN_PERCENTAGE 18 2086 /* 2) character cell horizontal granularity (pixels) - default 8 */ 2087 #define CVT_H_GRANULARITY 8 2088 /* 3) Minimum vertical porch (lines) - default 3 */ 2089 #define CVT_MIN_V_PORCH 3 2090 /* 4) Minimum number of vertical back porch lines - default 6 */ 2091 #define CVT_MIN_V_BPORCH 6 2092 /* Pixel Clock step (kHz) */ 2093 #define CVT_CLOCK_STEP 250 2094 struct drm_display_mode *drm_mode; 2095 unsigned int vfieldrate, hperiod; 2096 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 2097 int interlace; 2098 2099 /* allocate the drm_display_mode structure. If failure, we will 2100 * return directly 2101 */ 2102 drm_mode = drm_mode_create(); 2103 if (!drm_mode) 2104 return NULL; 2105 2106 /* the CVT default refresh rate is 60Hz */ 2107 if (!vrefresh) 2108 vrefresh = 60; 2109 2110 /* the required field fresh rate */ 2111 if (interlaced) 2112 vfieldrate = vrefresh * 2; 2113 else 2114 vfieldrate = vrefresh; 2115 2116 /* horizontal pixels */ 2117 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 2118 2119 /* determine the left&right borders */ 2120 hmargin = 0; 2121 if (margins) { 2122 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2123 hmargin -= hmargin % CVT_H_GRANULARITY; 2124 } 2125 /* find the total active pixels */ 2126 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 2127 2128 /* find the number of lines per field */ 2129 if (interlaced) 2130 vdisplay_rnd = vdisplay / 2; 2131 else 2132 vdisplay_rnd = vdisplay; 2133 2134 /* find the top & bottom borders */ 2135 vmargin = 0; 2136 if (margins) 2137 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2138 2139 drm_mode->vdisplay = vdisplay + 2 * vmargin; 2140 2141 /* Interlaced */ 2142 if (interlaced) 2143 interlace = 1; 2144 else 2145 interlace = 0; 2146 2147 /* Determine VSync Width from aspect ratio */ 2148 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 2149 vsync = 4; 2150 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 2151 vsync = 5; 2152 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 2153 vsync = 6; 2154 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 2155 vsync = 7; 2156 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 2157 vsync = 7; 2158 else /* custom */ 2159 vsync = 10; 2160 2161 if (!reduced) { 2162 /* simplify the GTF calculation */ 2163 /* 4) Minimum time of vertical sync + back porch interval 2164 * default 550.0 2165 */ 2166 int tmp1, tmp2; 2167 #define CVT_MIN_VSYNC_BP 550 2168 /* 3) Nominal HSync width (% of line period) - default 8 */ 2169 #define CVT_HSYNC_PERCENTAGE 8 2170 unsigned int hblank_percentage; 2171 int vsyncandback_porch, hblank; 2172 2173 /* estimated the horizontal period */ 2174 tmp1 = HV_FACTOR * 1000000 - 2175 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2176 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2177 interlace; 2178 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2179 2180 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2181 /* 9. Find number of lines in sync + backporch */ 2182 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2183 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2184 else 2185 vsyncandback_porch = tmp1; 2186 /* 10. Find number of lines in back porch 2187 * vback_porch = vsyncandback_porch - vsync; 2188 */ 2189 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2190 vsyncandback_porch + CVT_MIN_V_PORCH; 2191 /* 5) Definition of Horizontal blanking time limitation */ 2192 /* Gradient (%/kHz) - default 600 */ 2193 #define CVT_M_FACTOR 600 2194 /* Offset (%) - default 40 */ 2195 #define CVT_C_FACTOR 40 2196 /* Blanking time scaling factor - default 128 */ 2197 #define CVT_K_FACTOR 128 2198 /* Scaling factor weighting - default 20 */ 2199 #define CVT_J_FACTOR 20 2200 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2201 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2202 CVT_J_FACTOR) 2203 /* 12. Find ideal blanking duty cycle from formula */ 2204 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2205 hperiod / 1000; 2206 /* 13. Blanking time */ 2207 if (hblank_percentage < 20 * HV_FACTOR) 2208 hblank_percentage = 20 * HV_FACTOR; 2209 hblank = drm_mode->hdisplay * hblank_percentage / 2210 (100 * HV_FACTOR - hblank_percentage); 2211 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2212 /* 14. find the total pixels per line */ 2213 drm_mode->htotal = drm_mode->hdisplay + hblank; 2214 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2215 drm_mode->hsync_start = drm_mode->hsync_end - 2216 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2217 drm_mode->hsync_start += CVT_H_GRANULARITY - 2218 drm_mode->hsync_start % CVT_H_GRANULARITY; 2219 /* fill the Vsync values */ 2220 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2221 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2222 } else { 2223 /* Reduced blanking */ 2224 /* Minimum vertical blanking interval time - default 460 */ 2225 #define CVT_RB_MIN_VBLANK 460 2226 /* Fixed number of clocks for horizontal sync */ 2227 #define CVT_RB_H_SYNC 32 2228 /* Fixed number of clocks for horizontal blanking */ 2229 #define CVT_RB_H_BLANK 160 2230 /* Fixed number of lines for vertical front porch - default 3*/ 2231 #define CVT_RB_VFPORCH 3 2232 int vbilines; 2233 int tmp1, tmp2; 2234 /* 8. Estimate Horizontal period. */ 2235 tmp1 = HV_FACTOR * 1000000 - 2236 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2237 tmp2 = vdisplay_rnd + 2 * vmargin; 2238 hperiod = tmp1 / (tmp2 * vfieldrate); 2239 /* 9. Find number of lines in vertical blanking */ 2240 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2241 /* 10. Check if vertical blanking is sufficient */ 2242 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2243 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2244 /* 11. Find total number of lines in vertical field */ 2245 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2246 /* 12. Find total number of pixels in a line */ 2247 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2248 /* Fill in HSync values */ 2249 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2250 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2251 /* Fill in VSync values */ 2252 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2253 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2254 } 2255 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2256 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2257 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2258 /* 18/16. Find actual vertical frame frequency */ 2259 /* ignore - just set the mode flag for interlaced */ 2260 if (interlaced) { 2261 drm_mode->vtotal *= 2; 2262 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2263 } 2264 2265 if (reduced) 2266 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2267 DRM_MODE_FLAG_NVSYNC); 2268 else 2269 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2270 DRM_MODE_FLAG_NHSYNC); 2271 2272 return drm_mode; 2273 } 2274 2275 static int 2276 cea_db_payload_len(const u8 *db) 2277 { 2278 return db[0] & 0x1f; 2279 } 2280 2281 static int 2282 cea_db_extended_tag(const u8 *db) 2283 { 2284 return db[1]; 2285 } 2286 2287 static int 2288 cea_db_tag(const u8 *db) 2289 { 2290 return db[0] >> 5; 2291 } 2292 2293 #define for_each_cea_db(cea, i, start, end) \ 2294 for ((i) = (start); (i) < (end) && (i) + \ 2295 cea_db_payload_len(&(cea)[(i)]) < \ 2296 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2297 2298 static int 2299 cea_revision(const u8 *cea) 2300 { 2301 return cea[1]; 2302 } 2303 2304 static int 2305 cea_db_offsets(const u8 *cea, int *start, int *end) 2306 { 2307 /* Data block offset in CEA extension block */ 2308 *start = 4; 2309 *end = cea[2]; 2310 if (*end == 0) 2311 *end = 127; 2312 if (*end < 4 || *end > 127) 2313 return -ERANGE; 2314 2315 /* 2316 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2317 */ 2318 if (*end != 4) { 2319 int i; 2320 2321 i = *start; 2322 while (i < (*end) && 2323 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2324 i += cea_db_payload_len(&(cea)[i]) + 1; 2325 2326 if (cea_db_payload_len(&(cea)[i]) && 2327 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2328 (*end)++; 2329 } 2330 2331 return 0; 2332 } 2333 2334 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2335 { 2336 int hdmi_id; 2337 2338 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2339 return false; 2340 2341 if (cea_db_payload_len(db) < 5) 2342 return false; 2343 2344 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2345 2346 return hdmi_id == HDMI_IEEE_OUI; 2347 } 2348 2349 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2350 { 2351 unsigned int oui; 2352 2353 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2354 return false; 2355 2356 if (cea_db_payload_len(db) < 7) 2357 return false; 2358 2359 oui = db[3] << 16 | db[2] << 8 | db[1]; 2360 2361 return oui == HDMI_FORUM_IEEE_OUI; 2362 } 2363 2364 static bool cea_db_is_y420cmdb(const u8 *db) 2365 { 2366 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2367 return false; 2368 2369 if (!cea_db_payload_len(db)) 2370 return false; 2371 2372 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2373 return false; 2374 2375 return true; 2376 } 2377 2378 static bool cea_db_is_y420vdb(const u8 *db) 2379 { 2380 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2381 return false; 2382 2383 if (!cea_db_payload_len(db)) 2384 return false; 2385 2386 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2387 return false; 2388 2389 return true; 2390 } 2391 2392 static bool drm_valid_hdmi_vic(u8 vic) 2393 { 2394 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2395 } 2396 2397 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2398 const struct drm_display_mode *mode) 2399 { 2400 struct drm_display_mode *mode_buf = data->mode_buf; 2401 2402 if (data->modes >= MODE_LEN) 2403 return; 2404 mode_buf[(data->modes)++] = *mode; 2405 } 2406 2407 static bool drm_valid_cea_vic(u8 vic) 2408 { 2409 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2410 } 2411 2412 static u8 svd_to_vic(u8 svd) 2413 { 2414 /* 0-6 bit vic, 7th bit native mode indicator */ 2415 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2416 return svd & 127; 2417 2418 return svd; 2419 } 2420 2421 static struct drm_display_mode * 2422 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2423 u8 video_index) 2424 { 2425 struct drm_display_mode *newmode; 2426 u8 vic; 2427 2428 if (!video_db || video_index >= video_len) 2429 return NULL; 2430 2431 /* CEA modes are numbered 1..127 */ 2432 vic = svd_to_vic(video_db[video_index]); 2433 if (!drm_valid_cea_vic(vic)) 2434 return NULL; 2435 2436 newmode = drm_mode_create(); 2437 if (!newmode) 2438 return NULL; 2439 2440 *newmode = edid_cea_modes[vic]; 2441 newmode->vrefresh = 0; 2442 2443 return newmode; 2444 } 2445 2446 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2447 { 2448 unsigned long *p = map + BIT_WORD(start); 2449 const unsigned int size = start + len; 2450 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2451 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2452 2453 while (len - bits_to_set >= 0) { 2454 *p |= mask_to_set; 2455 len -= bits_to_set; 2456 bits_to_set = BITS_PER_LONG; 2457 mask_to_set = ~0UL; 2458 p++; 2459 } 2460 if (len) { 2461 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2462 *p |= mask_to_set; 2463 } 2464 } 2465 2466 static void 2467 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2468 { 2469 u8 vic = svd_to_vic(svd); 2470 2471 if (!drm_valid_cea_vic(vic)) 2472 return; 2473 2474 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2475 } 2476 2477 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2478 { 2479 int i, modes = 0; 2480 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2481 2482 for (i = 0; i < len; i++) { 2483 struct drm_display_mode *mode; 2484 2485 mode = drm_display_mode_from_vic_index(db, len, i); 2486 if (mode) { 2487 /* 2488 * YCBCR420 capability block contains a bitmap which 2489 * gives the index of CEA modes from CEA VDB, which 2490 * can support YCBCR 420 sampling output also (apart 2491 * from RGB/YCBCR444 etc). 2492 * For example, if the bit 0 in bitmap is set, 2493 * first mode in VDB can support YCBCR420 output too. 2494 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2495 */ 2496 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2497 drm_add_cmdb_modes(db[i], hdmi); 2498 drm_add_hdmi_modes(data, mode); 2499 drm_mode_destroy(mode); 2500 modes++; 2501 } 2502 } 2503 2504 return modes; 2505 } 2506 2507 /* 2508 * do_y420vdb_modes - Parse YCBCR 420 only modes 2509 * @data: the structure that save parsed hdmi edid data 2510 * @svds: start of the data block of CEA YCBCR 420 VDB 2511 * @svds_len: length of the CEA YCBCR 420 VDB 2512 * @hdmi: runtime information about the connected HDMI sink 2513 * 2514 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2515 * which contains modes which can be supported in YCBCR 420 2516 * output format only. 2517 */ 2518 static int 2519 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2520 { 2521 int modes = 0, i; 2522 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2523 2524 for (i = 0; i < svds_len; i++) { 2525 u8 vic = svd_to_vic(svds[i]); 2526 2527 if (!drm_valid_cea_vic(vic)) 2528 continue; 2529 2530 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2531 drm_add_hdmi_modes(data, &edid_cea_modes[vic]); 2532 modes++; 2533 } 2534 2535 return modes; 2536 } 2537 2538 struct stereo_mandatory_mode { 2539 int width, height, vrefresh; 2540 unsigned int flags; 2541 }; 2542 2543 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2544 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2545 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2546 { 1920, 1080, 50, 2547 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2548 { 1920, 1080, 60, 2549 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2550 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2551 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2552 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2553 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2554 }; 2555 2556 static bool 2557 stereo_match_mandatory(const struct drm_display_mode *mode, 2558 const struct stereo_mandatory_mode *stereo_mode) 2559 { 2560 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2561 2562 return mode->hdisplay == stereo_mode->width && 2563 mode->vdisplay == stereo_mode->height && 2564 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2565 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2566 } 2567 2568 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2569 { 2570 const struct drm_display_mode *mode; 2571 int num = data->modes, modes = 0, i, k; 2572 2573 for (k = 0; k < num; k++) { 2574 mode = &data->mode_buf[k]; 2575 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2576 const struct stereo_mandatory_mode *mandatory; 2577 struct drm_display_mode *new_mode; 2578 2579 if (!stereo_match_mandatory(mode, 2580 &stereo_mandatory_modes[i])) 2581 continue; 2582 2583 mandatory = &stereo_mandatory_modes[i]; 2584 new_mode = drm_mode_create(); 2585 if (!new_mode) 2586 continue; 2587 2588 *new_mode = *mode; 2589 new_mode->flags |= mandatory->flags; 2590 drm_add_hdmi_modes(data, new_mode); 2591 drm_mode_destroy(new_mode); 2592 modes++; 2593 } 2594 } 2595 2596 return modes; 2597 } 2598 2599 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2600 const u8 *video_db, u8 video_len, u8 video_index) 2601 { 2602 struct drm_display_mode *newmode; 2603 int modes = 0; 2604 2605 if (structure & (1 << 0)) { 2606 newmode = drm_display_mode_from_vic_index(video_db, 2607 video_len, 2608 video_index); 2609 if (newmode) { 2610 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2611 drm_add_hdmi_modes(data, newmode); 2612 modes++; 2613 drm_mode_destroy(newmode); 2614 } 2615 } 2616 if (structure & (1 << 6)) { 2617 newmode = drm_display_mode_from_vic_index(video_db, 2618 video_len, 2619 video_index); 2620 if (newmode) { 2621 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2622 drm_add_hdmi_modes(data, newmode); 2623 modes++; 2624 drm_mode_destroy(newmode); 2625 } 2626 } 2627 if (structure & (1 << 8)) { 2628 newmode = drm_display_mode_from_vic_index(video_db, 2629 video_len, 2630 video_index); 2631 if (newmode) { 2632 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2633 drm_add_hdmi_modes(data, newmode); 2634 modes++; 2635 drm_mode_destroy(newmode); 2636 } 2637 } 2638 2639 return modes; 2640 } 2641 2642 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2643 { 2644 if (!drm_valid_hdmi_vic(vic)) { 2645 debug("Unknown HDMI VIC: %d\n", vic); 2646 return 0; 2647 } 2648 2649 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2650 2651 return 1; 2652 } 2653 2654 /* 2655 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2656 * @db: start of the CEA vendor specific block 2657 * @len: length of the CEA block payload, ie. one can access up to db[len] 2658 * 2659 * Parses the HDMI VSDB looking for modes to add to @data. This function 2660 * also adds the stereo 3d modes when applicable. 2661 */ 2662 static int 2663 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2664 struct hdmi_edid_data *data) 2665 { 2666 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2667 u8 vic_len, hdmi_3d_len = 0; 2668 u16 mask; 2669 u16 structure_all; 2670 2671 if (len < 8) 2672 goto out; 2673 2674 /* no HDMI_Video_Present */ 2675 if (!(db[8] & (1 << 5))) 2676 goto out; 2677 2678 /* Latency_Fields_Present */ 2679 if (db[8] & (1 << 7)) 2680 offset += 2; 2681 2682 /* I_Latency_Fields_Present */ 2683 if (db[8] & (1 << 6)) 2684 offset += 2; 2685 2686 /* the declared length is not long enough for the 2 first bytes 2687 * of additional video format capabilities 2688 */ 2689 if (len < (8 + offset + 2)) 2690 goto out; 2691 2692 /* 3D_Present */ 2693 offset++; 2694 if (db[8 + offset] & (1 << 7)) { 2695 modes += add_hdmi_mandatory_stereo_modes(data); 2696 2697 /* 3D_Multi_present */ 2698 multi_present = (db[8 + offset] & 0x60) >> 5; 2699 } 2700 2701 offset++; 2702 vic_len = db[8 + offset] >> 5; 2703 hdmi_3d_len = db[8 + offset] & 0x1f; 2704 2705 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2706 u8 vic; 2707 2708 vic = db[9 + offset + i]; 2709 modes += add_hdmi_mode(data, vic); 2710 } 2711 2712 offset += 1 + vic_len; 2713 2714 if (multi_present == 1) 2715 multi_len = 2; 2716 else if (multi_present == 2) 2717 multi_len = 4; 2718 else 2719 multi_len = 0; 2720 2721 if (len < (8 + offset + hdmi_3d_len - 1)) 2722 goto out; 2723 2724 if (hdmi_3d_len < multi_len) 2725 goto out; 2726 2727 if (multi_present == 1 || multi_present == 2) { 2728 /* 3D_Structure_ALL */ 2729 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2730 2731 /* check if 3D_MASK is present */ 2732 if (multi_present == 2) 2733 mask = (db[10 + offset] << 8) | db[11 + offset]; 2734 else 2735 mask = 0xffff; 2736 2737 for (i = 0; i < 16; i++) { 2738 if (mask & (1 << i)) 2739 modes += add_3d_struct_modes(data, 2740 structure_all, 2741 video_db, 2742 video_len, i); 2743 } 2744 } 2745 2746 offset += multi_len; 2747 2748 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2749 int vic_index; 2750 struct drm_display_mode *newmode = NULL; 2751 unsigned int newflag = 0; 2752 bool detail_present; 2753 2754 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2755 2756 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2757 break; 2758 2759 /* 2D_VIC_order_X */ 2760 vic_index = db[8 + offset + i] >> 4; 2761 2762 /* 3D_Structure_X */ 2763 switch (db[8 + offset + i] & 0x0f) { 2764 case 0: 2765 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2766 break; 2767 case 6: 2768 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2769 break; 2770 case 8: 2771 /* 3D_Detail_X */ 2772 if ((db[9 + offset + i] >> 4) == 1) 2773 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2774 break; 2775 } 2776 2777 if (newflag != 0) { 2778 newmode = drm_display_mode_from_vic_index( 2779 video_db, 2780 video_len, 2781 vic_index); 2782 2783 if (newmode) { 2784 newmode->flags |= newflag; 2785 drm_add_hdmi_modes(data, newmode); 2786 modes++; 2787 drm_mode_destroy(newmode); 2788 } 2789 } 2790 2791 if (detail_present) 2792 i++; 2793 } 2794 2795 out: 2796 return modes; 2797 } 2798 2799 /** 2800 * edid_get_quirks - return quirk flags for a given EDID 2801 * @edid: EDID to process 2802 * 2803 * This tells subsequent routines what fixes they need to apply. 2804 */ 2805 static u32 edid_get_quirks(struct edid *edid) 2806 { 2807 struct edid_quirk *quirk; 2808 int i; 2809 2810 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2811 quirk = &edid_quirk_list[i]; 2812 2813 if (edid_vendor(edid, quirk->vendor) && 2814 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2815 return quirk->quirks; 2816 } 2817 2818 return 0; 2819 } 2820 2821 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 2822 const u8 *db) 2823 { 2824 struct drm_display_info *info = &data->display_info; 2825 struct drm_hdmi_info *hdmi = &info->hdmi; 2826 u8 map_len = cea_db_payload_len(db) - 1; 2827 u8 count; 2828 u64 map = 0; 2829 2830 if (map_len == 0) { 2831 /* All CEA modes support ycbcr420 sampling also.*/ 2832 hdmi->y420_cmdb_map = U64_MAX; 2833 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2834 return; 2835 } 2836 2837 /* 2838 * This map indicates which of the existing CEA block modes 2839 * from VDB can support YCBCR420 output too. So if bit=0 is 2840 * set, first mode from VDB can support YCBCR420 output too. 2841 * We will parse and keep this map, before parsing VDB itself 2842 * to avoid going through the same block again and again. 2843 * 2844 * Spec is not clear about max possible size of this block. 2845 * Clamping max bitmap block size at 8 bytes. Every byte can 2846 * address 8 CEA modes, in this way this map can address 2847 * 8*8 = first 64 SVDs. 2848 */ 2849 if (map_len > 8) 2850 map_len = 8; 2851 2852 for (count = 0; count < map_len; count++) 2853 map |= (u64)db[2 + count] << (8 * count); 2854 2855 if (map) 2856 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2857 2858 hdmi->y420_cmdb_map = map; 2859 } 2860 2861 static 2862 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 2863 { 2864 switch (max_frl_rate) { 2865 case 1: 2866 *max_lanes = 3; 2867 *max_rate_per_lane = 3; 2868 break; 2869 case 2: 2870 *max_lanes = 3; 2871 *max_rate_per_lane = 6; 2872 break; 2873 case 3: 2874 *max_lanes = 4; 2875 *max_rate_per_lane = 6; 2876 break; 2877 case 4: 2878 *max_lanes = 4; 2879 *max_rate_per_lane = 8; 2880 break; 2881 case 5: 2882 *max_lanes = 4; 2883 *max_rate_per_lane = 10; 2884 break; 2885 case 6: 2886 *max_lanes = 4; 2887 *max_rate_per_lane = 12; 2888 break; 2889 case 0: 2890 default: 2891 *max_lanes = 0; 2892 *max_rate_per_lane = 0; 2893 } 2894 } 2895 2896 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 2897 const u8 *db) 2898 { 2899 u8 dc_mask; 2900 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2901 2902 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 2903 hdmi->y420_dc_modes |= dc_mask; 2904 } 2905 2906 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 2907 const u8 *hf_vsdb) 2908 { 2909 struct drm_display_info *display = &data->display_info; 2910 struct drm_hdmi_info *hdmi = &display->hdmi; 2911 2912 if (hf_vsdb[6] & 0x80) { 2913 hdmi->scdc.supported = true; 2914 if (hf_vsdb[6] & 0x40) 2915 hdmi->scdc.read_request = true; 2916 } 2917 2918 /* 2919 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 2920 * And as per the spec, three factors confirm this: 2921 * * Availability of a HF-VSDB block in EDID (check) 2922 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 2923 * * SCDC support available (let's check) 2924 * Lets check it out. 2925 */ 2926 2927 if (hf_vsdb[5]) { 2928 /* max clock is 5000 KHz times block value */ 2929 u32 max_tmds_clock = hf_vsdb[5] * 5000; 2930 struct drm_scdc *scdc = &hdmi->scdc; 2931 2932 if (max_tmds_clock > 340000) { 2933 display->max_tmds_clock = max_tmds_clock; 2934 debug("HF-VSDB: max TMDS clock %d kHz\n", 2935 display->max_tmds_clock); 2936 } 2937 2938 if (scdc->supported) { 2939 scdc->scrambling.supported = true; 2940 2941 /* Few sinks support scrambling for cloks < 340M */ 2942 if ((hf_vsdb[6] & 0x8)) 2943 scdc->scrambling.low_rates = true; 2944 } 2945 } 2946 2947 if (hf_vsdb[7]) { 2948 u8 max_frl_rate; 2949 u8 dsc_max_frl_rate; 2950 u8 dsc_max_slices; 2951 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 2952 2953 debug("hdmi_21 sink detected. parsing edid\n"); 2954 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 2955 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 2956 &hdmi->max_frl_rate_per_lane); 2957 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 2958 2959 if (hdmi_dsc->v_1p2) { 2960 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 2961 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 2962 2963 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 2964 hdmi_dsc->bpc_supported = 16; 2965 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 2966 hdmi_dsc->bpc_supported = 12; 2967 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 2968 hdmi_dsc->bpc_supported = 10; 2969 else 2970 hdmi_dsc->bpc_supported = 0; 2971 2972 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 2973 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 2974 &hdmi_dsc->max_frl_rate_per_lane); 2975 hdmi_dsc->total_chunk_kbytes = 2976 hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 2977 2978 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 2979 switch (dsc_max_slices) { 2980 case 1: 2981 hdmi_dsc->max_slices = 1; 2982 hdmi_dsc->clk_per_slice = 340; 2983 break; 2984 case 2: 2985 hdmi_dsc->max_slices = 2; 2986 hdmi_dsc->clk_per_slice = 340; 2987 break; 2988 case 3: 2989 hdmi_dsc->max_slices = 4; 2990 hdmi_dsc->clk_per_slice = 340; 2991 break; 2992 case 4: 2993 hdmi_dsc->max_slices = 8; 2994 hdmi_dsc->clk_per_slice = 340; 2995 break; 2996 case 5: 2997 hdmi_dsc->max_slices = 8; 2998 hdmi_dsc->clk_per_slice = 400; 2999 break; 3000 case 6: 3001 hdmi_dsc->max_slices = 12; 3002 hdmi_dsc->clk_per_slice = 400; 3003 break; 3004 case 7: 3005 hdmi_dsc->max_slices = 16; 3006 hdmi_dsc->clk_per_slice = 400; 3007 break; 3008 case 0: 3009 default: 3010 hdmi_dsc->max_slices = 0; 3011 hdmi_dsc->clk_per_slice = 0; 3012 } 3013 } 3014 } 3015 3016 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 3017 } 3018 3019 /** 3020 * drm_default_rgb_quant_range - default RGB quantization range 3021 * @mode: display mode 3022 * 3023 * Determine the default RGB quantization range for the mode, 3024 * as specified in CEA-861. 3025 * 3026 * Return: The default RGB quantization range for the mode 3027 */ 3028 enum hdmi_quantization_range 3029 drm_default_rgb_quant_range(struct drm_display_mode *mode) 3030 { 3031 /* All CEA modes other than VIC 1 use limited quantization range. */ 3032 return drm_match_cea_mode(mode) > 1 ? 3033 HDMI_QUANTIZATION_RANGE_LIMITED : 3034 HDMI_QUANTIZATION_RANGE_FULL; 3035 } 3036 3037 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 3038 const u8 *hdmi) 3039 { 3040 struct drm_display_info *info = &data->display_info; 3041 unsigned int dc_bpc = 0; 3042 3043 /* HDMI supports at least 8 bpc */ 3044 info->bpc = 8; 3045 3046 if (cea_db_payload_len(hdmi) < 6) 3047 return; 3048 3049 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3050 dc_bpc = 10; 3051 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3052 debug("HDMI sink does deep color 30.\n"); 3053 } 3054 3055 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3056 dc_bpc = 12; 3057 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3058 debug("HDMI sink does deep color 36.\n"); 3059 } 3060 3061 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3062 dc_bpc = 16; 3063 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3064 debug("HDMI sink does deep color 48.\n"); 3065 } 3066 3067 if (dc_bpc == 0) { 3068 debug("No deep color support on this HDMI sink.\n"); 3069 return; 3070 } 3071 3072 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 3073 info->bpc = dc_bpc; 3074 3075 /* YCRCB444 is optional according to spec. */ 3076 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3077 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 3078 debug("HDMI sink does YCRCB444 in deep color.\n"); 3079 } 3080 3081 /* 3082 * Spec says that if any deep color mode is supported at all, 3083 * then deep color 36 bit must be supported. 3084 */ 3085 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 3086 debug("HDMI sink should do DC_36, but does not!\n"); 3087 } 3088 3089 /* 3090 * Search EDID for CEA extension block. 3091 */ 3092 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 3093 { 3094 u8 *edid_ext = NULL; 3095 int i; 3096 3097 /* No EDID or EDID extensions */ 3098 if (!edid || !edid->extensions) 3099 return NULL; 3100 3101 /* Find CEA extension */ 3102 for (i = 0; i < edid->extensions; i++) { 3103 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 3104 if (edid_ext[0] == ext_id) 3105 break; 3106 } 3107 3108 if (i == edid->extensions) 3109 return NULL; 3110 3111 return edid_ext; 3112 } 3113 3114 static u8 *drm_find_cea_extension(struct edid *edid) 3115 { 3116 return drm_find_edid_extension(edid, 0x02); 3117 } 3118 3119 #define AUDIO_BLOCK 0x01 3120 #define VIDEO_BLOCK 0x02 3121 #define VENDOR_BLOCK 0x03 3122 #define SPEAKER_BLOCK 0x04 3123 #define EDID_BASIC_AUDIO BIT(6) 3124 3125 /** 3126 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3127 * @edid: monitor EDID information 3128 * 3129 * Parse the CEA extension according to CEA-861-B. 3130 * 3131 * Return: True if the monitor is HDMI, false if not or unknown. 3132 */ 3133 bool drm_detect_hdmi_monitor(struct edid *edid) 3134 { 3135 u8 *edid_ext; 3136 int i; 3137 int start_offset, end_offset; 3138 3139 edid_ext = drm_find_cea_extension(edid); 3140 if (!edid_ext) 3141 return false; 3142 3143 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3144 return false; 3145 3146 /* 3147 * Because HDMI identifier is in Vendor Specific Block, 3148 * search it from all data blocks of CEA extension. 3149 */ 3150 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3151 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3152 return true; 3153 } 3154 3155 return false; 3156 } 3157 3158 /** 3159 * drm_detect_monitor_audio - check monitor audio capability 3160 * @edid: EDID block to scan 3161 * 3162 * Monitor should have CEA extension block. 3163 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3164 * audio' only. If there is any audio extension block and supported 3165 * audio format, assume at least 'basic audio' support, even if 'basic 3166 * audio' is not defined in EDID. 3167 * 3168 * Return: True if the monitor supports audio, false otherwise. 3169 */ 3170 bool drm_detect_monitor_audio(struct edid *edid) 3171 { 3172 u8 *edid_ext; 3173 int i, j; 3174 bool has_audio = false; 3175 int start_offset, end_offset; 3176 3177 edid_ext = drm_find_cea_extension(edid); 3178 if (!edid_ext) 3179 goto end; 3180 3181 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3182 3183 if (has_audio) { 3184 printf("Monitor has basic audio support\n"); 3185 goto end; 3186 } 3187 3188 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3189 goto end; 3190 3191 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3192 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3193 has_audio = true; 3194 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 3195 j += 3) 3196 debug("CEA audio format %d\n", 3197 (edid_ext[i + j] >> 3) & 0xf); 3198 goto end; 3199 } 3200 } 3201 end: 3202 return has_audio; 3203 } 3204 3205 static void 3206 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 3207 { 3208 struct drm_display_info *info = &data->display_info; 3209 u8 len = cea_db_payload_len(db); 3210 3211 if (len >= 6) 3212 info->dvi_dual = db[6] & 1; 3213 if (len >= 7) 3214 info->max_tmds_clock = db[7] * 5000; 3215 3216 drm_parse_hdmi_deep_color_info(data, db); 3217 } 3218 3219 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 3220 struct edid *edid) 3221 { 3222 struct drm_display_info *info = &data->display_info; 3223 const u8 *edid_ext; 3224 int i, start, end; 3225 3226 edid_ext = drm_find_cea_extension(edid); 3227 if (!edid_ext) 3228 return; 3229 3230 info->cea_rev = edid_ext[1]; 3231 3232 /* The existence of a CEA block should imply RGB support */ 3233 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3234 if (edid_ext[3] & EDID_CEA_YCRCB444) 3235 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3236 if (edid_ext[3] & EDID_CEA_YCRCB422) 3237 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3238 3239 if (cea_db_offsets(edid_ext, &start, &end)) 3240 return; 3241 3242 for_each_cea_db(edid_ext, i, start, end) { 3243 const u8 *db = &edid_ext[i]; 3244 3245 if (cea_db_is_hdmi_vsdb(db)) 3246 drm_parse_hdmi_vsdb_video(data, db); 3247 if (cea_db_is_hdmi_forum_vsdb(db)) 3248 drm_parse_hdmi_forum_vsdb(data, db); 3249 if (cea_db_is_y420cmdb(db)) 3250 drm_parse_y420cmdb_bitmap(data, db); 3251 } 3252 } 3253 3254 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 3255 { 3256 struct drm_display_info *info = &data->display_info; 3257 3258 info->width_mm = edid->width_cm * 10; 3259 info->height_mm = edid->height_cm * 10; 3260 3261 /* driver figures it out in this case */ 3262 info->bpc = 0; 3263 info->color_formats = 0; 3264 info->cea_rev = 0; 3265 info->max_tmds_clock = 0; 3266 info->dvi_dual = false; 3267 info->edid_hdmi_dc_modes = 0; 3268 3269 memset(&info->hdmi, 0, sizeof(info->hdmi)); 3270 3271 if (edid->revision < 3) 3272 return; 3273 3274 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3275 return; 3276 3277 drm_parse_cea_ext(data, edid); 3278 3279 /* 3280 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3281 * 3282 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3283 * tells us to assume 8 bpc color depth if the EDID doesn't have 3284 * extensions which tell otherwise. 3285 */ 3286 if ((info->bpc == 0) && (edid->revision < 4) && 3287 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3288 info->bpc = 8; 3289 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3290 } 3291 3292 /* Only defined for 1.4 with digital displays */ 3293 if (edid->revision < 4) 3294 return; 3295 3296 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3297 case DRM_EDID_DIGITAL_DEPTH_6: 3298 info->bpc = 6; 3299 break; 3300 case DRM_EDID_DIGITAL_DEPTH_8: 3301 info->bpc = 8; 3302 break; 3303 case DRM_EDID_DIGITAL_DEPTH_10: 3304 info->bpc = 10; 3305 break; 3306 case DRM_EDID_DIGITAL_DEPTH_12: 3307 info->bpc = 12; 3308 break; 3309 case DRM_EDID_DIGITAL_DEPTH_14: 3310 info->bpc = 14; 3311 break; 3312 case DRM_EDID_DIGITAL_DEPTH_16: 3313 info->bpc = 16; 3314 break; 3315 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3316 default: 3317 info->bpc = 0; 3318 break; 3319 } 3320 3321 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3322 info->bpc); 3323 3324 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3325 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3326 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3327 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3328 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3329 } 3330 3331 static 3332 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3333 { 3334 const u8 *cea = drm_find_cea_extension(edid); 3335 const u8 *db, *hdmi = NULL, *video = NULL; 3336 u8 dbl, hdmi_len, video_len = 0; 3337 int modes = 0; 3338 3339 if (cea && cea_revision(cea) >= 3) { 3340 int i, start, end; 3341 3342 if (cea_db_offsets(cea, &start, &end)) 3343 return 0; 3344 3345 for_each_cea_db(cea, i, start, end) { 3346 db = &cea[i]; 3347 dbl = cea_db_payload_len(db); 3348 3349 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3350 video = db + 1; 3351 video_len = dbl; 3352 modes += do_cea_modes(data, video, dbl); 3353 } else if (cea_db_is_hdmi_vsdb(db)) { 3354 hdmi = db; 3355 hdmi_len = dbl; 3356 } else if (cea_db_is_y420vdb(db)) { 3357 const u8 *vdb420 = &db[2]; 3358 3359 /* Add 4:2:0(only) modes present in EDID */ 3360 modes += do_y420vdb_modes(data, vdb420, 3361 dbl - 1); 3362 } 3363 } 3364 } 3365 3366 /* 3367 * We parse the HDMI VSDB after having added the cea modes as we will 3368 * be patching their flags when the sink supports stereo 3D. 3369 */ 3370 if (hdmi) 3371 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3372 video_len, data); 3373 3374 return modes; 3375 } 3376 3377 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3378 3379 static void 3380 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3381 { 3382 int i, n = 0; 3383 u8 d = ext[0x02]; 3384 u8 *det_base = ext + d; 3385 3386 n = (127 - d) / 18; 3387 for (i = 0; i < n; i++) 3388 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3389 } 3390 3391 static void 3392 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3393 { 3394 unsigned int i, n = min((int)ext[0x02], 6); 3395 u8 *det_base = ext + 5; 3396 3397 if (ext[0x01] != 1) 3398 return; /* unknown version */ 3399 3400 for (i = 0; i < n; i++) 3401 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3402 } 3403 3404 static void 3405 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3406 { 3407 int i; 3408 struct edid *edid = (struct edid *)raw_edid; 3409 3410 if (!edid) 3411 return; 3412 3413 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3414 cb(&edid->detailed_timings[i], closure); 3415 3416 for (i = 1; i <= raw_edid[0x7e]; i++) { 3417 u8 *ext = raw_edid + (i * EDID_SIZE); 3418 3419 switch (*ext) { 3420 case CEA_EXT: 3421 cea_for_each_detailed_block(ext, cb, closure); 3422 break; 3423 case VTB_EXT: 3424 vtb_for_each_detailed_block(ext, cb, closure); 3425 break; 3426 default: 3427 break; 3428 } 3429 } 3430 } 3431 3432 /* 3433 * EDID is delightfully ambiguous about how interlaced modes are to be 3434 * encoded. Our internal representation is of frame height, but some 3435 * HDTV detailed timings are encoded as field height. 3436 * 3437 * The format list here is from CEA, in frame size. Technically we 3438 * should be checking refresh rate too. Whatever. 3439 */ 3440 static void 3441 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3442 struct detailed_pixel_timing *pt) 3443 { 3444 int i; 3445 3446 static const struct { 3447 int w, h; 3448 } cea_interlaced[] = { 3449 { 1920, 1080 }, 3450 { 720, 480 }, 3451 { 1440, 480 }, 3452 { 2880, 480 }, 3453 { 720, 576 }, 3454 { 1440, 576 }, 3455 { 2880, 576 }, 3456 }; 3457 3458 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3459 return; 3460 3461 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3462 if ((mode->hdisplay == cea_interlaced[i].w) && 3463 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3464 mode->vdisplay *= 2; 3465 mode->vsync_start *= 2; 3466 mode->vsync_end *= 2; 3467 mode->vtotal *= 2; 3468 mode->vtotal |= 1; 3469 } 3470 } 3471 3472 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3473 } 3474 3475 /** 3476 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3477 * @edid: EDID block 3478 * @timing: EDID detailed timing info 3479 * @quirks: quirks to apply 3480 * 3481 * An EDID detailed timing block contains enough info for us to create and 3482 * return a new struct drm_display_mode. 3483 */ 3484 static 3485 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3486 struct detailed_timing *timing, 3487 u32 quirks) 3488 { 3489 struct drm_display_mode *mode; 3490 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3491 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3492 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3493 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3494 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3495 unsigned hsync_offset = 3496 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3497 pt->hsync_offset_lo; 3498 unsigned hsync_pulse_width = 3499 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3500 pt->hsync_pulse_width_lo; 3501 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3502 2 | pt->vsync_offset_pulse_width_lo >> 4; 3503 unsigned vsync_pulse_width = 3504 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3505 (pt->vsync_offset_pulse_width_lo & 0xf); 3506 3507 /* ignore tiny modes */ 3508 if (hactive < 64 || vactive < 64) 3509 return NULL; 3510 3511 if (pt->misc & DRM_EDID_PT_STEREO) { 3512 debug("stereo mode not supported\n"); 3513 return NULL; 3514 } 3515 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3516 debug("composite sync not supported\n"); 3517 3518 /* it is incorrect if hsync/vsync width is zero */ 3519 if (!hsync_pulse_width || !vsync_pulse_width) { 3520 debug("Incorrect Detailed timing. "); 3521 debug("Wrong Hsync/Vsync pulse width\n"); 3522 return NULL; 3523 } 3524 3525 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3526 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3527 if (!mode) 3528 return NULL; 3529 3530 goto set_refresh; 3531 } 3532 3533 mode = drm_mode_create(); 3534 if (!mode) 3535 return NULL; 3536 3537 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3538 timing->pixel_clock = cpu_to_le16(1088); 3539 3540 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3541 3542 mode->hdisplay = hactive; 3543 mode->hsync_start = mode->hdisplay + hsync_offset; 3544 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3545 mode->htotal = mode->hdisplay + hblank; 3546 3547 mode->vdisplay = vactive; 3548 mode->vsync_start = mode->vdisplay + vsync_offset; 3549 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3550 mode->vtotal = mode->vdisplay + vblank; 3551 3552 /* Some EDIDs have bogus h/vtotal values */ 3553 if (mode->hsync_end > mode->htotal) 3554 mode->htotal = mode->hsync_end + 1; 3555 if (mode->vsync_end > mode->vtotal) 3556 mode->vtotal = mode->vsync_end + 1; 3557 3558 drm_mode_do_interlace_quirk(mode, pt); 3559 3560 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3561 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3562 DRM_EDID_PT_VSYNC_POSITIVE; 3563 3564 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3565 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3566 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3567 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3568 3569 set_refresh: 3570 3571 mode->type = DRM_MODE_TYPE_DRIVER; 3572 mode->vrefresh = drm_get_vrefresh(mode); 3573 3574 return mode; 3575 } 3576 3577 /* 3578 * Calculate the alternate clock for the CEA mode 3579 * (60Hz vs. 59.94Hz etc.) 3580 */ 3581 static unsigned int 3582 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3583 { 3584 unsigned int clock = cea_mode->clock; 3585 3586 if (cea_mode->vrefresh % 6 != 0) 3587 return clock; 3588 3589 /* 3590 * edid_cea_modes contains the 59.94Hz 3591 * variant for 240 and 480 line modes, 3592 * and the 60Hz variant otherwise. 3593 */ 3594 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3595 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3596 else 3597 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3598 3599 return clock; 3600 } 3601 3602 /** 3603 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3604 * @mode1: first mode 3605 * @mode2: second mode 3606 * 3607 * Check to see if @mode1 and @mode2 are equivalent, but 3608 * don't check the pixel clocks nor the stereo layout. 3609 * 3610 * Returns: 3611 * True if the modes are equal, false otherwise. 3612 */ 3613 3614 static 3615 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3616 const struct drm_display_mode *mode2) 3617 { 3618 unsigned int flags_mask = 3619 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3620 3621 if (mode1->hdisplay == mode2->hdisplay && 3622 mode1->hsync_start == mode2->hsync_start && 3623 mode1->hsync_end == mode2->hsync_end && 3624 mode1->htotal == mode2->htotal && 3625 mode1->vdisplay == mode2->vdisplay && 3626 mode1->vsync_start == mode2->vsync_start && 3627 mode1->vsync_end == mode2->vsync_end && 3628 mode1->vtotal == mode2->vtotal && 3629 mode1->vscan == mode2->vscan && 3630 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3631 return true; 3632 3633 return false; 3634 } 3635 3636 /** 3637 * drm_mode_equal_no_clocks - test modes for equality 3638 * @mode1: first mode 3639 * @mode2: second mode 3640 * 3641 * Check to see if @mode1 and @mode2 are equivalent, but 3642 * don't check the pixel clocks. 3643 * 3644 * Returns: 3645 * True if the modes are equal, false otherwise. 3646 */ 3647 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3648 const struct drm_display_mode *mode2) 3649 { 3650 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3651 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3652 return false; 3653 3654 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3655 } 3656 3657 static 3658 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3659 unsigned int clock_tolerance) 3660 { 3661 u8 vic; 3662 3663 if (!to_match->clock) 3664 return 0; 3665 3666 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3667 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 3668 unsigned int clock1, clock2; 3669 3670 /* Check both 60Hz and 59.94Hz */ 3671 clock1 = cea_mode->clock; 3672 clock2 = cea_mode_alternate_clock(cea_mode); 3673 3674 if (abs(to_match->clock - clock1) > clock_tolerance && 3675 abs(to_match->clock - clock2) > clock_tolerance) 3676 continue; 3677 3678 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3679 return vic; 3680 } 3681 3682 return 0; 3683 } 3684 3685 static unsigned int 3686 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3687 { 3688 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3689 return hdmi_mode->clock; 3690 3691 return cea_mode_alternate_clock(hdmi_mode); 3692 } 3693 3694 static 3695 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3696 unsigned int clock_tolerance) 3697 { 3698 u8 vic; 3699 3700 if (!to_match->clock) 3701 return 0; 3702 3703 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3704 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3705 unsigned int clock1, clock2; 3706 3707 /* Make sure to also match alternate clocks */ 3708 clock1 = hdmi_mode->clock; 3709 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3710 3711 if (abs(to_match->clock - clock1) > clock_tolerance && 3712 abs(to_match->clock - clock2) > clock_tolerance) 3713 continue; 3714 3715 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3716 return vic; 3717 } 3718 3719 return 0; 3720 } 3721 3722 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3723 { 3724 const struct drm_display_mode *cea_mode; 3725 int clock1, clock2, clock; 3726 u8 vic; 3727 const char *type; 3728 3729 /* 3730 * allow 5kHz clock difference either way to account for 3731 * the 10kHz clock resolution limit of detailed timings. 3732 */ 3733 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3734 if (drm_valid_cea_vic(vic)) { 3735 type = "CEA"; 3736 cea_mode = &edid_cea_modes[vic]; 3737 clock1 = cea_mode->clock; 3738 clock2 = cea_mode_alternate_clock(cea_mode); 3739 } else { 3740 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3741 if (drm_valid_hdmi_vic(vic)) { 3742 type = "HDMI"; 3743 cea_mode = &edid_4k_modes[vic]; 3744 clock1 = cea_mode->clock; 3745 clock2 = hdmi_mode_alternate_clock(cea_mode); 3746 } else { 3747 return; 3748 } 3749 } 3750 3751 /* pick whichever is closest */ 3752 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3753 clock = clock1; 3754 else 3755 clock = clock2; 3756 3757 if (mode->clock == clock) 3758 return; 3759 3760 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3761 type, vic, mode->clock, clock); 3762 mode->clock = clock; 3763 } 3764 3765 static void 3766 do_detailed_mode(struct detailed_timing *timing, void *c) 3767 { 3768 struct detailed_mode_closure *closure = c; 3769 struct drm_display_mode *newmode; 3770 3771 if (timing->pixel_clock) { 3772 newmode = drm_mode_detailed( 3773 closure->edid, timing, 3774 closure->quirks); 3775 if (!newmode) 3776 return; 3777 3778 if (closure->preferred) 3779 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3780 3781 /* 3782 * Detailed modes are limited to 10kHz pixel clock resolution, 3783 * so fix up anything that looks like CEA/HDMI mode, 3784 * but the clock is just slightly off. 3785 */ 3786 fixup_detailed_cea_mode_clock(newmode); 3787 drm_add_hdmi_modes(closure->data, newmode); 3788 drm_mode_destroy(newmode); 3789 closure->modes++; 3790 closure->preferred = 0; 3791 } 3792 } 3793 3794 /* 3795 * add_detailed_modes - Add modes from detailed timings 3796 * @data: attached data 3797 * @edid: EDID block to scan 3798 * @quirks: quirks to apply 3799 */ 3800 static int 3801 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 3802 u32 quirks) 3803 { 3804 struct detailed_mode_closure closure = { 3805 .data = data, 3806 .edid = edid, 3807 .preferred = 1, 3808 .quirks = quirks, 3809 }; 3810 3811 if (closure.preferred && !version_greater(edid, 1, 3)) 3812 closure.preferred = 3813 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3814 3815 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3816 3817 return closure.modes; 3818 } 3819 3820 static int drm_cvt_modes(struct hdmi_edid_data *data, 3821 struct detailed_timing *timing) 3822 { 3823 int i, j, modes = 0; 3824 struct drm_display_mode *newmode; 3825 struct cvt_timing *cvt; 3826 const int rates[] = { 60, 85, 75, 60, 50 }; 3827 const u8 empty[3] = { 0, 0, 0 }; 3828 3829 for (i = 0; i < 4; i++) { 3830 int uninitialized_var(width), height; 3831 3832 cvt = &timing->data.other_data.data.cvt[i]; 3833 3834 if (!memcmp(cvt->code, empty, 3)) 3835 continue; 3836 3837 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3838 switch (cvt->code[1] & 0x0c) { 3839 case 0x00: 3840 width = height * 4 / 3; 3841 break; 3842 case 0x04: 3843 width = height * 16 / 9; 3844 break; 3845 case 0x08: 3846 width = height * 16 / 10; 3847 break; 3848 case 0x0c: 3849 width = height * 15 / 9; 3850 break; 3851 } 3852 3853 for (j = 1; j < 5; j++) { 3854 if (cvt->code[2] & (1 << j)) { 3855 newmode = drm_cvt_mode(width, height, 3856 rates[j], j == 0, 3857 false, false); 3858 if (newmode) { 3859 drm_add_hdmi_modes(data, newmode); 3860 modes++; 3861 drm_mode_destroy(newmode); 3862 } 3863 } 3864 } 3865 } 3866 3867 return modes; 3868 } 3869 3870 static void 3871 do_cvt_mode(struct detailed_timing *timing, void *c) 3872 { 3873 struct detailed_mode_closure *closure = c; 3874 struct detailed_non_pixel *data = &timing->data.other_data; 3875 3876 if (data->type == EDID_DETAIL_CVT_3BYTE) 3877 closure->modes += drm_cvt_modes(closure->data, timing); 3878 } 3879 3880 static int 3881 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 3882 { 3883 struct detailed_mode_closure closure = { 3884 .data = data, 3885 .edid = edid, 3886 }; 3887 3888 if (version_greater(edid, 1, 2)) 3889 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3890 3891 /* XXX should also look for CVT codes in VTB blocks */ 3892 3893 return closure.modes; 3894 } 3895 3896 static void 3897 find_gtf2(struct detailed_timing *t, void *data) 3898 { 3899 u8 *r = (u8 *)t; 3900 3901 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 3902 *(u8 **)data = r; 3903 } 3904 3905 /* Secondary GTF curve kicks in above some break frequency */ 3906 static int 3907 drm_gtf2_hbreak(struct edid *edid) 3908 { 3909 u8 *r = NULL; 3910 3911 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3912 return r ? (r[12] * 2) : 0; 3913 } 3914 3915 static int 3916 drm_gtf2_2c(struct edid *edid) 3917 { 3918 u8 *r = NULL; 3919 3920 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3921 return r ? r[13] : 0; 3922 } 3923 3924 static int 3925 drm_gtf2_m(struct edid *edid) 3926 { 3927 u8 *r = NULL; 3928 3929 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3930 return r ? (r[15] << 8) + r[14] : 0; 3931 } 3932 3933 static int 3934 drm_gtf2_k(struct edid *edid) 3935 { 3936 u8 *r = NULL; 3937 3938 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3939 return r ? r[16] : 0; 3940 } 3941 3942 static int 3943 drm_gtf2_2j(struct edid *edid) 3944 { 3945 u8 *r = NULL; 3946 3947 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3948 return r ? r[17] : 0; 3949 } 3950 3951 /** 3952 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 3953 * @edid: EDID block to scan 3954 */ 3955 static int standard_timing_level(struct edid *edid) 3956 { 3957 if (edid->revision >= 2) { 3958 if (edid->revision >= 4 && 3959 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 3960 return LEVEL_CVT; 3961 if (drm_gtf2_hbreak(edid)) 3962 return LEVEL_GTF2; 3963 return LEVEL_GTF; 3964 } 3965 return LEVEL_DMT; 3966 } 3967 3968 /* 3969 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3970 * monitors fill with ascii space (0x20) instead. 3971 */ 3972 static int 3973 bad_std_timing(u8 a, u8 b) 3974 { 3975 return (a == 0x00 && b == 0x00) || 3976 (a == 0x01 && b == 0x01) || 3977 (a == 0x20 && b == 0x20); 3978 } 3979 3980 static void 3981 is_rb(struct detailed_timing *t, void *data) 3982 { 3983 u8 *r = (u8 *)t; 3984 3985 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 3986 if (r[15] & 0x10) 3987 *(bool *)data = true; 3988 } 3989 3990 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3991 static bool 3992 drm_monitor_supports_rb(struct edid *edid) 3993 { 3994 if (edid->revision >= 4) { 3995 bool ret = false; 3996 3997 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 3998 return ret; 3999 } 4000 4001 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 4002 } 4003 4004 static bool 4005 mode_is_rb(const struct drm_display_mode *mode) 4006 { 4007 return (mode->htotal - mode->hdisplay == 160) && 4008 (mode->hsync_end - mode->hdisplay == 80) && 4009 (mode->hsync_end - mode->hsync_start == 32) && 4010 (mode->vsync_start - mode->vdisplay == 3); 4011 } 4012 4013 /* 4014 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 4015 * @hsize: Mode width 4016 * @vsize: Mode height 4017 * @fresh: Mode refresh rate 4018 * @rb: Mode reduced-blanking-ness 4019 * 4020 * Walk the DMT mode list looking for a match for the given parameters. 4021 * 4022 * Return: A newly allocated copy of the mode, or NULL if not found. 4023 */ 4024 static struct drm_display_mode *drm_mode_find_dmt( 4025 int hsize, int vsize, int fresh, 4026 bool rb) 4027 { 4028 int i; 4029 struct drm_display_mode *newmode; 4030 4031 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4032 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4033 4034 if (hsize != ptr->hdisplay) 4035 continue; 4036 if (vsize != ptr->vdisplay) 4037 continue; 4038 if (fresh != drm_get_vrefresh(ptr)) 4039 continue; 4040 if (rb != mode_is_rb(ptr)) 4041 continue; 4042 4043 newmode = drm_mode_create(); 4044 *newmode = *ptr; 4045 return newmode; 4046 } 4047 4048 return NULL; 4049 } 4050 4051 static struct drm_display_mode * 4052 drm_gtf_mode_complex(int hdisplay, int vdisplay, 4053 int vrefresh, bool interlaced, int margins, 4054 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 4055 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 4056 #define GTF_MARGIN_PERCENTAGE 18 4057 /* 2) character cell horizontal granularity (pixels) - default 8 */ 4058 #define GTF_CELL_GRAN 8 4059 /* 3) Minimum vertical porch (lines) - default 3 */ 4060 #define GTF_MIN_V_PORCH 1 4061 /* width of vsync in lines */ 4062 #define V_SYNC_RQD 3 4063 /* width of hsync as % of total line */ 4064 #define H_SYNC_PERCENT 8 4065 /* min time of vsync + back porch (microsec) */ 4066 #define MIN_VSYNC_PLUS_BP 550 4067 /* C' and M' are part of the Blanking Duty Cycle computation */ 4068 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 4069 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 4070 struct drm_display_mode *drm_mode; 4071 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 4072 int top_margin, bottom_margin; 4073 int interlace; 4074 unsigned int hfreq_est; 4075 int vsync_plus_bp; 4076 unsigned int vtotal_lines; 4077 int left_margin, right_margin; 4078 unsigned int total_active_pixels, ideal_duty_cycle; 4079 unsigned int hblank, total_pixels, pixel_freq; 4080 int hsync, hfront_porch, vodd_front_porch_lines; 4081 unsigned int tmp1, tmp2; 4082 4083 drm_mode = drm_mode_create(); 4084 if (!drm_mode) 4085 return NULL; 4086 4087 /* 1. In order to give correct results, the number of horizontal 4088 * pixels requested is first processed to ensure that it is divisible 4089 * by the character size, by rounding it to the nearest character 4090 * cell boundary: 4091 */ 4092 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4093 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 4094 4095 /* 2. If interlace is requested, the number of vertical lines assumed 4096 * by the calculation must be halved, as the computation calculates 4097 * the number of vertical lines per field. 4098 */ 4099 if (interlaced) 4100 vdisplay_rnd = vdisplay / 2; 4101 else 4102 vdisplay_rnd = vdisplay; 4103 4104 /* 3. Find the frame rate required: */ 4105 if (interlaced) 4106 vfieldrate_rqd = vrefresh * 2; 4107 else 4108 vfieldrate_rqd = vrefresh; 4109 4110 /* 4. Find number of lines in Top margin: */ 4111 top_margin = 0; 4112 if (margins) 4113 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4114 1000; 4115 /* 5. Find number of lines in bottom margin: */ 4116 bottom_margin = top_margin; 4117 4118 /* 6. If interlace is required, then set variable interlace: */ 4119 if (interlaced) 4120 interlace = 1; 4121 else 4122 interlace = 0; 4123 4124 /* 7. Estimate the Horizontal frequency */ 4125 { 4126 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 4127 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 4128 2 + interlace; 4129 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 4130 } 4131 4132 /* 8. Find the number of lines in V sync + back porch */ 4133 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 4134 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 4135 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 4136 /* 9. Find the number of lines in V back porch alone: 4137 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 4138 */ 4139 /* 10. Find the total number of lines in Vertical field period: */ 4140 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 4141 vsync_plus_bp + GTF_MIN_V_PORCH; 4142 /* 11. Estimate the Vertical field frequency: 4143 * vfieldrate_est = hfreq_est / vtotal_lines; 4144 */ 4145 4146 /* 12. Find the actual horizontal period: 4147 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 4148 */ 4149 /* 13. Find the actual Vertical field frequency: 4150 * vfield_rate = hfreq_est / vtotal_lines; 4151 */ 4152 /* 14. Find the Vertical frame frequency: 4153 * if (interlaced) 4154 * vframe_rate = vfield_rate / 2; 4155 * else 4156 * vframe_rate = vfield_rate; 4157 */ 4158 /* 15. Find number of pixels in left margin: */ 4159 if (margins) 4160 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4161 1000; 4162 else 4163 left_margin = 0; 4164 4165 /* 16.Find number of pixels in right margin: */ 4166 right_margin = left_margin; 4167 /* 17.Find total number of active pixels in image and left and right */ 4168 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 4169 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 4170 ideal_duty_cycle = GTF_C_PRIME * 1000 - 4171 (GTF_M_PRIME * 1000000 / hfreq_est); 4172 /* 19.Find the number of pixels in the blanking time to the nearest 4173 * double character cell: 4174 */ 4175 hblank = total_active_pixels * ideal_duty_cycle / 4176 (100000 - ideal_duty_cycle); 4177 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 4178 hblank = hblank * 2 * GTF_CELL_GRAN; 4179 /* 20.Find total number of pixels: */ 4180 total_pixels = total_active_pixels + hblank; 4181 /* 21.Find pixel clock frequency: */ 4182 pixel_freq = total_pixels * hfreq_est / 1000; 4183 /* Stage 1 computations are now complete; I should really pass 4184 * the results to another function and do the Stage 2 computations, 4185 * but I only need a few more values so I'll just append the 4186 * computations here for now 4187 */ 4188 4189 /* 17. Find the number of pixels in the horizontal sync period: */ 4190 hsync = H_SYNC_PERCENT * total_pixels / 100; 4191 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4192 hsync = hsync * GTF_CELL_GRAN; 4193 /* 18. Find the number of pixels in horizontal front porch period */ 4194 hfront_porch = hblank / 2 - hsync; 4195 /* 36. Find the number of lines in the odd front porch period: */ 4196 vodd_front_porch_lines = GTF_MIN_V_PORCH; 4197 4198 /* finally, pack the results in the mode struct */ 4199 drm_mode->hdisplay = hdisplay_rnd; 4200 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 4201 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 4202 drm_mode->htotal = total_pixels; 4203 drm_mode->vdisplay = vdisplay_rnd; 4204 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 4205 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 4206 drm_mode->vtotal = vtotal_lines; 4207 4208 drm_mode->clock = pixel_freq; 4209 4210 if (interlaced) { 4211 drm_mode->vtotal *= 2; 4212 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 4213 } 4214 4215 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 4216 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 4217 else 4218 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 4219 4220 return drm_mode; 4221 } 4222 4223 /** 4224 * drm_gtf_mode - create the mode based on the GTF algorithm 4225 * @hdisplay: hdisplay size 4226 * @vdisplay: vdisplay size 4227 * @vrefresh: vrefresh rate. 4228 * @interlaced: whether to compute an interlaced mode 4229 * @margins: desired margin (borders) size 4230 * 4231 * return the mode based on GTF algorithm 4232 * 4233 * This function is to create the mode based on the GTF algorithm. 4234 * Generalized Timing Formula is derived from: 4235 * GTF Spreadsheet by Andy Morrish (1/5/97) 4236 * available at http://www.vesa.org 4237 * 4238 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 4239 * What I have done is to translate it by using integer calculation. 4240 * I also refer to the function of fb_get_mode in the file of 4241 * drivers/video/fbmon.c 4242 * 4243 * Standard GTF parameters: 4244 * M = 600 4245 * C = 40 4246 * K = 128 4247 * J = 20 4248 * 4249 * Returns: 4250 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 4251 * The display mode object is allocated with drm_mode_create(). Returns NULL 4252 * when no mode could be allocated. 4253 */ 4254 static struct drm_display_mode * 4255 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 4256 bool interlaced, int margins) 4257 { 4258 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 4259 interlaced, margins, 4260 600, 40 * 2, 128, 20 * 2); 4261 } 4262 4263 /** drm_mode_hsync - get the hsync of a mode 4264 * @mode: mode 4265 * 4266 * Returns: 4267 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 4268 * value first if it is not yet set. 4269 */ 4270 static int drm_mode_hsync(const struct drm_display_mode *mode) 4271 { 4272 unsigned int calc_val; 4273 4274 if (mode->htotal < 0) 4275 return 0; 4276 4277 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 4278 calc_val += 500; /* round to 1000Hz */ 4279 calc_val /= 1000; /* truncate to kHz */ 4280 4281 return calc_val; 4282 } 4283 4284 /** 4285 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 4286 * @data: the structure that save parsed hdmi edid data 4287 * @edid: EDID block to scan 4288 * @t: standard timing params 4289 * 4290 * Take the standard timing params (in this case width, aspect, and refresh) 4291 * and convert them into a real mode using CVT/GTF/DMT. 4292 */ 4293 static struct drm_display_mode * 4294 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4295 struct std_timing *t) 4296 { 4297 struct drm_display_mode *mode = NULL; 4298 int i, hsize, vsize; 4299 int vrefresh_rate; 4300 int num = data->modes; 4301 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4302 >> EDID_TIMING_ASPECT_SHIFT; 4303 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4304 >> EDID_TIMING_VFREQ_SHIFT; 4305 int timing_level = standard_timing_level(edid); 4306 4307 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4308 return NULL; 4309 4310 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4311 hsize = t->hsize * 8 + 248; 4312 /* vrefresh_rate = vfreq + 60 */ 4313 vrefresh_rate = vfreq + 60; 4314 /* the vdisplay is calculated based on the aspect ratio */ 4315 if (aspect_ratio == 0) { 4316 if (edid->revision < 3) 4317 vsize = hsize; 4318 else 4319 vsize = (hsize * 10) / 16; 4320 } else if (aspect_ratio == 1) { 4321 vsize = (hsize * 3) / 4; 4322 } else if (aspect_ratio == 2) { 4323 vsize = (hsize * 4) / 5; 4324 } else { 4325 vsize = (hsize * 9) / 16; 4326 } 4327 4328 /* HDTV hack, part 1 */ 4329 if (vrefresh_rate == 60 && 4330 ((hsize == 1360 && vsize == 765) || 4331 (hsize == 1368 && vsize == 769))) { 4332 hsize = 1366; 4333 vsize = 768; 4334 } 4335 4336 /* 4337 * If we already has a mode for this size and refresh 4338 * rate (because it came from detailed or CVT info), use that 4339 * instead. This way we don't have to guess at interlace or 4340 * reduced blanking. 4341 */ 4342 for (i = 0; i < num; i++) 4343 if (data->mode_buf[i].hdisplay == hsize && 4344 data->mode_buf[i].vdisplay == vsize && 4345 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4346 return NULL; 4347 4348 /* HDTV hack, part 2 */ 4349 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4350 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4351 false); 4352 mode->hdisplay = 1366; 4353 mode->hsync_start = mode->hsync_start - 1; 4354 mode->hsync_end = mode->hsync_end - 1; 4355 return mode; 4356 } 4357 4358 /* check whether it can be found in default mode table */ 4359 if (drm_monitor_supports_rb(edid)) { 4360 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4361 true); 4362 if (mode) 4363 return mode; 4364 } 4365 4366 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4367 if (mode) 4368 return mode; 4369 4370 /* okay, generate it */ 4371 switch (timing_level) { 4372 case LEVEL_DMT: 4373 break; 4374 case LEVEL_GTF: 4375 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4376 break; 4377 case LEVEL_GTF2: 4378 /* 4379 * This is potentially wrong if there's ever a monitor with 4380 * more than one ranges section, each claiming a different 4381 * secondary GTF curve. Please don't do that. 4382 */ 4383 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4384 if (!mode) 4385 return NULL; 4386 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4387 drm_mode_destroy(mode); 4388 mode = drm_gtf_mode_complex(hsize, vsize, 4389 vrefresh_rate, 0, 0, 4390 drm_gtf2_m(edid), 4391 drm_gtf2_2c(edid), 4392 drm_gtf2_k(edid), 4393 drm_gtf2_2j(edid)); 4394 } 4395 break; 4396 case LEVEL_CVT: 4397 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4398 false); 4399 break; 4400 } 4401 4402 return mode; 4403 } 4404 4405 static void 4406 do_standard_modes(struct detailed_timing *timing, void *c) 4407 { 4408 struct detailed_mode_closure *closure = c; 4409 struct detailed_non_pixel *data = &timing->data.other_data; 4410 struct edid *edid = closure->edid; 4411 4412 if (data->type == EDID_DETAIL_STD_MODES) { 4413 int i; 4414 4415 for (i = 0; i < 6; i++) { 4416 struct std_timing *std; 4417 struct drm_display_mode *newmode; 4418 4419 std = &data->data.timings[i]; 4420 newmode = drm_mode_std(closure->data, edid, std); 4421 if (newmode) { 4422 drm_add_hdmi_modes(closure->data, newmode); 4423 closure->modes++; 4424 drm_mode_destroy(newmode); 4425 } 4426 } 4427 } 4428 } 4429 4430 /** 4431 * add_standard_modes - get std. modes from EDID and add them 4432 * @data: data to add mode(s) to 4433 * @edid: EDID block to scan 4434 * 4435 * Standard modes can be calculated using the appropriate standard (DMT, 4436 * GTF or CVT. Grab them from @edid and add them to the list. 4437 */ 4438 static int 4439 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4440 { 4441 int i, modes = 0; 4442 struct detailed_mode_closure closure = { 4443 .data = data, 4444 .edid = edid, 4445 }; 4446 4447 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4448 struct drm_display_mode *newmode; 4449 4450 newmode = drm_mode_std(data, edid, 4451 &edid->standard_timings[i]); 4452 if (newmode) { 4453 drm_add_hdmi_modes(data, newmode); 4454 modes++; 4455 drm_mode_destroy(newmode); 4456 } 4457 } 4458 4459 if (version_greater(edid, 1, 0)) 4460 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4461 &closure); 4462 4463 /* XXX should also look for standard codes in VTB blocks */ 4464 4465 return modes + closure.modes; 4466 } 4467 4468 static int 4469 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4470 { 4471 int i, j, m, modes = 0; 4472 struct drm_display_mode *mode; 4473 u8 *est = ((u8 *)timing) + 6; 4474 4475 for (i = 0; i < 6; i++) { 4476 for (j = 7; j >= 0; j--) { 4477 m = (i * 8) + (7 - j); 4478 if (m >= ARRAY_SIZE(est3_modes)) 4479 break; 4480 if (est[i] & (1 << j)) { 4481 mode = drm_mode_find_dmt( 4482 est3_modes[m].w, 4483 est3_modes[m].h, 4484 est3_modes[m].r, 4485 est3_modes[m].rb); 4486 if (mode) { 4487 drm_add_hdmi_modes(data, mode); 4488 modes++; 4489 drm_mode_destroy(mode); 4490 } 4491 } 4492 } 4493 } 4494 4495 return modes; 4496 } 4497 4498 static void 4499 do_established_modes(struct detailed_timing *timing, void *c) 4500 { 4501 struct detailed_mode_closure *closure = c; 4502 struct detailed_non_pixel *data = &timing->data.other_data; 4503 4504 if (data->type == EDID_DETAIL_EST_TIMINGS) 4505 closure->modes += drm_est3_modes(closure->data, timing); 4506 } 4507 4508 /** 4509 * add_established_modes - get est. modes from EDID and add them 4510 * @data: data to add mode(s) to 4511 * @edid: EDID block to scan 4512 * 4513 * Each EDID block contains a bitmap of the supported "established modes" list 4514 * (defined above). Tease them out and add them to the modes list. 4515 */ 4516 static int 4517 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4518 { 4519 unsigned long est_bits = edid->established_timings.t1 | 4520 (edid->established_timings.t2 << 8) | 4521 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4522 int i, modes = 0; 4523 struct detailed_mode_closure closure = { 4524 .data = data, 4525 .edid = edid, 4526 }; 4527 4528 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4529 if (est_bits & (1 << i)) { 4530 struct drm_display_mode *newmode = drm_mode_create(); 4531 *newmode = edid_est_modes[i]; 4532 if (newmode) { 4533 drm_add_hdmi_modes(data, newmode); 4534 modes++; 4535 drm_mode_destroy(newmode); 4536 } 4537 } 4538 } 4539 4540 if (version_greater(edid, 1, 0)) 4541 drm_for_each_detailed_block((u8 *)edid, 4542 do_established_modes, &closure); 4543 4544 return modes + closure.modes; 4545 } 4546 4547 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4548 { 4549 u8 vic; 4550 4551 if (!to_match->clock) 4552 return 0; 4553 4554 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4555 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4556 unsigned int clock1, clock2; 4557 4558 /* Make sure to also match alternate clocks */ 4559 clock1 = hdmi_mode->clock; 4560 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4561 4562 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4563 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4564 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4565 return vic; 4566 } 4567 return 0; 4568 } 4569 4570 static int 4571 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4572 { 4573 struct drm_display_mode *mode; 4574 int i, num, modes = 0; 4575 4576 /* Don't add CEA modes if the CEA extension block is missing */ 4577 if (!drm_find_cea_extension(edid)) 4578 return 0; 4579 4580 /* 4581 * Go through all probed modes and create a new mode 4582 * with the alternate clock for certain CEA modes. 4583 */ 4584 num = data->modes; 4585 4586 for (i = 0; i < num; i++) { 4587 const struct drm_display_mode *cea_mode = NULL; 4588 struct drm_display_mode *newmode; 4589 u8 vic; 4590 unsigned int clock1, clock2; 4591 4592 mode = &data->mode_buf[i]; 4593 vic = drm_match_cea_mode(mode); 4594 4595 if (drm_valid_cea_vic(vic)) { 4596 cea_mode = &edid_cea_modes[vic]; 4597 clock2 = cea_mode_alternate_clock(cea_mode); 4598 } else { 4599 vic = drm_match_hdmi_mode(mode); 4600 if (drm_valid_hdmi_vic(vic)) { 4601 cea_mode = &edid_4k_modes[vic]; 4602 clock2 = hdmi_mode_alternate_clock(cea_mode); 4603 } 4604 } 4605 4606 if (!cea_mode) 4607 continue; 4608 4609 clock1 = cea_mode->clock; 4610 4611 if (clock1 == clock2) 4612 continue; 4613 4614 if (mode->clock != clock1 && mode->clock != clock2) 4615 continue; 4616 4617 newmode = drm_mode_create(); 4618 *newmode = *cea_mode; 4619 if (!newmode) 4620 continue; 4621 4622 /* Carry over the stereo flags */ 4623 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4624 4625 /* 4626 * The current mode could be either variant. Make 4627 * sure to pick the "other" clock for the new mode. 4628 */ 4629 if (mode->clock != clock1) 4630 newmode->clock = clock1; 4631 else 4632 newmode->clock = clock2; 4633 4634 drm_add_hdmi_modes(data, newmode); 4635 modes++; 4636 drm_mode_destroy(newmode); 4637 } 4638 4639 return modes; 4640 } 4641 4642 static u8 *drm_find_displayid_extension(struct edid *edid) 4643 { 4644 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4645 } 4646 4647 static int validate_displayid(u8 *displayid, int length, int idx) 4648 { 4649 int i; 4650 u8 csum = 0; 4651 struct displayid_hdr *base; 4652 4653 base = (struct displayid_hdr *)&displayid[idx]; 4654 4655 debug("base revision 0x%x, length %d, %d %d\n", 4656 base->rev, base->bytes, base->prod_id, base->ext_count); 4657 4658 if (base->bytes + 5 > length - idx) 4659 return -EINVAL; 4660 for (i = idx; i <= base->bytes + 5; i++) 4661 csum += displayid[i]; 4662 if (csum) { 4663 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4664 return -EINVAL; 4665 } 4666 return 0; 4667 } 4668 4669 static struct 4670 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4671 *timings) 4672 { 4673 struct drm_display_mode *mode; 4674 unsigned pixel_clock = (timings->pixel_clock[0] | 4675 (timings->pixel_clock[1] << 8) | 4676 (timings->pixel_clock[2] << 16)); 4677 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4678 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4679 unsigned hsync = (timings->hsync[0] | 4680 (timings->hsync[1] & 0x7f) << 8) + 1; 4681 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4682 unsigned vactive = (timings->vactive[0] | 4683 timings->vactive[1] << 8) + 1; 4684 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4685 unsigned vsync = (timings->vsync[0] | 4686 (timings->vsync[1] & 0x7f) << 8) + 1; 4687 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4688 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4689 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4690 4691 mode = drm_mode_create(); 4692 if (!mode) 4693 return NULL; 4694 4695 mode->clock = pixel_clock * 10; 4696 mode->hdisplay = hactive; 4697 mode->hsync_start = mode->hdisplay + hsync; 4698 mode->hsync_end = mode->hsync_start + hsync_width; 4699 mode->htotal = mode->hdisplay + hblank; 4700 4701 mode->vdisplay = vactive; 4702 mode->vsync_start = mode->vdisplay + vsync; 4703 mode->vsync_end = mode->vsync_start + vsync_width; 4704 mode->vtotal = mode->vdisplay + vblank; 4705 4706 mode->flags = 0; 4707 mode->flags |= 4708 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4709 mode->flags |= 4710 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4711 mode->type = DRM_MODE_TYPE_DRIVER; 4712 4713 if (timings->flags & 0x80) 4714 mode->type |= DRM_MODE_TYPE_PREFERRED; 4715 mode->vrefresh = drm_get_vrefresh(mode); 4716 4717 return mode; 4718 } 4719 4720 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 4721 struct displayid_block *block) 4722 { 4723 struct displayid_detailed_timing_block *det; 4724 int i; 4725 int num_timings; 4726 struct drm_display_mode *newmode; 4727 int num_modes = 0; 4728 4729 det = (struct displayid_detailed_timing_block *)block; 4730 /* blocks must be multiple of 20 bytes length */ 4731 if (block->num_bytes % 20) 4732 return 0; 4733 4734 num_timings = block->num_bytes / 20; 4735 for (i = 0; i < num_timings; i++) { 4736 struct displayid_detailed_timings_1 *timings = 4737 &det->timings[i]; 4738 4739 newmode = drm_displayid_detailed(timings); 4740 if (!newmode) 4741 continue; 4742 4743 drm_add_hdmi_modes(data, newmode); 4744 num_modes++; 4745 drm_mode_destroy(newmode); 4746 } 4747 return num_modes; 4748 } 4749 4750 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 4751 struct edid *edid) 4752 { 4753 u8 *displayid; 4754 int ret; 4755 int idx = 1; 4756 int length = EDID_SIZE; 4757 struct displayid_block *block; 4758 int num_modes = 0; 4759 4760 displayid = drm_find_displayid_extension(edid); 4761 if (!displayid) 4762 return 0; 4763 4764 ret = validate_displayid(displayid, length, idx); 4765 if (ret) 4766 return 0; 4767 4768 idx += sizeof(struct displayid_hdr); 4769 while (block = (struct displayid_block *)&displayid[idx], 4770 idx + sizeof(struct displayid_block) <= length && 4771 idx + sizeof(struct displayid_block) + block->num_bytes <= 4772 length && block->num_bytes > 0) { 4773 idx += block->num_bytes + sizeof(struct displayid_block); 4774 switch (block->tag) { 4775 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4776 num_modes += 4777 add_displayid_detailed_1_modes(data, block); 4778 break; 4779 } 4780 } 4781 return num_modes; 4782 } 4783 4784 static bool 4785 mode_in_hsync_range(const struct drm_display_mode *mode, 4786 struct edid *edid, u8 *t) 4787 { 4788 int hsync, hmin, hmax; 4789 4790 hmin = t[7]; 4791 if (edid->revision >= 4) 4792 hmin += ((t[4] & 0x04) ? 255 : 0); 4793 hmax = t[8]; 4794 if (edid->revision >= 4) 4795 hmax += ((t[4] & 0x08) ? 255 : 0); 4796 hsync = drm_mode_hsync(mode); 4797 4798 return (hsync <= hmax && hsync >= hmin); 4799 } 4800 4801 static bool 4802 mode_in_vsync_range(const struct drm_display_mode *mode, 4803 struct edid *edid, u8 *t) 4804 { 4805 int vsync, vmin, vmax; 4806 4807 vmin = t[5]; 4808 if (edid->revision >= 4) 4809 vmin += ((t[4] & 0x01) ? 255 : 0); 4810 vmax = t[6]; 4811 if (edid->revision >= 4) 4812 vmax += ((t[4] & 0x02) ? 255 : 0); 4813 vsync = drm_get_vrefresh(mode); 4814 4815 return (vsync <= vmax && vsync >= vmin); 4816 } 4817 4818 static u32 4819 range_pixel_clock(struct edid *edid, u8 *t) 4820 { 4821 /* unspecified */ 4822 if (t[9] == 0 || t[9] == 255) 4823 return 0; 4824 4825 /* 1.4 with CVT support gives us real precision, yay */ 4826 if (edid->revision >= 4 && t[10] == 0x04) 4827 return (t[9] * 10000) - ((t[12] >> 2) * 250); 4828 4829 /* 1.3 is pathetic, so fuzz up a bit */ 4830 return t[9] * 10000 + 5001; 4831 } 4832 4833 static bool 4834 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 4835 struct detailed_timing *timing) 4836 { 4837 u32 max_clock; 4838 u8 *t = (u8 *)timing; 4839 4840 if (!mode_in_hsync_range(mode, edid, t)) 4841 return false; 4842 4843 if (!mode_in_vsync_range(mode, edid, t)) 4844 return false; 4845 4846 max_clock = range_pixel_clock(edid, t); 4847 if (max_clock) 4848 if (mode->clock > max_clock) 4849 return false; 4850 4851 /* 1.4 max horizontal check */ 4852 if (edid->revision >= 4 && t[10] == 0x04) 4853 if (t[13] && mode->hdisplay > 8 * 4854 (t[13] + (256 * (t[12] & 0x3)))) 4855 return false; 4856 4857 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 4858 return false; 4859 4860 return true; 4861 } 4862 4863 static bool valid_inferred_mode(struct hdmi_edid_data *data, 4864 const struct drm_display_mode *mode) 4865 { 4866 const struct drm_display_mode *m; 4867 bool ok = false; 4868 int i; 4869 4870 for (i = 0; i < data->modes; i++) { 4871 m = &data->mode_buf[i]; 4872 if (mode->hdisplay == m->hdisplay && 4873 mode->vdisplay == m->vdisplay && 4874 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 4875 return false; /* duplicated */ 4876 if (mode->hdisplay <= m->hdisplay && 4877 mode->vdisplay <= m->vdisplay) 4878 ok = true; 4879 } 4880 return ok; 4881 } 4882 4883 static int 4884 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4885 struct detailed_timing *timing) 4886 { 4887 int i, modes = 0; 4888 4889 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4890 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 4891 valid_inferred_mode(data, drm_dmt_modes + i)) { 4892 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 4893 modes++; 4894 } 4895 } 4896 4897 return modes; 4898 } 4899 4900 /* fix up 1366x768 mode from 1368x768; 4901 * GFT/CVT can't express 1366 width which isn't dividable by 8 4902 */ 4903 static void fixup_mode_1366x768(struct drm_display_mode *mode) 4904 { 4905 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 4906 mode->hdisplay = 1366; 4907 mode->hsync_start--; 4908 mode->hsync_end--; 4909 } 4910 } 4911 4912 static int 4913 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4914 struct detailed_timing *timing) 4915 { 4916 int i, modes = 0; 4917 struct drm_display_mode *newmode; 4918 4919 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4920 const struct minimode *m = &extra_modes[i]; 4921 4922 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 4923 if (!newmode) 4924 return modes; 4925 4926 fixup_mode_1366x768(newmode); 4927 if (!mode_in_range(newmode, edid, timing) || 4928 !valid_inferred_mode(data, newmode)) { 4929 drm_mode_destroy(newmode); 4930 continue; 4931 } 4932 4933 drm_add_hdmi_modes(data, newmode); 4934 modes++; 4935 drm_mode_destroy(newmode); 4936 } 4937 4938 return modes; 4939 } 4940 4941 static int 4942 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4943 struct detailed_timing *timing) 4944 { 4945 int i, modes = 0; 4946 struct drm_display_mode *newmode; 4947 bool rb = drm_monitor_supports_rb(edid); 4948 4949 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4950 const struct minimode *m = &extra_modes[i]; 4951 4952 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 4953 if (!newmode) 4954 return modes; 4955 4956 fixup_mode_1366x768(newmode); 4957 if (!mode_in_range(newmode, edid, timing) || 4958 !valid_inferred_mode(data, newmode)) { 4959 drm_mode_destroy(newmode); 4960 continue; 4961 } 4962 4963 drm_add_hdmi_modes(data, newmode); 4964 modes++; 4965 drm_mode_destroy(newmode); 4966 } 4967 4968 return modes; 4969 } 4970 4971 static void 4972 do_inferred_modes(struct detailed_timing *timing, void *c) 4973 { 4974 struct detailed_mode_closure *closure = c; 4975 struct detailed_non_pixel *data = &timing->data.other_data; 4976 struct detailed_data_monitor_range *range = &data->data.range; 4977 4978 if (data->type != EDID_DETAIL_MONITOR_RANGE) 4979 return; 4980 4981 closure->modes += drm_dmt_modes_for_range(closure->data, 4982 closure->edid, 4983 timing); 4984 4985 if (!version_greater(closure->edid, 1, 1)) 4986 return; /* GTF not defined yet */ 4987 4988 switch (range->flags) { 4989 case 0x02: /* secondary gtf, XXX could do more */ 4990 case 0x00: /* default gtf */ 4991 closure->modes += drm_gtf_modes_for_range(closure->data, 4992 closure->edid, 4993 timing); 4994 break; 4995 case 0x04: /* cvt, only in 1.4+ */ 4996 if (!version_greater(closure->edid, 1, 3)) 4997 break; 4998 4999 closure->modes += drm_cvt_modes_for_range(closure->data, 5000 closure->edid, 5001 timing); 5002 break; 5003 case 0x01: /* just the ranges, no formula */ 5004 default: 5005 break; 5006 } 5007 } 5008 5009 static int 5010 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 5011 { 5012 struct detailed_mode_closure closure = { 5013 .data = data, 5014 .edid = edid, 5015 }; 5016 5017 if (version_greater(edid, 1, 0)) 5018 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 5019 &closure); 5020 5021 return closure.modes; 5022 } 5023 5024 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 5025 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 5026 5027 /** 5028 * edid_fixup_preferred - set preferred modes based on quirk list 5029 * @data: the structure that save parsed hdmi edid data 5030 * @quirks: quirks list 5031 * 5032 * Walk the mode list, clearing the preferred status 5033 * on existing modes and setting it anew for the right mode ala @quirks. 5034 */ 5035 static void edid_fixup_preferred(struct hdmi_edid_data *data, 5036 u32 quirks) 5037 { 5038 struct drm_display_mode *cur_mode, *preferred_mode; 5039 int i, target_refresh = 0; 5040 int num = data->modes; 5041 int cur_vrefresh, preferred_vrefresh; 5042 5043 if (!num) 5044 return; 5045 5046 preferred_mode = data->preferred_mode; 5047 5048 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 5049 target_refresh = 60; 5050 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 5051 target_refresh = 75; 5052 5053 for (i = 0; i < num; i++) { 5054 cur_mode = &data->mode_buf[i]; 5055 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 5056 5057 if (cur_mode == preferred_mode) 5058 continue; 5059 5060 /* Largest mode is preferred */ 5061 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 5062 preferred_mode = cur_mode; 5063 5064 cur_vrefresh = cur_mode->vrefresh ? 5065 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 5066 preferred_vrefresh = preferred_mode->vrefresh ? 5067 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 5068 /* At a given size, try to get closest to target refresh */ 5069 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 5070 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 5071 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 5072 preferred_mode = cur_mode; 5073 } 5074 } 5075 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 5076 data->preferred_mode = preferred_mode; 5077 } 5078 5079 static const u8 edid_header[] = { 5080 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 5081 }; 5082 5083 /** 5084 * drm_edid_header_is_valid - sanity check the header of the base EDID block 5085 * @raw_edid: pointer to raw base EDID block 5086 * 5087 * Sanity check the header of the base EDID block. 5088 * 5089 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 5090 */ 5091 static int drm_edid_header_is_valid(const u8 *raw_edid) 5092 { 5093 int i, score = 0; 5094 5095 for (i = 0; i < sizeof(edid_header); i++) 5096 if (raw_edid[i] == edid_header[i]) 5097 score++; 5098 5099 return score; 5100 } 5101 5102 static int drm_edid_block_checksum(const u8 *raw_edid) 5103 { 5104 int i; 5105 u8 csum = 0; 5106 5107 for (i = 0; i < EDID_SIZE; i++) 5108 csum += raw_edid[i]; 5109 5110 return csum; 5111 } 5112 5113 static bool drm_edid_is_zero(const u8 *in_edid, int length) 5114 { 5115 if (memchr_inv(in_edid, 0, length)) 5116 return false; 5117 5118 return true; 5119 } 5120 5121 /** 5122 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 5123 * @raw_edid: pointer to raw EDID block 5124 * @block: type of block to validate (0 for base, extension otherwise) 5125 * @print_bad_edid: if true, dump bad EDID blocks to the console 5126 * @edid_corrupt: if true, the header or checksum is invalid 5127 * 5128 * Validate a base or extension EDID block and optionally dump bad blocks to 5129 * the console. 5130 * 5131 * Return: True if the block is valid, false otherwise. 5132 */ 5133 static 5134 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 5135 bool *edid_corrupt) 5136 { 5137 u8 csum; 5138 int edid_fixup = 6; 5139 struct edid *edid = (struct edid *)raw_edid; 5140 5141 if ((!raw_edid)) 5142 return false; 5143 5144 if (block == 0) { 5145 int score = drm_edid_header_is_valid(raw_edid); 5146 5147 if (score == 8) { 5148 if (edid_corrupt) 5149 *edid_corrupt = false; 5150 } else if (score >= edid_fixup) { 5151 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 5152 * The corrupt flag needs to be set here otherwise, the 5153 * fix-up code here will correct the problem, the 5154 * checksum is correct and the test fails 5155 */ 5156 if (edid_corrupt) 5157 *edid_corrupt = true; 5158 debug("Fixing header, your hardware may be failing\n"); 5159 memcpy(raw_edid, edid_header, sizeof(edid_header)); 5160 } else { 5161 if (edid_corrupt) 5162 *edid_corrupt = true; 5163 goto bad; 5164 } 5165 } 5166 5167 csum = drm_edid_block_checksum(raw_edid); 5168 if (csum) { 5169 if (print_bad_edid) { 5170 debug("EDID checksum is invalid, remainder is %d\n", 5171 csum); 5172 } 5173 5174 if (edid_corrupt) 5175 *edid_corrupt = true; 5176 5177 /* allow CEA to slide through, switches mangle this */ 5178 if (raw_edid[0] != 0x02) 5179 goto bad; 5180 } 5181 5182 /* per-block-type checks */ 5183 switch (raw_edid[0]) { 5184 case 0: /* base */ 5185 if (edid->version != 1) { 5186 debug("EDID has major version %d, instead of 1\n", 5187 edid->version); 5188 goto bad; 5189 } 5190 5191 if (edid->revision > 4) 5192 debug("minor > 4, assuming backward compatibility\n"); 5193 break; 5194 5195 default: 5196 break; 5197 } 5198 5199 return true; 5200 5201 bad: 5202 if (print_bad_edid) { 5203 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 5204 debug("EDID block is all zeroes\n"); 5205 } else { 5206 debug("Raw EDID:\n"); 5207 print_hex_dump("", DUMP_PREFIX_NONE, 16, 1, 5208 raw_edid, EDID_SIZE, false); 5209 } 5210 } 5211 return false; 5212 } 5213 5214 /** 5215 * drm_edid_is_valid - sanity check EDID data 5216 * @edid: EDID data 5217 * 5218 * Sanity-check an entire EDID record (including extensions) 5219 * 5220 * Return: True if the EDID data is valid, false otherwise. 5221 */ 5222 static bool drm_edid_is_valid(struct edid *edid) 5223 { 5224 int i; 5225 u8 *raw = (u8 *)edid; 5226 5227 if (!edid) 5228 return false; 5229 5230 for (i = 0; i <= edid->extensions; i++) 5231 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 5232 return false; 5233 5234 return true; 5235 } 5236 5237 /** 5238 * drm_add_edid_modes - add modes from EDID data, if available 5239 * @data: data we're probing 5240 * @edid: EDID data 5241 * 5242 * Add the specified modes to the data's mode list. 5243 * 5244 * Return: The number of modes added or 0 if we couldn't find any. 5245 */ 5246 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 5247 { 5248 int num_modes = 0; 5249 u32 quirks; 5250 struct edid *edid = (struct edid *)raw_edid; 5251 5252 if (!edid) { 5253 debug("no edid\n"); 5254 return 0; 5255 } 5256 5257 if (!drm_edid_is_valid(edid)) { 5258 debug("EDID invalid\n"); 5259 return 0; 5260 } 5261 5262 if (!data->mode_buf) { 5263 debug("mode buff is null\n"); 5264 return 0; 5265 } 5266 5267 quirks = edid_get_quirks(edid); 5268 /* 5269 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5270 * To avoid multiple parsing of same block, lets parse that map 5271 * from sink info, before parsing CEA modes. 5272 */ 5273 drm_add_display_info(data, edid); 5274 5275 /* 5276 * EDID spec says modes should be preferred in this order: 5277 * - preferred detailed mode 5278 * - other detailed modes from base block 5279 * - detailed modes from extension blocks 5280 * - CVT 3-byte code modes 5281 * - standard timing codes 5282 * - established timing codes 5283 * - modes inferred from GTF or CVT range information 5284 * 5285 * We get this pretty much right. 5286 * 5287 * XXX order for additional mode types in extension blocks? 5288 */ 5289 num_modes += add_detailed_modes(data, edid, quirks); 5290 num_modes += add_cvt_modes(data, edid); 5291 num_modes += add_standard_modes(data, edid); 5292 num_modes += add_established_modes(data, edid); 5293 num_modes += add_cea_modes(data, edid); 5294 num_modes += add_alternate_cea_modes(data, edid); 5295 num_modes += add_displayid_detailed_modes(data, edid); 5296 5297 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5298 num_modes += add_inferred_modes(data, edid); 5299 5300 if (num_modes > 0) 5301 data->preferred_mode = &data->mode_buf[0]; 5302 5303 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5304 edid_fixup_preferred(data, quirks); 5305 5306 if (quirks & EDID_QUIRK_FORCE_6BPC) 5307 data->display_info.bpc = 6; 5308 5309 if (quirks & EDID_QUIRK_FORCE_8BPC) 5310 data->display_info.bpc = 8; 5311 5312 if (quirks & EDID_QUIRK_FORCE_10BPC) 5313 data->display_info.bpc = 10; 5314 5315 if (quirks & EDID_QUIRK_FORCE_12BPC) 5316 data->display_info.bpc = 12; 5317 5318 return num_modes; 5319 } 5320 5321 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5322 { 5323 u8 vic; 5324 5325 if (!to_match->clock) { 5326 printf("can't find to match\n"); 5327 return 0; 5328 } 5329 5330 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 5331 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 5332 unsigned int clock1, clock2; 5333 5334 /* Check both 60Hz and 59.94Hz */ 5335 clock1 = cea_mode->clock; 5336 clock2 = cea_mode_alternate_clock(cea_mode); 5337 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5338 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5339 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5340 return vic; 5341 } 5342 5343 return 0; 5344 } 5345 5346 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5347 { 5348 return edid_cea_modes[video_code].picture_aspect_ratio; 5349 } 5350 5351 int 5352 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5353 struct drm_display_mode *mode, 5354 bool is_hdmi2_sink) 5355 { 5356 int err; 5357 5358 if (!frame || !mode) 5359 return -EINVAL; 5360 5361 err = hdmi_avi_infoframe_init(frame); 5362 if (err < 0) 5363 return err; 5364 5365 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5366 frame->pixel_repeat = 1; 5367 5368 frame->video_code = drm_match_cea_mode(mode); 5369 5370 /* 5371 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5372 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5373 * have to make sure we dont break HDMI 1.4 sinks. 5374 */ 5375 if (!is_hdmi2_sink && frame->video_code > 64) 5376 frame->video_code = 0; 5377 5378 /* 5379 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5380 * we should send its VIC in vendor infoframes, else send the 5381 * VIC in AVI infoframes. Lets check if this mode is present in 5382 * HDMI 1.4b 4K modes 5383 */ 5384 if (frame->video_code) { 5385 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5386 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5387 5388 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5389 frame->video_code = 0; 5390 } 5391 5392 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5393 5394 /* 5395 * Populate picture aspect ratio from either 5396 * user input (if specified) or from the CEA mode list. 5397 */ 5398 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5399 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5400 frame->picture_aspect = mode->picture_aspect_ratio; 5401 else if (frame->video_code > 0) 5402 frame->picture_aspect = drm_get_cea_aspect_ratio( 5403 frame->video_code); 5404 5405 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5406 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5407 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5408 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5409 5410 return 0; 5411 } 5412 5413 /** 5414 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5415 * @frame: HDMI vendor infoframe 5416 * 5417 * Returns 0 on success or a negative error code on failure. 5418 */ 5419 int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5420 { 5421 memset(frame, 0, sizeof(*frame)); 5422 5423 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5424 frame->version = 1; 5425 5426 frame->oui = HDMI_IEEE_OUI; 5427 5428 /* 5429 * 0 is a valid value for s3d_struct, so we use a special "not set" 5430 * value 5431 */ 5432 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5433 5434 return 0; 5435 } 5436 5437 /** 5438 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5439 * quantization range information 5440 * @frame: HDMI AVI infoframe 5441 * @rgb_quant_range: RGB quantization range (Q) 5442 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 5443 */ 5444 void 5445 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5446 struct drm_display_mode *mode, 5447 enum hdmi_quantization_range rgb_quant_range, 5448 bool rgb_quant_range_selectable) 5449 { 5450 /* 5451 * CEA-861: 5452 * "A Source shall not send a non-zero Q value that does not correspond 5453 * to the default RGB Quantization Range for the transmitted Picture 5454 * unless the Sink indicates support for the Q bit in a Video 5455 * Capabilities Data Block." 5456 * 5457 * HDMI 2.0 recommends sending non-zero Q when it does match the 5458 * default RGB quantization range for the mode, even when QS=0. 5459 */ 5460 if (rgb_quant_range_selectable || 5461 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5462 frame->quantization_range = rgb_quant_range; 5463 else 5464 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5465 5466 /* 5467 * CEA-861-F: 5468 * "When transmitting any RGB colorimetry, the Source should set the 5469 * YQ-field to match the RGB Quantization Range being transmitted 5470 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5471 * set YQ=1) and the Sink shall ignore the YQ-field." 5472 */ 5473 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5474 frame->ycc_quantization_range = 5475 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5476 else 5477 frame->ycc_quantization_range = 5478 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5479 } 5480 5481 static enum hdmi_3d_structure 5482 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5483 { 5484 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5485 5486 switch (layout) { 5487 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5488 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5489 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5490 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5491 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5492 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5493 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5494 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5495 case DRM_MODE_FLAG_3D_L_DEPTH: 5496 return HDMI_3D_STRUCTURE_L_DEPTH; 5497 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5498 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5499 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5500 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5501 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5502 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5503 default: 5504 return HDMI_3D_STRUCTURE_INVALID; 5505 } 5506 } 5507 5508 int 5509 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5510 struct drm_display_mode *mode) 5511 { 5512 int err; 5513 u32 s3d_flags; 5514 u8 vic; 5515 5516 if (!frame || !mode) 5517 return -EINVAL; 5518 5519 vic = drm_match_hdmi_mode(mode); 5520 5521 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5522 5523 if (!vic && !s3d_flags) 5524 return -EINVAL; 5525 5526 if (vic && s3d_flags) 5527 return -EINVAL; 5528 5529 err = hdmi_vendor_infoframe_init(frame); 5530 if (err < 0) 5531 return err; 5532 5533 if (vic) 5534 frame->vic = vic; 5535 else 5536 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5537 5538 return 0; 5539 } 5540 5541 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5542 { 5543 u8 csum = 0; 5544 size_t i; 5545 5546 /* compute checksum */ 5547 for (i = 0; i < size; i++) 5548 csum += ptr[i]; 5549 5550 return 256 - csum; 5551 } 5552 5553 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5554 { 5555 u8 *ptr = buffer; 5556 5557 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5558 } 5559 5560 /** 5561 * hdmi_avi_infoframe_init() - initialize an HDMI AVI infoframe 5562 * @frame: HDMI AVI infoframe 5563 * 5564 * Returns 0 on success or a negative error code on failure. 5565 */ 5566 int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5567 { 5568 memset(frame, 0, sizeof(*frame)); 5569 5570 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5571 frame->version = 2; 5572 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5573 5574 return 0; 5575 } 5576 EXPORT_SYMBOL(hdmi_avi_infoframe_init); 5577 5578 /** 5579 * hdmi_avi_infoframe_pack() - write HDMI AVI infoframe to binary buffer 5580 * @frame: HDMI AVI infoframe 5581 * @buffer: destination buffer 5582 * @size: size of buffer 5583 * 5584 * Packs the information contained in the @frame structure into a binary 5585 * representation that can be written into the corresponding controller 5586 * registers. Also computes the checksum as required by section 5.3.5 of 5587 * the HDMI 1.4 specification. 5588 * 5589 * Returns the number of bytes packed into the binary buffer or a negative 5590 * error code on failure. 5591 */ 5592 ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, 5593 size_t size) 5594 { 5595 u8 *ptr = buffer; 5596 size_t length; 5597 5598 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5599 5600 if (size < length) 5601 return -ENOSPC; 5602 5603 memset(buffer, 0, size); 5604 5605 ptr[0] = frame->type; 5606 ptr[1] = frame->version; 5607 ptr[2] = frame->length; 5608 ptr[3] = 0; /* checksum */ 5609 5610 /* start infoframe payload */ 5611 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5612 5613 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 5614 5615 /* 5616 * Data byte 1, bit 4 has to be set if we provide the active format 5617 * aspect ratio 5618 */ 5619 if (frame->active_aspect & 0xf) 5620 ptr[0] |= BIT(4); 5621 5622 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 5623 if (frame->top_bar || frame->bottom_bar) 5624 ptr[0] |= BIT(3); 5625 5626 if (frame->left_bar || frame->right_bar) 5627 ptr[0] |= BIT(2); 5628 5629 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 5630 ((frame->picture_aspect & 0x3) << 4) | 5631 (frame->active_aspect & 0xf); 5632 5633 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 5634 ((frame->quantization_range & 0x3) << 2) | 5635 (frame->nups & 0x3); 5636 5637 if (frame->itc) 5638 ptr[2] |= BIT(7); 5639 5640 ptr[3] = frame->video_code & 0x7f; 5641 5642 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 5643 ((frame->content_type & 0x3) << 4) | 5644 (frame->pixel_repeat & 0xf); 5645 5646 ptr[5] = frame->top_bar & 0xff; 5647 ptr[6] = (frame->top_bar >> 8) & 0xff; 5648 ptr[7] = frame->bottom_bar & 0xff; 5649 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 5650 ptr[9] = frame->left_bar & 0xff; 5651 ptr[10] = (frame->left_bar >> 8) & 0xff; 5652 ptr[11] = frame->right_bar & 0xff; 5653 ptr[12] = (frame->right_bar >> 8) & 0xff; 5654 5655 hdmi_infoframe_set_checksum(buffer, length); 5656 5657 return length; 5658 } 5659 EXPORT_SYMBOL(hdmi_avi_infoframe_pack); 5660 5661 static int hdmi_avi_infoframe_check_only(const struct hdmi_avi_infoframe *frame) 5662 { 5663 if (frame->type != HDMI_INFOFRAME_TYPE_AVI || 5664 frame->version != 2 || 5665 frame->length != HDMI_AVI_INFOFRAME_SIZE) 5666 return -EINVAL; 5667 5668 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5669 return -EINVAL; 5670 5671 return 0; 5672 } 5673 5674 /** 5675 * hdmi_avi_infoframe_check() - check a HDMI AVI infoframe 5676 * @frame: HDMI AVI infoframe 5677 * 5678 * Validates that the infoframe is consistent and updates derived fields 5679 * (eg. length) based on other fields. 5680 * 5681 * Returns 0 on success or a negative error code on failure. 5682 */ 5683 int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame) 5684 { 5685 return hdmi_avi_infoframe_check_only(frame); 5686 } 5687 EXPORT_SYMBOL(hdmi_avi_infoframe_check); 5688 5689 /** 5690 * hdmi_avi_infoframe_pack_only() - write HDMI AVI infoframe to binary buffer 5691 * @frame: HDMI AVI infoframe 5692 * @buffer: destination buffer 5693 * @size: size of buffer 5694 * 5695 * Packs the information contained in the @frame structure into a binary 5696 * representation that can be written into the corresponding controller 5697 * registers. Also computes the checksum as required by section 5.3.5 of 5698 * the HDMI 1.4 specification. 5699 * 5700 * Returns the number of bytes packed into the binary buffer or a negative 5701 * error code on failure. 5702 */ 5703 ssize_t hdmi_avi_infoframe_pack_only(const struct hdmi_avi_infoframe *frame, 5704 void *buffer, size_t size) 5705 { 5706 u8 *ptr = buffer; 5707 size_t length; 5708 int ret; 5709 5710 ret = hdmi_avi_infoframe_check_only(frame); 5711 if (ret) 5712 return ret; 5713 5714 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5715 5716 if (size < length) 5717 return -ENOSPC; 5718 5719 memset(buffer, 0, size); 5720 5721 ptr[0] = frame->type; 5722 ptr[1] = frame->version; 5723 ptr[2] = frame->length; 5724 ptr[3] = 0; /* checksum */ 5725 5726 /* start infoframe payload */ 5727 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5728 5729 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 5730 5731 /* 5732 * Data byte 1, bit 4 has to be set if we provide the active format 5733 * aspect ratio 5734 */ 5735 if (frame->active_aspect & 0xf) 5736 ptr[0] |= BIT(4); 5737 5738 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 5739 if (frame->top_bar || frame->bottom_bar) 5740 ptr[0] |= BIT(3); 5741 5742 if (frame->left_bar || frame->right_bar) 5743 ptr[0] |= BIT(2); 5744 5745 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 5746 ((frame->picture_aspect & 0x3) << 4) | 5747 (frame->active_aspect & 0xf); 5748 5749 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 5750 ((frame->quantization_range & 0x3) << 2) | 5751 (frame->nups & 0x3); 5752 5753 if (frame->itc) 5754 ptr[2] |= BIT(7); 5755 5756 ptr[3] = frame->video_code & 0xff; 5757 5758 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 5759 ((frame->content_type & 0x3) << 4) | 5760 (frame->pixel_repeat & 0xf); 5761 5762 ptr[5] = frame->top_bar & 0xff; 5763 ptr[6] = (frame->top_bar >> 8) & 0xff; 5764 ptr[7] = frame->bottom_bar & 0xff; 5765 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 5766 ptr[9] = frame->left_bar & 0xff; 5767 ptr[10] = (frame->left_bar >> 8) & 0xff; 5768 ptr[11] = frame->right_bar & 0xff; 5769 ptr[12] = (frame->right_bar >> 8) & 0xff; 5770 5771 hdmi_infoframe_set_checksum(buffer, length); 5772 5773 return length; 5774 } 5775 EXPORT_SYMBOL(hdmi_avi_infoframe_pack_only); 5776 5777 /** 5778 * hdmi_spd_infoframe_init() - initialize an HDMI SPD infoframe 5779 * @frame: HDMI SPD infoframe 5780 * @vendor: vendor string 5781 * @product: product string 5782 * 5783 * Returns 0 on success or a negative error code on failure. 5784 */ 5785 int hdmi_spd_infoframe_init(struct hdmi_spd_infoframe *frame, 5786 const char *vendor, const char *product) 5787 { 5788 memset(frame, 0, sizeof(*frame)); 5789 5790 frame->type = HDMI_INFOFRAME_TYPE_SPD; 5791 frame->version = 1; 5792 frame->length = HDMI_SPD_INFOFRAME_SIZE; 5793 5794 strncpy(frame->vendor, vendor, sizeof(frame->vendor)); 5795 strncpy(frame->product, product, sizeof(frame->product)); 5796 5797 return 0; 5798 } 5799 EXPORT_SYMBOL(hdmi_spd_infoframe_init); 5800 5801 /** 5802 * hdmi_spd_infoframe_pack() - write HDMI SPD infoframe to binary buffer 5803 * @frame: HDMI SPD infoframe 5804 * @buffer: destination buffer 5805 * @size: size of buffer 5806 * 5807 * Packs the information contained in the @frame structure into a binary 5808 * representation that can be written into the corresponding controller 5809 * registers. Also computes the checksum as required by section 5.3.5 of 5810 * the HDMI 1.4 specification. 5811 * 5812 * Returns the number of bytes packed into the binary buffer or a negative 5813 * error code on failure. 5814 */ 5815 ssize_t hdmi_spd_infoframe_pack(struct hdmi_spd_infoframe *frame, void *buffer, 5816 size_t size) 5817 { 5818 u8 *ptr = buffer; 5819 size_t length; 5820 5821 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5822 5823 if (size < length) 5824 return -ENOSPC; 5825 5826 memset(buffer, 0, size); 5827 5828 ptr[0] = frame->type; 5829 ptr[1] = frame->version; 5830 ptr[2] = frame->length; 5831 ptr[3] = 0; /* checksum */ 5832 5833 /* start infoframe payload */ 5834 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5835 5836 memcpy(ptr, frame->vendor, sizeof(frame->vendor)); 5837 memcpy(ptr + 8, frame->product, sizeof(frame->product)); 5838 5839 ptr[24] = frame->sdi; 5840 5841 hdmi_infoframe_set_checksum(buffer, length); 5842 5843 return length; 5844 } 5845 EXPORT_SYMBOL(hdmi_spd_infoframe_pack); 5846 5847 /** 5848 * hdmi_audio_infoframe_init() - initialize an HDMI audio infoframe 5849 * @frame: HDMI audio infoframe 5850 * 5851 * Returns 0 on success or a negative error code on failure. 5852 */ 5853 int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame) 5854 { 5855 memset(frame, 0, sizeof(*frame)); 5856 5857 frame->type = HDMI_INFOFRAME_TYPE_AUDIO; 5858 frame->version = 1; 5859 frame->length = HDMI_AUDIO_INFOFRAME_SIZE; 5860 5861 return 0; 5862 } 5863 5864 /** 5865 * hdmi_audio_infoframe_pack() - write HDMI audio infoframe to binary buffer 5866 * @frame: HDMI audio infoframe 5867 * @buffer: destination buffer 5868 * @size: size of buffer 5869 * 5870 * Packs the information contained in the @frame structure into a binary 5871 * representation that can be written into the corresponding controller 5872 * registers. Also computes the checksum as required by section 5.3.5 of 5873 * the HDMI 1.4 specification. 5874 * 5875 * Returns the number of bytes packed into the binary buffer or a negative 5876 * error code on failure. 5877 */ 5878 ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame, 5879 void *buffer, size_t size) 5880 { 5881 unsigned char channels; 5882 char *ptr = buffer; 5883 size_t length; 5884 5885 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5886 5887 if (size < length) 5888 return -ENOSPC; 5889 5890 memset(buffer, 0, size); 5891 5892 if (frame->channels >= 2) 5893 channels = frame->channels - 1; 5894 else 5895 channels = 0; 5896 5897 ptr[0] = frame->type; 5898 ptr[1] = frame->version; 5899 ptr[2] = frame->length; 5900 ptr[3] = 0; /* checksum */ 5901 5902 /* start infoframe payload */ 5903 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5904 5905 ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7); 5906 ptr[1] = ((frame->sample_frequency & 0x7) << 2) | 5907 (frame->sample_size & 0x3); 5908 ptr[2] = frame->coding_type_ext & 0x1f; 5909 ptr[3] = frame->channel_allocation; 5910 ptr[4] = (frame->level_shift_value & 0xf) << 3; 5911 5912 if (frame->downmix_inhibit) 5913 ptr[4] |= BIT(7); 5914 5915 hdmi_infoframe_set_checksum(buffer, length); 5916 5917 return length; 5918 } 5919 5920 /** 5921 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 5922 * @frame: HDMI infoframe 5923 * @buffer: destination buffer 5924 * @size: size of buffer 5925 * 5926 * Packs the information contained in the @frame structure into a binary 5927 * representation that can be written into the corresponding controller 5928 * registers. Also computes the checksum as required by section 5.3.5 of 5929 * the HDMI 1.4 specification. 5930 * 5931 * Returns the number of bytes packed into the binary buffer or a negative 5932 * error code on failure. 5933 */ 5934 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 5935 void *buffer, size_t size) 5936 { 5937 char *ptr = buffer; 5938 size_t length; 5939 5940 /* empty info frame */ 5941 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 5942 return -EINVAL; 5943 5944 /* only one of those can be supplied */ 5945 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 5946 return -EINVAL; 5947 5948 /* for side by side (half) we also need to provide 3D_Ext_Data */ 5949 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5950 frame->length = 6; 5951 else 5952 frame->length = 5; 5953 5954 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5955 5956 if (size < length) 5957 return -ENOSPC; 5958 5959 memset(buffer, 0, size); 5960 5961 ptr[0] = frame->type; 5962 ptr[1] = frame->version; 5963 ptr[2] = frame->length; 5964 ptr[3] = 0; /* checksum */ 5965 5966 /* HDMI OUI */ 5967 ptr[4] = 0x03; 5968 ptr[5] = 0x0c; 5969 ptr[6] = 0x00; 5970 5971 if (frame->vic) { 5972 ptr[7] = 0x1 << 5; /* video format */ 5973 ptr[8] = frame->vic; 5974 } else { 5975 ptr[7] = 0x2 << 5; /* video format */ 5976 ptr[8] = (frame->s3d_struct & 0xf) << 4; 5977 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5978 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 5979 } 5980 5981 hdmi_infoframe_set_checksum(buffer, length); 5982 5983 return length; 5984 } 5985 5986 /** 5987 * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and 5988 * mastering infoframe 5989 * @frame: HDMI DRM infoframe 5990 * 5991 * Returns 0 on success or a negative error code on failure. 5992 */ 5993 int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame) 5994 { 5995 memset(frame, 0, sizeof(*frame)); 5996 5997 frame->type = HDMI_INFOFRAME_TYPE_DRM; 5998 frame->version = 1; 5999 6000 return 0; 6001 } 6002 6003 /** 6004 * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer 6005 * @frame: HDMI DRM infoframe 6006 * @buffer: destination buffer 6007 * @size: size of buffer 6008 * 6009 * Packs the information contained in the @frame structure into a binary 6010 * representation that can be written into the corresponding controller 6011 * registers. Also computes the checksum as required by section 5.3.5 of 6012 * the HDMI 1.4 specification. 6013 * 6014 * Returns the number of bytes packed into the binary buffer or a negative 6015 * error code on failure. 6016 */ 6017 ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer, 6018 size_t size) 6019 { 6020 u8 *ptr = buffer; 6021 size_t length; 6022 6023 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6024 6025 if (size < length) 6026 return -ENOSPC; 6027 6028 memset(buffer, 0, size); 6029 6030 ptr[0] = frame->type; 6031 ptr[1] = frame->version; 6032 ptr[2] = frame->length; 6033 ptr[3] = 0; /* checksum */ 6034 6035 /* start infoframe payload */ 6036 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6037 6038 ptr[0] = frame->eotf; 6039 ptr[1] = frame->metadata_type; 6040 6041 ptr[2] = frame->display_primaries_x[0] & 0xff; 6042 ptr[3] = frame->display_primaries_x[0] >> 8; 6043 6044 ptr[4] = frame->display_primaries_x[1] & 0xff; 6045 ptr[5] = frame->display_primaries_x[1] >> 8; 6046 6047 ptr[6] = frame->display_primaries_x[2] & 0xff; 6048 ptr[7] = frame->display_primaries_x[2] >> 8; 6049 6050 ptr[9] = frame->display_primaries_y[0] & 0xff; 6051 ptr[10] = frame->display_primaries_y[0] >> 8; 6052 6053 ptr[11] = frame->display_primaries_y[1] & 0xff; 6054 ptr[12] = frame->display_primaries_y[1] >> 8; 6055 6056 ptr[13] = frame->display_primaries_y[2] & 0xff; 6057 ptr[14] = frame->display_primaries_y[2] >> 8; 6058 6059 ptr[15] = frame->white_point_x & 0xff; 6060 ptr[16] = frame->white_point_x >> 8; 6061 6062 ptr[17] = frame->white_point_y & 0xff; 6063 ptr[18] = frame->white_point_y >> 8; 6064 6065 ptr[19] = frame->max_mastering_display_luminance & 0xff; 6066 ptr[20] = frame->max_mastering_display_luminance >> 8; 6067 6068 ptr[21] = frame->min_mastering_display_luminance & 0xff; 6069 ptr[22] = frame->min_mastering_display_luminance >> 8; 6070 6071 ptr[23] = frame->max_cll & 0xff; 6072 ptr[24] = frame->max_cll >> 8; 6073 6074 ptr[25] = frame->max_fall & 0xff; 6075 ptr[26] = frame->max_fall >> 8; 6076 6077 hdmi_infoframe_set_checksum(buffer, length); 6078 6079 return length; 6080 } 6081 6082 /* 6083 * hdmi_vendor_any_infoframe_pack() - write a vendor infoframe to binary buffer 6084 */ 6085 static ssize_t 6086 hdmi_vendor_any_infoframe_pack(union hdmi_vendor_any_infoframe *frame, 6087 void *buffer, size_t size) 6088 { 6089 /* we only know about HDMI vendor infoframes */ 6090 if (frame->any.oui != HDMI_IEEE_OUI) 6091 return -EINVAL; 6092 6093 return hdmi_vendor_infoframe_pack(&frame->hdmi, buffer, size); 6094 } 6095 6096 /** 6097 * hdmi_infoframe_pack() - write a HDMI infoframe to binary buffer 6098 * @frame: HDMI infoframe 6099 * @buffer: destination buffer 6100 * @size: size of buffer 6101 * 6102 * Packs the information contained in the @frame structure into a binary 6103 * representation that can be written into the corresponding controller 6104 * registers. Also computes the checksum as required by section 5.3.5 of 6105 * the HDMI 1.4 specification. 6106 * 6107 * Returns the number of bytes packed into the binary buffer or a negative 6108 * error code on failure. 6109 */ 6110 ssize_t 6111 hdmi_infoframe_pack(union hdmi_infoframe *frame, void *buffer, size_t size) 6112 { 6113 ssize_t length; 6114 6115 switch (frame->any.type) { 6116 case HDMI_INFOFRAME_TYPE_AVI: 6117 length = hdmi_avi_infoframe_pack(&frame->avi, buffer, size); 6118 break; 6119 case HDMI_INFOFRAME_TYPE_DRM: 6120 length = hdmi_drm_infoframe_pack(&frame->drm, buffer, size); 6121 break; 6122 case HDMI_INFOFRAME_TYPE_SPD: 6123 length = hdmi_spd_infoframe_pack(&frame->spd, buffer, size); 6124 break; 6125 case HDMI_INFOFRAME_TYPE_AUDIO: 6126 length = hdmi_audio_infoframe_pack(&frame->audio, buffer, size); 6127 break; 6128 case HDMI_INFOFRAME_TYPE_VENDOR: 6129 length = hdmi_vendor_any_infoframe_pack(&frame->vendor, 6130 buffer, size); 6131 break; 6132 default: 6133 printf("Bad infoframe type %d\n", frame->any.type); 6134 length = -EINVAL; 6135 } 6136 6137 return length; 6138 } 6139 6140 /** 6141 * hdmi_avi_infoframe_unpack() - unpack binary buffer to a HDMI AVI infoframe 6142 * @buffer: source buffer 6143 * @frame: HDMI AVI infoframe 6144 * 6145 * Unpacks the information contained in binary @buffer into a structured 6146 * @frame of the HDMI Auxiliary Video (AVI) information frame. 6147 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6148 * specification. 6149 * 6150 * Returns 0 on success or a negative error code on failure. 6151 */ 6152 static int hdmi_avi_infoframe_unpack(struct hdmi_avi_infoframe *frame, 6153 void *buffer) 6154 { 6155 u8 *ptr = buffer; 6156 int ret; 6157 6158 if (ptr[0] != HDMI_INFOFRAME_TYPE_AVI || 6159 ptr[1] != 2 || 6160 ptr[2] != HDMI_AVI_INFOFRAME_SIZE) 6161 return -EINVAL; 6162 6163 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AVI)) != 0) 6164 return -EINVAL; 6165 6166 ret = hdmi_avi_infoframe_init(frame); 6167 if (ret) 6168 return ret; 6169 6170 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6171 6172 frame->colorspace = (ptr[0] >> 5) & 0x3; 6173 if (ptr[0] & 0x10) 6174 frame->active_aspect = ptr[1] & 0xf; 6175 if (ptr[0] & 0x8) { 6176 frame->top_bar = (ptr[5] << 8) + ptr[6]; 6177 frame->bottom_bar = (ptr[7] << 8) + ptr[8]; 6178 } 6179 if (ptr[0] & 0x4) { 6180 frame->left_bar = (ptr[9] << 8) + ptr[10]; 6181 frame->right_bar = (ptr[11] << 8) + ptr[12]; 6182 } 6183 frame->scan_mode = ptr[0] & 0x3; 6184 6185 frame->colorimetry = (ptr[1] >> 6) & 0x3; 6186 frame->picture_aspect = (ptr[1] >> 4) & 0x3; 6187 frame->active_aspect = ptr[1] & 0xf; 6188 6189 frame->itc = ptr[2] & 0x80 ? true : false; 6190 frame->extended_colorimetry = (ptr[2] >> 4) & 0x7; 6191 frame->quantization_range = (ptr[2] >> 2) & 0x3; 6192 frame->nups = ptr[2] & 0x3; 6193 6194 frame->video_code = ptr[3] & 0x7f; 6195 frame->ycc_quantization_range = (ptr[4] >> 6) & 0x3; 6196 frame->content_type = (ptr[4] >> 4) & 0x3; 6197 6198 frame->pixel_repeat = ptr[4] & 0xf; 6199 6200 return 0; 6201 } 6202 6203 /** 6204 * hdmi_spd_infoframe_unpack() - unpack binary buffer to a HDMI SPD infoframe 6205 * @buffer: source buffer 6206 * @frame: HDMI SPD infoframe 6207 * 6208 * Unpacks the information contained in binary @buffer into a structured 6209 * @frame of the HDMI Source Product Description (SPD) information frame. 6210 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6211 * specification. 6212 * 6213 * Returns 0 on success or a negative error code on failure. 6214 */ 6215 static int hdmi_spd_infoframe_unpack(struct hdmi_spd_infoframe *frame, 6216 void *buffer) 6217 { 6218 char *ptr = buffer; 6219 int ret; 6220 6221 if (ptr[0] != HDMI_INFOFRAME_TYPE_SPD || 6222 ptr[1] != 1 || 6223 ptr[2] != HDMI_SPD_INFOFRAME_SIZE) { 6224 return -EINVAL; 6225 } 6226 6227 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(SPD)) != 0) 6228 return -EINVAL; 6229 6230 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6231 6232 ret = hdmi_spd_infoframe_init(frame, ptr, ptr + 8); 6233 if (ret) 6234 return ret; 6235 6236 frame->sdi = ptr[24]; 6237 6238 return 0; 6239 } 6240 6241 /** 6242 * hdmi_audio_infoframe_unpack() - unpack binary buffer to a HDMI AUDIO infoframe 6243 * @buffer: source buffer 6244 * @frame: HDMI Audio infoframe 6245 * 6246 * Unpacks the information contained in binary @buffer into a structured 6247 * @frame of the HDMI Audio information frame. 6248 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6249 * specification. 6250 * 6251 * Returns 0 on success or a negative error code on failure. 6252 */ 6253 static int hdmi_audio_infoframe_unpack(struct hdmi_audio_infoframe *frame, 6254 void *buffer) 6255 { 6256 u8 *ptr = buffer; 6257 int ret; 6258 6259 if (ptr[0] != HDMI_INFOFRAME_TYPE_AUDIO || 6260 ptr[1] != 1 || 6261 ptr[2] != HDMI_AUDIO_INFOFRAME_SIZE) { 6262 return -EINVAL; 6263 } 6264 6265 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AUDIO)) != 0) 6266 return -EINVAL; 6267 6268 ret = hdmi_audio_infoframe_init(frame); 6269 if (ret) 6270 return ret; 6271 6272 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6273 6274 frame->channels = ptr[0] & 0x7; 6275 frame->coding_type = (ptr[0] >> 4) & 0xf; 6276 frame->sample_size = ptr[1] & 0x3; 6277 frame->sample_frequency = (ptr[1] >> 2) & 0x7; 6278 frame->coding_type_ext = ptr[2] & 0x1f; 6279 frame->channel_allocation = ptr[3]; 6280 frame->level_shift_value = (ptr[4] >> 3) & 0xf; 6281 frame->downmix_inhibit = ptr[4] & 0x80 ? true : false; 6282 6283 return 0; 6284 } 6285 6286 /** 6287 * hdmi_vendor_infoframe_unpack() - unpack binary buffer to a HDMI vendor infoframe 6288 * @buffer: source buffer 6289 * @frame: HDMI Vendor infoframe 6290 * 6291 * Unpacks the information contained in binary @buffer into a structured 6292 * @frame of the HDMI Vendor information frame. 6293 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6294 * specification. 6295 * 6296 * Returns 0 on success or a negative error code on failure. 6297 */ 6298 static int 6299 hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame, 6300 void *buffer) 6301 { 6302 u8 *ptr = buffer; 6303 size_t length; 6304 int ret; 6305 u8 hdmi_video_format; 6306 struct hdmi_vendor_infoframe *hvf = &frame->hdmi; 6307 6308 if (ptr[0] != HDMI_INFOFRAME_TYPE_VENDOR || 6309 ptr[1] != 1 || 6310 (ptr[2] != 4 && ptr[2] != 5 && ptr[2] != 6)) 6311 return -EINVAL; 6312 6313 length = ptr[2]; 6314 6315 if (hdmi_infoframe_checksum(buffer, 6316 HDMI_INFOFRAME_HEADER_SIZE + length) != 0) 6317 return -EINVAL; 6318 6319 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6320 6321 /* HDMI OUI */ 6322 if (ptr[0] != 0x03 || 6323 ptr[1] != 0x0c || 6324 ptr[2] != 0x00) 6325 return -EINVAL; 6326 6327 hdmi_video_format = ptr[3] >> 5; 6328 6329 if (hdmi_video_format > 0x2) 6330 return -EINVAL; 6331 6332 ret = hdmi_vendor_infoframe_init(hvf); 6333 if (ret) 6334 return ret; 6335 6336 hvf->length = length; 6337 6338 if (hdmi_video_format == 0x2) { 6339 if (length != 5 && length != 6) 6340 return -EINVAL; 6341 hvf->s3d_struct = ptr[4] >> 4; 6342 if (hvf->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) { 6343 if (length != 6) 6344 return -EINVAL; 6345 hvf->s3d_ext_data = ptr[5] >> 4; 6346 } 6347 } else if (hdmi_video_format == 0x1) { 6348 if (length != 5) 6349 return -EINVAL; 6350 hvf->vic = ptr[4]; 6351 } else { 6352 if (length != 4) 6353 return -EINVAL; 6354 } 6355 6356 return 0; 6357 } 6358 6359 /** 6360 * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe 6361 * @buffer: source buffer 6362 * @frame: HDMI infoframe 6363 * 6364 * Unpacks the information contained in binary buffer @buffer into a structured 6365 * @frame of a HDMI infoframe. 6366 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6367 * specification. 6368 * 6369 * Returns 0 on success or a negative error code on failure. 6370 */ 6371 int hdmi_infoframe_unpack(union hdmi_infoframe *frame, void *buffer) 6372 { 6373 int ret; 6374 u8 *ptr = buffer; 6375 6376 switch (ptr[0]) { 6377 case HDMI_INFOFRAME_TYPE_AVI: 6378 ret = hdmi_avi_infoframe_unpack(&frame->avi, buffer); 6379 break; 6380 case HDMI_INFOFRAME_TYPE_SPD: 6381 ret = hdmi_spd_infoframe_unpack(&frame->spd, buffer); 6382 break; 6383 case HDMI_INFOFRAME_TYPE_AUDIO: 6384 ret = hdmi_audio_infoframe_unpack(&frame->audio, buffer); 6385 break; 6386 case HDMI_INFOFRAME_TYPE_VENDOR: 6387 ret = hdmi_vendor_any_infoframe_unpack(&frame->vendor, buffer); 6388 break; 6389 default: 6390 ret = -EINVAL; 6391 break; 6392 } 6393 6394 return ret; 6395 } 6396 6397 bool drm_mode_equal(const struct base_drm_display_mode *mode1, 6398 const struct drm_display_mode *mode2) 6399 { 6400 if (mode1->clock == mode2->clock && 6401 mode1->hdisplay == mode2->hdisplay && 6402 mode1->hsync_start == mode2->hsync_start && 6403 mode1->hsync_end == mode2->hsync_end && 6404 mode1->htotal == mode2->htotal && 6405 mode1->vdisplay == mode2->vdisplay && 6406 mode1->vsync_start == mode2->vsync_start && 6407 mode1->vsync_end == mode2->vsync_end && 6408 mode1->vtotal == mode2->vtotal && 6409 mode1->flags == mode2->flags) 6410 return true; 6411 6412 return false; 6413 } 6414 6415 /** 6416 * drm_mode_sort - sort mode list 6417 * @edid_data: modes structures to sort 6418 * 6419 * Sort @edid_data by favorability, moving good modes to the head of the list. 6420 */ 6421 void drm_mode_sort(struct hdmi_edid_data *edid_data) 6422 { 6423 struct drm_display_mode *a, *b; 6424 struct drm_display_mode c; 6425 int diff, i, j; 6426 6427 for (i = 0; i < (edid_data->modes - 1); i++) { 6428 a = &edid_data->mode_buf[i]; 6429 for (j = i + 1; j < edid_data->modes; j++) { 6430 b = &edid_data->mode_buf[j]; 6431 diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) - 6432 ((a->type & DRM_MODE_TYPE_PREFERRED) != 0); 6433 if (diff) { 6434 if (diff > 0) { 6435 c = *a; 6436 *a = *b; 6437 *b = c; 6438 } 6439 continue; 6440 } 6441 6442 diff = b->hdisplay * b->vdisplay 6443 - a->hdisplay * a->vdisplay; 6444 if (diff) { 6445 if (diff > 0) { 6446 c = *a; 6447 *a = *b; 6448 *b = c; 6449 } 6450 continue; 6451 } 6452 6453 diff = b->vrefresh - a->vrefresh; 6454 if (diff) { 6455 if (diff > 0) { 6456 c = *a; 6457 *a = *b; 6458 *b = c; 6459 } 6460 continue; 6461 } 6462 6463 diff = b->clock - a->clock; 6464 if (diff > 0) { 6465 c = *a; 6466 *a = *b; 6467 *b = c; 6468 } 6469 } 6470 } 6471 edid_data->preferred_mode = &edid_data->mode_buf[0]; 6472 } 6473 6474 /** 6475 * drm_mode_prune_invalid - remove invalid modes from mode list 6476 * @edid_data: structure store mode list 6477 * Returns: 6478 * Number of valid modes. 6479 */ 6480 int drm_mode_prune_invalid(struct hdmi_edid_data *edid_data) 6481 { 6482 int i, j; 6483 int num = edid_data->modes; 6484 int len = sizeof(struct drm_display_mode); 6485 struct drm_display_mode *mode_buf = edid_data->mode_buf; 6486 6487 for (i = 0; i < num; i++) { 6488 if (mode_buf[i].invalid) { 6489 /* If mode is invalid, delete it. */ 6490 for (j = i; j < num - 1; j++) 6491 memcpy(&mode_buf[j], &mode_buf[j + 1], len); 6492 6493 num--; 6494 i--; 6495 } 6496 } 6497 /* Clear redundant modes of mode_buf. */ 6498 memset(&mode_buf[num], 0, len * (edid_data->modes - num)); 6499 6500 edid_data->modes = num; 6501 return num; 6502 } 6503 6504 /** 6505 * drm_rk_filter_whitelist - mark modes out of white list from mode list 6506 * @edid_data: structure store mode list 6507 */ 6508 void drm_rk_filter_whitelist(struct hdmi_edid_data *edid_data) 6509 { 6510 int i, j, white_len; 6511 6512 if (sizeof(resolution_white)) { 6513 white_len = sizeof(resolution_white) / 6514 sizeof(resolution_white[0]); 6515 for (i = 0; i < edid_data->modes; i++) { 6516 for (j = 0; j < white_len; j++) { 6517 if (drm_mode_equal(&resolution_white[j], 6518 &edid_data->mode_buf[i])) 6519 break; 6520 } 6521 6522 if (j == white_len) 6523 edid_data->mode_buf[i].invalid = true; 6524 } 6525 } 6526 } 6527 6528 void drm_rk_select_mode(struct hdmi_edid_data *edid_data, 6529 struct base_screen_info *screen_info) 6530 { 6531 int i; 6532 const struct base_drm_display_mode *base_mode; 6533 6534 if (!screen_info) { 6535 /* define init resolution here */ 6536 } else { 6537 base_mode = &screen_info->mode; 6538 for (i = 0; i < edid_data->modes; i++) { 6539 if (drm_mode_equal(base_mode, 6540 &edid_data->mode_buf[i])) { 6541 edid_data->preferred_mode = 6542 &edid_data->mode_buf[i]; 6543 break; 6544 } 6545 } 6546 } 6547 } 6548 6549 /** 6550 * drm_do_probe_ddc_edid() - get EDID information via I2C 6551 * @adap: ddc adapter 6552 * @buf: EDID data buffer to be filled 6553 * @block: 128 byte EDID block to start fetching from 6554 * @len: EDID data buffer length to fetch 6555 * 6556 * Try to fetch EDID information by calling I2C driver functions. 6557 * 6558 * Return: 0 on success or -1 on failure. 6559 */ 6560 static int 6561 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 6562 size_t len) 6563 { 6564 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 6565 unsigned char segment = block >> 1; 6566 unsigned char xfers = segment ? 3 : 2; 6567 int ret, retries = 5; 6568 6569 do { 6570 struct i2c_msg msgs[] = { 6571 { 6572 .addr = DDC_SEGMENT_ADDR, 6573 .flags = 0, 6574 .len = 1, 6575 .buf = &segment, 6576 }, { 6577 .addr = DDC_ADDR, 6578 .flags = 0, 6579 .len = 1, 6580 .buf = &start, 6581 }, { 6582 .addr = DDC_ADDR, 6583 .flags = I2C_M_RD, 6584 .len = len, 6585 .buf = buf, 6586 } 6587 }; 6588 6589 if (adap->ops) { 6590 ret = adap->ops->xfer(adap->i2c_bus, &msgs[3 - xfers], 6591 xfers); 6592 if (!ret) 6593 ret = xfers; 6594 } else { 6595 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 6596 } 6597 } while (ret != xfers && --retries); 6598 6599 /* All msg transfer successfully. */ 6600 return ret == xfers ? 0 : -1; 6601 } 6602 6603 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid) 6604 { 6605 int i, j, block_num, block = 0; 6606 bool edid_corrupt; 6607 #ifdef DEBUG 6608 u8 *buff; 6609 #endif 6610 6611 /* base block fetch */ 6612 for (i = 0; i < 4; i++) { 6613 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 6614 goto err; 6615 if (drm_edid_block_valid(edid, 0, true, 6616 &edid_corrupt)) 6617 break; 6618 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 6619 printf("edid base block is 0, get edid failed\n"); 6620 goto err; 6621 } 6622 } 6623 6624 if (i == 4) 6625 goto err; 6626 6627 block++; 6628 /* get the number of extensions */ 6629 block_num = edid[0x7e]; 6630 6631 for (j = 1; j <= block_num; j++) { 6632 for (i = 0; i < 4; i++) { 6633 if (drm_do_probe_ddc_edid(adap, &edid[0x80 * j], j, 6634 HDMI_EDID_BLOCK_SIZE)) 6635 goto err; 6636 if (drm_edid_block_valid(&edid[0x80 * j], j, 6637 true, NULL)) 6638 break; 6639 } 6640 6641 if (i == 4) 6642 goto err; 6643 block++; 6644 } 6645 6646 #ifdef DEBUG 6647 printf("RAW EDID:\n"); 6648 for (i = 0; i < block_num + 1; i++) { 6649 buff = &edid[0x80 * i]; 6650 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 6651 if (j % 16 == 0) 6652 printf("\n"); 6653 printf("0x%02x, ", buff[j]); 6654 } 6655 printf("\n"); 6656 } 6657 #endif 6658 6659 return 0; 6660 6661 err: 6662 printf("can't get edid block:%d\n", block); 6663 /* clear all read edid block, include invalid block */ 6664 memset(edid, 0, HDMI_EDID_BLOCK_SIZE * (block + 1)); 6665 return -EFAULT; 6666 } 6667 6668 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 6669 void *buffer, size_t size) 6670 { 6671 struct i2c_msg msgs[2] = { 6672 { 6673 .addr = addr, 6674 .flags = 0, 6675 .len = 1, 6676 .buf = &offset, 6677 }, { 6678 .addr = addr, 6679 .flags = I2C_M_RD, 6680 .len = size, 6681 .buf = buffer, 6682 } 6683 }; 6684 6685 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 6686 } 6687 6688 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 6689 const void *buffer, size_t size) 6690 { 6691 struct i2c_msg msg = { 6692 .addr = addr, 6693 .flags = 0, 6694 .len = 1 + size, 6695 .buf = NULL, 6696 }; 6697 void *data; 6698 int err; 6699 6700 data = malloc(1 + size); 6701 if (!data) 6702 return -ENOMEM; 6703 6704 msg.buf = data; 6705 6706 memcpy(data, &offset, sizeof(offset)); 6707 memcpy(data + 1, buffer, size); 6708 6709 err = adap->ddc_xfer(adap, &msg, 1); 6710 6711 free(data); 6712 6713 return err; 6714 } 6715 6716 /** 6717 * drm_scdc_readb - read a single byte from SCDC 6718 * @adap: ddc adapter 6719 * @offset: offset of register to read 6720 * @value: return location for the register value 6721 * 6722 * Reads a single byte from SCDC. This is a convenience wrapper around the 6723 * drm_scdc_read() function. 6724 * 6725 * Returns: 6726 * 0 on success or a negative error code on failure. 6727 */ 6728 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 6729 u8 *value) 6730 { 6731 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 6732 sizeof(*value)); 6733 } 6734 6735 /** 6736 * drm_scdc_writeb - write a single byte to SCDC 6737 * @adap: ddc adapter 6738 * @offset: offset of register to read 6739 * @value: return location for the register value 6740 * 6741 * Writes a single byte to SCDC. This is a convenience wrapper around the 6742 * drm_scdc_write() function. 6743 * 6744 * Returns: 6745 * 0 on success or a negative error code on failure. 6746 */ 6747 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 6748 u8 value) 6749 { 6750 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 6751 sizeof(value)); 6752 } 6753 6754