1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <malloc.h> 22 #include <linux/compat.h> 23 #include <linux/ctype.h> 24 #include <linux/fb.h> 25 #include <linux/hdmi.h> 26 #include <linux/string.h> 27 28 #define EDID_EST_TIMINGS 16 29 #define EDID_STD_TIMINGS 8 30 #define EDID_DETAILED_TIMINGS 4 31 #define BITS_PER_LONG 64 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 u32 quirks; 78 int modes; 79 }; 80 81 #define LEVEL_DMT 0 82 #define LEVEL_GTF 1 83 #define LEVEL_GTF2 2 84 #define LEVEL_CVT 3 85 86 static struct edid_quirk { 87 char vendor[4]; 88 int product_id; 89 u32 quirks; 90 } edid_quirk_list[] = { 91 /* Acer AL1706 */ 92 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 93 /* Acer F51 */ 94 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 95 /* Unknown Acer */ 96 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 97 98 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 99 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 100 101 /* Belinea 10 15 55 */ 102 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 103 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 104 105 /* Envision Peripherals, Inc. EN-7100e */ 106 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 107 /* Envision EN2028 */ 108 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 109 110 /* Funai Electronics PM36B */ 111 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 112 EDID_QUIRK_DETAILED_IN_CM }, 113 114 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 115 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 116 117 /* LG Philips LCD LP154W01-A5 */ 118 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 119 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 121 /* Philips 107p5 CRT */ 122 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 123 124 /* Proview AY765C */ 125 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 126 127 /* Samsung SyncMaster 205BW. Note: irony */ 128 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 129 /* Samsung SyncMaster 22[5-6]BW */ 130 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 131 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 132 133 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 134 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 135 136 /* ViewSonic VA2026w */ 137 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 138 139 /* Medion MD 30217 PG */ 140 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 141 142 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 143 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 144 145 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 146 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 147 }; 148 149 /* 150 * Probably taken from CEA-861 spec. 151 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 152 * 153 * Index using the VIC. 154 */ 155 static const struct drm_display_mode edid_cea_modes[] = { 156 /* 0 - dummy, VICs start at 1 */ 157 { }, 158 /* 1 - 640x480@60Hz */ 159 { DRM_MODE(25175, 640, 656, 160 752, 800, 480, 490, 492, 525, 0, 161 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 162 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 163 /* 2 - 720x480@60Hz */ 164 { DRM_MODE(27000, 720, 736, 165 798, 858, 480, 489, 495, 525, 0, 166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 167 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 168 /* 3 - 720x480@60Hz */ 169 { DRM_MODE(27000, 720, 736, 170 798, 858, 480, 489, 495, 525, 0, 171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 172 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 173 /* 4 - 1280x720@60Hz */ 174 { DRM_MODE(74250, 1280, 1390, 175 1430, 1650, 720, 725, 730, 750, 0, 176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 177 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 178 /* 5 - 1920x1080i@60Hz */ 179 { DRM_MODE(74250, 1920, 2008, 180 2052, 2200, 1080, 1084, 1094, 1125, 0, 181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 182 DRM_MODE_FLAG_INTERLACE), 183 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 184 /* 6 - 720(1440)x480i@60Hz */ 185 { DRM_MODE(13500, 720, 739, 186 801, 858, 480, 488, 494, 525, 0, 187 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 188 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 189 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 190 /* 7 - 720(1440)x480i@60Hz */ 191 { DRM_MODE(13500, 720, 739, 192 801, 858, 480, 488, 494, 525, 0, 193 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 194 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 195 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 196 /* 8 - 720(1440)x240@60Hz */ 197 { DRM_MODE(13500, 720, 739, 198 801, 858, 240, 244, 247, 262, 0, 199 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 200 DRM_MODE_FLAG_DBLCLK), 201 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 202 /* 9 - 720(1440)x240@60Hz */ 203 { DRM_MODE(13500, 720, 739, 204 801, 858, 240, 244, 247, 262, 0, 205 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 206 DRM_MODE_FLAG_DBLCLK), 207 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 208 /* 10 - 2880x480i@60Hz */ 209 { DRM_MODE(54000, 2880, 2956, 210 3204, 3432, 480, 488, 494, 525, 0, 211 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 212 DRM_MODE_FLAG_INTERLACE), 213 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 214 /* 11 - 2880x480i@60Hz */ 215 { DRM_MODE(54000, 2880, 2956, 216 3204, 3432, 480, 488, 494, 525, 0, 217 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 218 DRM_MODE_FLAG_INTERLACE), 219 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 220 /* 12 - 2880x240@60Hz */ 221 { DRM_MODE(54000, 2880, 2956, 222 3204, 3432, 240, 244, 247, 262, 0, 223 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 224 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 225 /* 13 - 2880x240@60Hz */ 226 { DRM_MODE(54000, 2880, 2956, 227 3204, 3432, 240, 244, 247, 262, 0, 228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 229 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 230 /* 14 - 1440x480@60Hz */ 231 { DRM_MODE(54000, 1440, 1472, 232 1596, 1716, 480, 489, 495, 525, 0, 233 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 234 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 235 /* 15 - 1440x480@60Hz */ 236 { DRM_MODE(54000, 1440, 1472, 237 1596, 1716, 480, 489, 495, 525, 0, 238 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 239 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 240 /* 16 - 1920x1080@60Hz */ 241 { DRM_MODE(148500, 1920, 2008, 242 2052, 2200, 1080, 1084, 1089, 1125, 0, 243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 244 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 245 /* 17 - 720x576@50Hz */ 246 { DRM_MODE(27000, 720, 732, 247 796, 864, 576, 581, 586, 625, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 249 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 250 /* 18 - 720x576@50Hz */ 251 { DRM_MODE(27000, 720, 732, 252 796, 864, 576, 581, 586, 625, 0, 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 254 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 255 /* 19 - 1280x720@50Hz */ 256 { DRM_MODE(74250, 1280, 1720, 257 1760, 1980, 720, 725, 730, 750, 0, 258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 259 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 260 /* 20 - 1920x1080i@50Hz */ 261 { DRM_MODE(74250, 1920, 2448, 262 2492, 2640, 1080, 1084, 1094, 1125, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 264 DRM_MODE_FLAG_INTERLACE), 265 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 266 /* 21 - 720(1440)x576i@50Hz */ 267 { DRM_MODE(13500, 720, 732, 268 795, 864, 576, 580, 586, 625, 0, 269 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 270 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 271 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 272 /* 22 - 720(1440)x576i@50Hz */ 273 { DRM_MODE(13500, 720, 732, 274 795, 864, 576, 580, 586, 625, 0, 275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 276 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 277 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 278 /* 23 - 720(1440)x288@50Hz */ 279 { DRM_MODE(13500, 720, 732, 280 795, 864, 288, 290, 293, 312, 0, 281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 282 DRM_MODE_FLAG_DBLCLK), 283 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 284 /* 24 - 720(1440)x288@50Hz */ 285 { DRM_MODE(13500, 720, 732, 286 795, 864, 288, 290, 293, 312, 0, 287 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 288 DRM_MODE_FLAG_DBLCLK), 289 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 290 /* 25 - 2880x576i@50Hz */ 291 { DRM_MODE(54000, 2880, 2928, 292 3180, 3456, 576, 580, 586, 625, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 294 DRM_MODE_FLAG_INTERLACE), 295 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 296 /* 26 - 2880x576i@50Hz */ 297 { DRM_MODE(54000, 2880, 2928, 298 3180, 3456, 576, 580, 586, 625, 0, 299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 300 DRM_MODE_FLAG_INTERLACE), 301 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 302 /* 27 - 2880x288@50Hz */ 303 { DRM_MODE(54000, 2880, 2928, 304 3180, 3456, 288, 290, 293, 312, 0, 305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 306 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 307 /* 28 - 2880x288@50Hz */ 308 { DRM_MODE(54000, 2880, 2928, 309 3180, 3456, 288, 290, 293, 312, 0, 310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 311 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 312 /* 29 - 1440x576@50Hz */ 313 { DRM_MODE(54000, 1440, 1464, 314 1592, 1728, 576, 581, 586, 625, 0, 315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 316 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 317 /* 30 - 1440x576@50Hz */ 318 { DRM_MODE(54000, 1440, 1464, 319 1592, 1728, 576, 581, 586, 625, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 321 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 322 /* 31 - 1920x1080@50Hz */ 323 { DRM_MODE(148500, 1920, 2448, 324 2492, 2640, 1080, 1084, 1089, 1125, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 326 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 327 /* 32 - 1920x1080@24Hz */ 328 { DRM_MODE(74250, 1920, 2558, 329 2602, 2750, 1080, 1084, 1089, 1125, 0, 330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 331 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 332 /* 33 - 1920x1080@25Hz */ 333 { DRM_MODE(74250, 1920, 2448, 334 2492, 2640, 1080, 1084, 1089, 1125, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 336 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 337 /* 34 - 1920x1080@30Hz */ 338 { DRM_MODE(74250, 1920, 2008, 339 2052, 2200, 1080, 1084, 1089, 1125, 0, 340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 341 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 342 /* 35 - 2880x480@60Hz */ 343 { DRM_MODE(108000, 2880, 2944, 344 3192, 3432, 480, 489, 495, 525, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 346 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 347 /* 36 - 2880x480@60Hz */ 348 { DRM_MODE(108000, 2880, 2944, 349 3192, 3432, 480, 489, 495, 525, 0, 350 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 351 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 352 /* 37 - 2880x576@50Hz */ 353 { DRM_MODE(108000, 2880, 2928, 354 3184, 3456, 576, 581, 586, 625, 0, 355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 356 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 357 /* 38 - 2880x576@50Hz */ 358 { DRM_MODE(108000, 2880, 2928, 359 3184, 3456, 576, 581, 586, 625, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 361 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 362 /* 39 - 1920x1080i@50Hz */ 363 { DRM_MODE(72000, 1920, 1952, 364 2120, 2304, 1080, 1126, 1136, 1250, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 366 DRM_MODE_FLAG_INTERLACE), 367 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 368 /* 40 - 1920x1080i@100Hz */ 369 { DRM_MODE(148500, 1920, 2448, 370 2492, 2640, 1080, 1084, 1094, 1125, 0, 371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 372 DRM_MODE_FLAG_INTERLACE), 373 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 374 /* 41 - 1280x720@100Hz */ 375 { DRM_MODE(148500, 1280, 1720, 376 1760, 1980, 720, 725, 730, 750, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 378 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 379 /* 42 - 720x576@100Hz */ 380 { DRM_MODE(54000, 720, 732, 381 796, 864, 576, 581, 586, 625, 0, 382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 383 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 384 /* 43 - 720x576@100Hz */ 385 { DRM_MODE(54000, 720, 732, 386 796, 864, 576, 581, 586, 625, 0, 387 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 388 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 389 /* 44 - 720(1440)x576i@100Hz */ 390 { DRM_MODE(27000, 720, 732, 391 795, 864, 576, 580, 586, 625, 0, 392 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 393 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 394 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 395 /* 45 - 720(1440)x576i@100Hz */ 396 { DRM_MODE(27000, 720, 732, 397 795, 864, 576, 580, 586, 625, 0, 398 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 399 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 400 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 401 /* 46 - 1920x1080i@120Hz */ 402 { DRM_MODE(148500, 1920, 2008, 403 2052, 2200, 1080, 1084, 1094, 1125, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 405 DRM_MODE_FLAG_INTERLACE), 406 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 407 /* 47 - 1280x720@120Hz */ 408 { DRM_MODE(148500, 1280, 1390, 409 1430, 1650, 720, 725, 730, 750, 0, 410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 411 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 412 /* 48 - 720x480@120Hz */ 413 { DRM_MODE(54000, 720, 736, 414 798, 858, 480, 489, 495, 525, 0, 415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 416 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 417 /* 49 - 720x480@120Hz */ 418 { DRM_MODE(54000, 720, 736, 419 798, 858, 480, 489, 495, 525, 0, 420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 421 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 422 /* 50 - 720(1440)x480i@120Hz */ 423 { DRM_MODE(27000, 720, 739, 424 801, 858, 480, 488, 494, 525, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 426 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 427 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 428 /* 51 - 720(1440)x480i@120Hz */ 429 { DRM_MODE(27000, 720, 739, 430 801, 858, 480, 488, 494, 525, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 432 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 433 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 434 /* 52 - 720x576@200Hz */ 435 { DRM_MODE(108000, 720, 732, 436 796, 864, 576, 581, 586, 625, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 438 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 439 /* 53 - 720x576@200Hz */ 440 { DRM_MODE(108000, 720, 732, 441 796, 864, 576, 581, 586, 625, 0, 442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 443 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 444 /* 54 - 720(1440)x576i@200Hz */ 445 { DRM_MODE(54000, 720, 732, 446 795, 864, 576, 580, 586, 625, 0, 447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 448 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 449 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 450 /* 55 - 720(1440)x576i@200Hz */ 451 { DRM_MODE(54000, 720, 732, 452 795, 864, 576, 580, 586, 625, 0, 453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 454 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 455 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 456 /* 56 - 720x480@240Hz */ 457 { DRM_MODE(108000, 720, 736, 458 798, 858, 480, 489, 495, 525, 0, 459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 460 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 461 /* 57 - 720x480@240Hz */ 462 { DRM_MODE(108000, 720, 736, 463 798, 858, 480, 489, 495, 525, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 465 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 466 /* 58 - 720(1440)x480i@240 */ 467 { DRM_MODE(54000, 720, 739, 468 801, 858, 480, 488, 494, 525, 0, 469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 470 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 471 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 472 /* 59 - 720(1440)x480i@240 */ 473 { DRM_MODE(54000, 720, 739, 474 801, 858, 480, 488, 494, 525, 0, 475 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 476 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 477 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 478 /* 60 - 1280x720@24Hz */ 479 { DRM_MODE(59400, 1280, 3040, 480 3080, 3300, 720, 725, 730, 750, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 482 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 483 /* 61 - 1280x720@25Hz */ 484 { DRM_MODE(74250, 1280, 3700, 485 3740, 3960, 720, 725, 730, 750, 0, 486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 487 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 488 /* 62 - 1280x720@30Hz */ 489 { DRM_MODE(74250, 1280, 3040, 490 3080, 3300, 720, 725, 730, 750, 0, 491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 492 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 493 /* 63 - 1920x1080@120Hz */ 494 { DRM_MODE(297000, 1920, 2008, 495 2052, 2200, 1080, 1084, 1089, 1125, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 497 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 498 /* 64 - 1920x1080@100Hz */ 499 { DRM_MODE(297000, 1920, 2448, 500 2492, 2640, 1080, 1084, 1089, 1125, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 502 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 503 /* 65 - 1280x720@24Hz */ 504 { DRM_MODE(59400, 1280, 3040, 505 3080, 3300, 720, 725, 730, 750, 0, 506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 507 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 508 /* 66 - 1280x720@25Hz */ 509 { DRM_MODE(74250, 1280, 3700, 510 3740, 3960, 720, 725, 730, 750, 0, 511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 512 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 513 /* 67 - 1280x720@30Hz */ 514 { DRM_MODE(74250, 1280, 3040, 515 3080, 3300, 720, 725, 730, 750, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 517 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 518 /* 68 - 1280x720@50Hz */ 519 { DRM_MODE(74250, 1280, 1720, 520 1760, 1980, 720, 725, 730, 750, 0, 521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 522 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 523 /* 69 - 1280x720@60Hz */ 524 { DRM_MODE(74250, 1280, 1390, 525 1430, 1650, 720, 725, 730, 750, 0, 526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 527 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 528 /* 70 - 1280x720@100Hz */ 529 { DRM_MODE(148500, 1280, 1720, 530 1760, 1980, 720, 725, 730, 750, 0, 531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 532 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 533 /* 71 - 1280x720@120Hz */ 534 { DRM_MODE(148500, 1280, 1390, 535 1430, 1650, 720, 725, 730, 750, 0, 536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 537 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 538 /* 72 - 1920x1080@24Hz */ 539 { DRM_MODE(74250, 1920, 2558, 540 2602, 2750, 1080, 1084, 1089, 1125, 0, 541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 542 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 543 /* 73 - 1920x1080@25Hz */ 544 { DRM_MODE(74250, 1920, 2448, 545 2492, 2640, 1080, 1084, 1089, 1125, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 547 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 548 /* 74 - 1920x1080@30Hz */ 549 { DRM_MODE(74250, 1920, 2008, 550 2052, 2200, 1080, 1084, 1089, 1125, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 552 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 553 /* 75 - 1920x1080@50Hz */ 554 { DRM_MODE(148500, 1920, 2448, 555 2492, 2640, 1080, 1084, 1089, 1125, 0, 556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 557 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 558 /* 76 - 1920x1080@60Hz */ 559 { DRM_MODE(148500, 1920, 2008, 560 2052, 2200, 1080, 1084, 1089, 1125, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 562 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 563 /* 77 - 1920x1080@100Hz */ 564 { DRM_MODE(297000, 1920, 2448, 565 2492, 2640, 1080, 1084, 1089, 1125, 0, 566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 567 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 568 /* 78 - 1920x1080@120Hz */ 569 { DRM_MODE(297000, 1920, 2008, 570 2052, 2200, 1080, 1084, 1089, 1125, 0, 571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 572 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 573 /* 79 - 1680x720@24Hz */ 574 { DRM_MODE(59400, 1680, 3040, 575 3080, 3300, 720, 725, 730, 750, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 577 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 578 /* 80 - 1680x720@25Hz */ 579 { DRM_MODE(59400, 1680, 2908, 580 2948, 3168, 720, 725, 730, 750, 0, 581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 582 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 583 /* 81 - 1680x720@30Hz */ 584 { DRM_MODE(59400, 1680, 2380, 585 2420, 2640, 720, 725, 730, 750, 0, 586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 587 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 588 /* 82 - 1680x720@50Hz */ 589 { DRM_MODE(82500, 1680, 1940, 590 1980, 2200, 720, 725, 730, 750, 0, 591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 592 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 593 /* 83 - 1680x720@60Hz */ 594 { DRM_MODE(99000, 1680, 1940, 595 1980, 2200, 720, 725, 730, 750, 0, 596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 597 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 598 /* 84 - 1680x720@100Hz */ 599 { DRM_MODE(165000, 1680, 1740, 600 1780, 2000, 720, 725, 730, 825, 0, 601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 602 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 603 /* 85 - 1680x720@120Hz */ 604 { DRM_MODE(198000, 1680, 1740, 605 1780, 2000, 720, 725, 730, 825, 0, 606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 607 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 608 /* 86 - 2560x1080@24Hz */ 609 { DRM_MODE(99000, 2560, 3558, 610 3602, 3750, 1080, 1084, 1089, 1100, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 612 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 613 /* 87 - 2560x1080@25Hz */ 614 { DRM_MODE(90000, 2560, 3008, 615 3052, 3200, 1080, 1084, 1089, 1125, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 617 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 618 /* 88 - 2560x1080@30Hz */ 619 { DRM_MODE(118800, 2560, 3328, 620 3372, 3520, 1080, 1084, 1089, 1125, 0, 621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 622 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 623 /* 89 - 2560x1080@50Hz */ 624 { DRM_MODE(185625, 2560, 3108, 625 3152, 3300, 1080, 1084, 1089, 1125, 0, 626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 627 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 628 /* 90 - 2560x1080@60Hz */ 629 { DRM_MODE(198000, 2560, 2808, 630 2852, 3000, 1080, 1084, 1089, 1100, 0, 631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 632 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 633 /* 91 - 2560x1080@100Hz */ 634 { DRM_MODE(371250, 2560, 2778, 635 2822, 2970, 1080, 1084, 1089, 1250, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 637 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 638 /* 92 - 2560x1080@120Hz */ 639 { DRM_MODE(495000, 2560, 3108, 640 3152, 3300, 1080, 1084, 1089, 1250, 0, 641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 642 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 643 /* 93 - 3840x2160p@24Hz 16:9 */ 644 { DRM_MODE(297000, 3840, 5116, 645 5204, 5500, 2160, 2168, 2178, 2250, 0, 646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 647 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 648 /* 94 - 3840x2160p@25Hz 16:9 */ 649 { DRM_MODE(297000, 3840, 4896, 650 4984, 5280, 2160, 2168, 2178, 2250, 0, 651 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 652 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 653 /* 95 - 3840x2160p@30Hz 16:9 */ 654 { DRM_MODE(297000, 3840, 4016, 655 4104, 4400, 2160, 2168, 2178, 2250, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 657 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 658 /* 96 - 3840x2160p@50Hz 16:9 */ 659 { DRM_MODE(594000, 3840, 4896, 660 4984, 5280, 2160, 2168, 2178, 2250, 0, 661 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 662 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 663 /* 97 - 3840x2160p@60Hz 16:9 */ 664 { DRM_MODE(594000, 3840, 4016, 665 4104, 4400, 2160, 2168, 2178, 2250, 0, 666 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 667 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 668 /* 98 - 4096x2160p@24Hz 256:135 */ 669 { DRM_MODE(297000, 4096, 5116, 670 5204, 5500, 2160, 2168, 2178, 2250, 0, 671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 672 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 673 /* 99 - 4096x2160p@25Hz 256:135 */ 674 { DRM_MODE(297000, 4096, 5064, 675 5152, 5280, 2160, 2168, 2178, 2250, 0, 676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 677 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 678 /* 100 - 4096x2160p@30Hz 256:135 */ 679 { DRM_MODE(297000, 4096, 4184, 680 4272, 4400, 2160, 2168, 2178, 2250, 0, 681 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 682 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 683 /* 101 - 4096x2160p@50Hz 256:135 */ 684 { DRM_MODE(594000, 4096, 5064, 685 5152, 5280, 2160, 2168, 2178, 2250, 0, 686 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 687 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 688 /* 102 - 4096x2160p@60Hz 256:135 */ 689 { DRM_MODE(594000, 4096, 4184, 690 4272, 4400, 2160, 2168, 2178, 2250, 0, 691 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 692 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 693 /* 103 - 3840x2160p@24Hz 64:27 */ 694 { DRM_MODE(297000, 3840, 5116, 695 5204, 5500, 2160, 2168, 2178, 2250, 0, 696 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 697 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 698 /* 104 - 3840x2160p@25Hz 64:27 */ 699 { DRM_MODE(297000, 3840, 4016, 700 4104, 4400, 2160, 2168, 2178, 2250, 0, 701 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 702 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 703 /* 105 - 3840x2160p@30Hz 64:27 */ 704 { DRM_MODE(297000, 3840, 4016, 705 4104, 4400, 2160, 2168, 2178, 2250, 0, 706 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 707 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 708 /* 106 - 3840x2160p@50Hz 64:27 */ 709 { DRM_MODE(594000, 3840, 4896, 710 4984, 5280, 2160, 2168, 2178, 2250, 0, 711 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 712 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 713 /* 107 - 3840x2160p@60Hz 64:27 */ 714 { DRM_MODE(594000, 3840, 4016, 715 4104, 4400, 2160, 2168, 2178, 2250, 0, 716 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 717 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 718 }; 719 720 /* 721 * HDMI 1.4 4k modes. Index using the VIC. 722 */ 723 static const struct drm_display_mode edid_4k_modes[] = { 724 /* 0 - dummy, VICs start at 1 */ 725 { }, 726 /* 1 - 3840x2160@30Hz */ 727 { DRM_MODE(297000, 728 3840, 4016, 4104, 4400, 729 2160, 2168, 2178, 2250, 0, 730 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 731 .vrefresh = 30, }, 732 /* 2 - 3840x2160@25Hz */ 733 { DRM_MODE(297000, 734 3840, 4896, 4984, 5280, 735 2160, 2168, 2178, 2250, 0, 736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 737 .vrefresh = 25, }, 738 /* 3 - 3840x2160@24Hz */ 739 { DRM_MODE(297000, 740 3840, 5116, 5204, 5500, 741 2160, 2168, 2178, 2250, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 743 .vrefresh = 24, }, 744 /* 4 - 4096x2160@24Hz (SMPTE) */ 745 { DRM_MODE(297000, 746 4096, 5116, 5204, 5500, 747 2160, 2168, 2178, 2250, 0, 748 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 749 .vrefresh = 24, }, 750 }; 751 752 /* 753 * Autogenerated from the DMT spec. 754 * This table is copied from xfree86/modes/xf86EdidModes.c. 755 */ 756 static const struct drm_display_mode drm_dmt_modes[] = { 757 /* 0x01 - 640x350@85Hz */ 758 { DRM_MODE(31500, 640, 672, 759 736, 832, 350, 382, 385, 445, 0, 760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 761 /* 0x02 - 640x400@85Hz */ 762 { DRM_MODE(31500, 640, 672, 763 736, 832, 400, 401, 404, 445, 0, 764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 765 /* 0x03 - 720x400@85Hz */ 766 { DRM_MODE(35500, 720, 756, 767 828, 936, 400, 401, 404, 446, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 769 /* 0x04 - 640x480@60Hz */ 770 { DRM_MODE(25175, 640, 656, 771 752, 800, 480, 490, 492, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 773 /* 0x05 - 640x480@72Hz */ 774 { DRM_MODE(31500, 640, 664, 775 704, 832, 480, 489, 492, 520, 0, 776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 777 /* 0x06 - 640x480@75Hz */ 778 { DRM_MODE(31500, 640, 656, 779 720, 840, 480, 481, 484, 500, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 781 /* 0x07 - 640x480@85Hz */ 782 { DRM_MODE(36000, 640, 696, 783 752, 832, 480, 481, 484, 509, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 785 /* 0x08 - 800x600@56Hz */ 786 { DRM_MODE(36000, 800, 824, 787 896, 1024, 600, 601, 603, 625, 0, 788 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 789 /* 0x09 - 800x600@60Hz */ 790 { DRM_MODE(40000, 800, 840, 791 968, 1056, 600, 601, 605, 628, 0, 792 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 793 /* 0x0a - 800x600@72Hz */ 794 { DRM_MODE(50000, 800, 856, 795 976, 1040, 600, 637, 643, 666, 0, 796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 797 /* 0x0b - 800x600@75Hz */ 798 { DRM_MODE(49500, 800, 816, 799 896, 1056, 600, 601, 604, 625, 0, 800 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 801 /* 0x0c - 800x600@85Hz */ 802 { DRM_MODE(56250, 800, 832, 803 896, 1048, 600, 601, 604, 631, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 805 /* 0x0d - 800x600@120Hz RB */ 806 { DRM_MODE(73250, 800, 848, 807 880, 960, 600, 603, 607, 636, 0, 808 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 809 /* 0x0e - 848x480@60Hz */ 810 { DRM_MODE(33750, 848, 864, 811 976, 1088, 480, 486, 494, 517, 0, 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 813 /* 0x0f - 1024x768@43Hz, interlace */ 814 { DRM_MODE(44900, 1024, 1032, 815 1208, 1264, 768, 768, 772, 817, 0, 816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 817 DRM_MODE_FLAG_INTERLACE) }, 818 /* 0x10 - 1024x768@60Hz */ 819 { DRM_MODE(65000, 1024, 1048, 820 1184, 1344, 768, 771, 777, 806, 0, 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 822 /* 0x11 - 1024x768@70Hz */ 823 { DRM_MODE(75000, 1024, 1048, 824 1184, 1328, 768, 771, 777, 806, 0, 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 826 /* 0x12 - 1024x768@75Hz */ 827 { DRM_MODE(78750, 1024, 1040, 828 1136, 1312, 768, 769, 772, 800, 0, 829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 830 /* 0x13 - 1024x768@85Hz */ 831 { DRM_MODE(94500, 1024, 1072, 832 1168, 1376, 768, 769, 772, 808, 0, 833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 834 /* 0x14 - 1024x768@120Hz RB */ 835 { DRM_MODE(115500, 1024, 1072, 836 1104, 1184, 768, 771, 775, 813, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 838 /* 0x15 - 1152x864@75Hz */ 839 { DRM_MODE(108000, 1152, 1216, 840 1344, 1600, 864, 865, 868, 900, 0, 841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 842 /* 0x55 - 1280x720@60Hz */ 843 { DRM_MODE(74250, 1280, 1390, 844 1430, 1650, 720, 725, 730, 750, 0, 845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 846 /* 0x16 - 1280x768@60Hz RB */ 847 { DRM_MODE(68250, 1280, 1328, 848 1360, 1440, 768, 771, 778, 790, 0, 849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 850 /* 0x17 - 1280x768@60Hz */ 851 { DRM_MODE(79500, 1280, 1344, 852 1472, 1664, 768, 771, 778, 798, 0, 853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 854 /* 0x18 - 1280x768@75Hz */ 855 { DRM_MODE(102250, 1280, 1360, 856 1488, 1696, 768, 771, 778, 805, 0, 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 858 /* 0x19 - 1280x768@85Hz */ 859 { DRM_MODE(117500, 1280, 1360, 860 1496, 1712, 768, 771, 778, 809, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 862 /* 0x1a - 1280x768@120Hz RB */ 863 { DRM_MODE(140250, 1280, 1328, 864 1360, 1440, 768, 771, 778, 813, 0, 865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 866 /* 0x1b - 1280x800@60Hz RB */ 867 { DRM_MODE(71000, 1280, 1328, 868 1360, 1440, 800, 803, 809, 823, 0, 869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 870 /* 0x1c - 1280x800@60Hz */ 871 { DRM_MODE(83500, 1280, 1352, 872 1480, 1680, 800, 803, 809, 831, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 874 /* 0x1d - 1280x800@75Hz */ 875 { DRM_MODE(106500, 1280, 1360, 876 1488, 1696, 800, 803, 809, 838, 0, 877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 878 /* 0x1e - 1280x800@85Hz */ 879 { DRM_MODE(122500, 1280, 1360, 880 1496, 1712, 800, 803, 809, 843, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 882 /* 0x1f - 1280x800@120Hz RB */ 883 { DRM_MODE(146250, 1280, 1328, 884 1360, 1440, 800, 803, 809, 847, 0, 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 886 /* 0x20 - 1280x960@60Hz */ 887 { DRM_MODE(108000, 1280, 1376, 888 1488, 1800, 960, 961, 964, 1000, 0, 889 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 890 /* 0x21 - 1280x960@85Hz */ 891 { DRM_MODE(148500, 1280, 1344, 892 1504, 1728, 960, 961, 964, 1011, 0, 893 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 894 /* 0x22 - 1280x960@120Hz RB */ 895 { DRM_MODE(175500, 1280, 1328, 896 1360, 1440, 960, 963, 967, 1017, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 898 /* 0x23 - 1280x1024@60Hz */ 899 { DRM_MODE(108000, 1280, 1328, 900 1440, 1688, 1024, 1025, 1028, 1066, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 902 /* 0x24 - 1280x1024@75Hz */ 903 { DRM_MODE(135000, 1280, 1296, 904 1440, 1688, 1024, 1025, 1028, 1066, 0, 905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 906 /* 0x25 - 1280x1024@85Hz */ 907 { DRM_MODE(157500, 1280, 1344, 908 1504, 1728, 1024, 1025, 1028, 1072, 0, 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 910 /* 0x26 - 1280x1024@120Hz RB */ 911 { DRM_MODE(187250, 1280, 1328, 912 1360, 1440, 1024, 1027, 1034, 1084, 0, 913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 914 /* 0x27 - 1360x768@60Hz */ 915 { DRM_MODE(85500, 1360, 1424, 916 1536, 1792, 768, 771, 777, 795, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 918 /* 0x28 - 1360x768@120Hz RB */ 919 { DRM_MODE(148250, 1360, 1408, 920 1440, 1520, 768, 771, 776, 813, 0, 921 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 922 /* 0x51 - 1366x768@60Hz */ 923 { DRM_MODE(85500, 1366, 1436, 924 1579, 1792, 768, 771, 774, 798, 0, 925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 926 /* 0x56 - 1366x768@60Hz */ 927 { DRM_MODE(72000, 1366, 1380, 928 1436, 1500, 768, 769, 772, 800, 0, 929 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 930 /* 0x29 - 1400x1050@60Hz RB */ 931 { DRM_MODE(101000, 1400, 1448, 932 1480, 1560, 1050, 1053, 1057, 1080, 0, 933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 934 /* 0x2a - 1400x1050@60Hz */ 935 { DRM_MODE(121750, 1400, 1488, 936 1632, 1864, 1050, 1053, 1057, 1089, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 938 /* 0x2b - 1400x1050@75Hz */ 939 { DRM_MODE(156000, 1400, 1504, 940 1648, 1896, 1050, 1053, 1057, 1099, 0, 941 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 942 /* 0x2c - 1400x1050@85Hz */ 943 { DRM_MODE(179500, 1400, 1504, 944 1656, 1912, 1050, 1053, 1057, 1105, 0, 945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 946 /* 0x2d - 1400x1050@120Hz RB */ 947 { DRM_MODE(208000, 1400, 1448, 948 1480, 1560, 1050, 1053, 1057, 1112, 0, 949 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 950 /* 0x2e - 1440x900@60Hz RB */ 951 { DRM_MODE(88750, 1440, 1488, 952 1520, 1600, 900, 903, 909, 926, 0, 953 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 954 /* 0x2f - 1440x900@60Hz */ 955 { DRM_MODE(106500, 1440, 1520, 956 1672, 1904, 900, 903, 909, 934, 0, 957 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 958 /* 0x30 - 1440x900@75Hz */ 959 { DRM_MODE(136750, 1440, 1536, 960 1688, 1936, 900, 903, 909, 942, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 962 /* 0x31 - 1440x900@85Hz */ 963 { DRM_MODE(157000, 1440, 1544, 964 1696, 1952, 900, 903, 909, 948, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 966 /* 0x32 - 1440x900@120Hz RB */ 967 { DRM_MODE(182750, 1440, 1488, 968 1520, 1600, 900, 903, 909, 953, 0, 969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 970 /* 0x53 - 1600x900@60Hz */ 971 { DRM_MODE(108000, 1600, 1624, 972 1704, 1800, 900, 901, 904, 1000, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 974 /* 0x33 - 1600x1200@60Hz */ 975 { DRM_MODE(162000, 1600, 1664, 976 1856, 2160, 1200, 1201, 1204, 1250, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 978 /* 0x34 - 1600x1200@65Hz */ 979 { DRM_MODE(175500, 1600, 1664, 980 1856, 2160, 1200, 1201, 1204, 1250, 0, 981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 982 /* 0x35 - 1600x1200@70Hz */ 983 { DRM_MODE(189000, 1600, 1664, 984 1856, 2160, 1200, 1201, 1204, 1250, 0, 985 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 986 /* 0x36 - 1600x1200@75Hz */ 987 { DRM_MODE(202500, 1600, 1664, 988 1856, 2160, 1200, 1201, 1204, 1250, 0, 989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 990 /* 0x37 - 1600x1200@85Hz */ 991 { DRM_MODE(229500, 1600, 1664, 992 1856, 2160, 1200, 1201, 1204, 1250, 0, 993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 994 /* 0x38 - 1600x1200@120Hz RB */ 995 { DRM_MODE(268250, 1600, 1648, 996 1680, 1760, 1200, 1203, 1207, 1271, 0, 997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 998 /* 0x39 - 1680x1050@60Hz RB */ 999 { DRM_MODE(119000, 1680, 1728, 1000 1760, 1840, 1050, 1053, 1059, 1080, 0, 1001 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1002 /* 0x3a - 1680x1050@60Hz */ 1003 { DRM_MODE(146250, 1680, 1784, 1004 1960, 2240, 1050, 1053, 1059, 1089, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1006 /* 0x3b - 1680x1050@75Hz */ 1007 { DRM_MODE(187000, 1680, 1800, 1008 1976, 2272, 1050, 1053, 1059, 1099, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1010 /* 0x3c - 1680x1050@85Hz */ 1011 { DRM_MODE(214750, 1680, 1808, 1012 1984, 2288, 1050, 1053, 1059, 1105, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1014 /* 0x3d - 1680x1050@120Hz RB */ 1015 { DRM_MODE(245500, 1680, 1728, 1016 1760, 1840, 1050, 1053, 1059, 1112, 0, 1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1018 /* 0x3e - 1792x1344@60Hz */ 1019 { DRM_MODE(204750, 1792, 1920, 1020 2120, 2448, 1344, 1345, 1348, 1394, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1022 /* 0x3f - 1792x1344@75Hz */ 1023 { DRM_MODE(261000, 1792, 1888, 1024 2104, 2456, 1344, 1345, 1348, 1417, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1026 /* 0x40 - 1792x1344@120Hz RB */ 1027 { DRM_MODE(333250, 1792, 1840, 1028 1872, 1952, 1344, 1347, 1351, 1423, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1030 /* 0x41 - 1856x1392@60Hz */ 1031 { DRM_MODE(218250, 1856, 1952, 1032 2176, 2528, 1392, 1393, 1396, 1439, 0, 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1034 /* 0x42 - 1856x1392@75Hz */ 1035 { DRM_MODE(288000, 1856, 1984, 1036 2208, 2560, 1392, 1393, 1396, 1500, 0, 1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1038 /* 0x43 - 1856x1392@120Hz RB */ 1039 { DRM_MODE(356500, 1856, 1904, 1040 1936, 2016, 1392, 1395, 1399, 1474, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1042 /* 0x52 - 1920x1080@60Hz */ 1043 { DRM_MODE(148500, 1920, 2008, 1044 2052, 2200, 1080, 1084, 1089, 1125, 0, 1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1046 /* 0x44 - 1920x1200@60Hz RB */ 1047 { DRM_MODE(154000, 1920, 1968, 1048 2000, 2080, 1200, 1203, 1209, 1235, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1050 /* 0x45 - 1920x1200@60Hz */ 1051 { DRM_MODE(193250, 1920, 2056, 1052 2256, 2592, 1200, 1203, 1209, 1245, 0, 1053 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1054 /* 0x46 - 1920x1200@75Hz */ 1055 { DRM_MODE(245250, 1920, 2056, 1056 2264, 2608, 1200, 1203, 1209, 1255, 0, 1057 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1058 /* 0x47 - 1920x1200@85Hz */ 1059 { DRM_MODE(281250, 1920, 2064, 1060 2272, 2624, 1200, 1203, 1209, 1262, 0, 1061 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1062 /* 0x48 - 1920x1200@120Hz RB */ 1063 { DRM_MODE(317000, 1920, 1968, 1064 2000, 2080, 1200, 1203, 1209, 1271, 0, 1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1066 /* 0x49 - 1920x1440@60Hz */ 1067 { DRM_MODE(234000, 1920, 2048, 1068 2256, 2600, 1440, 1441, 1444, 1500, 0, 1069 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1070 /* 0x4a - 1920x1440@75Hz */ 1071 { DRM_MODE(297000, 1920, 2064, 1072 2288, 2640, 1440, 1441, 1444, 1500, 0, 1073 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1074 /* 0x4b - 1920x1440@120Hz RB */ 1075 { DRM_MODE(380500, 1920, 1968, 1076 2000, 2080, 1440, 1443, 1447, 1525, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1078 /* 0x54 - 2048x1152@60Hz */ 1079 { DRM_MODE(162000, 2048, 2074, 1080 2154, 2250, 1152, 1153, 1156, 1200, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1082 /* 0x4c - 2560x1600@60Hz RB */ 1083 { DRM_MODE(268500, 2560, 2608, 1084 2640, 2720, 1600, 1603, 1609, 1646, 0, 1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1086 /* 0x4d - 2560x1600@60Hz */ 1087 { DRM_MODE(348500, 2560, 2752, 1088 3032, 3504, 1600, 1603, 1609, 1658, 0, 1089 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1090 /* 0x4e - 2560x1600@75Hz */ 1091 { DRM_MODE(443250, 2560, 2768, 1092 3048, 3536, 1600, 1603, 1609, 1672, 0, 1093 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1094 /* 0x4f - 2560x1600@85Hz */ 1095 { DRM_MODE(505250, 2560, 2768, 1096 3048, 3536, 1600, 1603, 1609, 1682, 0, 1097 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1098 /* 0x50 - 2560x1600@120Hz RB */ 1099 { DRM_MODE(552750, 2560, 2608, 1100 2640, 2720, 1600, 1603, 1609, 1694, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1102 /* 0x57 - 4096x2160@60Hz RB */ 1103 { DRM_MODE(556744, 4096, 4104, 1104 4136, 4176, 2160, 2208, 2216, 2222, 0, 1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1106 /* 0x58 - 4096x2160@59.94Hz RB */ 1107 { DRM_MODE(556188, 4096, 4104, 1108 4136, 4176, 2160, 2208, 2216, 2222, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1110 }; 1111 1112 /* 1113 * These more or less come from the DMT spec. The 720x400 modes are 1114 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1115 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1116 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1117 * mode. 1118 * 1119 * The DMT modes have been fact-checked; the rest are mild guesses. 1120 */ 1121 static const struct drm_display_mode edid_est_modes[] = { 1122 /* 800x600@60Hz */ 1123 { DRM_MODE(40000, 800, 840, 1124 968, 1056, 600, 601, 605, 628, 0, 1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1126 /* 800x600@56Hz */ 1127 { DRM_MODE(36000, 800, 824, 1128 896, 1024, 600, 601, 603, 625, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1130 /* 640x480@75Hz */ 1131 { DRM_MODE(31500, 640, 656, 1132 720, 840, 480, 481, 484, 500, 0, 1133 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1134 /* 640x480@72Hz */ 1135 { DRM_MODE(31500, 640, 664, 1136 704, 832, 480, 489, 492, 520, 0, 1137 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1138 /* 640x480@67Hz */ 1139 { DRM_MODE(30240, 640, 704, 1140 768, 864, 480, 483, 486, 525, 0, 1141 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1142 /* 640x480@60Hz */ 1143 { DRM_MODE(25175, 640, 656, 1144 752, 800, 480, 490, 492, 525, 0, 1145 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1146 /* 720x400@88Hz */ 1147 { DRM_MODE(35500, 720, 738, 1148 846, 900, 400, 421, 423, 449, 0, 1149 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1150 /* 720x400@70Hz */ 1151 { DRM_MODE(28320, 720, 738, 1152 846, 900, 400, 412, 414, 449, 0, 1153 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1154 /* 1280x1024@75Hz */ 1155 { DRM_MODE(135000, 1280, 1296, 1156 1440, 1688, 1024, 1025, 1028, 1066, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1158 /* 1024x768@75Hz */ 1159 { DRM_MODE(78750, 1024, 1040, 1160 1136, 1312, 768, 769, 772, 800, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1162 /* 1024x768@70Hz */ 1163 { DRM_MODE(75000, 1024, 1048, 1164 1184, 1328, 768, 771, 777, 806, 0, 1165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1166 /* 1024x768@60Hz */ 1167 { DRM_MODE(65000, 1024, 1048, 1168 1184, 1344, 768, 771, 777, 806, 0, 1169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1170 /* 1024x768@43Hz */ 1171 { DRM_MODE(44900, 1024, 1032, 1172 1208, 1264, 768, 768, 776, 817, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1174 DRM_MODE_FLAG_INTERLACE) }, 1175 /* 832x624@75Hz */ 1176 { DRM_MODE(57284, 832, 864, 1177 928, 1152, 624, 625, 628, 667, 0, 1178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1179 /* 800x600@75Hz */ 1180 { DRM_MODE(49500, 800, 816, 1181 896, 1056, 600, 601, 604, 625, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1183 /* 800x600@72Hz */ 1184 { DRM_MODE(50000, 800, 856, 1185 976, 1040, 600, 637, 643, 666, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1187 /* 1152x864@75Hz */ 1188 { DRM_MODE(108000, 1152, 1216, 1189 1344, 1600, 864, 865, 868, 900, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1191 }; 1192 1193 struct minimode { 1194 short w; 1195 short h; 1196 short r; 1197 short rb; 1198 }; 1199 1200 static const struct minimode est3_modes[] = { 1201 /* byte 6 */ 1202 { 640, 350, 85, 0 }, 1203 { 640, 400, 85, 0 }, 1204 { 720, 400, 85, 0 }, 1205 { 640, 480, 85, 0 }, 1206 { 848, 480, 60, 0 }, 1207 { 800, 600, 85, 0 }, 1208 { 1024, 768, 85, 0 }, 1209 { 1152, 864, 75, 0 }, 1210 /* byte 7 */ 1211 { 1280, 768, 60, 1 }, 1212 { 1280, 768, 60, 0 }, 1213 { 1280, 768, 75, 0 }, 1214 { 1280, 768, 85, 0 }, 1215 { 1280, 960, 60, 0 }, 1216 { 1280, 960, 85, 0 }, 1217 { 1280, 1024, 60, 0 }, 1218 { 1280, 1024, 85, 0 }, 1219 /* byte 8 */ 1220 { 1360, 768, 60, 0 }, 1221 { 1440, 900, 60, 1 }, 1222 { 1440, 900, 60, 0 }, 1223 { 1440, 900, 75, 0 }, 1224 { 1440, 900, 85, 0 }, 1225 { 1400, 1050, 60, 1 }, 1226 { 1400, 1050, 60, 0 }, 1227 { 1400, 1050, 75, 0 }, 1228 /* byte 9 */ 1229 { 1400, 1050, 85, 0 }, 1230 { 1680, 1050, 60, 1 }, 1231 { 1680, 1050, 60, 0 }, 1232 { 1680, 1050, 75, 0 }, 1233 { 1680, 1050, 85, 0 }, 1234 { 1600, 1200, 60, 0 }, 1235 { 1600, 1200, 65, 0 }, 1236 { 1600, 1200, 70, 0 }, 1237 /* byte 10 */ 1238 { 1600, 1200, 75, 0 }, 1239 { 1600, 1200, 85, 0 }, 1240 { 1792, 1344, 60, 0 }, 1241 { 1792, 1344, 75, 0 }, 1242 { 1856, 1392, 60, 0 }, 1243 { 1856, 1392, 75, 0 }, 1244 { 1920, 1200, 60, 1 }, 1245 { 1920, 1200, 60, 0 }, 1246 /* byte 11 */ 1247 { 1920, 1200, 75, 0 }, 1248 { 1920, 1200, 85, 0 }, 1249 { 1920, 1440, 60, 0 }, 1250 { 1920, 1440, 75, 0 }, 1251 }; 1252 1253 static const struct minimode extra_modes[] = { 1254 { 1024, 576, 60, 0 }, 1255 { 1366, 768, 60, 0 }, 1256 { 1600, 900, 60, 0 }, 1257 { 1680, 945, 60, 0 }, 1258 { 1920, 1080, 60, 0 }, 1259 { 2048, 1152, 60, 0 }, 1260 { 2048, 1536, 60, 0 }, 1261 }; 1262 1263 int edid_check_info(struct edid1_info *edid_info) 1264 { 1265 if ((edid_info == NULL) || (edid_info->version == 0)) 1266 return -1; 1267 1268 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1269 return -1; 1270 1271 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1272 return -1; 1273 1274 return 0; 1275 } 1276 1277 int edid_check_checksum(u8 *edid_block) 1278 { 1279 u8 checksum = 0; 1280 int i; 1281 1282 for (i = 0; i < 128; i++) 1283 checksum += edid_block[i]; 1284 1285 return (checksum == 0) ? 0 : -EINVAL; 1286 } 1287 1288 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1289 unsigned int *hmax, unsigned int *vmin, 1290 unsigned int *vmax) 1291 { 1292 int i; 1293 struct edid_monitor_descriptor *monitor; 1294 1295 *hmin = *hmax = *vmin = *vmax = 0; 1296 if (edid_check_info(edid)) 1297 return -1; 1298 1299 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1300 monitor = &edid->monitor_details.descriptor[i]; 1301 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1302 *hmin = monitor->data.range_data.horizontal_min; 1303 *hmax = monitor->data.range_data.horizontal_max; 1304 *vmin = monitor->data.range_data.vertical_min; 1305 *vmax = monitor->data.range_data.vertical_max; 1306 return 0; 1307 } 1308 } 1309 return -1; 1310 } 1311 1312 /* Set all parts of a timing entry to the same value */ 1313 static void set_entry(struct timing_entry *entry, u32 value) 1314 { 1315 entry->min = value; 1316 entry->typ = value; 1317 entry->max = value; 1318 } 1319 1320 /** 1321 * decode_timing() - Decoding an 18-byte detailed timing record 1322 * 1323 * @buf: Pointer to EDID detailed timing record 1324 * @timing: Place to put timing 1325 */ 1326 static void decode_timing(u8 *buf, struct display_timing *timing) 1327 { 1328 uint x_mm, y_mm; 1329 unsigned int ha, hbl, hso, hspw, hborder; 1330 unsigned int va, vbl, vso, vspw, vborder; 1331 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1332 1333 /* Edid contains pixel clock in terms of 10KHz */ 1334 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1335 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1336 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1337 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1338 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1339 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1340 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1341 hborder = buf[15]; 1342 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1343 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1344 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1345 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1346 vborder = buf[16]; 1347 1348 set_entry(&timing->hactive, ha); 1349 set_entry(&timing->hfront_porch, hso); 1350 set_entry(&timing->hback_porch, hbl - hso - hspw); 1351 set_entry(&timing->hsync_len, hspw); 1352 1353 set_entry(&timing->vactive, va); 1354 set_entry(&timing->vfront_porch, vso); 1355 set_entry(&timing->vback_porch, vbl - vso - vspw); 1356 set_entry(&timing->vsync_len, vspw); 1357 1358 timing->flags = 0; 1359 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1360 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1361 else 1362 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1363 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1364 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1365 else 1366 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1367 1368 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1369 timing->flags = DISPLAY_FLAGS_INTERLACED; 1370 1371 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1372 " %04x %04x %04x %04x hborder %x\n" 1373 " %04x %04x %04x %04x vborder %x\n", 1374 timing->pixelclock.typ, 1375 x_mm, y_mm, 1376 ha, ha + hso, ha + hso + hspw, 1377 ha + hbl, hborder, 1378 va, va + vso, va + vso + vspw, 1379 va + vbl, vborder); 1380 } 1381 1382 /** 1383 * decode_mode() - Decoding an 18-byte detailed timing record 1384 * 1385 * @buf: Pointer to EDID detailed timing record 1386 * @timing: Place to put timing 1387 */ 1388 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1389 { 1390 uint x_mm, y_mm; 1391 unsigned int ha, hbl, hso, hspw, hborder; 1392 unsigned int va, vbl, vso, vspw, vborder; 1393 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1394 1395 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1396 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1397 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1398 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1399 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1400 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1401 hborder = buf[15]; 1402 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1403 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1404 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1405 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1406 vborder = buf[16]; 1407 1408 /* Edid contains pixel clock in terms of 10KHz */ 1409 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1410 mode->hdisplay = ha; 1411 mode->hsync_start = ha + hso; 1412 mode->hsync_end = ha + hso + hspw; 1413 mode->htotal = ha + hbl; 1414 mode->vdisplay = va; 1415 mode->vsync_start = va + vso; 1416 mode->vsync_end = va + vso + vspw; 1417 mode->vtotal = va + vbl; 1418 1419 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1420 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1421 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1422 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1423 1424 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1425 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1426 1427 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1428 " %04d %04d %04d %04d hborder %d\n" 1429 " %04d %04d %04d %04d vborder %d\n", 1430 mode->clock, 1431 x_mm, y_mm, mode->flags, 1432 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1433 mode->htotal, hborder, 1434 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1435 mode->vtotal, vborder); 1436 } 1437 1438 /** 1439 * edid_vendor - match a string against EDID's obfuscated vendor field 1440 * @edid: EDID to match 1441 * @vendor: vendor string 1442 * 1443 * Returns true if @vendor is in @edid, false otherwise 1444 */ 1445 static bool edid_vendor(struct edid1_info *edid, char *vendor) 1446 { 1447 char edid_vendor[3]; 1448 1449 edid_vendor[0] = ((edid->manufacturer_name[0] & 0x7c) >> 2) + '@'; 1450 edid_vendor[1] = (((edid->manufacturer_name[0] & 0x3) << 3) | 1451 ((edid->manufacturer_name[1] & 0xe0) >> 5)) + '@'; 1452 edid_vendor[2] = (edid->manufacturer_name[1] & 0x1f) + '@'; 1453 1454 return !strncmp(edid_vendor, vendor, 3); 1455 } 1456 1457 /** 1458 * Check if HDMI vendor specific data block is present in CEA block 1459 * @param info CEA extension block 1460 * @return true if block is found 1461 */ 1462 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1463 { 1464 u8 end, i = 0; 1465 1466 /* check for end of data block */ 1467 end = info->dtd_offset; 1468 if (end == 0) 1469 end = sizeof(info->data); 1470 if (end < 4 || end > sizeof(info->data)) 1471 return false; 1472 end -= 4; 1473 1474 while (i < end) { 1475 /* Look for vendor specific data block of appropriate size */ 1476 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1477 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1478 u8 *db = &info->data[i + 1]; 1479 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1480 1481 if (oui == HDMI_IEEE_OUI) 1482 return true; 1483 } 1484 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1485 } 1486 1487 return false; 1488 } 1489 1490 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1491 int *panel_bits_per_colourp) 1492 { 1493 struct edid1_info *edid = (struct edid1_info *)buf; 1494 bool timing_done; 1495 int i; 1496 1497 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1498 debug("%s: Invalid buffer\n", __func__); 1499 return -EINVAL; 1500 } 1501 1502 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1503 debug("%s: No preferred timing\n", __func__); 1504 return -ENOENT; 1505 } 1506 1507 /* Look for detailed timing */ 1508 timing_done = false; 1509 for (i = 0; i < 4; i++) { 1510 struct edid_monitor_descriptor *desc; 1511 1512 desc = &edid->monitor_details.descriptor[i]; 1513 if (desc->zero_flag_1 != 0) { 1514 decode_mode((u8 *)desc, mode); 1515 timing_done = true; 1516 break; 1517 } 1518 } 1519 if (!timing_done) 1520 return -EINVAL; 1521 1522 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1523 debug("%s: Not a digital display\n", __func__); 1524 return -ENOSYS; 1525 } 1526 if (edid->version != 1 || edid->revision < 4) { 1527 debug("%s: EDID version %d.%d does not have required info\n", 1528 __func__, edid->version, edid->revision); 1529 *panel_bits_per_colourp = -1; 1530 } else { 1531 *panel_bits_per_colourp = 1532 ((edid->video_input_definition & 0x70) >> 3) + 4; 1533 } 1534 1535 return 0; 1536 } 1537 1538 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 1539 int *panel_bits_per_colourp) 1540 { 1541 struct edid1_info *edid = (struct edid1_info *)buf; 1542 bool timing_done; 1543 int i; 1544 1545 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1546 debug("%s: Invalid buffer\n", __func__); 1547 return -EINVAL; 1548 } 1549 1550 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1551 debug("%s: No preferred timing\n", __func__); 1552 return -ENOENT; 1553 } 1554 1555 /* Look for detailed timing */ 1556 timing_done = false; 1557 for (i = 0; i < 4; i++) { 1558 struct edid_monitor_descriptor *desc; 1559 1560 desc = &edid->monitor_details.descriptor[i]; 1561 if (desc->zero_flag_1 != 0) { 1562 decode_timing((u8 *)desc, timing); 1563 timing_done = true; 1564 break; 1565 } 1566 } 1567 if (!timing_done) 1568 return -EINVAL; 1569 1570 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1571 debug("%s: Not a digital display\n", __func__); 1572 return -ENOSYS; 1573 } 1574 if (edid->version != 1 || edid->revision < 4) { 1575 debug("%s: EDID version %d.%d does not have required info\n", 1576 __func__, edid->version, edid->revision); 1577 *panel_bits_per_colourp = -1; 1578 } else { 1579 *panel_bits_per_colourp = 1580 ((edid->video_input_definition & 0x70) >> 3) + 4; 1581 } 1582 1583 timing->hdmi_monitor = false; 1584 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 1585 struct edid_cea861_info *info = 1586 (struct edid_cea861_info *)(buf + sizeof(*edid)); 1587 1588 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 1589 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 1590 } 1591 1592 return 0; 1593 } 1594 1595 /** 1596 * Snip the tailing whitespace/return of a string. 1597 * 1598 * @param string The string to be snipped 1599 * @return the snipped string 1600 */ 1601 static char *snip(char *string) 1602 { 1603 char *s; 1604 1605 /* 1606 * This is always a 13 character buffer 1607 * and it's not always terminated. 1608 */ 1609 string[12] = '\0'; 1610 s = &string[strlen(string) - 1]; 1611 1612 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 1613 *s == '\0')) 1614 *(s--) = '\0'; 1615 1616 return string; 1617 } 1618 1619 /** 1620 * Print an EDID monitor descriptor block 1621 * 1622 * @param monitor The EDID monitor descriptor block 1623 * @have_timing Modifies to 1 if the desciptor contains timing info 1624 */ 1625 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 1626 unsigned int *have_timing) 1627 { 1628 unsigned char *bytes = (unsigned char *)monitor; 1629 struct edid_detailed_timing *timing = 1630 (struct edid_detailed_timing *)monitor; 1631 1632 if (bytes[0] == 0 && bytes[1] == 0) { 1633 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 1634 printf("Monitor serial number: %s\n", 1635 snip(monitor->data.string)); 1636 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 1637 printf("Monitor ID: %s\n", 1638 snip(monitor->data.string)); 1639 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 1640 printf("Monitor name: %s\n", 1641 snip(monitor->data.string)); 1642 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 1643 printf("Monitor range limits, horizontal sync: " 1644 "%d-%d kHz, vertical refresh: " 1645 "%d-%d Hz, max pixel clock: " 1646 "%d MHz\n", 1647 monitor->data.range_data.horizontal_min, 1648 monitor->data.range_data.horizontal_max, 1649 monitor->data.range_data.vertical_min, 1650 monitor->data.range_data.vertical_max, 1651 monitor->data.range_data.pixel_clock_max * 10); 1652 } else { 1653 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 1654 u32 h_total, v_total, vfreq; 1655 1656 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 1657 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 1658 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 1659 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 1660 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 1661 1662 h_total = h_active + h_blanking; 1663 v_total = v_active + v_blanking; 1664 if (v_total > 0 && h_total > 0) 1665 vfreq = pixclock / (v_total * h_total); 1666 else 1667 vfreq = 1; /* Error case */ 1668 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 1669 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 1670 *have_timing = 1; 1671 } 1672 } 1673 1674 /** 1675 * Get the manufacturer name from an EDID info. 1676 * 1677 * @param edid_info The EDID info to be printed 1678 * @param name Returns the string of the manufacturer name 1679 */ 1680 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 1681 { 1682 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 1683 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 1684 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 1685 name[3] = '\0'; 1686 } 1687 1688 void edid_print_info(struct edid1_info *edid_info) 1689 { 1690 int i; 1691 char manufacturer[4]; 1692 unsigned int have_timing = 0; 1693 u32 serial_number; 1694 1695 if (edid_check_info(edid_info)) { 1696 printf("Not a valid EDID\n"); 1697 return; 1698 } 1699 1700 printf("EDID version: %d.%d\n", 1701 edid_info->version, edid_info->revision); 1702 1703 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 1704 1705 edid_get_manufacturer_name(edid_info, manufacturer); 1706 printf("Manufacturer: %s\n", manufacturer); 1707 1708 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 1709 if (serial_number != 0xffffffff) { 1710 if (strcmp(manufacturer, "MAG") == 0) 1711 serial_number -= 0x7000000; 1712 if (strcmp(manufacturer, "OQI") == 0) 1713 serial_number -= 456150000; 1714 if (strcmp(manufacturer, "VSC") == 0) 1715 serial_number -= 640000000; 1716 } 1717 printf("Serial number: %08x\n", serial_number); 1718 printf("Manufactured in week: %d year: %d\n", 1719 edid_info->week, edid_info->year + 1990); 1720 1721 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 1722 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 1723 "digital signal, " : "analog signal, ", 1724 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 1725 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 1726 ", blank to black" : "", 1727 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 1728 ", separate sync" : "", 1729 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 1730 ", composite sync" : "", 1731 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 1732 ", sync on green" : "", 1733 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 1734 ", serration v" : ""); 1735 1736 printf("Monitor is %s\n", 1737 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 1738 1739 printf("Maximum visible display size: %d cm x %d cm\n", 1740 edid_info->max_size_horizontal, 1741 edid_info->max_size_vertical); 1742 1743 printf("Power management features: %s%s, %s%s, %s%s\n", 1744 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 1745 "" : "no ", "active off", 1746 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 1747 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 1748 1749 printf("Estabilished timings:\n"); 1750 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 1751 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 1752 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 1753 printf("\t720x400\t\t88 Hz (XGA2)\n"); 1754 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 1755 printf("\t640x480\t\t60 Hz (VGA)\n"); 1756 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 1757 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 1758 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 1759 printf("\t640x480\t\t72 Hz (VESA)\n"); 1760 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 1761 printf("\t640x480\t\t75 Hz (VESA)\n"); 1762 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 1763 printf("\t800x600\t\t56 Hz (VESA)\n"); 1764 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 1765 printf("\t800x600\t\t60 Hz (VESA)\n"); 1766 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 1767 printf("\t800x600\t\t72 Hz (VESA)\n"); 1768 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 1769 printf("\t800x600\t\t75 Hz (VESA)\n"); 1770 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 1771 printf("\t832x624\t\t75 Hz (Mac II)\n"); 1772 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 1773 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 1774 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 1775 printf("\t1024x768\t60 Hz (VESA)\n"); 1776 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 1777 printf("\t1024x768\t70 Hz (VESA)\n"); 1778 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 1779 printf("\t1024x768\t75 Hz (VESA)\n"); 1780 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 1781 printf("\t1280x1024\t75 (VESA)\n"); 1782 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 1783 printf("\t1152x870\t75 (Mac II)\n"); 1784 1785 /* Standard timings. */ 1786 printf("Standard timings:\n"); 1787 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 1788 unsigned int aspect = 10000; 1789 unsigned int x, y; 1790 unsigned char xres, vfreq; 1791 1792 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 1793 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 1794 if ((xres != vfreq) || 1795 ((xres != 0) && (xres != 1)) || 1796 ((vfreq != 0) && (vfreq != 1))) { 1797 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 1798 i)) { 1799 case ASPECT_625: 1800 aspect = 6250; 1801 break; 1802 case ASPECT_75: 1803 aspect = 7500; 1804 break; 1805 case ASPECT_8: 1806 aspect = 8000; 1807 break; 1808 case ASPECT_5625: 1809 aspect = 5625; 1810 break; 1811 } 1812 x = (xres + 31) * 8; 1813 y = x * aspect / 10000; 1814 printf("\t%dx%d%c\t%d Hz\n", x, y, 1815 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 1816 have_timing = 1; 1817 } 1818 } 1819 1820 /* Detailed timing information. */ 1821 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 1822 i++) { 1823 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 1824 &have_timing); 1825 } 1826 1827 if (!have_timing) 1828 printf("\tNone\n"); 1829 } 1830 1831 /** 1832 * drm_mode_create - create a new display mode 1833 * 1834 * Create a new, cleared drm_display_mode. 1835 * 1836 * Returns: 1837 * Pointer to new mode on success, NULL on error. 1838 */ 1839 static struct drm_display_mode *drm_mode_create(void) 1840 { 1841 struct drm_display_mode *nmode; 1842 1843 nmode = malloc(sizeof(struct drm_display_mode)); 1844 memset(nmode, 0, sizeof(struct drm_display_mode)); 1845 if (!nmode) 1846 return NULL; 1847 1848 return nmode; 1849 } 1850 1851 /** 1852 * drm_mode_destroy - remove a mode 1853 * @mode: mode to remove 1854 * 1855 */ 1856 static void drm_mode_destroy(struct drm_display_mode *mode) 1857 { 1858 if (!mode) 1859 return; 1860 1861 kfree(mode); 1862 } 1863 1864 /** 1865 * drm_cvt_mode -create a modeline based on the CVT algorithm 1866 * @hdisplay: hdisplay size 1867 * @vdisplay: vdisplay size 1868 * @vrefresh: vrefresh rate 1869 * @reduced: whether to use reduced blanking 1870 * @interlaced: whether to compute an interlaced mode 1871 * @margins: whether to add margins (borders) 1872 * 1873 * This function is called to generate the modeline based on CVT algorithm 1874 * according to the hdisplay, vdisplay, vrefresh. 1875 * It is based from the VESA(TM) Coordinated Video Timing Generator by 1876 * Graham Loveridge April 9, 2003 available at 1877 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 1878 * 1879 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 1880 * What I have done is to translate it by using integer calculation. 1881 * 1882 * Returns: 1883 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 1884 * The display mode object is allocated with drm_mode_create(). Returns NULL 1885 * when no mode could be allocated. 1886 */ 1887 static 1888 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 1889 bool reduced, bool interlaced, 1890 bool margins) 1891 { 1892 #define HV_FACTOR 1000 1893 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 1894 #define CVT_MARGIN_PERCENTAGE 18 1895 /* 2) character cell horizontal granularity (pixels) - default 8 */ 1896 #define CVT_H_GRANULARITY 8 1897 /* 3) Minimum vertical porch (lines) - default 3 */ 1898 #define CVT_MIN_V_PORCH 3 1899 /* 4) Minimum number of vertical back porch lines - default 6 */ 1900 #define CVT_MIN_V_BPORCH 6 1901 /* Pixel Clock step (kHz) */ 1902 #define CVT_CLOCK_STEP 250 1903 struct drm_display_mode *drm_mode; 1904 unsigned int vfieldrate, hperiod; 1905 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 1906 int interlace; 1907 1908 /* allocate the drm_display_mode structure. If failure, we will 1909 * return directly 1910 */ 1911 drm_mode = drm_mode_create(); 1912 if (!drm_mode) 1913 return NULL; 1914 1915 /* the CVT default refresh rate is 60Hz */ 1916 if (!vrefresh) 1917 vrefresh = 60; 1918 1919 /* the required field fresh rate */ 1920 if (interlaced) 1921 vfieldrate = vrefresh * 2; 1922 else 1923 vfieldrate = vrefresh; 1924 1925 /* horizontal pixels */ 1926 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 1927 1928 /* determine the left&right borders */ 1929 hmargin = 0; 1930 if (margins) { 1931 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1932 hmargin -= hmargin % CVT_H_GRANULARITY; 1933 } 1934 /* find the total active pixels */ 1935 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 1936 1937 /* find the number of lines per field */ 1938 if (interlaced) 1939 vdisplay_rnd = vdisplay / 2; 1940 else 1941 vdisplay_rnd = vdisplay; 1942 1943 /* find the top & bottom borders */ 1944 vmargin = 0; 1945 if (margins) 1946 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1947 1948 drm_mode->vdisplay = vdisplay + 2 * vmargin; 1949 1950 /* Interlaced */ 1951 if (interlaced) 1952 interlace = 1; 1953 else 1954 interlace = 0; 1955 1956 /* Determine VSync Width from aspect ratio */ 1957 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 1958 vsync = 4; 1959 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 1960 vsync = 5; 1961 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 1962 vsync = 6; 1963 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 1964 vsync = 7; 1965 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 1966 vsync = 7; 1967 else /* custom */ 1968 vsync = 10; 1969 1970 if (!reduced) { 1971 /* simplify the GTF calculation */ 1972 /* 4) Minimum time of vertical sync + back porch interval 1973 * default 550.0 1974 */ 1975 int tmp1, tmp2; 1976 #define CVT_MIN_VSYNC_BP 550 1977 /* 3) Nominal HSync width (% of line period) - default 8 */ 1978 #define CVT_HSYNC_PERCENTAGE 8 1979 unsigned int hblank_percentage; 1980 int vsyncandback_porch, vback_porch, hblank; 1981 1982 /* estimated the horizontal period */ 1983 tmp1 = HV_FACTOR * 1000000 - 1984 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 1985 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 1986 interlace; 1987 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 1988 1989 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 1990 /* 9. Find number of lines in sync + backporch */ 1991 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 1992 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 1993 else 1994 vsyncandback_porch = tmp1; 1995 /* 10. Find number of lines in back porch */ 1996 vback_porch = vsyncandback_porch - vsync; 1997 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 1998 vsyncandback_porch + CVT_MIN_V_PORCH; 1999 /* 5) Definition of Horizontal blanking time limitation */ 2000 /* Gradient (%/kHz) - default 600 */ 2001 #define CVT_M_FACTOR 600 2002 /* Offset (%) - default 40 */ 2003 #define CVT_C_FACTOR 40 2004 /* Blanking time scaling factor - default 128 */ 2005 #define CVT_K_FACTOR 128 2006 /* Scaling factor weighting - default 20 */ 2007 #define CVT_J_FACTOR 20 2008 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2009 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2010 CVT_J_FACTOR) 2011 /* 12. Find ideal blanking duty cycle from formula */ 2012 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2013 hperiod / 1000; 2014 /* 13. Blanking time */ 2015 if (hblank_percentage < 20 * HV_FACTOR) 2016 hblank_percentage = 20 * HV_FACTOR; 2017 hblank = drm_mode->hdisplay * hblank_percentage / 2018 (100 * HV_FACTOR - hblank_percentage); 2019 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2020 /* 14. find the total pixels per line */ 2021 drm_mode->htotal = drm_mode->hdisplay + hblank; 2022 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2023 drm_mode->hsync_start = drm_mode->hsync_end - 2024 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2025 drm_mode->hsync_start += CVT_H_GRANULARITY - 2026 drm_mode->hsync_start % CVT_H_GRANULARITY; 2027 /* fill the Vsync values */ 2028 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2029 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2030 } else { 2031 /* Reduced blanking */ 2032 /* Minimum vertical blanking interval time - default 460 */ 2033 #define CVT_RB_MIN_VBLANK 460 2034 /* Fixed number of clocks for horizontal sync */ 2035 #define CVT_RB_H_SYNC 32 2036 /* Fixed number of clocks for horizontal blanking */ 2037 #define CVT_RB_H_BLANK 160 2038 /* Fixed number of lines for vertical front porch - default 3*/ 2039 #define CVT_RB_VFPORCH 3 2040 int vbilines; 2041 int tmp1, tmp2; 2042 /* 8. Estimate Horizontal period. */ 2043 tmp1 = HV_FACTOR * 1000000 - 2044 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2045 tmp2 = vdisplay_rnd + 2 * vmargin; 2046 hperiod = tmp1 / (tmp2 * vfieldrate); 2047 /* 9. Find number of lines in vertical blanking */ 2048 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2049 /* 10. Check if vertical blanking is sufficient */ 2050 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2051 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2052 /* 11. Find total number of lines in vertical field */ 2053 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2054 /* 12. Find total number of pixels in a line */ 2055 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2056 /* Fill in HSync values */ 2057 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2058 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2059 /* Fill in VSync values */ 2060 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2061 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2062 } 2063 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2064 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2065 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2066 /* 18/16. Find actual vertical frame frequency */ 2067 /* ignore - just set the mode flag for interlaced */ 2068 if (interlaced) { 2069 drm_mode->vtotal *= 2; 2070 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2071 } 2072 2073 if (reduced) 2074 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2075 DRM_MODE_FLAG_NVSYNC); 2076 else 2077 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2078 DRM_MODE_FLAG_NHSYNC); 2079 2080 return drm_mode; 2081 } 2082 2083 static int 2084 cea_db_payload_len(const u8 *db) 2085 { 2086 return db[0] & 0x1f; 2087 } 2088 2089 static int 2090 cea_db_extended_tag(const u8 *db) 2091 { 2092 return db[1]; 2093 } 2094 2095 static int 2096 cea_db_tag(const u8 *db) 2097 { 2098 return db[0] >> 5; 2099 } 2100 2101 #define for_each_cea_db(cea, i, start, end) \ 2102 for ((i) = (start); (i) < (end) && (i) + \ 2103 cea_db_payload_len(&(cea)[(i)]) < \ 2104 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2105 2106 static int 2107 cea_revision(const u8 *cea) 2108 { 2109 return cea[1]; 2110 } 2111 2112 static int 2113 cea_db_offsets(const u8 *cea, int *start, int *end) 2114 { 2115 /* Data block offset in CEA extension block */ 2116 *start = 4; 2117 *end = cea[2]; 2118 if (*end == 0) 2119 *end = 127; 2120 if (*end < 4 || *end > 127) 2121 return -ERANGE; 2122 2123 /* 2124 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2125 */ 2126 if (*end != 4) { 2127 int i; 2128 2129 i = *start; 2130 while (i < (*end) && 2131 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2132 i += cea_db_payload_len(&(cea)[i]) + 1; 2133 2134 if (cea_db_payload_len(&(cea)[i]) && 2135 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2136 (*end)++; 2137 } 2138 2139 return 0; 2140 } 2141 2142 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2143 { 2144 int hdmi_id; 2145 2146 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2147 return false; 2148 2149 if (cea_db_payload_len(db) < 5) 2150 return false; 2151 2152 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2153 2154 return hdmi_id == HDMI_IEEE_OUI; 2155 } 2156 2157 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2158 { 2159 unsigned int oui; 2160 2161 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2162 return false; 2163 2164 if (cea_db_payload_len(db) < 7) 2165 return false; 2166 2167 oui = db[3] << 16 | db[2] << 8 | db[1]; 2168 2169 return oui == HDMI_FORUM_IEEE_OUI; 2170 } 2171 2172 static bool cea_db_is_y420cmdb(const u8 *db) 2173 { 2174 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2175 return false; 2176 2177 if (!cea_db_payload_len(db)) 2178 return false; 2179 2180 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2181 return false; 2182 2183 return true; 2184 } 2185 2186 static bool cea_db_is_y420vdb(const u8 *db) 2187 { 2188 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2189 return false; 2190 2191 if (!cea_db_payload_len(db)) 2192 return false; 2193 2194 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2195 return false; 2196 2197 return true; 2198 } 2199 2200 static bool drm_valid_hdmi_vic(u8 vic) 2201 { 2202 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2203 } 2204 2205 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2206 struct drm_display_mode *mode) 2207 { 2208 int ret; 2209 struct drm_display_mode *mode_buf = data->mode_buf; 2210 2211 mode_buf[(data->modes)++] = *mode; 2212 } 2213 2214 static bool drm_valid_cea_vic(u8 vic) 2215 { 2216 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2217 } 2218 2219 static u8 svd_to_vic(u8 svd) 2220 { 2221 /* 0-6 bit vic, 7th bit native mode indicator */ 2222 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2223 return svd & 127; 2224 2225 return svd; 2226 } 2227 2228 static struct drm_display_mode * 2229 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2230 u8 video_index) 2231 { 2232 struct drm_display_mode *newmode; 2233 u8 vic; 2234 2235 if (!video_db || video_index >= video_len) 2236 return NULL; 2237 2238 /* CEA modes are numbered 1..127 */ 2239 vic = svd_to_vic(video_db[video_index]); 2240 if (!drm_valid_cea_vic(vic)) 2241 return NULL; 2242 2243 newmode = drm_mode_create(); 2244 if (!newmode) 2245 return NULL; 2246 2247 *newmode = edid_cea_modes[vic]; 2248 newmode->vrefresh = 0; 2249 2250 return newmode; 2251 } 2252 2253 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2254 { 2255 unsigned long *p = map + BIT_WORD(start); 2256 const unsigned int size = start + len; 2257 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2258 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2259 2260 while (len - bits_to_set >= 0) { 2261 *p |= mask_to_set; 2262 len -= bits_to_set; 2263 bits_to_set = BITS_PER_LONG; 2264 mask_to_set = ~0UL; 2265 p++; 2266 } 2267 if (len) { 2268 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2269 *p |= mask_to_set; 2270 } 2271 } 2272 2273 static void 2274 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2275 { 2276 u8 vic = svd_to_vic(svd); 2277 2278 if (!drm_valid_cea_vic(vic)) 2279 return; 2280 2281 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2282 } 2283 2284 static int 2285 do_cea_modes(const u8 *db, u8 len, struct drm_hdmi_info *hdmi, 2286 struct hdmi_edid_data *data) 2287 { 2288 int i, modes = 0; 2289 2290 for (i = 0; i < len; i++) { 2291 struct drm_display_mode *mode; 2292 2293 mode = drm_display_mode_from_vic_index(db, len, i); 2294 if (mode) { 2295 /* 2296 * YCBCR420 capability block contains a bitmap which 2297 * gives the index of CEA modes from CEA VDB, which 2298 * can support YCBCR 420 sampling output also (apart 2299 * from RGB/YCBCR444 etc). 2300 * For example, if the bit 0 in bitmap is set, 2301 * first mode in VDB can support YCBCR420 output too. 2302 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2303 */ 2304 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2305 drm_add_cmdb_modes(db[i], hdmi); 2306 drm_add_hdmi_modes(data, mode); 2307 drm_mode_destroy(mode); 2308 modes++; 2309 } 2310 } 2311 2312 return modes; 2313 } 2314 2315 /* 2316 * do_y420vdb_modes - Parse YCBCR 420 only modes 2317 * @data: the structure that save parsed hdmi edid data 2318 * @svds: start of the data block of CEA YCBCR 420 VDB 2319 * @svds_len: length of the CEA YCBCR 420 VDB 2320 * @hdmi: runtime information about the connected HDMI sink 2321 * 2322 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2323 * which contains modes which can be supported in YCBCR 420 2324 * output format only. 2325 */ 2326 static 2327 int do_y420vdb_modes(const u8 *svds, u8 svds_len, struct drm_hdmi_info *hdmi, 2328 struct hdmi_edid_data *data) 2329 { 2330 int modes = 0, i, ret; 2331 struct drm_display_mode *mode_buf = data->mode_buf; 2332 2333 for (i = 0; i < svds_len; i++) { 2334 u8 vic = svd_to_vic(svds[i]); 2335 2336 if (!drm_valid_cea_vic(vic)) 2337 continue; 2338 2339 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2340 drm_add_hdmi_modes(data, &edid_cea_modes[vic]); 2341 modes++; 2342 } 2343 2344 return modes; 2345 } 2346 2347 struct stereo_mandatory_mode { 2348 int width, height, vrefresh; 2349 unsigned int flags; 2350 }; 2351 2352 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2353 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2354 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2355 { 1920, 1080, 50, 2356 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2357 { 1920, 1080, 60, 2358 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2359 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2360 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2361 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2362 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2363 }; 2364 2365 static bool 2366 stereo_match_mandatory(const struct drm_display_mode *mode, 2367 const struct stereo_mandatory_mode *stereo_mode) 2368 { 2369 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2370 2371 return mode->hdisplay == stereo_mode->width && 2372 mode->vdisplay == stereo_mode->height && 2373 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2374 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2375 } 2376 2377 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2378 { 2379 const struct drm_display_mode *mode; 2380 int num = data->modes, modes = 0, i, k; 2381 2382 for (k = 0; k < num; k++) { 2383 mode = &data->mode_buf[k]; 2384 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2385 const struct stereo_mandatory_mode *mandatory; 2386 struct drm_display_mode *new_mode; 2387 2388 if (!stereo_match_mandatory(mode, 2389 &stereo_mandatory_modes[i])) 2390 continue; 2391 2392 mandatory = &stereo_mandatory_modes[i]; 2393 new_mode = drm_mode_create(); 2394 if (!new_mode) 2395 continue; 2396 2397 *new_mode = *mode; 2398 new_mode->flags |= mandatory->flags; 2399 drm_add_hdmi_modes(data, new_mode); 2400 drm_mode_destroy(new_mode); 2401 modes++; 2402 } 2403 } 2404 2405 return modes; 2406 } 2407 2408 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2409 const u8 *video_db, u8 video_len, u8 video_index) 2410 { 2411 struct drm_display_mode *newmode; 2412 int modes = 0; 2413 2414 if (structure & (1 << 0)) { 2415 newmode = drm_display_mode_from_vic_index(video_db, 2416 video_len, 2417 video_index); 2418 if (newmode) { 2419 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2420 drm_add_hdmi_modes(data, newmode); 2421 modes++; 2422 drm_mode_destroy(newmode); 2423 } 2424 } 2425 if (structure & (1 << 6)) { 2426 newmode = drm_display_mode_from_vic_index(video_db, 2427 video_len, 2428 video_index); 2429 if (newmode) { 2430 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2431 drm_add_hdmi_modes(data, newmode); 2432 modes++; 2433 drm_mode_destroy(newmode); 2434 } 2435 } 2436 if (structure & (1 << 8)) { 2437 newmode = drm_display_mode_from_vic_index(video_db, 2438 video_len, 2439 video_index); 2440 if (newmode) { 2441 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2442 drm_add_hdmi_modes(data, newmode); 2443 modes++; 2444 drm_mode_destroy(newmode); 2445 } 2446 } 2447 2448 return modes; 2449 } 2450 2451 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2452 { 2453 struct drm_display_mode *newmode; 2454 2455 if (!drm_valid_hdmi_vic(vic)) { 2456 debug("Unknown HDMI VIC: %d\n", vic); 2457 return 0; 2458 } 2459 2460 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2461 2462 return 1; 2463 } 2464 2465 /* 2466 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2467 * @db: start of the CEA vendor specific block 2468 * @len: length of the CEA block payload, ie. one can access up to db[len] 2469 * 2470 * Parses the HDMI VSDB looking for modes to add to @data. This function 2471 * also adds the stereo 3d modes when applicable. 2472 */ 2473 static int 2474 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2475 struct hdmi_edid_data *data) 2476 { 2477 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2478 u8 vic_len, hdmi_3d_len = 0; 2479 u16 mask; 2480 u16 structure_all; 2481 2482 if (len < 8) 2483 goto out; 2484 2485 /* no HDMI_Video_Present */ 2486 if (!(db[8] & (1 << 5))) 2487 goto out; 2488 2489 /* Latency_Fields_Present */ 2490 if (db[8] & (1 << 7)) 2491 offset += 2; 2492 2493 /* I_Latency_Fields_Present */ 2494 if (db[8] & (1 << 6)) 2495 offset += 2; 2496 2497 /* the declared length is not long enough for the 2 first bytes 2498 * of additional video format capabilities 2499 */ 2500 if (len < (8 + offset + 2)) 2501 goto out; 2502 2503 /* 3D_Present */ 2504 offset++; 2505 if (db[8 + offset] & (1 << 7)) { 2506 modes += add_hdmi_mandatory_stereo_modes(data); 2507 2508 /* 3D_Multi_present */ 2509 multi_present = (db[8 + offset] & 0x60) >> 5; 2510 } 2511 2512 offset++; 2513 vic_len = db[8 + offset] >> 5; 2514 hdmi_3d_len = db[8 + offset] & 0x1f; 2515 2516 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2517 u8 vic; 2518 2519 vic = db[9 + offset + i]; 2520 modes += add_hdmi_mode(data, vic); 2521 } 2522 2523 offset += 1 + vic_len; 2524 2525 if (multi_present == 1) 2526 multi_len = 2; 2527 else if (multi_present == 2) 2528 multi_len = 4; 2529 else 2530 multi_len = 0; 2531 2532 if (len < (8 + offset + hdmi_3d_len - 1)) 2533 goto out; 2534 2535 if (hdmi_3d_len < multi_len) 2536 goto out; 2537 2538 if (multi_present == 1 || multi_present == 2) { 2539 /* 3D_Structure_ALL */ 2540 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2541 2542 /* check if 3D_MASK is present */ 2543 if (multi_present == 2) 2544 mask = (db[10 + offset] << 8) | db[11 + offset]; 2545 else 2546 mask = 0xffff; 2547 2548 for (i = 0; i < 16; i++) { 2549 if (mask & (1 << i)) 2550 modes += add_3d_struct_modes(data, 2551 structure_all, 2552 video_db, 2553 video_len, i); 2554 } 2555 } 2556 2557 offset += multi_len; 2558 2559 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2560 int vic_index; 2561 struct drm_display_mode *newmode = NULL; 2562 unsigned int newflag = 0; 2563 bool detail_present; 2564 2565 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2566 2567 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2568 break; 2569 2570 /* 2D_VIC_order_X */ 2571 vic_index = db[8 + offset + i] >> 4; 2572 2573 /* 3D_Structure_X */ 2574 switch (db[8 + offset + i] & 0x0f) { 2575 case 0: 2576 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2577 break; 2578 case 6: 2579 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2580 break; 2581 case 8: 2582 /* 3D_Detail_X */ 2583 if ((db[9 + offset + i] >> 4) == 1) 2584 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2585 break; 2586 } 2587 2588 if (newflag != 0) { 2589 newmode = drm_display_mode_from_vic_index( 2590 video_db, 2591 video_len, 2592 vic_index); 2593 2594 if (newmode) { 2595 newmode->flags |= newflag; 2596 drm_add_hdmi_modes(data, newmode); 2597 modes++; 2598 drm_mode_destroy(newmode); 2599 } 2600 } 2601 2602 if (detail_present) 2603 i++; 2604 } 2605 2606 out: 2607 return modes; 2608 } 2609 2610 /** 2611 * edid_get_quirks - return quirk flags for a given EDID 2612 * @edid: EDID to process 2613 * 2614 * This tells subsequent routines what fixes they need to apply. 2615 */ 2616 static u32 edid_get_quirks(struct edid *edid) 2617 { 2618 struct edid_quirk *quirk; 2619 int i; 2620 2621 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2622 quirk = &edid_quirk_list[i]; 2623 2624 if (edid_vendor(edid, quirk->vendor) && 2625 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2626 return quirk->quirks; 2627 } 2628 2629 return 0; 2630 } 2631 2632 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 2633 const u8 *db) 2634 { 2635 struct drm_display_info *info = &data->display_info; 2636 struct drm_hdmi_info *hdmi = &info->hdmi; 2637 u8 map_len = cea_db_payload_len(db) - 1; 2638 u8 count; 2639 u64 map = 0; 2640 2641 if (map_len == 0) { 2642 /* All CEA modes support ycbcr420 sampling also.*/ 2643 hdmi->y420_cmdb_map = U64_MAX; 2644 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2645 return; 2646 } 2647 2648 /* 2649 * This map indicates which of the existing CEA block modes 2650 * from VDB can support YCBCR420 output too. So if bit=0 is 2651 * set, first mode from VDB can support YCBCR420 output too. 2652 * We will parse and keep this map, before parsing VDB itself 2653 * to avoid going through the same block again and again. 2654 * 2655 * Spec is not clear about max possible size of this block. 2656 * Clamping max bitmap block size at 8 bytes. Every byte can 2657 * address 8 CEA modes, in this way this map can address 2658 * 8*8 = first 64 SVDs. 2659 */ 2660 if (map_len > 8) 2661 map_len = 8; 2662 2663 for (count = 0; count < map_len; count++) 2664 map |= (u64)db[2 + count] << (8 * count); 2665 2666 if (map) 2667 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2668 2669 hdmi->y420_cmdb_map = map; 2670 } 2671 2672 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 2673 const u8 *db) 2674 { 2675 u8 dc_mask; 2676 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2677 2678 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 2679 hdmi->y420_dc_modes |= dc_mask; 2680 } 2681 2682 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 2683 const u8 *hf_vsdb) 2684 { 2685 struct drm_display_info *display = &data->display_info; 2686 struct drm_hdmi_info *hdmi = &display->hdmi; 2687 2688 if (hf_vsdb[6] & 0x80) { 2689 hdmi->scdc.supported = true; 2690 if (hf_vsdb[6] & 0x40) 2691 hdmi->scdc.read_request = true; 2692 } 2693 2694 /* 2695 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 2696 * And as per the spec, three factors confirm this: 2697 * * Availability of a HF-VSDB block in EDID (check) 2698 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 2699 * * SCDC support available (let's check) 2700 * Lets check it out. 2701 */ 2702 2703 if (hf_vsdb[5]) { 2704 /* max clock is 5000 KHz times block value */ 2705 u32 max_tmds_clock = hf_vsdb[5] * 5000; 2706 struct drm_scdc *scdc = &hdmi->scdc; 2707 2708 if (max_tmds_clock > 340000) { 2709 display->max_tmds_clock = max_tmds_clock; 2710 debug("HF-VSDB: max TMDS clock %d kHz\n", 2711 display->max_tmds_clock); 2712 } 2713 2714 if (scdc->supported) { 2715 scdc->scrambling.supported = true; 2716 2717 /* Few sinks support scrambling for cloks < 340M */ 2718 if ((hf_vsdb[6] & 0x8)) 2719 scdc->scrambling.low_rates = true; 2720 } 2721 } 2722 2723 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 2724 } 2725 2726 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 2727 const u8 *hdmi) 2728 { 2729 struct drm_display_info *info = &data->display_info; 2730 unsigned int dc_bpc = 0; 2731 2732 /* HDMI supports at least 8 bpc */ 2733 info->bpc = 8; 2734 2735 if (cea_db_payload_len(hdmi) < 6) 2736 return; 2737 2738 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 2739 dc_bpc = 10; 2740 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 2741 debug("HDMI sink does deep color 30.\n"); 2742 } 2743 2744 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 2745 dc_bpc = 12; 2746 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 2747 debug("HDMI sink does deep color 36.\n"); 2748 } 2749 2750 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 2751 dc_bpc = 16; 2752 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 2753 debug("HDMI sink does deep color 48.\n"); 2754 } 2755 2756 if (dc_bpc == 0) { 2757 debug("No deep color support on this HDMI sink.\n"); 2758 return; 2759 } 2760 2761 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 2762 info->bpc = dc_bpc; 2763 2764 /* YCRCB444 is optional according to spec. */ 2765 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 2766 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 2767 debug("HDMI sink does YCRCB444 in deep color.\n"); 2768 } 2769 2770 /* 2771 * Spec says that if any deep color mode is supported at all, 2772 * then deep color 36 bit must be supported. 2773 */ 2774 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 2775 debug("HDMI sink should do DC_36, but does not!\n"); 2776 } 2777 2778 /* 2779 * Search EDID for CEA extension block. 2780 */ 2781 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2782 { 2783 u8 *edid_ext = NULL; 2784 int i; 2785 2786 /* No EDID or EDID extensions */ 2787 if (!edid || !edid->extensions) 2788 return NULL; 2789 2790 /* Find CEA extension */ 2791 for (i = 0; i < edid->extensions; i++) { 2792 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 2793 if (edid_ext[0] == ext_id) 2794 break; 2795 } 2796 2797 if (i == edid->extensions) 2798 return NULL; 2799 2800 return edid_ext; 2801 } 2802 2803 static u8 *drm_find_cea_extension(struct edid *edid) 2804 { 2805 return drm_find_edid_extension(edid, 0x02); 2806 } 2807 2808 #define AUDIO_BLOCK 0x01 2809 #define VIDEO_BLOCK 0x02 2810 #define VENDOR_BLOCK 0x03 2811 #define SPEAKER_BLOCK 0x04 2812 #define EDID_BASIC_AUDIO BIT(6) 2813 2814 /** 2815 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 2816 * @edid: monitor EDID information 2817 * 2818 * Parse the CEA extension according to CEA-861-B. 2819 * 2820 * Return: True if the monitor is HDMI, false if not or unknown. 2821 */ 2822 bool drm_detect_hdmi_monitor(struct edid *edid) 2823 { 2824 u8 *edid_ext; 2825 int i; 2826 int start_offset, end_offset; 2827 2828 edid_ext = drm_find_cea_extension(edid); 2829 if (!edid_ext) 2830 return false; 2831 2832 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2833 return false; 2834 2835 /* 2836 * Because HDMI identifier is in Vendor Specific Block, 2837 * search it from all data blocks of CEA extension. 2838 */ 2839 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2840 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 2841 return true; 2842 } 2843 2844 return false; 2845 } 2846 2847 /** 2848 * drm_detect_monitor_audio - check monitor audio capability 2849 * @edid: EDID block to scan 2850 * 2851 * Monitor should have CEA extension block. 2852 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 2853 * audio' only. If there is any audio extension block and supported 2854 * audio format, assume at least 'basic audio' support, even if 'basic 2855 * audio' is not defined in EDID. 2856 * 2857 * Return: True if the monitor supports audio, false otherwise. 2858 */ 2859 bool drm_detect_monitor_audio(struct edid *edid) 2860 { 2861 u8 *edid_ext; 2862 int i, j; 2863 bool has_audio = false; 2864 int start_offset, end_offset; 2865 2866 edid_ext = drm_find_cea_extension(edid); 2867 if (!edid_ext) 2868 goto end; 2869 2870 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 2871 2872 if (has_audio) { 2873 printf("Monitor has basic audio support\n"); 2874 goto end; 2875 } 2876 2877 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2878 goto end; 2879 2880 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2881 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 2882 has_audio = true; 2883 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 2884 j += 3) 2885 debug("CEA audio format %d\n", 2886 (edid_ext[i + j] >> 3) & 0xf); 2887 goto end; 2888 } 2889 } 2890 end: 2891 return has_audio; 2892 } 2893 2894 static void 2895 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 2896 { 2897 struct drm_display_info *info = &data->display_info; 2898 u8 len = cea_db_payload_len(db); 2899 2900 if (len >= 6) 2901 info->dvi_dual = db[6] & 1; 2902 if (len >= 7) 2903 info->max_tmds_clock = db[7] * 5000; 2904 2905 drm_parse_hdmi_deep_color_info(data, db); 2906 } 2907 2908 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 2909 struct edid *edid) 2910 { 2911 struct drm_display_info *info = &data->display_info; 2912 const u8 *edid_ext; 2913 int i, start, end; 2914 2915 edid_ext = drm_find_cea_extension(edid); 2916 if (!edid_ext) 2917 return; 2918 2919 info->cea_rev = edid_ext[1]; 2920 2921 /* The existence of a CEA block should imply RGB support */ 2922 info->color_formats = DRM_COLOR_FORMAT_RGB444; 2923 if (edid_ext[3] & EDID_CEA_YCRCB444) 2924 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 2925 if (edid_ext[3] & EDID_CEA_YCRCB422) 2926 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 2927 2928 if (cea_db_offsets(edid_ext, &start, &end)) 2929 return; 2930 2931 for_each_cea_db(edid_ext, i, start, end) { 2932 const u8 *db = &edid_ext[i]; 2933 2934 if (cea_db_is_hdmi_vsdb(db)) 2935 drm_parse_hdmi_vsdb_video(data, db); 2936 if (cea_db_is_hdmi_forum_vsdb(db)) 2937 drm_parse_hdmi_forum_vsdb(data, db); 2938 if (cea_db_is_y420cmdb(db)) 2939 drm_parse_y420cmdb_bitmap(data, db); 2940 } 2941 } 2942 2943 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 2944 { 2945 struct drm_display_info *info = &data->display_info; 2946 2947 info->width_mm = edid->width_cm * 10; 2948 info->height_mm = edid->height_cm * 10; 2949 2950 /* driver figures it out in this case */ 2951 info->bpc = 0; 2952 info->color_formats = 0; 2953 info->cea_rev = 0; 2954 info->max_tmds_clock = 0; 2955 info->dvi_dual = false; 2956 info->edid_hdmi_dc_modes = 0; 2957 2958 memset(&info->hdmi, 0, sizeof(info->hdmi)); 2959 2960 if (edid->revision < 3) 2961 return; 2962 2963 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 2964 return; 2965 2966 drm_parse_cea_ext(data, edid); 2967 2968 /* 2969 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 2970 * 2971 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 2972 * tells us to assume 8 bpc color depth if the EDID doesn't have 2973 * extensions which tell otherwise. 2974 */ 2975 if ((info->bpc == 0) && (edid->revision < 4) && 2976 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 2977 info->bpc = 8; 2978 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 2979 } 2980 2981 /* Only defined for 1.4 with digital displays */ 2982 if (edid->revision < 4) 2983 return; 2984 2985 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 2986 case DRM_EDID_DIGITAL_DEPTH_6: 2987 info->bpc = 6; 2988 break; 2989 case DRM_EDID_DIGITAL_DEPTH_8: 2990 info->bpc = 8; 2991 break; 2992 case DRM_EDID_DIGITAL_DEPTH_10: 2993 info->bpc = 10; 2994 break; 2995 case DRM_EDID_DIGITAL_DEPTH_12: 2996 info->bpc = 12; 2997 break; 2998 case DRM_EDID_DIGITAL_DEPTH_14: 2999 info->bpc = 14; 3000 break; 3001 case DRM_EDID_DIGITAL_DEPTH_16: 3002 info->bpc = 16; 3003 break; 3004 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3005 default: 3006 info->bpc = 0; 3007 break; 3008 } 3009 3010 debug("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3011 info->bpc); 3012 3013 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3014 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3015 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3016 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3017 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3018 } 3019 3020 static 3021 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3022 { 3023 struct edid_cea861_info *info; 3024 const u8 *cea = drm_find_cea_extension(edid); 3025 const u8 *db, *hdmi = NULL, *video = NULL; 3026 u8 dbl, hdmi_len, video_len = 0; 3027 int modes = 0; 3028 u8 end, i = 0; 3029 3030 if (cea && cea_revision(cea) >= 3) { 3031 int i, start, end; 3032 3033 if (cea_db_offsets(cea, &start, &end)) 3034 return 0; 3035 3036 for_each_cea_db(cea, i, start, end) { 3037 db = &cea[i]; 3038 dbl = cea_db_payload_len(db); 3039 3040 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3041 video = db + 1; 3042 video_len = dbl; 3043 modes += do_cea_modes(video, dbl, 3044 &data->hdmi_info, data); 3045 } else if (cea_db_is_hdmi_vsdb(db)) { 3046 hdmi = db; 3047 hdmi_len = dbl; 3048 } else if (cea_db_is_y420vdb(db)) { 3049 const u8 *vdb420 = &db[2]; 3050 3051 /* Add 4:2:0(only) modes present in EDID */ 3052 modes += do_y420vdb_modes(vdb420, dbl - 1, 3053 &data->hdmi_info, 3054 data); 3055 } 3056 } 3057 } 3058 3059 /* 3060 * We parse the HDMI VSDB after having added the cea modes as we will 3061 * be patching their flags when the sink supports stereo 3D. 3062 */ 3063 if (hdmi) 3064 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3065 video_len, data); 3066 3067 return modes; 3068 } 3069 3070 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3071 3072 static 3073 void cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3074 { 3075 int i, n = 0; 3076 u8 d = ext[0x02]; 3077 u8 *det_base = ext + d; 3078 3079 n = (127 - d) / 18; 3080 for (i = 0; i < n; i++) 3081 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3082 } 3083 3084 static 3085 void vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3086 { 3087 unsigned int i, n = min((int)ext[0x02], 6); 3088 u8 *det_base = ext + 5; 3089 3090 if (ext[0x01] != 1) 3091 return; /* unknown version */ 3092 3093 for (i = 0; i < n; i++) 3094 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3095 } 3096 3097 static 3098 void drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3099 { 3100 int i; 3101 struct edid *edid = (struct edid *)raw_edid; 3102 3103 if (!edid) 3104 return; 3105 3106 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3107 cb(&edid->detailed_timings[i], closure); 3108 3109 for (i = 1; i <= raw_edid[0x7e]; i++) { 3110 u8 *ext = raw_edid + (i * EDID_SIZE); 3111 3112 switch (*ext) { 3113 case CEA_EXT: 3114 cea_for_each_detailed_block(ext, cb, closure); 3115 break; 3116 case VTB_EXT: 3117 vtb_for_each_detailed_block(ext, cb, closure); 3118 break; 3119 default: 3120 break; 3121 } 3122 } 3123 } 3124 3125 /* 3126 * EDID is delightfully ambiguous about how interlaced modes are to be 3127 * encoded. Our internal representation is of frame height, but some 3128 * HDTV detailed timings are encoded as field height. 3129 * 3130 * The format list here is from CEA, in frame size. Technically we 3131 * should be checking refresh rate too. Whatever. 3132 */ 3133 static void 3134 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3135 struct detailed_pixel_timing *pt) 3136 { 3137 int i; 3138 3139 static const struct { 3140 int w, h; 3141 } cea_interlaced[] = { 3142 { 1920, 1080 }, 3143 { 720, 480 }, 3144 { 1440, 480 }, 3145 { 2880, 480 }, 3146 { 720, 576 }, 3147 { 1440, 576 }, 3148 { 2880, 576 }, 3149 }; 3150 3151 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3152 return; 3153 3154 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3155 if ((mode->hdisplay == cea_interlaced[i].w) && 3156 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3157 mode->vdisplay *= 2; 3158 mode->vsync_start *= 2; 3159 mode->vsync_end *= 2; 3160 mode->vtotal *= 2; 3161 mode->vtotal |= 1; 3162 } 3163 } 3164 3165 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3166 } 3167 3168 /** 3169 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3170 * @edid: EDID block 3171 * @timing: EDID detailed timing info 3172 * @quirks: quirks to apply 3173 * 3174 * An EDID detailed timing block contains enough info for us to create and 3175 * return a new struct drm_display_mode. 3176 */ 3177 static 3178 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3179 struct detailed_timing *timing, 3180 u32 quirks) 3181 { 3182 struct drm_display_mode *mode; 3183 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3184 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3185 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3186 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3187 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3188 unsigned hsync_offset = 3189 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3190 pt->hsync_offset_lo; 3191 unsigned hsync_pulse_width = 3192 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3193 pt->hsync_pulse_width_lo; 3194 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3195 2 | pt->vsync_offset_pulse_width_lo >> 4; 3196 unsigned vsync_pulse_width = 3197 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3198 (pt->vsync_offset_pulse_width_lo & 0xf); 3199 3200 /* ignore tiny modes */ 3201 if (hactive < 64 || vactive < 64) 3202 return NULL; 3203 3204 if (pt->misc & DRM_EDID_PT_STEREO) { 3205 debug("stereo mode not supported\n"); 3206 return NULL; 3207 } 3208 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3209 debug("composite sync not supported\n"); 3210 3211 /* it is incorrect if hsync/vsync width is zero */ 3212 if (!hsync_pulse_width || !vsync_pulse_width) { 3213 debug("Incorrect Detailed timing. " 3214 "Wrong Hsync/Vsync pulse width\n"); 3215 return NULL; 3216 } 3217 3218 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3219 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3220 if (!mode) 3221 return NULL; 3222 3223 goto set_refresh; 3224 } 3225 3226 mode = drm_mode_create(); 3227 if (!mode) 3228 return NULL; 3229 3230 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3231 timing->pixel_clock = cpu_to_le16(1088); 3232 3233 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3234 3235 mode->hdisplay = hactive; 3236 mode->hsync_start = mode->hdisplay + hsync_offset; 3237 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3238 mode->htotal = mode->hdisplay + hblank; 3239 3240 mode->vdisplay = vactive; 3241 mode->vsync_start = mode->vdisplay + vsync_offset; 3242 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3243 mode->vtotal = mode->vdisplay + vblank; 3244 3245 /* Some EDIDs have bogus h/vtotal values */ 3246 if (mode->hsync_end > mode->htotal) 3247 mode->htotal = mode->hsync_end + 1; 3248 if (mode->vsync_end > mode->vtotal) 3249 mode->vtotal = mode->vsync_end + 1; 3250 3251 drm_mode_do_interlace_quirk(mode, pt); 3252 3253 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3254 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3255 DRM_EDID_PT_VSYNC_POSITIVE; 3256 3257 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3258 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3259 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3260 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3261 3262 set_refresh: 3263 3264 mode->vrefresh = drm_mode_vrefresh(mode); 3265 3266 return mode; 3267 } 3268 3269 /* 3270 * Calculate the alternate clock for the CEA mode 3271 * (60Hz vs. 59.94Hz etc.) 3272 */ 3273 static unsigned int 3274 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3275 { 3276 unsigned int clock = cea_mode->clock; 3277 3278 if (cea_mode->vrefresh % 6 != 0) 3279 return clock; 3280 3281 /* 3282 * edid_cea_modes contains the 59.94Hz 3283 * variant for 240 and 480 line modes, 3284 * and the 60Hz variant otherwise. 3285 */ 3286 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3287 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3288 else 3289 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3290 3291 return clock; 3292 } 3293 3294 /** 3295 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3296 * @mode1: first mode 3297 * @mode2: second mode 3298 * 3299 * Check to see if @mode1 and @mode2 are equivalent, but 3300 * don't check the pixel clocks nor the stereo layout. 3301 * 3302 * Returns: 3303 * True if the modes are equal, false otherwise. 3304 */ 3305 3306 static 3307 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3308 const struct drm_display_mode *mode2) 3309 { 3310 unsigned int flags_mask = 3311 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3312 3313 if (mode1->hdisplay == mode2->hdisplay && 3314 mode1->hsync_start == mode2->hsync_start && 3315 mode1->hsync_end == mode2->hsync_end && 3316 mode1->htotal == mode2->htotal && 3317 mode1->vdisplay == mode2->vdisplay && 3318 mode1->vsync_start == mode2->vsync_start && 3319 mode1->vsync_end == mode2->vsync_end && 3320 mode1->vtotal == mode2->vtotal && 3321 mode1->vscan == mode2->vscan && 3322 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3323 return true; 3324 3325 return false; 3326 } 3327 3328 /** 3329 * drm_mode_equal_no_clocks - test modes for equality 3330 * @mode1: first mode 3331 * @mode2: second mode 3332 * 3333 * Check to see if @mode1 and @mode2 are equivalent, but 3334 * don't check the pixel clocks. 3335 * 3336 * Returns: 3337 * True if the modes are equal, false otherwise. 3338 */ 3339 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3340 const struct drm_display_mode *mode2) 3341 { 3342 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3343 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3344 return false; 3345 3346 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3347 } 3348 3349 static 3350 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3351 unsigned int clock_tolerance) 3352 { 3353 u8 vic; 3354 3355 if (!to_match->clock) 3356 return 0; 3357 3358 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3359 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 3360 unsigned int clock1, clock2; 3361 3362 /* Check both 60Hz and 59.94Hz */ 3363 clock1 = cea_mode->clock; 3364 clock2 = cea_mode_alternate_clock(cea_mode); 3365 3366 if (abs(to_match->clock - clock1) > clock_tolerance && 3367 abs(to_match->clock - clock2) > clock_tolerance) 3368 continue; 3369 3370 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3371 return vic; 3372 } 3373 3374 return 0; 3375 } 3376 3377 static unsigned int 3378 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3379 { 3380 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3381 return hdmi_mode->clock; 3382 3383 return cea_mode_alternate_clock(hdmi_mode); 3384 } 3385 3386 static 3387 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3388 unsigned int clock_tolerance) 3389 { 3390 u8 vic; 3391 3392 if (!to_match->clock) 3393 return 0; 3394 3395 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3396 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3397 unsigned int clock1, clock2; 3398 3399 /* Make sure to also match alternate clocks */ 3400 clock1 = hdmi_mode->clock; 3401 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3402 3403 if (abs(to_match->clock - clock1) > clock_tolerance && 3404 abs(to_match->clock - clock2) > clock_tolerance) 3405 continue; 3406 3407 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3408 return vic; 3409 } 3410 3411 return 0; 3412 } 3413 3414 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3415 { 3416 const struct drm_display_mode *cea_mode; 3417 int clock1, clock2, clock; 3418 u8 vic; 3419 const char *type; 3420 3421 /* 3422 * allow 5kHz clock difference either way to account for 3423 * the 10kHz clock resolution limit of detailed timings. 3424 */ 3425 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3426 if (drm_valid_cea_vic(vic)) { 3427 type = "CEA"; 3428 cea_mode = &edid_cea_modes[vic]; 3429 clock1 = cea_mode->clock; 3430 clock2 = cea_mode_alternate_clock(cea_mode); 3431 } else { 3432 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3433 if (drm_valid_hdmi_vic(vic)) { 3434 type = "HDMI"; 3435 cea_mode = &edid_4k_modes[vic]; 3436 clock1 = cea_mode->clock; 3437 clock2 = hdmi_mode_alternate_clock(cea_mode); 3438 } else { 3439 return; 3440 } 3441 } 3442 3443 /* pick whichever is closest */ 3444 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3445 clock = clock1; 3446 else 3447 clock = clock2; 3448 3449 if (mode->clock == clock) 3450 return; 3451 3452 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3453 type, vic, mode->clock, clock); 3454 mode->clock = clock; 3455 } 3456 3457 static void 3458 do_detailed_mode(struct detailed_timing *timing, void *c) 3459 { 3460 struct detailed_mode_closure *closure = c; 3461 struct drm_display_mode *newmode; 3462 3463 if (timing->pixel_clock) { 3464 newmode = drm_mode_detailed( 3465 closure->edid, timing, 3466 closure->quirks); 3467 if (!newmode) 3468 return; 3469 3470 /* 3471 * Detailed modes are limited to 10kHz pixel clock resolution, 3472 * so fix up anything that looks like CEA/HDMI mode, 3473 * but the clock is just slightly off. 3474 */ 3475 fixup_detailed_cea_mode_clock(newmode); 3476 drm_add_hdmi_modes(closure->data, newmode); 3477 drm_mode_destroy(newmode); 3478 closure->modes++; 3479 } 3480 } 3481 3482 /* 3483 * add_detailed_modes - Add modes from detailed timings 3484 * @data: attached data 3485 * @edid: EDID block to scan 3486 * @quirks: quirks to apply 3487 */ 3488 static int 3489 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 3490 u32 quirks) 3491 { 3492 struct detailed_mode_closure closure = { 3493 .data = data, 3494 .edid = edid, 3495 .quirks = quirks, 3496 }; 3497 3498 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3499 3500 return closure.modes; 3501 } 3502 3503 static int drm_cvt_modes(struct hdmi_edid_data *data, 3504 struct detailed_timing *timing) 3505 { 3506 int i, j, modes = 0; 3507 struct drm_display_mode *newmode; 3508 struct cvt_timing *cvt; 3509 const int rates[] = { 60, 85, 75, 60, 50 }; 3510 const u8 empty[3] = { 0, 0, 0 }; 3511 3512 for (i = 0; i < 4; i++) { 3513 int uninitialized_var(width), height; 3514 3515 cvt = &timing->data.other_data.data.cvt[i]; 3516 3517 if (!memcmp(cvt->code, empty, 3)) 3518 continue; 3519 3520 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3521 switch (cvt->code[1] & 0x0c) { 3522 case 0x00: 3523 width = height * 4 / 3; 3524 break; 3525 case 0x04: 3526 width = height * 16 / 9; 3527 break; 3528 case 0x08: 3529 width = height * 16 / 10; 3530 break; 3531 case 0x0c: 3532 width = height * 15 / 9; 3533 break; 3534 } 3535 3536 for (j = 1; j < 5; j++) { 3537 if (cvt->code[2] & (1 << j)) { 3538 newmode = drm_cvt_mode(width, height, 3539 rates[j], j == 0, 3540 false, false); 3541 if (newmode) { 3542 drm_add_hdmi_modes(data, newmode); 3543 modes++; 3544 drm_mode_destroy(newmode); 3545 } 3546 } 3547 } 3548 } 3549 3550 return modes; 3551 } 3552 3553 static void 3554 do_cvt_mode(struct detailed_timing *timing, void *c) 3555 { 3556 struct detailed_mode_closure *closure = c; 3557 struct detailed_non_pixel *data = &timing->data.other_data; 3558 3559 if (data->type == EDID_DETAIL_CVT_3BYTE) 3560 closure->modes += drm_cvt_modes(closure->data, timing); 3561 } 3562 3563 static int 3564 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 3565 { 3566 struct detailed_mode_closure closure = { 3567 .data = data, 3568 .edid = edid, 3569 }; 3570 3571 if (version_greater(edid, 1, 2)) 3572 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3573 3574 /* XXX should also look for CVT codes in VTB blocks */ 3575 3576 return closure.modes; 3577 } 3578 3579 static void 3580 find_gtf2(struct detailed_timing *t, void *data) 3581 { 3582 u8 *r = (u8 *)t; 3583 3584 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 3585 *(u8 **)data = r; 3586 } 3587 3588 /* Secondary GTF curve kicks in above some break frequency */ 3589 static int 3590 drm_gtf2_hbreak(struct edid *edid) 3591 { 3592 u8 *r = NULL; 3593 3594 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3595 return r ? (r[12] * 2) : 0; 3596 } 3597 3598 static int 3599 drm_gtf2_2c(struct edid *edid) 3600 { 3601 u8 *r = NULL; 3602 3603 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3604 return r ? r[13] : 0; 3605 } 3606 3607 static int 3608 drm_gtf2_m(struct edid *edid) 3609 { 3610 u8 *r = NULL; 3611 3612 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3613 return r ? (r[15] << 8) + r[14] : 0; 3614 } 3615 3616 static int 3617 drm_gtf2_k(struct edid *edid) 3618 { 3619 u8 *r = NULL; 3620 3621 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3622 return r ? r[16] : 0; 3623 } 3624 3625 static int 3626 drm_gtf2_2j(struct edid *edid) 3627 { 3628 u8 *r = NULL; 3629 3630 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3631 return r ? r[17] : 0; 3632 } 3633 3634 /** 3635 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 3636 * @edid: EDID block to scan 3637 */ 3638 static int standard_timing_level(struct edid *edid) 3639 { 3640 if (edid->revision >= 2) { 3641 if (edid->revision >= 4 && 3642 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 3643 return LEVEL_CVT; 3644 if (drm_gtf2_hbreak(edid)) 3645 return LEVEL_GTF2; 3646 return LEVEL_GTF; 3647 } 3648 return LEVEL_DMT; 3649 } 3650 3651 /* 3652 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3653 * monitors fill with ascii space (0x20) instead. 3654 */ 3655 static int 3656 bad_std_timing(u8 a, u8 b) 3657 { 3658 return (a == 0x00 && b == 0x00) || 3659 (a == 0x01 && b == 0x01) || 3660 (a == 0x20 && b == 0x20); 3661 } 3662 3663 static void 3664 is_rb(struct detailed_timing *t, void *data) 3665 { 3666 u8 *r = (u8 *)t; 3667 3668 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 3669 if (r[15] & 0x10) 3670 *(bool *)data = true; 3671 } 3672 3673 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3674 static bool 3675 drm_monitor_supports_rb(struct edid *edid) 3676 { 3677 if (edid->revision >= 4) { 3678 bool ret = false; 3679 3680 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 3681 return ret; 3682 } 3683 3684 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3685 } 3686 3687 static bool 3688 mode_is_rb(const struct drm_display_mode *mode) 3689 { 3690 return (mode->htotal - mode->hdisplay == 160) && 3691 (mode->hsync_end - mode->hdisplay == 80) && 3692 (mode->hsync_end - mode->hsync_start == 32) && 3693 (mode->vsync_start - mode->vdisplay == 3); 3694 } 3695 3696 /* 3697 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3698 * @hsize: Mode width 3699 * @vsize: Mode height 3700 * @fresh: Mode refresh rate 3701 * @rb: Mode reduced-blanking-ness 3702 * 3703 * Walk the DMT mode list looking for a match for the given parameters. 3704 * 3705 * Return: A newly allocated copy of the mode, or NULL if not found. 3706 */ 3707 static struct drm_display_mode *drm_mode_find_dmt( 3708 int hsize, int vsize, int fresh, 3709 bool rb) 3710 { 3711 int i; 3712 struct drm_display_mode *newmode; 3713 3714 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3715 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3716 3717 if (hsize != ptr->hdisplay) 3718 continue; 3719 if (vsize != ptr->vdisplay) 3720 continue; 3721 if (fresh != drm_mode_vrefresh(ptr)) 3722 continue; 3723 if (rb != mode_is_rb(ptr)) 3724 continue; 3725 3726 newmode = drm_mode_create(); 3727 *newmode = *ptr; 3728 return newmode; 3729 } 3730 3731 return NULL; 3732 } 3733 3734 static struct drm_display_mode * 3735 drm_gtf_mode_complex(int hdisplay, int vdisplay, 3736 int vrefresh, bool interlaced, int margins, 3737 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 3738 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 3739 #define GTF_MARGIN_PERCENTAGE 18 3740 /* 2) character cell horizontal granularity (pixels) - default 8 */ 3741 #define GTF_CELL_GRAN 8 3742 /* 3) Minimum vertical porch (lines) - default 3 */ 3743 #define GTF_MIN_V_PORCH 1 3744 /* width of vsync in lines */ 3745 #define V_SYNC_RQD 3 3746 /* width of hsync as % of total line */ 3747 #define H_SYNC_PERCENT 8 3748 /* min time of vsync + back porch (microsec) */ 3749 #define MIN_VSYNC_PLUS_BP 550 3750 /* C' and M' are part of the Blanking Duty Cycle computation */ 3751 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 3752 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 3753 struct drm_display_mode *drm_mode; 3754 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 3755 int top_margin, bottom_margin; 3756 int interlace; 3757 unsigned int hfreq_est; 3758 int vsync_plus_bp, vback_porch; 3759 unsigned int vtotal_lines, vfieldrate_est, hperiod; 3760 unsigned int vfield_rate, vframe_rate; 3761 int left_margin, right_margin; 3762 unsigned int total_active_pixels, ideal_duty_cycle; 3763 unsigned int hblank, total_pixels, pixel_freq; 3764 int hsync, hfront_porch, vodd_front_porch_lines; 3765 unsigned int tmp1, tmp2; 3766 3767 drm_mode = drm_mode_create(); 3768 if (!drm_mode) 3769 return NULL; 3770 3771 /* 1. In order to give correct results, the number of horizontal 3772 * pixels requested is first processed to ensure that it is divisible 3773 * by the character size, by rounding it to the nearest character 3774 * cell boundary: 3775 */ 3776 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3777 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 3778 3779 /* 2. If interlace is requested, the number of vertical lines assumed 3780 * by the calculation must be halved, as the computation calculates 3781 * the number of vertical lines per field. 3782 */ 3783 if (interlaced) 3784 vdisplay_rnd = vdisplay / 2; 3785 else 3786 vdisplay_rnd = vdisplay; 3787 3788 /* 3. Find the frame rate required: */ 3789 if (interlaced) 3790 vfieldrate_rqd = vrefresh * 2; 3791 else 3792 vfieldrate_rqd = vrefresh; 3793 3794 /* 4. Find number of lines in Top margin: */ 3795 top_margin = 0; 3796 if (margins) 3797 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3798 1000; 3799 /* 5. Find number of lines in bottom margin: */ 3800 bottom_margin = top_margin; 3801 3802 /* 6. If interlace is required, then set variable interlace: */ 3803 if (interlaced) 3804 interlace = 1; 3805 else 3806 interlace = 0; 3807 3808 /* 7. Estimate the Horizontal frequency */ 3809 { 3810 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 3811 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 3812 2 + interlace; 3813 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 3814 } 3815 3816 /* 8. Find the number of lines in V sync + back porch */ 3817 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 3818 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 3819 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 3820 /* 9. Find the number of lines in V back porch alone: */ 3821 vback_porch = vsync_plus_bp - V_SYNC_RQD; 3822 /* 10. Find the total number of lines in Vertical field period: */ 3823 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 3824 vsync_plus_bp + GTF_MIN_V_PORCH; 3825 /* 11. Estimate the Vertical field frequency: */ 3826 vfieldrate_est = hfreq_est / vtotal_lines; 3827 /* 12. Find the actual horizontal period: */ 3828 hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 3829 3830 /* 13. Find the actual Vertical field frequency: */ 3831 vfield_rate = hfreq_est / vtotal_lines; 3832 /* 14. Find the Vertical frame frequency: */ 3833 if (interlaced) 3834 vframe_rate = vfield_rate / 2; 3835 else 3836 vframe_rate = vfield_rate; 3837 /* 15. Find number of pixels in left margin: */ 3838 if (margins) 3839 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3840 1000; 3841 else 3842 left_margin = 0; 3843 3844 /* 16.Find number of pixels in right margin: */ 3845 right_margin = left_margin; 3846 /* 17.Find total number of active pixels in image and left and right */ 3847 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 3848 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 3849 ideal_duty_cycle = GTF_C_PRIME * 1000 - 3850 (GTF_M_PRIME * 1000000 / hfreq_est); 3851 /* 19.Find the number of pixels in the blanking time to the nearest 3852 * double character cell: 3853 */ 3854 hblank = total_active_pixels * ideal_duty_cycle / 3855 (100000 - ideal_duty_cycle); 3856 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 3857 hblank = hblank * 2 * GTF_CELL_GRAN; 3858 /* 20.Find total number of pixels: */ 3859 total_pixels = total_active_pixels + hblank; 3860 /* 21.Find pixel clock frequency: */ 3861 pixel_freq = total_pixels * hfreq_est / 1000; 3862 /* Stage 1 computations are now complete; I should really pass 3863 * the results to another function and do the Stage 2 computations, 3864 * but I only need a few more values so I'll just append the 3865 * computations here for now 3866 */ 3867 3868 /* 17. Find the number of pixels in the horizontal sync period: */ 3869 hsync = H_SYNC_PERCENT * total_pixels / 100; 3870 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3871 hsync = hsync * GTF_CELL_GRAN; 3872 /* 18. Find the number of pixels in horizontal front porch period */ 3873 hfront_porch = hblank / 2 - hsync; 3874 /* 36. Find the number of lines in the odd front porch period: */ 3875 vodd_front_porch_lines = GTF_MIN_V_PORCH; 3876 3877 /* finally, pack the results in the mode struct */ 3878 drm_mode->hdisplay = hdisplay_rnd; 3879 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 3880 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 3881 drm_mode->htotal = total_pixels; 3882 drm_mode->vdisplay = vdisplay_rnd; 3883 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 3884 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 3885 drm_mode->vtotal = vtotal_lines; 3886 3887 drm_mode->clock = pixel_freq; 3888 3889 if (interlaced) { 3890 drm_mode->vtotal *= 2; 3891 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 3892 } 3893 3894 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 3895 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 3896 else 3897 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 3898 3899 return drm_mode; 3900 } 3901 3902 /** 3903 * drm_gtf_mode - create the mode based on the GTF algorithm 3904 * @hdisplay: hdisplay size 3905 * @vdisplay: vdisplay size 3906 * @vrefresh: vrefresh rate. 3907 * @interlaced: whether to compute an interlaced mode 3908 * @margins: desired margin (borders) size 3909 * 3910 * return the mode based on GTF algorithm 3911 * 3912 * This function is to create the mode based on the GTF algorithm. 3913 * Generalized Timing Formula is derived from: 3914 * GTF Spreadsheet by Andy Morrish (1/5/97) 3915 * available at http://www.vesa.org 3916 * 3917 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 3918 * What I have done is to translate it by using integer calculation. 3919 * I also refer to the function of fb_get_mode in the file of 3920 * drivers/video/fbmon.c 3921 * 3922 * Standard GTF parameters: 3923 * M = 600 3924 * C = 40 3925 * K = 128 3926 * J = 20 3927 * 3928 * Returns: 3929 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 3930 * The display mode object is allocated with drm_mode_create(). Returns NULL 3931 * when no mode could be allocated. 3932 */ 3933 static struct drm_display_mode * 3934 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 3935 bool interlaced, int margins) 3936 { 3937 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 3938 interlaced, margins, 3939 600, 40 * 2, 128, 20 * 2); 3940 } 3941 3942 /** drm_mode_hsync - get the hsync of a mode 3943 * @mode: mode 3944 * 3945 * Returns: 3946 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 3947 * value first if it is not yet set. 3948 */ 3949 static int drm_mode_hsync(const struct drm_display_mode *mode) 3950 { 3951 unsigned int calc_val; 3952 3953 if (mode->htotal < 0) 3954 return 0; 3955 3956 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 3957 calc_val += 500; /* round to 1000Hz */ 3958 calc_val /= 1000; /* truncate to kHz */ 3959 3960 return calc_val; 3961 } 3962 3963 /** 3964 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 3965 * @data: the structure that save parsed hdmi edid data 3966 * @edid: EDID block to scan 3967 * @t: standard timing params 3968 * 3969 * Take the standard timing params (in this case width, aspect, and refresh) 3970 * and convert them into a real mode using CVT/GTF/DMT. 3971 */ 3972 static struct drm_display_mode * 3973 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 3974 struct std_timing *t) 3975 { 3976 struct drm_display_mode *m, *mode = NULL; 3977 int i, hsize, vsize; 3978 int vrefresh_rate; 3979 int num = data->modes; 3980 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3981 >> EDID_TIMING_ASPECT_SHIFT; 3982 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3983 >> EDID_TIMING_VFREQ_SHIFT; 3984 int timing_level = standard_timing_level(edid); 3985 3986 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3987 return NULL; 3988 3989 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3990 hsize = t->hsize * 8 + 248; 3991 /* vrefresh_rate = vfreq + 60 */ 3992 vrefresh_rate = vfreq + 60; 3993 /* the vdisplay is calculated based on the aspect ratio */ 3994 if (aspect_ratio == 0) { 3995 if (edid->revision < 3) 3996 vsize = hsize; 3997 else 3998 vsize = (hsize * 10) / 16; 3999 } else if (aspect_ratio == 1) { 4000 vsize = (hsize * 3) / 4; 4001 } else if (aspect_ratio == 2) { 4002 vsize = (hsize * 4) / 5; 4003 } else { 4004 vsize = (hsize * 9) / 16; 4005 } 4006 4007 /* HDTV hack, part 1 */ 4008 if (vrefresh_rate == 60 && 4009 ((hsize == 1360 && vsize == 765) || 4010 (hsize == 1368 && vsize == 769))) { 4011 hsize = 1366; 4012 vsize = 768; 4013 } 4014 4015 /* 4016 * If we already has a mode for this size and refresh 4017 * rate (because it came from detailed or CVT info), use that 4018 * instead. This way we don't have to guess at interlace or 4019 * reduced blanking. 4020 */ 4021 for (i = 0; i < num; i++) 4022 if (data->mode_buf[i].hdisplay == hsize && 4023 data->mode_buf[i].hdisplay && 4024 drm_mode_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4025 return NULL; 4026 4027 /* HDTV hack, part 2 */ 4028 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4029 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4030 false); 4031 mode->hdisplay = 1366; 4032 mode->hsync_start = mode->hsync_start - 1; 4033 mode->hsync_end = mode->hsync_end - 1; 4034 return mode; 4035 } 4036 4037 /* check whether it can be found in default mode table */ 4038 if (drm_monitor_supports_rb(edid)) { 4039 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4040 true); 4041 if (mode) 4042 return mode; 4043 } 4044 4045 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4046 if (mode) 4047 return mode; 4048 4049 /* okay, generate it */ 4050 switch (timing_level) { 4051 case LEVEL_DMT: 4052 break; 4053 case LEVEL_GTF: 4054 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4055 break; 4056 case LEVEL_GTF2: 4057 /* 4058 * This is potentially wrong if there's ever a monitor with 4059 * more than one ranges section, each claiming a different 4060 * secondary GTF curve. Please don't do that. 4061 */ 4062 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4063 if (!mode) 4064 return NULL; 4065 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4066 drm_mode_destroy(mode); 4067 mode = drm_gtf_mode_complex(hsize, vsize, 4068 vrefresh_rate, 0, 0, 4069 drm_gtf2_m(edid), 4070 drm_gtf2_2c(edid), 4071 drm_gtf2_k(edid), 4072 drm_gtf2_2j(edid)); 4073 } 4074 break; 4075 case LEVEL_CVT: 4076 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4077 false); 4078 break; 4079 } 4080 4081 return mode; 4082 } 4083 4084 static void 4085 do_standard_modes(struct detailed_timing *timing, void *c) 4086 { 4087 struct detailed_mode_closure *closure = c; 4088 struct detailed_non_pixel *data = &timing->data.other_data; 4089 struct edid *edid = closure->edid; 4090 4091 if (data->type == EDID_DETAIL_STD_MODES) { 4092 int i; 4093 4094 for (i = 0; i < 6; i++) { 4095 struct std_timing *std; 4096 struct drm_display_mode *newmode; 4097 4098 std = &data->data.timings[i]; 4099 newmode = drm_mode_std(closure->data, edid, std); 4100 if (newmode) { 4101 drm_add_hdmi_modes(closure->data, newmode); 4102 closure->modes++; 4103 drm_mode_destroy(newmode); 4104 } 4105 } 4106 } 4107 } 4108 4109 /** 4110 * add_standard_modes - get std. modes from EDID and add them 4111 * @data: data to add mode(s) to 4112 * @edid: EDID block to scan 4113 * 4114 * Standard modes can be calculated using the appropriate standard (DMT, 4115 * GTF or CVT. Grab them from @edid and add them to the list. 4116 */ 4117 static int 4118 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4119 { 4120 int i, modes = 0; 4121 struct detailed_mode_closure closure = { 4122 .data = data, 4123 .edid = edid, 4124 }; 4125 4126 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4127 struct drm_display_mode *newmode; 4128 4129 newmode = drm_mode_std(data, edid, 4130 &edid->standard_timings[i]); 4131 if (newmode) { 4132 drm_add_hdmi_modes(data, newmode); 4133 modes++; 4134 drm_mode_destroy(newmode); 4135 } 4136 } 4137 4138 if (version_greater(edid, 1, 0)) 4139 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4140 &closure); 4141 4142 /* XXX should also look for standard codes in VTB blocks */ 4143 4144 return modes + closure.modes; 4145 } 4146 4147 static int 4148 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4149 { 4150 int i, j, m, modes = 0; 4151 struct drm_display_mode *mode; 4152 u8 *est = ((u8 *)timing) + 6; 4153 4154 for (i = 0; i < 6; i++) { 4155 for (j = 7; j >= 0; j--) { 4156 m = (i * 8) + (7 - j); 4157 if (m >= ARRAY_SIZE(est3_modes)) 4158 break; 4159 if (est[i] & (1 << j)) { 4160 mode = drm_mode_find_dmt( 4161 est3_modes[m].w, 4162 est3_modes[m].h, 4163 est3_modes[m].r, 4164 est3_modes[m].rb); 4165 if (mode) { 4166 drm_add_hdmi_modes(data, mode); 4167 modes++; 4168 drm_mode_destroy(mode); 4169 } 4170 } 4171 } 4172 } 4173 4174 return modes; 4175 } 4176 4177 static void 4178 do_established_modes(struct detailed_timing *timing, void *c) 4179 { 4180 struct detailed_mode_closure *closure = c; 4181 struct detailed_non_pixel *data = &timing->data.other_data; 4182 4183 if (data->type == EDID_DETAIL_EST_TIMINGS) 4184 closure->modes += drm_est3_modes(closure->data, timing); 4185 } 4186 4187 /** 4188 * add_established_modes - get est. modes from EDID and add them 4189 * @data: data to add mode(s) to 4190 * @edid: EDID block to scan 4191 * 4192 * Each EDID block contains a bitmap of the supported "established modes" list 4193 * (defined above). Tease them out and add them to the modes list. 4194 */ 4195 static int 4196 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4197 { 4198 unsigned long est_bits = edid->established_timings.t1 | 4199 (edid->established_timings.t2 << 8) | 4200 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4201 int i, modes = 0; 4202 struct detailed_mode_closure closure = { 4203 .data = data, 4204 .edid = edid, 4205 }; 4206 4207 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4208 if (est_bits & (1 << i)) { 4209 struct drm_display_mode *newmode = drm_mode_create(); 4210 *newmode = edid_est_modes[i]; 4211 if (newmode) { 4212 drm_add_hdmi_modes(data, newmode); 4213 modes++; 4214 drm_mode_destroy(newmode); 4215 } 4216 } 4217 } 4218 4219 if (version_greater(edid, 1, 0)) 4220 drm_for_each_detailed_block((u8 *)edid, 4221 do_established_modes, &closure); 4222 4223 return modes + closure.modes; 4224 } 4225 4226 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4227 { 4228 u8 vic; 4229 4230 if (!to_match->clock) 4231 return 0; 4232 4233 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4234 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4235 unsigned int clock1, clock2; 4236 4237 /* Make sure to also match alternate clocks */ 4238 clock1 = hdmi_mode->clock; 4239 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4240 4241 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4242 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4243 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4244 return vic; 4245 } 4246 return 0; 4247 } 4248 4249 static int 4250 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4251 { 4252 struct drm_display_mode *mode, *tmp; 4253 int i, num, modes = 0; 4254 4255 /* Don't add CEA modes if the CEA extension block is missing */ 4256 if (!drm_find_cea_extension(edid)) 4257 return 0; 4258 4259 /* 4260 * Go through all probed modes and create a new mode 4261 * with the alternate clock for certain CEA modes. 4262 */ 4263 num = data->modes; 4264 4265 for (i = 0; i < num; i++) { 4266 const struct drm_display_mode *cea_mode = NULL; 4267 struct drm_display_mode *newmode; 4268 u8 vic; 4269 unsigned int clock1, clock2; 4270 4271 mode = &data->mode_buf[i]; 4272 vic = drm_match_cea_mode(mode); 4273 4274 if (drm_valid_cea_vic(vic)) { 4275 cea_mode = &edid_cea_modes[vic]; 4276 clock2 = cea_mode_alternate_clock(cea_mode); 4277 } else { 4278 vic = drm_match_hdmi_mode(mode); 4279 if (drm_valid_hdmi_vic(vic)) { 4280 cea_mode = &edid_4k_modes[vic]; 4281 clock2 = hdmi_mode_alternate_clock(cea_mode); 4282 } 4283 } 4284 4285 if (!cea_mode) 4286 continue; 4287 4288 clock1 = cea_mode->clock; 4289 4290 if (clock1 == clock2) 4291 continue; 4292 4293 if (mode->clock != clock1 && mode->clock != clock2) 4294 continue; 4295 4296 newmode = drm_mode_create(); 4297 *newmode = *cea_mode; 4298 if (!newmode) 4299 continue; 4300 4301 /* Carry over the stereo flags */ 4302 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4303 4304 /* 4305 * The current mode could be either variant. Make 4306 * sure to pick the "other" clock for the new mode. 4307 */ 4308 if (mode->clock != clock1) 4309 newmode->clock = clock1; 4310 else 4311 newmode->clock = clock2; 4312 4313 drm_add_hdmi_modes(data, newmode); 4314 modes++; 4315 drm_mode_destroy(newmode); 4316 } 4317 4318 return modes; 4319 } 4320 4321 static u8 *drm_find_displayid_extension(struct edid *edid) 4322 { 4323 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4324 } 4325 4326 static int validate_displayid(u8 *displayid, int length, int idx) 4327 { 4328 int i; 4329 u8 csum = 0; 4330 struct displayid_hdr *base; 4331 4332 base = (struct displayid_hdr *)&displayid[idx]; 4333 4334 debug("base revision 0x%x, length %d, %d %d\n", 4335 base->rev, base->bytes, base->prod_id, base->ext_count); 4336 4337 if (base->bytes + 5 > length - idx) 4338 return -EINVAL; 4339 for (i = idx; i <= base->bytes + 5; i++) 4340 csum += displayid[i]; 4341 if (csum) { 4342 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4343 return -EINVAL; 4344 } 4345 return 0; 4346 } 4347 4348 static struct 4349 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4350 *timings) 4351 { 4352 struct drm_display_mode *mode; 4353 unsigned pixel_clock = (timings->pixel_clock[0] | 4354 (timings->pixel_clock[1] << 8) | 4355 (timings->pixel_clock[2] << 16)); 4356 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4357 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4358 unsigned hsync = (timings->hsync[0] | 4359 (timings->hsync[1] & 0x7f) << 8) + 1; 4360 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4361 unsigned vactive = (timings->vactive[0] | 4362 timings->vactive[1] << 8) + 1; 4363 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4364 unsigned vsync = (timings->vsync[0] | 4365 (timings->vsync[1] & 0x7f) << 8) + 1; 4366 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4367 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4368 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4369 4370 mode = drm_mode_create(); 4371 if (!mode) 4372 return NULL; 4373 4374 mode->clock = pixel_clock * 10; 4375 mode->hdisplay = hactive; 4376 mode->hsync_start = mode->hdisplay + hsync; 4377 mode->hsync_end = mode->hsync_start + hsync_width; 4378 mode->htotal = mode->hdisplay + hblank; 4379 4380 mode->vdisplay = vactive; 4381 mode->vsync_start = mode->vdisplay + vsync; 4382 mode->vsync_end = mode->vsync_start + vsync_width; 4383 mode->vtotal = mode->vdisplay + vblank; 4384 4385 mode->flags = 0; 4386 mode->flags |= 4387 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4388 mode->flags |= 4389 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4390 4391 if (timings->flags & 0x80) 4392 mode->vrefresh = drm_mode_vrefresh(mode); 4393 4394 return mode; 4395 } 4396 4397 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 4398 struct displayid_block *block) 4399 { 4400 struct displayid_detailed_timing_block *det; 4401 int i; 4402 int num_timings; 4403 struct drm_display_mode *newmode; 4404 int num_modes = 0; 4405 4406 det = (struct displayid_detailed_timing_block *)block; 4407 /* blocks must be multiple of 20 bytes length */ 4408 if (block->num_bytes % 20) 4409 return 0; 4410 4411 num_timings = block->num_bytes / 20; 4412 for (i = 0; i < num_timings; i++) { 4413 struct displayid_detailed_timings_1 *timings = 4414 &det->timings[i]; 4415 4416 newmode = drm_displayid_detailed(timings); 4417 if (!newmode) 4418 continue; 4419 4420 drm_add_hdmi_modes(data, newmode); 4421 num_modes++; 4422 drm_mode_destroy(newmode); 4423 } 4424 return num_modes; 4425 } 4426 4427 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 4428 struct edid *edid) 4429 { 4430 u8 *displayid; 4431 int ret; 4432 int idx = 1; 4433 int length = EDID_SIZE; 4434 struct displayid_block *block; 4435 int num_modes = 0; 4436 4437 displayid = drm_find_displayid_extension(edid); 4438 if (!displayid) 4439 return 0; 4440 4441 ret = validate_displayid(displayid, length, idx); 4442 if (ret) 4443 return 0; 4444 4445 idx += sizeof(struct displayid_hdr); 4446 while (block = (struct displayid_block *)&displayid[idx], 4447 idx + sizeof(struct displayid_block) <= length && 4448 idx + sizeof(struct displayid_block) + block->num_bytes <= 4449 length && block->num_bytes > 0) { 4450 idx += block->num_bytes + sizeof(struct displayid_block); 4451 switch (block->tag) { 4452 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4453 num_modes += 4454 add_displayid_detailed_1_modes(data, block); 4455 break; 4456 } 4457 } 4458 return num_modes; 4459 } 4460 4461 static bool 4462 mode_in_hsync_range(const struct drm_display_mode *mode, 4463 struct edid *edid, u8 *t) 4464 { 4465 int hsync, hmin, hmax; 4466 4467 hmin = t[7]; 4468 if (edid->revision >= 4) 4469 hmin += ((t[4] & 0x04) ? 255 : 0); 4470 hmax = t[8]; 4471 if (edid->revision >= 4) 4472 hmax += ((t[4] & 0x08) ? 255 : 0); 4473 hsync = drm_mode_hsync(mode); 4474 4475 return (hsync <= hmax && hsync >= hmin); 4476 } 4477 4478 static bool 4479 mode_in_vsync_range(const struct drm_display_mode *mode, 4480 struct edid *edid, u8 *t) 4481 { 4482 int vsync, vmin, vmax; 4483 4484 vmin = t[5]; 4485 if (edid->revision >= 4) 4486 vmin += ((t[4] & 0x01) ? 255 : 0); 4487 vmax = t[6]; 4488 if (edid->revision >= 4) 4489 vmax += ((t[4] & 0x02) ? 255 : 0); 4490 vsync = drm_mode_vrefresh(mode); 4491 4492 return (vsync <= vmax && vsync >= vmin); 4493 } 4494 4495 static u32 4496 range_pixel_clock(struct edid *edid, u8 *t) 4497 { 4498 /* unspecified */ 4499 if (t[9] == 0 || t[9] == 255) 4500 return 0; 4501 4502 /* 1.4 with CVT support gives us real precision, yay */ 4503 if (edid->revision >= 4 && t[10] == 0x04) 4504 return (t[9] * 10000) - ((t[12] >> 2) * 250); 4505 4506 /* 1.3 is pathetic, so fuzz up a bit */ 4507 return t[9] * 10000 + 5001; 4508 } 4509 4510 static bool 4511 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 4512 struct detailed_timing *timing) 4513 { 4514 u32 max_clock; 4515 u8 *t = (u8 *)timing; 4516 4517 if (!mode_in_hsync_range(mode, edid, t)) 4518 return false; 4519 4520 if (!mode_in_vsync_range(mode, edid, t)) 4521 return false; 4522 4523 max_clock = range_pixel_clock(edid, t); 4524 if (max_clock) 4525 if (mode->clock > max_clock) 4526 return false; 4527 4528 /* 1.4 max horizontal check */ 4529 if (edid->revision >= 4 && t[10] == 0x04) 4530 if (t[13] && mode->hdisplay > 8 * 4531 (t[13] + (256 * (t[12] & 0x3)))) 4532 return false; 4533 4534 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 4535 return false; 4536 4537 return true; 4538 } 4539 4540 static bool valid_inferred_mode(struct hdmi_edid_data *data, 4541 const struct drm_display_mode *mode) 4542 { 4543 const struct drm_display_mode *m; 4544 bool ok = false; 4545 int i; 4546 4547 for (i = 0; i < data->modes; i++) { 4548 m = &data->mode_buf[i]; 4549 if (mode->hdisplay == m->hdisplay && 4550 mode->vdisplay == m->vdisplay && 4551 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 4552 return false; /* duplicated */ 4553 if (mode->hdisplay <= m->hdisplay && 4554 mode->vdisplay <= m->vdisplay) 4555 ok = true; 4556 } 4557 return ok; 4558 } 4559 4560 static int 4561 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4562 struct detailed_timing *timing) 4563 { 4564 int i, modes = 0; 4565 4566 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4567 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 4568 valid_inferred_mode(data, drm_dmt_modes + i)) { 4569 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 4570 modes++; 4571 } 4572 } 4573 4574 return modes; 4575 } 4576 4577 /* fix up 1366x768 mode from 1368x768; 4578 * GFT/CVT can't express 1366 width which isn't dividable by 8 4579 */ 4580 static void fixup_mode_1366x768(struct drm_display_mode *mode) 4581 { 4582 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 4583 mode->hdisplay = 1366; 4584 mode->hsync_start--; 4585 mode->hsync_end--; 4586 } 4587 } 4588 4589 static int 4590 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4591 struct detailed_timing *timing) 4592 { 4593 int i, modes = 0; 4594 struct drm_display_mode *newmode; 4595 4596 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4597 const struct minimode *m = &extra_modes[i]; 4598 4599 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 4600 if (!newmode) 4601 return modes; 4602 4603 fixup_mode_1366x768(newmode); 4604 if (!mode_in_range(newmode, edid, timing) || 4605 !valid_inferred_mode(data, newmode)) { 4606 drm_mode_destroy(newmode); 4607 continue; 4608 } 4609 4610 drm_add_hdmi_modes(data, newmode); 4611 modes++; 4612 drm_mode_destroy(newmode); 4613 } 4614 4615 return modes; 4616 } 4617 4618 static int 4619 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4620 struct detailed_timing *timing) 4621 { 4622 int i, modes = 0; 4623 struct drm_display_mode *newmode; 4624 bool rb = drm_monitor_supports_rb(edid); 4625 4626 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4627 const struct minimode *m = &extra_modes[i]; 4628 4629 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 4630 if (!newmode) 4631 return modes; 4632 4633 fixup_mode_1366x768(newmode); 4634 if (!mode_in_range(newmode, edid, timing) || 4635 !valid_inferred_mode(data, newmode)) { 4636 drm_mode_destroy(newmode); 4637 continue; 4638 } 4639 4640 drm_add_hdmi_modes(data, newmode); 4641 modes++; 4642 drm_mode_destroy(newmode); 4643 } 4644 4645 return modes; 4646 } 4647 4648 static void 4649 do_inferred_modes(struct detailed_timing *timing, void *c) 4650 { 4651 struct detailed_mode_closure *closure = c; 4652 struct detailed_non_pixel *data = &timing->data.other_data; 4653 struct detailed_data_monitor_range *range = &data->data.range; 4654 4655 if (data->type != EDID_DETAIL_MONITOR_RANGE) 4656 return; 4657 4658 closure->modes += drm_dmt_modes_for_range(closure->data, 4659 closure->edid, 4660 timing); 4661 4662 if (!version_greater(closure->edid, 1, 1)) 4663 return; /* GTF not defined yet */ 4664 4665 switch (range->flags) { 4666 case 0x02: /* secondary gtf, XXX could do more */ 4667 case 0x00: /* default gtf */ 4668 closure->modes += drm_gtf_modes_for_range(closure->data, 4669 closure->edid, 4670 timing); 4671 break; 4672 case 0x04: /* cvt, only in 1.4+ */ 4673 if (!version_greater(closure->edid, 1, 3)) 4674 break; 4675 4676 closure->modes += drm_cvt_modes_for_range(closure->data, 4677 closure->edid, 4678 timing); 4679 break; 4680 case 0x01: /* just the ranges, no formula */ 4681 default: 4682 break; 4683 } 4684 } 4685 4686 static int 4687 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 4688 { 4689 struct detailed_mode_closure closure = { 4690 .data = data, 4691 .edid = edid, 4692 }; 4693 4694 if (version_greater(edid, 1, 0)) 4695 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 4696 &closure); 4697 4698 return closure.modes; 4699 } 4700 4701 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 4702 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 4703 4704 /** 4705 * edid_fixup_preferred - set preferred modes based on quirk list 4706 * @data: the structure that save parsed hdmi edid data 4707 * @quirks: quirks list 4708 * 4709 * Walk the mode list, clearing the preferred status 4710 * on existing modes and setting it anew for the right mode ala @quirks. 4711 */ 4712 static void edid_fixup_preferred(struct hdmi_edid_data *data, 4713 u32 quirks) 4714 { 4715 struct drm_display_mode *t, *cur_mode, *preferred_mode; 4716 int i, target_refresh = 0; 4717 int num = data->modes; 4718 int cur_vrefresh, preferred_vrefresh; 4719 4720 if (!num) 4721 return; 4722 4723 preferred_mode = data->preferred_mode; 4724 4725 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 4726 target_refresh = 60; 4727 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 4728 target_refresh = 75; 4729 4730 for (i = 0; i < num; i++) { 4731 cur_mode = &data->mode_buf[i]; 4732 4733 if (cur_mode == preferred_mode) 4734 continue; 4735 4736 /* Largest mode is preferred */ 4737 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 4738 preferred_mode = cur_mode; 4739 4740 cur_vrefresh = cur_mode->vrefresh ? 4741 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 4742 preferred_vrefresh = preferred_mode->vrefresh ? 4743 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 4744 /* At a given size, try to get closest to target refresh */ 4745 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 4746 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 4747 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 4748 preferred_mode = cur_mode; 4749 } 4750 } 4751 data->preferred_mode = preferred_mode; 4752 } 4753 4754 static const u8 edid_header[] = { 4755 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 4756 }; 4757 4758 /** 4759 * drm_edid_header_is_valid - sanity check the header of the base EDID block 4760 * @raw_edid: pointer to raw base EDID block 4761 * 4762 * Sanity check the header of the base EDID block. 4763 * 4764 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 4765 */ 4766 static int drm_edid_header_is_valid(const u8 *raw_edid) 4767 { 4768 int i, score = 0; 4769 4770 for (i = 0; i < sizeof(edid_header); i++) 4771 if (raw_edid[i] == edid_header[i]) 4772 score++; 4773 4774 return score; 4775 } 4776 4777 static int drm_edid_block_checksum(const u8 *raw_edid) 4778 { 4779 int i; 4780 u8 csum = 0; 4781 4782 for (i = 0; i < EDID_SIZE; i++) 4783 csum += raw_edid[i]; 4784 4785 return csum; 4786 } 4787 4788 static bool drm_edid_is_zero(const u8 *in_edid, int length) 4789 { 4790 if (memchr_inv(in_edid, 0, length)) 4791 return false; 4792 4793 return true; 4794 } 4795 4796 /** 4797 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 4798 * @raw_edid: pointer to raw EDID block 4799 * @block: type of block to validate (0 for base, extension otherwise) 4800 * @print_bad_edid: if true, dump bad EDID blocks to the console 4801 * @edid_corrupt: if true, the header or checksum is invalid 4802 * 4803 * Validate a base or extension EDID block and optionally dump bad blocks to 4804 * the console. 4805 * 4806 * Return: True if the block is valid, false otherwise. 4807 */ 4808 static 4809 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 4810 bool *edid_corrupt) 4811 { 4812 u8 csum; 4813 int edid_fixup = 6; 4814 struct edid *edid = (struct edid *)raw_edid; 4815 4816 if ((!raw_edid)) 4817 return false; 4818 4819 if (block == 0) { 4820 int score = drm_edid_header_is_valid(raw_edid); 4821 4822 if (score == 8) { 4823 if (edid_corrupt) 4824 *edid_corrupt = false; 4825 } else if (score >= edid_fixup) { 4826 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 4827 * The corrupt flag needs to be set here otherwise, the 4828 * fix-up code here will correct the problem, the 4829 * checksum is correct and the test fails 4830 */ 4831 if (edid_corrupt) 4832 *edid_corrupt = true; 4833 debug("Fixing header, your hardware may be failing\n"); 4834 memcpy(raw_edid, edid_header, sizeof(edid_header)); 4835 } else { 4836 if (edid_corrupt) 4837 *edid_corrupt = true; 4838 goto bad; 4839 } 4840 } 4841 4842 csum = drm_edid_block_checksum(raw_edid); 4843 if (csum) { 4844 if (print_bad_edid) { 4845 debug("EDID checksum is invalid, remainder is %d\n", 4846 csum); 4847 } 4848 4849 if (edid_corrupt) 4850 *edid_corrupt = true; 4851 4852 /* allow CEA to slide through, switches mangle this */ 4853 if (raw_edid[0] != 0x02) 4854 goto bad; 4855 } 4856 4857 /* per-block-type checks */ 4858 switch (raw_edid[0]) { 4859 case 0: /* base */ 4860 if (edid->version != 1) { 4861 debug("EDID has major version %d, instead of 1\n", 4862 edid->version); 4863 goto bad; 4864 } 4865 4866 if (edid->revision > 4) 4867 debug("minor > 4, assuming backward compatibility\n"); 4868 break; 4869 4870 default: 4871 break; 4872 } 4873 4874 return true; 4875 4876 bad: 4877 if (print_bad_edid) { 4878 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 4879 debug("EDID block is all zeroes\n"); 4880 } else { 4881 debug("Raw EDID:\n"); 4882 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 4883 raw_edid, EDID_SIZE, false); 4884 } 4885 } 4886 return false; 4887 } 4888 4889 /** 4890 * drm_edid_is_valid - sanity check EDID data 4891 * @edid: EDID data 4892 * 4893 * Sanity-check an entire EDID record (including extensions) 4894 * 4895 * Return: True if the EDID data is valid, false otherwise. 4896 */ 4897 static bool drm_edid_is_valid(struct edid *edid) 4898 { 4899 int i; 4900 u8 *raw = (u8 *)edid; 4901 4902 if (!edid) 4903 return false; 4904 4905 for (i = 0; i <= edid->extensions; i++) 4906 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 4907 return false; 4908 4909 return true; 4910 } 4911 4912 /** 4913 * drm_add_edid_modes - add modes from EDID data, if available 4914 * @data: data we're probing 4915 * @edid: EDID data 4916 * 4917 * Add the specified modes to the data's mode list. 4918 * 4919 * Return: The number of modes added or 0 if we couldn't find any. 4920 */ 4921 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 4922 { 4923 int num_modes = 0; 4924 u32 quirks; 4925 struct edid *edid = (struct edid *)raw_edid; 4926 4927 if (!edid) { 4928 debug("no edid\n"); 4929 return 0; 4930 } 4931 4932 if (!drm_edid_is_valid(edid)) { 4933 debug("EDID invalid\n"); 4934 return 0; 4935 } 4936 4937 if (!data->mode_buf) { 4938 debug("mode buff is null\n"); 4939 return 0; 4940 } 4941 4942 quirks = edid_get_quirks(edid); 4943 /* 4944 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4945 * To avoid multiple parsing of same block, lets parse that map 4946 * from sink info, before parsing CEA modes. 4947 */ 4948 drm_add_display_info(data, edid); 4949 4950 /* 4951 * EDID spec says modes should be preferred in this order: 4952 * - preferred detailed mode 4953 * - other detailed modes from base block 4954 * - detailed modes from extension blocks 4955 * - CVT 3-byte code modes 4956 * - standard timing codes 4957 * - established timing codes 4958 * - modes inferred from GTF or CVT range information 4959 * 4960 * We get this pretty much right. 4961 * 4962 * XXX order for additional mode types in extension blocks? 4963 */ 4964 num_modes += add_detailed_modes(data, edid, quirks); 4965 num_modes += add_cvt_modes(data, edid); 4966 num_modes += add_standard_modes(data, edid); 4967 num_modes += add_established_modes(data, edid); 4968 num_modes += add_cea_modes(data, edid); 4969 num_modes += add_alternate_cea_modes(data, edid); 4970 num_modes += add_displayid_detailed_modes(data, edid); 4971 4972 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4973 num_modes += add_inferred_modes(data, edid); 4974 4975 if (num_modes > 0) 4976 data->preferred_mode = &data->mode_buf[0]; 4977 4978 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4979 edid_fixup_preferred(data, quirks); 4980 4981 if (quirks & EDID_QUIRK_FORCE_6BPC) 4982 data->display_info.bpc = 6; 4983 4984 if (quirks & EDID_QUIRK_FORCE_8BPC) 4985 data->display_info.bpc = 8; 4986 4987 if (quirks & EDID_QUIRK_FORCE_10BPC) 4988 data->display_info.bpc = 10; 4989 4990 if (quirks & EDID_QUIRK_FORCE_12BPC) 4991 data->display_info.bpc = 12; 4992 4993 return num_modes; 4994 } 4995 4996 static int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 4997 { 4998 memset(frame, 0, sizeof(*frame)); 4999 5000 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5001 frame->version = 2; 5002 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5003 5004 return 0; 5005 } 5006 5007 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5008 { 5009 u8 vic; 5010 5011 if (!to_match->clock) { 5012 printf("can't find to match\n"); 5013 return 0; 5014 } 5015 5016 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 5017 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 5018 unsigned int clock1, clock2; 5019 5020 /* Check both 60Hz and 59.94Hz */ 5021 clock1 = cea_mode->clock; 5022 clock2 = cea_mode_alternate_clock(cea_mode); 5023 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5024 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5025 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5026 return vic; 5027 } 5028 5029 return 0; 5030 } 5031 5032 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5033 { 5034 return edid_cea_modes[video_code].picture_aspect_ratio; 5035 } 5036 5037 int 5038 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5039 struct drm_display_mode *mode, 5040 bool is_hdmi2_sink) 5041 { 5042 int err; 5043 5044 if (!frame || !mode) 5045 return -EINVAL; 5046 5047 err = hdmi_avi_infoframe_init(frame); 5048 if (err < 0) 5049 return err; 5050 5051 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5052 frame->pixel_repeat = 1; 5053 5054 frame->video_code = drm_match_cea_mode(mode); 5055 5056 /* 5057 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5058 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5059 * have to make sure we dont break HDMI 1.4 sinks. 5060 */ 5061 if (!is_hdmi2_sink && frame->video_code > 64) 5062 frame->video_code = 0; 5063 5064 /* 5065 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5066 * we should send its VIC in vendor infoframes, else send the 5067 * VIC in AVI infoframes. Lets check if this mode is present in 5068 * HDMI 1.4b 4K modes 5069 */ 5070 if (frame->video_code) { 5071 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5072 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5073 5074 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5075 frame->video_code = 0; 5076 } 5077 5078 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5079 5080 /* 5081 * Populate picture aspect ratio from either 5082 * user input (if specified) or from the CEA mode list. 5083 */ 5084 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5085 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5086 frame->picture_aspect = mode->picture_aspect_ratio; 5087 else if (frame->video_code > 0) 5088 frame->picture_aspect = drm_get_cea_aspect_ratio( 5089 frame->video_code); 5090 5091 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5092 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5093 5094 return 0; 5095 } 5096 5097 /** 5098 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5099 * @frame: HDMI vendor infoframe 5100 * 5101 * Returns 0 on success or a negative error code on failure. 5102 */ 5103 static int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5104 { 5105 memset(frame, 0, sizeof(*frame)); 5106 5107 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5108 frame->version = 1; 5109 5110 frame->oui = HDMI_IEEE_OUI; 5111 5112 /* 5113 * 0 is a valid value for s3d_struct, so we use a special "not set" 5114 * value 5115 */ 5116 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5117 5118 return 0; 5119 } 5120 5121 static enum hdmi_3d_structure 5122 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5123 { 5124 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5125 5126 switch (layout) { 5127 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5128 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5129 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5130 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5131 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5132 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5133 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5134 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5135 case DRM_MODE_FLAG_3D_L_DEPTH: 5136 return HDMI_3D_STRUCTURE_L_DEPTH; 5137 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5138 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5139 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5140 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5141 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5142 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5143 default: 5144 return HDMI_3D_STRUCTURE_INVALID; 5145 } 5146 } 5147 5148 int 5149 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5150 struct drm_display_mode *mode) 5151 { 5152 int err; 5153 u32 s3d_flags; 5154 u8 vic; 5155 5156 if (!frame || !mode) 5157 return -EINVAL; 5158 5159 vic = drm_match_hdmi_mode(mode); 5160 5161 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5162 5163 if (!vic && !s3d_flags) 5164 return -EINVAL; 5165 5166 if (vic && s3d_flags) 5167 return -EINVAL; 5168 5169 err = hdmi_vendor_infoframe_init(frame); 5170 if (err < 0) 5171 return err; 5172 5173 if (vic) 5174 frame->vic = vic; 5175 else 5176 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5177 5178 return 0; 5179 } 5180 5181 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5182 { 5183 u8 csum = 0; 5184 size_t i; 5185 5186 /* compute checksum */ 5187 for (i = 0; i < size; i++) 5188 csum += ptr[i]; 5189 5190 return 256 - csum; 5191 } 5192 5193 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5194 { 5195 u8 *ptr = buffer; 5196 5197 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5198 } 5199 5200 /** 5201 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 5202 * @frame: HDMI infoframe 5203 * @buffer: destination buffer 5204 * @size: size of buffer 5205 * 5206 * Packs the information contained in the @frame structure into a binary 5207 * representation that can be written into the corresponding controller 5208 * registers. Also computes the checksum as required by section 5.3.5 of 5209 * the HDMI 1.4 specification. 5210 * 5211 * Returns the number of bytes packed into the binary buffer or a negative 5212 * error code on failure. 5213 */ 5214 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 5215 void *buffer, size_t size) 5216 { 5217 u8 *ptr = buffer; 5218 size_t length; 5219 5220 /* empty info frame */ 5221 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 5222 return -EINVAL; 5223 5224 /* only one of those can be supplied */ 5225 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 5226 return -EINVAL; 5227 5228 /* for side by side (half) we also need to provide 3D_Ext_Data */ 5229 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5230 frame->length = 6; 5231 else 5232 frame->length = 5; 5233 5234 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5235 5236 if (size < length) 5237 return -ENOSPC; 5238 5239 memset(buffer, 0, size); 5240 5241 ptr[0] = frame->type; 5242 ptr[1] = frame->version; 5243 ptr[2] = frame->length; 5244 ptr[3] = 0; /* checksum */ 5245 5246 /* HDMI OUI */ 5247 ptr[4] = 0x03; 5248 ptr[5] = 0x0c; 5249 ptr[6] = 0x00; 5250 5251 if (frame->vic) { 5252 ptr[7] = 0x1 << 5; /* video format */ 5253 ptr[8] = frame->vic; 5254 } else { 5255 ptr[7] = 0x2 << 5; /* video format */ 5256 ptr[8] = (frame->s3d_struct & 0xf) << 4; 5257 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5258 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 5259 } 5260 5261 hdmi_infoframe_set_checksum(buffer, length); 5262 5263 return length; 5264 } 5265