1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <hexdump.h> 22 #include <malloc.h> 23 #include <linux/compat.h> 24 #include <linux/ctype.h> 25 #include <linux/fb.h> 26 #include <linux/hdmi.h> 27 #include <linux/string.h> 28 29 #define EDID_EST_TIMINGS 16 30 #define EDID_STD_TIMINGS 8 31 #define EDID_DETAILED_TIMINGS 4 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 bool preferred; 78 u32 quirks; 79 int modes; 80 }; 81 82 #define LEVEL_DMT 0 83 #define LEVEL_GTF 1 84 #define LEVEL_GTF2 2 85 #define LEVEL_CVT 3 86 87 static struct edid_quirk { 88 char vendor[4]; 89 int product_id; 90 u32 quirks; 91 } edid_quirk_list[] = { 92 /* Acer AL1706 */ 93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Acer F51 */ 95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Unknown Acer */ 97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 98 99 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 100 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 116 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 146 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 147 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Probably taken from CEA-861 spec. 152 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 153 * 154 * Index using the VIC. 155 */ 156 /* 157 * From CEA/CTA-861 spec. 158 * Do not access directly, instead always use cea_mode_for_vic(). 159 */ 160 static const struct drm_display_mode edid_cea_modes_1[] = { 161 /* 1 - 640x480@60Hz */ 162 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 163 752, 800, 480, 490, 492, 525, 0, 164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 165 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 166 /* 2 - 720x480@60Hz */ 167 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 168 798, 858, 480, 489, 495, 525, 0, 169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 170 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 171 /* 3 - 720x480@60Hz */ 172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 173 798, 858, 480, 489, 495, 525, 0, 174 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 175 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 176 /* 4 - 1280x720@60Hz */ 177 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 178 1430, 1650, 720, 725, 730, 750, 0, 179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 180 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 181 /* 5 - 1920x1080i@60Hz */ 182 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 183 2052, 2200, 1080, 1084, 1094, 1125, 0, 184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 185 DRM_MODE_FLAG_INTERLACE), 186 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 187 /* 6 - 720(1440)x480i@60Hz */ 188 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 189 801, 858, 480, 488, 494, 525, 0, 190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 191 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 193 /* 7 - 720(1440)x480i@60Hz */ 194 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 195 801, 858, 480, 488, 494, 525, 0, 196 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 197 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 198 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 199 /* 8 - 720(1440)x240@60Hz */ 200 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 201 801, 858, 240, 244, 247, 262, 0, 202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 203 DRM_MODE_FLAG_DBLCLK), 204 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 205 /* 9 - 720(1440)x240@60Hz */ 206 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 207 801, 858, 240, 244, 247, 262, 0, 208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 209 DRM_MODE_FLAG_DBLCLK), 210 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 211 /* 10 - 2880x480i@60Hz */ 212 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 213 3204, 3432, 480, 488, 494, 525, 0, 214 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 215 DRM_MODE_FLAG_INTERLACE), 216 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 217 /* 11 - 2880x480i@60Hz */ 218 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 219 3204, 3432, 480, 488, 494, 525, 0, 220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 221 DRM_MODE_FLAG_INTERLACE), 222 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 223 /* 12 - 2880x240@60Hz */ 224 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 225 3204, 3432, 240, 244, 247, 262, 0, 226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 228 /* 13 - 2880x240@60Hz */ 229 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 230 3204, 3432, 240, 244, 247, 262, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 232 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 233 /* 14 - 1440x480@60Hz */ 234 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 235 1596, 1716, 480, 489, 495, 525, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 237 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 238 /* 15 - 1440x480@60Hz */ 239 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 240 1596, 1716, 480, 489, 495, 525, 0, 241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 242 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 243 /* 16 - 1920x1080@60Hz */ 244 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 245 2052, 2200, 1080, 1084, 1089, 1125, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 247 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 248 /* 17 - 720x576@50Hz */ 249 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 250 796, 864, 576, 581, 586, 625, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 252 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 253 /* 18 - 720x576@50Hz */ 254 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 255 796, 864, 576, 581, 586, 625, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 257 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 258 /* 19 - 1280x720@50Hz */ 259 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 260 1760, 1980, 720, 725, 730, 750, 0, 261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 262 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 263 /* 20 - 1920x1080i@50Hz */ 264 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 265 2492, 2640, 1080, 1084, 1094, 1125, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 267 DRM_MODE_FLAG_INTERLACE), 268 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 269 /* 21 - 720(1440)x576i@50Hz */ 270 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 271 795, 864, 576, 580, 586, 625, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 273 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 274 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 275 /* 22 - 720(1440)x576i@50Hz */ 276 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 277 795, 864, 576, 580, 586, 625, 0, 278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 279 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 280 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 281 /* 23 - 720(1440)x288@50Hz */ 282 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 283 795, 864, 288, 290, 293, 312, 0, 284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 285 DRM_MODE_FLAG_DBLCLK), 286 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 287 /* 24 - 720(1440)x288@50Hz */ 288 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 289 795, 864, 288, 290, 293, 312, 0, 290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 291 DRM_MODE_FLAG_DBLCLK), 292 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 293 /* 25 - 2880x576i@50Hz */ 294 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 295 3180, 3456, 576, 580, 586, 625, 0, 296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 297 DRM_MODE_FLAG_INTERLACE), 298 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 299 /* 26 - 2880x576i@50Hz */ 300 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 301 3180, 3456, 576, 580, 586, 625, 0, 302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 303 DRM_MODE_FLAG_INTERLACE), 304 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 305 /* 27 - 2880x288@50Hz */ 306 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 307 3180, 3456, 288, 290, 293, 312, 0, 308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 309 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 310 /* 28 - 2880x288@50Hz */ 311 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 312 3180, 3456, 288, 290, 293, 312, 0, 313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 314 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 315 /* 29 - 1440x576@50Hz */ 316 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 317 1592, 1728, 576, 581, 586, 625, 0, 318 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 319 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 320 /* 30 - 1440x576@50Hz */ 321 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 322 1592, 1728, 576, 581, 586, 625, 0, 323 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 324 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 325 /* 31 - 1920x1080@50Hz */ 326 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 327 2492, 2640, 1080, 1084, 1089, 1125, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 329 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 330 /* 32 - 1920x1080@24Hz */ 331 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 332 2602, 2750, 1080, 1084, 1089, 1125, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 334 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 335 /* 33 - 1920x1080@25Hz */ 336 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 337 2492, 2640, 1080, 1084, 1089, 1125, 0, 338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 339 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 340 /* 34 - 1920x1080@30Hz */ 341 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 342 2052, 2200, 1080, 1084, 1089, 1125, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 344 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 345 /* 35 - 2880x480@60Hz */ 346 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 347 3192, 3432, 480, 489, 495, 525, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 349 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 350 /* 36 - 2880x480@60Hz */ 351 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 352 3192, 3432, 480, 489, 495, 525, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 354 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 355 /* 37 - 2880x576@50Hz */ 356 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 357 3184, 3456, 576, 581, 586, 625, 0, 358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 359 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 360 /* 38 - 2880x576@50Hz */ 361 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 362 3184, 3456, 576, 581, 586, 625, 0, 363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 364 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 365 /* 39 - 1920x1080i@50Hz */ 366 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 367 2120, 2304, 1080, 1126, 1136, 1250, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 369 DRM_MODE_FLAG_INTERLACE), 370 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 371 /* 40 - 1920x1080i@100Hz */ 372 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 373 2492, 2640, 1080, 1084, 1094, 1125, 0, 374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 375 DRM_MODE_FLAG_INTERLACE), 376 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 377 /* 41 - 1280x720@100Hz */ 378 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 379 1760, 1980, 720, 725, 730, 750, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 381 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 382 /* 42 - 720x576@100Hz */ 383 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 384 796, 864, 576, 581, 586, 625, 0, 385 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 386 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 387 /* 43 - 720x576@100Hz */ 388 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 389 796, 864, 576, 581, 586, 625, 0, 390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 391 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 392 /* 44 - 720(1440)x576i@100Hz */ 393 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 394 795, 864, 576, 580, 586, 625, 0, 395 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 396 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 397 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 398 /* 45 - 720(1440)x576i@100Hz */ 399 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 400 795, 864, 576, 580, 586, 625, 0, 401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 402 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 403 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 404 /* 46 - 1920x1080i@120Hz */ 405 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 406 2052, 2200, 1080, 1084, 1094, 1125, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 408 DRM_MODE_FLAG_INTERLACE), 409 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 410 /* 47 - 1280x720@120Hz */ 411 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 412 1430, 1650, 720, 725, 730, 750, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 414 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 415 /* 48 - 720x480@120Hz */ 416 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 417 798, 858, 480, 489, 495, 525, 0, 418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 419 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 420 /* 49 - 720x480@120Hz */ 421 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 422 798, 858, 480, 489, 495, 525, 0, 423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 424 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 425 /* 50 - 720(1440)x480i@120Hz */ 426 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 427 801, 858, 480, 488, 494, 525, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 429 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 430 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 431 /* 51 - 720(1440)x480i@120Hz */ 432 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 433 801, 858, 480, 488, 494, 525, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 435 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 436 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 437 /* 52 - 720x576@200Hz */ 438 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 439 796, 864, 576, 581, 586, 625, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 441 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 442 /* 53 - 720x576@200Hz */ 443 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 444 796, 864, 576, 581, 586, 625, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 446 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 447 /* 54 - 720(1440)x576i@200Hz */ 448 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 449 795, 864, 576, 580, 586, 625, 0, 450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 451 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 452 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 453 /* 55 - 720(1440)x576i@200Hz */ 454 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 455 795, 864, 576, 580, 586, 625, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 457 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 458 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 459 /* 56 - 720x480@240Hz */ 460 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 461 798, 858, 480, 489, 495, 525, 0, 462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 463 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 464 /* 57 - 720x480@240Hz */ 465 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 466 798, 858, 480, 489, 495, 525, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 468 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 469 /* 58 - 720(1440)x480i@240 */ 470 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 471 801, 858, 480, 488, 494, 525, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 473 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 474 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 475 /* 59 - 720(1440)x480i@240 */ 476 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 477 801, 858, 480, 488, 494, 525, 0, 478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 479 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 480 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 481 /* 60 - 1280x720@24Hz */ 482 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 483 3080, 3300, 720, 725, 730, 750, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 485 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 486 /* 61 - 1280x720@25Hz */ 487 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 488 3740, 3960, 720, 725, 730, 750, 0, 489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 490 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 491 /* 62 - 1280x720@30Hz */ 492 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 493 3080, 3300, 720, 725, 730, 750, 0, 494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 495 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 496 /* 63 - 1920x1080@120Hz */ 497 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 498 2052, 2200, 1080, 1084, 1089, 1125, 0, 499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 500 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 501 /* 64 - 1920x1080@100Hz */ 502 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 503 2492, 2640, 1080, 1084, 1089, 1125, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 505 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 506 /* 65 - 1280x720@24Hz */ 507 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 508 3080, 3300, 720, 725, 730, 750, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 510 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 511 /* 66 - 1280x720@25Hz */ 512 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 513 3740, 3960, 720, 725, 730, 750, 0, 514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 515 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 516 /* 67 - 1280x720@30Hz */ 517 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 518 3080, 3300, 720, 725, 730, 750, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 520 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 521 /* 68 - 1280x720@50Hz */ 522 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 523 1760, 1980, 720, 725, 730, 750, 0, 524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 525 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 526 /* 69 - 1280x720@60Hz */ 527 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 528 1430, 1650, 720, 725, 730, 750, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 530 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 531 /* 70 - 1280x720@100Hz */ 532 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 533 1760, 1980, 720, 725, 730, 750, 0, 534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 535 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 536 /* 71 - 1280x720@120Hz */ 537 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 538 1430, 1650, 720, 725, 730, 750, 0, 539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 540 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 541 /* 72 - 1920x1080@24Hz */ 542 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 543 2602, 2750, 1080, 1084, 1089, 1125, 0, 544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 545 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 546 /* 73 - 1920x1080@25Hz */ 547 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 548 2492, 2640, 1080, 1084, 1089, 1125, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 550 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 551 /* 74 - 1920x1080@30Hz */ 552 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 553 2052, 2200, 1080, 1084, 1089, 1125, 0, 554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 555 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 556 /* 75 - 1920x1080@50Hz */ 557 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 558 2492, 2640, 1080, 1084, 1089, 1125, 0, 559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 560 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 561 /* 76 - 1920x1080@60Hz */ 562 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 563 2052, 2200, 1080, 1084, 1089, 1125, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 565 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 566 /* 77 - 1920x1080@100Hz */ 567 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 568 2492, 2640, 1080, 1084, 1089, 1125, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 570 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 571 /* 78 - 1920x1080@120Hz */ 572 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 573 2052, 2200, 1080, 1084, 1089, 1125, 0, 574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 575 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 576 /* 79 - 1680x720@24Hz */ 577 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 578 3080, 3300, 720, 725, 730, 750, 0, 579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 580 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 581 /* 80 - 1680x720@25Hz */ 582 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 583 2948, 3168, 720, 725, 730, 750, 0, 584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 585 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 586 /* 81 - 1680x720@30Hz */ 587 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 588 2420, 2640, 720, 725, 730, 750, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 590 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 591 /* 82 - 1680x720@50Hz */ 592 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 593 1980, 2200, 720, 725, 730, 750, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 595 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 596 /* 83 - 1680x720@60Hz */ 597 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 598 1980, 2200, 720, 725, 730, 750, 0, 599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 600 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 601 /* 84 - 1680x720@100Hz */ 602 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 603 1780, 2000, 720, 725, 730, 825, 0, 604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 605 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 606 /* 85 - 1680x720@120Hz */ 607 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 608 1780, 2000, 720, 725, 730, 825, 0, 609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 610 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 611 /* 86 - 2560x1080@24Hz */ 612 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 613 3602, 3750, 1080, 1084, 1089, 1100, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 615 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 616 /* 87 - 2560x1080@25Hz */ 617 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 618 3052, 3200, 1080, 1084, 1089, 1125, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 620 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 621 /* 88 - 2560x1080@30Hz */ 622 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 623 3372, 3520, 1080, 1084, 1089, 1125, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 625 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 626 /* 89 - 2560x1080@50Hz */ 627 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 628 3152, 3300, 1080, 1084, 1089, 1125, 0, 629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 630 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 631 /* 90 - 2560x1080@60Hz */ 632 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 633 2852, 3000, 1080, 1084, 1089, 1100, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 635 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 636 /* 91 - 2560x1080@100Hz */ 637 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 638 2822, 2970, 1080, 1084, 1089, 1250, 0, 639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 640 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 641 /* 92 - 2560x1080@120Hz */ 642 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 643 3152, 3300, 1080, 1084, 1089, 1250, 0, 644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 645 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 646 /* 93 - 3840x2160p@24Hz 16:9 */ 647 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 648 5204, 5500, 2160, 2168, 2178, 2250, 0, 649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 650 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 651 /* 94 - 3840x2160p@25Hz 16:9 */ 652 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 653 4984, 5280, 2160, 2168, 2178, 2250, 0, 654 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 655 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 656 /* 95 - 3840x2160p@30Hz 16:9 */ 657 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 658 4104, 4400, 2160, 2168, 2178, 2250, 0, 659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 660 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 661 /* 96 - 3840x2160p@50Hz 16:9 */ 662 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 663 4984, 5280, 2160, 2168, 2178, 2250, 0, 664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 665 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 666 /* 97 - 3840x2160p@60Hz 16:9 */ 667 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 668 4104, 4400, 2160, 2168, 2178, 2250, 0, 669 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 671 /* 98 - 4096x2160p@24Hz 256:135 */ 672 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 673 5204, 5500, 2160, 2168, 2178, 2250, 0, 674 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 675 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 676 /* 99 - 4096x2160p@25Hz 256:135 */ 677 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 678 5152, 5280, 2160, 2168, 2178, 2250, 0, 679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 680 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 681 /* 100 - 4096x2160p@30Hz 256:135 */ 682 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 683 4272, 4400, 2160, 2168, 2178, 2250, 0, 684 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 685 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 686 /* 101 - 4096x2160p@50Hz 256:135 */ 687 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 688 5152, 5280, 2160, 2168, 2178, 2250, 0, 689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 690 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 691 /* 102 - 4096x2160p@60Hz 256:135 */ 692 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 693 4272, 4400, 2160, 2168, 2178, 2250, 0, 694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 696 /* 103 - 3840x2160p@24Hz 64:27 */ 697 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 698 5204, 5500, 2160, 2168, 2178, 2250, 0, 699 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 700 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 701 /* 104 - 3840x2160p@25Hz 64:27 */ 702 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 703 4104, 4400, 2160, 2168, 2178, 2250, 0, 704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 705 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 706 /* 105 - 3840x2160p@30Hz 64:27 */ 707 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 708 4104, 4400, 2160, 2168, 2178, 2250, 0, 709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 710 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 711 /* 106 - 3840x2160p@50Hz 64:27 */ 712 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 713 4984, 5280, 2160, 2168, 2178, 2250, 0, 714 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 715 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 716 /* 107 - 3840x2160p@60Hz 64:27 */ 717 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 718 4104, 4400, 2160, 2168, 2178, 2250, 0, 719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 721 /* 108 - 1280x720@48Hz 16:9 */ 722 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 723 2280, 2500, 720, 725, 730, 750, 0, 724 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 725 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 726 /* 109 - 1280x720@48Hz 64:27 */ 727 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 728 2280, 2500, 720, 725, 730, 750, 0, 729 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 730 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 731 /* 110 - 1680x720@48Hz 64:27 */ 732 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 733 2530, 2750, 720, 725, 730, 750, 0, 734 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 735 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 736 /* 111 - 1920x1080@48Hz 16:9 */ 737 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 738 2602, 2750, 1080, 1084, 1089, 1125, 0, 739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 740 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 112 - 1920x1080@48Hz 64:27 */ 742 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 743 2602, 2750, 1080, 1084, 1089, 1125, 0, 744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 745 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 746 /* 113 - 2560x1080@48Hz 64:27 */ 747 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 748 3602, 3750, 1080, 1084, 1089, 1100, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 751 /* 114 - 3840x2160@48Hz 16:9 */ 752 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 753 5204, 5500, 2160, 2168, 2178, 2250, 0, 754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 755 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 115 - 4096x2160@48Hz 256:135 */ 757 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 758 5204, 5500, 2160, 2168, 2178, 2250, 0, 759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 760 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 761 /* 116 - 3840x2160@48Hz 64:27 */ 762 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 763 5204, 5500, 2160, 2168, 2178, 2250, 0, 764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 765 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 766 /* 117 - 3840x2160@100Hz 16:9 */ 767 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 768 4984, 5280, 2160, 2168, 2178, 2250, 0, 769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 770 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 771 /* 118 - 3840x2160@120Hz 16:9 */ 772 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 773 4104, 4400, 2160, 2168, 2178, 2250, 0, 774 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 775 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 119 - 3840x2160@100Hz 64:27 */ 777 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 778 4984, 5280, 2160, 2168, 2178, 2250, 0, 779 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 780 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 781 /* 120 - 3840x2160@120Hz 64:27 */ 782 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 783 4104, 4400, 2160, 2168, 2178, 2250, 0, 784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 785 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 786 /* 121 - 5120x2160@24Hz 64:27 */ 787 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 788 7204, 7500, 2160, 2168, 2178, 2200, 0, 789 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 790 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 791 /* 122 - 5120x2160@25Hz 64:27 */ 792 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 793 6904, 7200, 2160, 2168, 2178, 2200, 0, 794 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 795 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 796 /* 123 - 5120x2160@30Hz 64:27 */ 797 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 798 5872, 6000, 2160, 2168, 2178, 2200, 0, 799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 800 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 801 /* 124 - 5120x2160@48Hz 64:27 */ 802 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 803 5954, 6250, 2160, 2168, 2178, 2475, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 806 /* 125 - 5120x2160@50Hz 64:27 */ 807 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 808 6304, 6600, 2160, 2168, 2178, 2250, 0, 809 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 811 /* 126 - 5120x2160@60Hz 64:27 */ 812 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 813 5372, 5500, 2160, 2168, 2178, 2250, 0, 814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 815 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 816 /* 127 - 5120x2160@100Hz 64:27 */ 817 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 818 6304, 6600, 2160, 2168, 2178, 2250, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 821 }; 822 823 static const struct drm_display_mode edid_cea_modes_193[] = { 824 /* 193 - 5120x2160@120Hz 64:27 */ 825 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 826 5372, 5500, 2160, 2168, 2178, 2250, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 829 /* 194 - 7680x4320@24Hz 16:9 */ 830 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 831 10408, 11000, 4320, 4336, 4356, 4500, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 833 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 195 - 7680x4320@25Hz 16:9 */ 835 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 836 10208, 10800, 4320, 4336, 4356, 4400, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 838 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 196 - 7680x4320@30Hz 16:9 */ 840 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 841 8408, 9000, 4320, 4336, 4356, 4400, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 843 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 844 /* 197 - 7680x4320@48Hz 16:9 */ 845 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 846 10408, 11000, 4320, 4336, 4356, 4500, 0, 847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 848 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 198 - 7680x4320@50Hz 16:9 */ 850 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 851 10208, 10800, 4320, 4336, 4356, 4400, 0, 852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 854 /* 199 - 7680x4320@60Hz 16:9 */ 855 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 856 8408, 9000, 4320, 4336, 4356, 4400, 0, 857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 858 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 200 - 7680x4320@100Hz 16:9 */ 860 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 861 9968, 10560, 4320, 4336, 4356, 4500, 0, 862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 863 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 201 - 7680x4320@120Hz 16:9 */ 865 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 866 8208, 8800, 4320, 4336, 4356, 4500, 0, 867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 868 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 202 - 7680x4320@24Hz 64:27 */ 870 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 871 10408, 11000, 4320, 4336, 4356, 4500, 0, 872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 873 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 874 /* 203 - 7680x4320@25Hz 64:27 */ 875 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 876 10208, 10800, 4320, 4336, 4356, 4400, 0, 877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 878 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 879 /* 204 - 7680x4320@30Hz 64:27 */ 880 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 881 8408, 9000, 4320, 4336, 4356, 4400, 0, 882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 883 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 884 /* 205 - 7680x4320@48Hz 64:27 */ 885 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 886 10408, 11000, 4320, 4336, 4356, 4500, 0, 887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 888 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 889 /* 206 - 7680x4320@50Hz 64:27 */ 890 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 891 10208, 10800, 4320, 4336, 4356, 4400, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 893 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 894 /* 207 - 7680x4320@60Hz 64:27 */ 895 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 896 8408, 9000, 4320, 4336, 4356, 4400, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 899 /* 208 - 7680x4320@100Hz 64:27 */ 900 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 901 9968, 10560, 4320, 4336, 4356, 4500, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 904 /* 209 - 7680x4320@120Hz 64:27 */ 905 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 906 8208, 8800, 4320, 4336, 4356, 4500, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 909 /* 210 - 10240x4320@24Hz 64:27 */ 910 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 911 11908, 12500, 4320, 4336, 4356, 4950, 0, 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 913 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 914 /* 211 - 10240x4320@25Hz 64:27 */ 915 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 916 12908, 13500, 4320, 4336, 4356, 4400, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 919 /* 212 - 10240x4320@30Hz 64:27 */ 920 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 921 10704, 11000, 4320, 4336, 4356, 4500, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 923 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 924 /* 213 - 10240x4320@48Hz 64:27 */ 925 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 926 11908, 12500, 4320, 4336, 4356, 4950, 0, 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 928 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 929 /* 214 - 10240x4320@50Hz 64:27 */ 930 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 931 12908, 13500, 4320, 4336, 4356, 4400, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 933 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 934 /* 215 - 10240x4320@60Hz 64:27 */ 935 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 936 10704, 11000, 4320, 4336, 4356, 4500, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 939 /* 216 - 10240x4320@100Hz 64:27 */ 940 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 941 12608, 13200, 4320, 4336, 4356, 4500, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 944 /* 217 - 10240x4320@120Hz 64:27 */ 945 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 946 10704, 11000, 4320, 4336, 4356, 4500, 0, 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 949 /* 218 - 4096x2160@100Hz 256:135 */ 950 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 951 4984, 5280, 2160, 2168, 2178, 2250, 0, 952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 953 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 954 /* 219 - 4096x2160@120Hz 256:135 */ 955 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 956 4272, 4400, 2160, 2168, 2178, 2250, 0, 957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 958 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 959 }; 960 961 /* 962 * HDMI 1.4 4k modes. Index using the VIC. 963 */ 964 static const struct drm_display_mode edid_4k_modes[] = { 965 /* 0 - dummy, VICs start at 1 */ 966 { }, 967 /* 1 - 3840x2160@30Hz */ 968 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 969 3840, 4016, 4104, 4400, 970 2160, 2168, 2178, 2250, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 2 - 3840x2160@25Hz */ 974 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 975 3840, 4896, 4984, 5280, 976 2160, 2168, 2178, 2250, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 978 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 979 /* 3 - 3840x2160@24Hz */ 980 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 981 3840, 5116, 5204, 5500, 982 2160, 2168, 2178, 2250, 0, 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 984 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 4 - 4096x2160@24Hz (SMPTE) */ 986 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 987 4096, 5116, 5204, 5500, 988 2160, 2168, 2178, 2250, 0, 989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 990 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 991 }; 992 993 /* 994 * Autogenerated from the DMT spec. 995 * This table is copied from xfree86/modes/xf86EdidModes.c. 996 */ 997 static const struct drm_display_mode drm_dmt_modes[] = { 998 /* 0x01 - 640x350@85Hz */ 999 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1000 736, 832, 350, 382, 385, 445, 0, 1001 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1002 /* 0x02 - 640x400@85Hz */ 1003 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1004 736, 832, 400, 401, 404, 445, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1006 /* 0x03 - 720x400@85Hz */ 1007 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 1008 828, 936, 400, 401, 404, 446, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1010 /* 0x04 - 640x480@60Hz */ 1011 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1012 752, 800, 480, 490, 492, 525, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1014 /* 0x05 - 640x480@72Hz */ 1015 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1016 704, 832, 480, 489, 492, 520, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1018 /* 0x06 - 640x480@75Hz */ 1019 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1020 720, 840, 480, 481, 484, 500, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1022 /* 0x07 - 640x480@85Hz */ 1023 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 1024 752, 832, 480, 481, 484, 509, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1026 /* 0x08 - 800x600@56Hz */ 1027 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1028 896, 1024, 600, 601, 603, 625, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1030 /* 0x09 - 800x600@60Hz */ 1031 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1032 968, 1056, 600, 601, 605, 628, 0, 1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1034 /* 0x0a - 800x600@72Hz */ 1035 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1036 976, 1040, 600, 637, 643, 666, 0, 1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1038 /* 0x0b - 800x600@75Hz */ 1039 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1040 896, 1056, 600, 601, 604, 625, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1042 /* 0x0c - 800x600@85Hz */ 1043 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 1044 896, 1048, 600, 601, 604, 631, 0, 1045 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1046 /* 0x0d - 800x600@120Hz RB */ 1047 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 1048 880, 960, 600, 603, 607, 636, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1050 /* 0x0e - 848x480@60Hz */ 1051 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 1052 976, 1088, 480, 486, 494, 517, 0, 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1054 /* 0x0f - 1024x768@43Hz, interlace */ 1055 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1056 1208, 1264, 768, 768, 772, 817, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1058 DRM_MODE_FLAG_INTERLACE) }, 1059 /* 0x10 - 1024x768@60Hz */ 1060 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1061 1184, 1344, 768, 771, 777, 806, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1063 /* 0x11 - 1024x768@70Hz */ 1064 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1065 1184, 1328, 768, 771, 777, 806, 0, 1066 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1067 /* 0x12 - 1024x768@75Hz */ 1068 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1069 1136, 1312, 768, 769, 772, 800, 0, 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1071 /* 0x13 - 1024x768@85Hz */ 1072 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 1073 1168, 1376, 768, 769, 772, 808, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1075 /* 0x14 - 1024x768@120Hz RB */ 1076 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 1077 1104, 1184, 768, 771, 775, 813, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1079 /* 0x15 - 1152x864@75Hz */ 1080 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1081 1344, 1600, 864, 865, 868, 900, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1083 /* 0x55 - 1280x720@60Hz */ 1084 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1085 1430, 1650, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1087 /* 0x16 - 1280x768@60Hz RB */ 1088 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 1089 1360, 1440, 768, 771, 778, 790, 0, 1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1091 /* 0x17 - 1280x768@60Hz */ 1092 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 1093 1472, 1664, 768, 771, 778, 798, 0, 1094 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1095 /* 0x18 - 1280x768@75Hz */ 1096 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 1097 1488, 1696, 768, 771, 778, 805, 0, 1098 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1099 /* 0x19 - 1280x768@85Hz */ 1100 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 1101 1496, 1712, 768, 771, 778, 809, 0, 1102 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1103 /* 0x1a - 1280x768@120Hz RB */ 1104 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 1105 1360, 1440, 768, 771, 778, 813, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1107 /* 0x1b - 1280x800@60Hz RB */ 1108 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 1109 1360, 1440, 800, 803, 809, 823, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1111 /* 0x1c - 1280x800@60Hz */ 1112 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 1113 1480, 1680, 800, 803, 809, 831, 0, 1114 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1115 /* 0x1d - 1280x800@75Hz */ 1116 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 1117 1488, 1696, 800, 803, 809, 838, 0, 1118 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1119 /* 0x1e - 1280x800@85Hz */ 1120 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 1121 1496, 1712, 800, 803, 809, 843, 0, 1122 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1123 /* 0x1f - 1280x800@120Hz RB */ 1124 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 1125 1360, 1440, 800, 803, 809, 847, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1127 /* 0x20 - 1280x960@60Hz */ 1128 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 1129 1488, 1800, 960, 961, 964, 1000, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1131 /* 0x21 - 1280x960@85Hz */ 1132 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 1133 1504, 1728, 960, 961, 964, 1011, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1135 /* 0x22 - 1280x960@120Hz RB */ 1136 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 1137 1360, 1440, 960, 963, 967, 1017, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1139 /* 0x23 - 1280x1024@60Hz */ 1140 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 1141 1440, 1688, 1024, 1025, 1028, 1066, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1143 /* 0x24 - 1280x1024@75Hz */ 1144 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1145 1440, 1688, 1024, 1025, 1028, 1066, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1147 /* 0x25 - 1280x1024@85Hz */ 1148 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 1149 1504, 1728, 1024, 1025, 1028, 1072, 0, 1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1151 /* 0x26 - 1280x1024@120Hz RB */ 1152 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 1153 1360, 1440, 1024, 1027, 1034, 1084, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1155 /* 0x27 - 1360x768@60Hz */ 1156 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 1157 1536, 1792, 768, 771, 777, 795, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1159 /* 0x28 - 1360x768@120Hz RB */ 1160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 1161 1440, 1520, 768, 771, 776, 813, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1163 /* 0x51 - 1366x768@60Hz */ 1164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 1165 1579, 1792, 768, 771, 774, 798, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1167 /* 0x56 - 1366x768@60Hz */ 1168 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 1169 1436, 1500, 768, 769, 772, 800, 0, 1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1171 /* 0x29 - 1400x1050@60Hz RB */ 1172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 1173 1480, 1560, 1050, 1053, 1057, 1080, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1175 /* 0x2a - 1400x1050@60Hz */ 1176 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 1177 1632, 1864, 1050, 1053, 1057, 1089, 0, 1178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1179 /* 0x2b - 1400x1050@75Hz */ 1180 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 1181 1648, 1896, 1050, 1053, 1057, 1099, 0, 1182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1183 /* 0x2c - 1400x1050@85Hz */ 1184 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 1185 1656, 1912, 1050, 1053, 1057, 1105, 0, 1186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1187 /* 0x2d - 1400x1050@120Hz RB */ 1188 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 1189 1480, 1560, 1050, 1053, 1057, 1112, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1191 /* 0x2e - 1440x900@60Hz RB */ 1192 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 1193 1520, 1600, 900, 903, 909, 926, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1195 /* 0x2f - 1440x900@60Hz */ 1196 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 1197 1672, 1904, 900, 903, 909, 934, 0, 1198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1199 /* 0x30 - 1440x900@75Hz */ 1200 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 1201 1688, 1936, 900, 903, 909, 942, 0, 1202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1203 /* 0x31 - 1440x900@85Hz */ 1204 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 1205 1696, 1952, 900, 903, 909, 948, 0, 1206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1207 /* 0x32 - 1440x900@120Hz RB */ 1208 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 1209 1520, 1600, 900, 903, 909, 953, 0, 1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1211 /* 0x53 - 1600x900@60Hz */ 1212 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 1213 1704, 1800, 900, 901, 904, 1000, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1215 /* 0x33 - 1600x1200@60Hz */ 1216 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 1217 1856, 2160, 1200, 1201, 1204, 1250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1219 /* 0x34 - 1600x1200@65Hz */ 1220 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 1221 1856, 2160, 1200, 1201, 1204, 1250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1223 /* 0x35 - 1600x1200@70Hz */ 1224 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 1225 1856, 2160, 1200, 1201, 1204, 1250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1227 /* 0x36 - 1600x1200@75Hz */ 1228 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 1229 1856, 2160, 1200, 1201, 1204, 1250, 0, 1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1231 /* 0x37 - 1600x1200@85Hz */ 1232 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 1233 1856, 2160, 1200, 1201, 1204, 1250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1235 /* 0x38 - 1600x1200@120Hz RB */ 1236 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 1237 1680, 1760, 1200, 1203, 1207, 1271, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1239 /* 0x39 - 1680x1050@60Hz RB */ 1240 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1241 1760, 1840, 1050, 1053, 1059, 1080, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1243 /* 0x3a - 1680x1050@60Hz */ 1244 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1245 1960, 2240, 1050, 1053, 1059, 1089, 0, 1246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1247 /* 0x3b - 1680x1050@75Hz */ 1248 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1249 1976, 2272, 1050, 1053, 1059, 1099, 0, 1250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1251 /* 0x3c - 1680x1050@85Hz */ 1252 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1253 1984, 2288, 1050, 1053, 1059, 1105, 0, 1254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1255 /* 0x3d - 1680x1050@120Hz RB */ 1256 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1257 1760, 1840, 1050, 1053, 1059, 1112, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1259 /* 0x3e - 1792x1344@60Hz */ 1260 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1261 2120, 2448, 1344, 1345, 1348, 1394, 0, 1262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1263 /* 0x3f - 1792x1344@75Hz */ 1264 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1265 2104, 2456, 1344, 1345, 1348, 1417, 0, 1266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1267 /* 0x40 - 1792x1344@120Hz RB */ 1268 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1269 1872, 1952, 1344, 1347, 1351, 1423, 0, 1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1271 /* 0x41 - 1856x1392@60Hz */ 1272 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1273 2176, 2528, 1392, 1393, 1396, 1439, 0, 1274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1275 /* 0x42 - 1856x1392@75Hz */ 1276 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1277 2208, 2560, 1392, 1393, 1396, 1500, 0, 1278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1279 /* 0x43 - 1856x1392@120Hz RB */ 1280 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1281 1936, 2016, 1392, 1395, 1399, 1474, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1283 /* 0x52 - 1920x1080@60Hz */ 1284 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1285 2052, 2200, 1080, 1084, 1089, 1125, 0, 1286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1287 /* 0x44 - 1920x1200@60Hz RB */ 1288 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1289 2000, 2080, 1200, 1203, 1209, 1235, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1291 /* 0x45 - 1920x1200@60Hz */ 1292 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1293 2256, 2592, 1200, 1203, 1209, 1245, 0, 1294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1295 /* 0x46 - 1920x1200@75Hz */ 1296 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1297 2264, 2608, 1200, 1203, 1209, 1255, 0, 1298 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1299 /* 0x47 - 1920x1200@85Hz */ 1300 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1301 2272, 2624, 1200, 1203, 1209, 1262, 0, 1302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1303 /* 0x48 - 1920x1200@120Hz RB */ 1304 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1305 2000, 2080, 1200, 1203, 1209, 1271, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1307 /* 0x49 - 1920x1440@60Hz */ 1308 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1309 2256, 2600, 1440, 1441, 1444, 1500, 0, 1310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1311 /* 0x4a - 1920x1440@75Hz */ 1312 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1313 2288, 2640, 1440, 1441, 1444, 1500, 0, 1314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1315 /* 0x4b - 1920x1440@120Hz RB */ 1316 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1317 2000, 2080, 1440, 1443, 1447, 1525, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1319 /* 0x54 - 2048x1152@60Hz */ 1320 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1321 2154, 2250, 1152, 1153, 1156, 1200, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1323 /* 0x4c - 2560x1600@60Hz RB */ 1324 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1325 2640, 2720, 1600, 1603, 1609, 1646, 0, 1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1327 /* 0x4d - 2560x1600@60Hz */ 1328 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1329 3032, 3504, 1600, 1603, 1609, 1658, 0, 1330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1331 /* 0x4e - 2560x1600@75Hz */ 1332 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1333 3048, 3536, 1600, 1603, 1609, 1672, 0, 1334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1335 /* 0x4f - 2560x1600@85Hz */ 1336 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1337 3048, 3536, 1600, 1603, 1609, 1682, 0, 1338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1339 /* 0x50 - 2560x1600@120Hz RB */ 1340 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1341 2640, 2720, 1600, 1603, 1609, 1694, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1343 /* 0x57 - 4096x2160@60Hz RB */ 1344 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1345 4136, 4176, 2160, 2208, 2216, 2222, 0, 1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1347 /* 0x58 - 4096x2160@59.94Hz RB */ 1348 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1349 4136, 4176, 2160, 2208, 2216, 2222, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1351 }; 1352 1353 /* 1354 * These more or less come from the DMT spec. The 720x400 modes are 1355 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1356 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1357 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1358 * mode. 1359 * 1360 * The DMT modes have been fact-checked; the rest are mild guesses. 1361 */ 1362 static const struct drm_display_mode edid_est_modes[] = { 1363 /* 800x600@60Hz */ 1364 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1365 968, 1056, 600, 601, 605, 628, 0, 1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1367 /* 800x600@56Hz */ 1368 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1369 896, 1024, 600, 601, 603, 625, 0, 1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1371 /* 640x480@75Hz */ 1372 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1373 720, 840, 480, 481, 484, 500, 0, 1374 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1375 /* 640x480@72Hz */ 1376 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1377 704, 832, 480, 489, 492, 520, 0, 1378 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1379 /* 640x480@67Hz */ 1380 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1381 768, 864, 480, 483, 486, 525, 0, 1382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1383 /* 640x480@60Hz */ 1384 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1385 752, 800, 480, 490, 492, 525, 0, 1386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1387 /* 720x400@88Hz */ 1388 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1389 846, 900, 400, 421, 423, 449, 0, 1390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1391 /* 720x400@70Hz */ 1392 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1393 846, 900, 400, 412, 414, 449, 0, 1394 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1395 /* 1280x1024@75Hz */ 1396 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1397 1440, 1688, 1024, 1025, 1028, 1066, 0, 1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1399 /* 1024x768@75Hz */ 1400 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1401 1136, 1312, 768, 769, 772, 800, 0, 1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1403 /* 1024x768@70Hz */ 1404 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1405 1184, 1328, 768, 771, 777, 806, 0, 1406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1407 /* 1024x768@60Hz */ 1408 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1409 1184, 1344, 768, 771, 777, 806, 0, 1410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1411 /* 1024x768@43Hz */ 1412 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1413 1208, 1264, 768, 768, 776, 817, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1415 DRM_MODE_FLAG_INTERLACE) }, 1416 /* 832x624@75Hz */ 1417 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1418 928, 1152, 624, 625, 628, 667, 0, 1419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1420 /* 800x600@75Hz */ 1421 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1422 896, 1056, 600, 601, 604, 625, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1424 /* 800x600@72Hz */ 1425 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1426 976, 1040, 600, 637, 643, 666, 0, 1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1428 /* 1152x864@75Hz */ 1429 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1430 1344, 1600, 864, 865, 868, 900, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1432 }; 1433 1434 #define DRM_BASE_MODE(c, hd, hss, hse, ht, vd, vss, vse, vt, vs, f) \ 1435 .clock = (c), \ 1436 .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ 1437 .htotal = (ht), .vdisplay = (vd), \ 1438 .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ 1439 .vscan = (vs), .flags = (f) 1440 1441 static const struct base_drm_display_mode resolution_white[] = { 1442 /* 0. vic:2 - 720x480@60Hz */ 1443 { DRM_BASE_MODE(27000, 720, 736, 1444 798, 858, 480, 489, 495, 525, 0, 1445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1446 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1447 /* 1. vic:3 - 720x480@60Hz */ 1448 { DRM_BASE_MODE(27000, 720, 736, 1449 798, 858, 480, 489, 495, 525, 0, 1450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1451 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1452 /* 1024x768@60Hz */ 1453 { DRM_BASE_MODE(65000, 1024, 1048, 1454 1184, 1344, 768, 771, 777, 806, 0, 1455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1456 /* 2. vic:4 - 1280x720@60Hz */ 1457 { DRM_BASE_MODE(74250, 1280, 1390, 1458 1430, 1650, 720, 725, 730, 750, 0, 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1460 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1461 /* 3. vic:5 - 1920x1080i@60Hz */ 1462 { DRM_BASE_MODE(74250, 1920, 2008, 1463 2052, 2200, 1080, 1084, 1094, 1125, 0, 1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1465 DRM_MODE_FLAG_INTERLACE), 1466 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1467 /* 4. vic:6 - 720(1440)x480i@60Hz */ 1468 { DRM_BASE_MODE(13500, 720, 739, 1469 801, 858, 480, 488, 494, 525, 0, 1470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1471 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1472 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1473 /* 5. vic:16 - 1920x1080@60Hz */ 1474 { DRM_BASE_MODE(148500, 1920, 2008, 1475 2052, 2200, 1080, 1084, 1089, 1125, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1478 /* 6. vic:17 - 720x576@50Hz */ 1479 { DRM_BASE_MODE(27000, 720, 732, 1480 796, 864, 576, 581, 586, 625, 0, 1481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1482 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1483 /* 7. vic:18 - 720x576@50Hz */ 1484 { DRM_BASE_MODE(27000, 720, 732, 1485 796, 864, 576, 581, 586, 625, 0, 1486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1487 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1488 /* 8. vic:19 - 1280x720@50Hz */ 1489 { DRM_BASE_MODE(74250, 1280, 1720, 1490 1760, 1980, 720, 725, 730, 750, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1493 /* 9. vic:20 - 1920x1080i@50Hz */ 1494 { DRM_BASE_MODE(74250, 1920, 2448, 1495 2492, 2640, 1080, 1084, 1094, 1125, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1497 DRM_MODE_FLAG_INTERLACE), 1498 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1499 /* 10. vic:21 - 720(1440)x576i@50Hz */ 1500 { DRM_BASE_MODE(13500, 720, 732, 1501 795, 864, 576, 580, 586, 625, 0, 1502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1503 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1504 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1505 /* 11. vic:31 - 1920x1080@50Hz */ 1506 { DRM_BASE_MODE(148500, 1920, 2448, 1507 2492, 2640, 1080, 1084, 1089, 1125, 0, 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1509 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1510 /* 12. vic:32 - 1920x1080@24Hz */ 1511 { DRM_BASE_MODE(74250, 1920, 2558, 1512 2602, 2750, 1080, 1084, 1089, 1125, 0, 1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1514 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1515 /* 13. vic:33 - 1920x1080@25Hz */ 1516 { DRM_BASE_MODE(74250, 1920, 2448, 1517 2492, 2640, 1080, 1084, 1089, 1125, 0, 1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1519 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1520 /* 14. vic:34 - 1920x1080@30Hz */ 1521 { DRM_BASE_MODE(74250, 1920, 2008, 1522 2052, 2200, 1080, 1084, 1089, 1125, 0, 1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1524 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1525 /* 15. vic:39 - 1920x1080i@50Hz */ 1526 { DRM_BASE_MODE(72000, 1920, 1952, 1527 2120, 2304, 1080, 1126, 1136, 1250, 0, 1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 1529 DRM_MODE_FLAG_INTERLACE), 1530 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1531 /* 16. vic:60 - 1280x720@24Hz */ 1532 { DRM_BASE_MODE(59400, 1280, 3040, 1533 3080, 3300, 720, 725, 730, 750, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1536 /* 17. vic:61 - 1280x720@25Hz */ 1537 { DRM_BASE_MODE(74250, 1280, 3700, 1538 3740, 3960, 720, 725, 730, 750, 0, 1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1540 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1541 /* 18. vic:62 - 1280x720@30Hz */ 1542 { DRM_BASE_MODE(74250, 1280, 3040, 1543 3080, 3300, 720, 725, 730, 750, 0, 1544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1545 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1546 /* 19. vic:93 - 3840x2160p@24Hz 16:9 */ 1547 { DRM_BASE_MODE(297000, 3840, 5116, 1548 5204, 5500, 2160, 2168, 2178, 2250, 0, 1549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1550 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1551 /* 20. vic:94 - 3840x2160p@25Hz 16:9 */ 1552 { DRM_BASE_MODE(297000, 3840, 4896, 1553 4984, 5280, 2160, 2168, 2178, 2250, 0, 1554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1555 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1556 /* 21. vic:95 - 3840x2160p@30Hz 16:9 */ 1557 { DRM_BASE_MODE(297000, 3840, 4016, 1558 4104, 4400, 2160, 2168, 2178, 2250, 0, 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1560 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1561 /* 22. vic:96 - 3840x2160p@50Hz 16:9 */ 1562 { DRM_BASE_MODE(594000, 3840, 4896, 1563 4984, 5280, 2160, 2168, 2178, 2250, 0, 1564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1565 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1566 /* 23. vic:97 - 3840x2160p@60Hz 16:9 */ 1567 { DRM_BASE_MODE(594000, 3840, 4016, 1568 4104, 4400, 2160, 2168, 2178, 2250, 0, 1569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1570 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1571 /* 24. vic:98 - 4096x2160p@24Hz 256:135 */ 1572 { DRM_BASE_MODE(297000, 4096, 5116, 1573 5204, 5500, 2160, 2168, 2178, 2250, 0, 1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1575 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1576 /* 25. vic:99 - 4096x2160p@25Hz 256:135 */ 1577 { DRM_BASE_MODE(297000, 4096, 5064, 1578 5152, 5280, 2160, 2168, 2178, 2250, 0, 1579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1580 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1581 /* 26. vic:100 - 4096x2160p@30Hz 256:135 */ 1582 { DRM_BASE_MODE(297000, 4096, 4184, 1583 4272, 4400, 2160, 2168, 2178, 2250, 0, 1584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1585 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1586 /* 27. vic:101 - 4096x2160p@50Hz 256:135 */ 1587 { DRM_BASE_MODE(594000, 4096, 5064, 1588 5152, 5280, 2160, 2168, 2178, 2250, 0, 1589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1590 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1591 /* 28. vic:102 - 4096x2160p@60Hz 256:135 */ 1592 { DRM_BASE_MODE(594000, 4096, 4184, 1593 4272, 4400, 2160, 2168, 2178, 2250, 0, 1594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1595 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1596 /* 29. vic:118 - 3840x2160@120Hz 16:9 */ 1597 { DRM_BASE_MODE(1188000, 3840, 4016, 1598 4104, 4400, 2160, 2168, 2178, 2250, 0, 1599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1600 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1601 /* 30. vic:196 - 7680x4320@30Hz 16:9 */ 1602 { DRM_BASE_MODE(1188000, 7680, 8232, 1603 8408, 9000, 4320, 4336, 4356, 4400, 0, 1604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1605 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1606 /* 31. vic:198 - 7680x4320@50Hz 16:9 */ 1607 { DRM_BASE_MODE(2376000, 7680, 10032, 1608 10208, 10800, 4320, 4336, 4356, 4400, 0, 1609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1610 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1611 /* 32. vic:199 - 7680x4320@60Hz 16:9 */ 1612 { DRM_BASE_MODE(2376000, 7680, 8232, 1613 8408, 9000, 4320, 4336, 4356, 4400, 0, 1614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1615 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1616 }; 1617 1618 struct minimode { 1619 short w; 1620 short h; 1621 short r; 1622 short rb; 1623 }; 1624 1625 static const struct minimode est3_modes[] = { 1626 /* byte 6 */ 1627 { 640, 350, 85, 0 }, 1628 { 640, 400, 85, 0 }, 1629 { 720, 400, 85, 0 }, 1630 { 640, 480, 85, 0 }, 1631 { 848, 480, 60, 0 }, 1632 { 800, 600, 85, 0 }, 1633 { 1024, 768, 85, 0 }, 1634 { 1152, 864, 75, 0 }, 1635 /* byte 7 */ 1636 { 1280, 768, 60, 1 }, 1637 { 1280, 768, 60, 0 }, 1638 { 1280, 768, 75, 0 }, 1639 { 1280, 768, 85, 0 }, 1640 { 1280, 960, 60, 0 }, 1641 { 1280, 960, 85, 0 }, 1642 { 1280, 1024, 60, 0 }, 1643 { 1280, 1024, 85, 0 }, 1644 /* byte 8 */ 1645 { 1360, 768, 60, 0 }, 1646 { 1440, 900, 60, 1 }, 1647 { 1440, 900, 60, 0 }, 1648 { 1440, 900, 75, 0 }, 1649 { 1440, 900, 85, 0 }, 1650 { 1400, 1050, 60, 1 }, 1651 { 1400, 1050, 60, 0 }, 1652 { 1400, 1050, 75, 0 }, 1653 /* byte 9 */ 1654 { 1400, 1050, 85, 0 }, 1655 { 1680, 1050, 60, 1 }, 1656 { 1680, 1050, 60, 0 }, 1657 { 1680, 1050, 75, 0 }, 1658 { 1680, 1050, 85, 0 }, 1659 { 1600, 1200, 60, 0 }, 1660 { 1600, 1200, 65, 0 }, 1661 { 1600, 1200, 70, 0 }, 1662 /* byte 10 */ 1663 { 1600, 1200, 75, 0 }, 1664 { 1600, 1200, 85, 0 }, 1665 { 1792, 1344, 60, 0 }, 1666 { 1792, 1344, 75, 0 }, 1667 { 1856, 1392, 60, 0 }, 1668 { 1856, 1392, 75, 0 }, 1669 { 1920, 1200, 60, 1 }, 1670 { 1920, 1200, 60, 0 }, 1671 /* byte 11 */ 1672 { 1920, 1200, 75, 0 }, 1673 { 1920, 1200, 85, 0 }, 1674 { 1920, 1440, 60, 0 }, 1675 { 1920, 1440, 75, 0 }, 1676 }; 1677 1678 static const struct minimode extra_modes[] = { 1679 { 1024, 576, 60, 0 }, 1680 { 1366, 768, 60, 0 }, 1681 { 1600, 900, 60, 0 }, 1682 { 1680, 945, 60, 0 }, 1683 { 1920, 1080, 60, 0 }, 1684 { 2048, 1152, 60, 0 }, 1685 { 2048, 1536, 60, 0 }, 1686 }; 1687 1688 static const struct drm_display_mode *cea_mode_for_vic(u8 vic) 1689 { 1690 if (!vic) 1691 return NULL; 1692 else if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 1693 return &edid_cea_modes_1[vic - 1]; 1694 else if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 1695 return &edid_cea_modes_193[vic - 193]; 1696 1697 return NULL; 1698 } 1699 1700 static u8 cea_num_vics(void) 1701 { 1702 return 193 + ARRAY_SIZE(edid_cea_modes_193); 1703 } 1704 1705 static u8 cea_next_vic(u8 vic) 1706 { 1707 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 1708 vic = 193; 1709 1710 return vic; 1711 } 1712 1713 int edid_check_info(struct edid1_info *edid_info) 1714 { 1715 if ((edid_info == NULL) || (edid_info->version == 0)) 1716 return -1; 1717 1718 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1719 return -1; 1720 1721 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1722 return -1; 1723 1724 return 0; 1725 } 1726 1727 int edid_check_checksum(u8 *edid_block) 1728 { 1729 u8 checksum = 0; 1730 int i; 1731 1732 for (i = 0; i < 128; i++) 1733 checksum += edid_block[i]; 1734 1735 return (checksum == 0) ? 0 : -EINVAL; 1736 } 1737 1738 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1739 unsigned int *hmax, unsigned int *vmin, 1740 unsigned int *vmax) 1741 { 1742 int i; 1743 struct edid_monitor_descriptor *monitor; 1744 1745 *hmin = *hmax = *vmin = *vmax = 0; 1746 if (edid_check_info(edid)) 1747 return -1; 1748 1749 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1750 monitor = &edid->monitor_details.descriptor[i]; 1751 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1752 *hmin = monitor->data.range_data.horizontal_min; 1753 *hmax = monitor->data.range_data.horizontal_max; 1754 *vmin = monitor->data.range_data.vertical_min; 1755 *vmax = monitor->data.range_data.vertical_max; 1756 return 0; 1757 } 1758 } 1759 return -1; 1760 } 1761 1762 /* Set all parts of a timing entry to the same value */ 1763 static void set_entry(struct timing_entry *entry, u32 value) 1764 { 1765 entry->min = value; 1766 entry->typ = value; 1767 entry->max = value; 1768 } 1769 1770 /** 1771 * decode_timing() - Decoding an 18-byte detailed timing record 1772 * 1773 * @buf: Pointer to EDID detailed timing record 1774 * @timing: Place to put timing 1775 */ 1776 static void decode_timing(u8 *buf, struct display_timing *timing) 1777 { 1778 uint x_mm, y_mm; 1779 unsigned int ha, hbl, hso, hspw, hborder; 1780 unsigned int va, vbl, vso, vspw, vborder; 1781 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1782 1783 /* Edid contains pixel clock in terms of 10KHz */ 1784 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1785 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1786 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1787 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1788 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1789 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1790 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1791 hborder = buf[15]; 1792 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1793 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1794 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1795 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1796 vborder = buf[16]; 1797 1798 set_entry(&timing->hactive, ha); 1799 set_entry(&timing->hfront_porch, hso); 1800 set_entry(&timing->hback_porch, hbl - hso - hspw); 1801 set_entry(&timing->hsync_len, hspw); 1802 1803 set_entry(&timing->vactive, va); 1804 set_entry(&timing->vfront_porch, vso); 1805 set_entry(&timing->vback_porch, vbl - vso - vspw); 1806 set_entry(&timing->vsync_len, vspw); 1807 1808 timing->flags = 0; 1809 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1810 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1811 else 1812 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1813 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1814 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1815 else 1816 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1817 1818 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1819 timing->flags = DISPLAY_FLAGS_INTERLACED; 1820 1821 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1822 " %04x %04x %04x %04x hborder %x\n" 1823 " %04x %04x %04x %04x vborder %x\n", 1824 timing->pixelclock.typ, 1825 x_mm, y_mm, 1826 ha, ha + hso, ha + hso + hspw, 1827 ha + hbl, hborder, 1828 va, va + vso, va + vso + vspw, 1829 va + vbl, vborder); 1830 } 1831 1832 /** 1833 * decode_mode() - Decoding an 18-byte detailed timing record 1834 * 1835 * @buf: Pointer to EDID detailed timing record 1836 * @timing: Place to put timing 1837 */ 1838 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1839 { 1840 uint x_mm, y_mm; 1841 unsigned int ha, hbl, hso, hspw, hborder; 1842 unsigned int va, vbl, vso, vspw, vborder; 1843 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1844 1845 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1846 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1847 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1848 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1849 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1850 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1851 hborder = buf[15]; 1852 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1853 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1854 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1855 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1856 vborder = buf[16]; 1857 1858 /* Edid contains pixel clock in terms of 10KHz */ 1859 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1860 mode->hdisplay = ha; 1861 mode->hsync_start = ha + hso; 1862 mode->hsync_end = ha + hso + hspw; 1863 mode->htotal = ha + hbl; 1864 mode->vdisplay = va; 1865 mode->vsync_start = va + vso; 1866 mode->vsync_end = va + vso + vspw; 1867 mode->vtotal = va + vbl; 1868 1869 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1870 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1871 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1872 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1873 1874 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1875 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1876 1877 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1878 " %04d %04d %04d %04d hborder %d\n" 1879 " %04d %04d %04d %04d vborder %d\n", 1880 mode->clock, 1881 x_mm, y_mm, mode->flags, 1882 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1883 mode->htotal, hborder, 1884 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1885 mode->vtotal, vborder); 1886 } 1887 1888 /** 1889 * edid_vendor - match a string against EDID's obfuscated vendor field 1890 * @edid: EDID to match 1891 * @vendor: vendor string 1892 * 1893 * Returns true if @vendor is in @edid, false otherwise 1894 */ 1895 static bool edid_vendor(struct edid *edid, char *vendor) 1896 { 1897 char edid_vendor[3]; 1898 1899 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1900 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1901 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1902 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1903 1904 return !strncmp(edid_vendor, vendor, 3); 1905 } 1906 1907 /** 1908 * Check if HDMI vendor specific data block is present in CEA block 1909 * @param info CEA extension block 1910 * @return true if block is found 1911 */ 1912 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1913 { 1914 u8 end, i = 0; 1915 1916 /* check for end of data block */ 1917 end = info->dtd_offset; 1918 if (end == 0) 1919 end = sizeof(info->data); 1920 if (end < 4 || end > sizeof(info->data)) 1921 return false; 1922 end -= 4; 1923 1924 while (i < end) { 1925 /* Look for vendor specific data block of appropriate size */ 1926 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1927 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1928 u8 *db = &info->data[i + 1]; 1929 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1930 1931 if (oui == HDMI_IEEE_OUI) 1932 return true; 1933 } 1934 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1935 } 1936 1937 return false; 1938 } 1939 1940 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1941 { 1942 int refresh = 0; 1943 unsigned int calc_val; 1944 1945 if (mode->vrefresh > 0) { 1946 refresh = mode->vrefresh; 1947 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1948 int vtotal; 1949 1950 vtotal = mode->vtotal; 1951 /* work out vrefresh the value will be x1000 */ 1952 calc_val = (mode->clock * 1000); 1953 calc_val /= mode->htotal; 1954 refresh = (calc_val + vtotal / 2) / vtotal; 1955 1956 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1957 refresh *= 2; 1958 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1959 refresh /= 2; 1960 if (mode->vscan > 1) 1961 refresh /= mode->vscan; 1962 } 1963 return refresh; 1964 } 1965 1966 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1967 int *panel_bits_per_colourp) 1968 { 1969 struct edid1_info *edid = (struct edid1_info *)buf; 1970 bool timing_done; 1971 int i; 1972 1973 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1974 debug("%s: Invalid buffer\n", __func__); 1975 return -EINVAL; 1976 } 1977 1978 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1979 debug("%s: No preferred timing\n", __func__); 1980 return -ENOENT; 1981 } 1982 1983 /* Look for detailed timing */ 1984 timing_done = false; 1985 for (i = 0; i < 4; i++) { 1986 struct edid_monitor_descriptor *desc; 1987 1988 desc = &edid->monitor_details.descriptor[i]; 1989 if (desc->zero_flag_1 != 0) { 1990 decode_mode((u8 *)desc, mode); 1991 timing_done = true; 1992 break; 1993 } 1994 } 1995 if (!timing_done) 1996 return -EINVAL; 1997 1998 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1999 debug("%s: Not a digital display\n", __func__); 2000 return -ENOSYS; 2001 } 2002 if (edid->version != 1 || edid->revision < 4) { 2003 debug("%s: EDID version %d.%d does not have required info\n", 2004 __func__, edid->version, edid->revision); 2005 *panel_bits_per_colourp = -1; 2006 } else { 2007 *panel_bits_per_colourp = 2008 ((edid->video_input_definition & 0x70) >> 3) + 4; 2009 } 2010 2011 return 0; 2012 } 2013 2014 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 2015 int *panel_bits_per_colourp) 2016 { 2017 struct edid1_info *edid = (struct edid1_info *)buf; 2018 bool timing_done; 2019 int i; 2020 2021 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 2022 debug("%s: Invalid buffer\n", __func__); 2023 return -EINVAL; 2024 } 2025 2026 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 2027 debug("%s: No preferred timing\n", __func__); 2028 return -ENOENT; 2029 } 2030 2031 /* Look for detailed timing */ 2032 timing_done = false; 2033 for (i = 0; i < 4; i++) { 2034 struct edid_monitor_descriptor *desc; 2035 2036 desc = &edid->monitor_details.descriptor[i]; 2037 if (desc->zero_flag_1 != 0) { 2038 decode_timing((u8 *)desc, timing); 2039 timing_done = true; 2040 break; 2041 } 2042 } 2043 if (!timing_done) 2044 return -EINVAL; 2045 2046 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 2047 debug("%s: Not a digital display\n", __func__); 2048 return -ENOSYS; 2049 } 2050 if (edid->version != 1 || edid->revision < 4) { 2051 debug("%s: EDID version %d.%d does not have required info\n", 2052 __func__, edid->version, edid->revision); 2053 *panel_bits_per_colourp = -1; 2054 } else { 2055 *panel_bits_per_colourp = 2056 ((edid->video_input_definition & 0x70) >> 3) + 4; 2057 } 2058 2059 timing->hdmi_monitor = false; 2060 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 2061 struct edid_cea861_info *info = 2062 (struct edid_cea861_info *)(buf + sizeof(*edid)); 2063 2064 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 2065 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 2066 } 2067 2068 return 0; 2069 } 2070 2071 /** 2072 * Snip the tailing whitespace/return of a string. 2073 * 2074 * @param string The string to be snipped 2075 * @return the snipped string 2076 */ 2077 static char *snip(char *string) 2078 { 2079 char *s; 2080 2081 /* 2082 * This is always a 13 character buffer 2083 * and it's not always terminated. 2084 */ 2085 string[12] = '\0'; 2086 s = &string[strlen(string) - 1]; 2087 2088 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 2089 *s == '\0')) 2090 *(s--) = '\0'; 2091 2092 return string; 2093 } 2094 2095 /** 2096 * Print an EDID monitor descriptor block 2097 * 2098 * @param monitor The EDID monitor descriptor block 2099 * @have_timing Modifies to 1 if the desciptor contains timing info 2100 */ 2101 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 2102 unsigned int *have_timing) 2103 { 2104 unsigned char *bytes = (unsigned char *)monitor; 2105 struct edid_detailed_timing *timing = 2106 (struct edid_detailed_timing *)monitor; 2107 2108 if (bytes[0] == 0 && bytes[1] == 0) { 2109 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 2110 printf("Monitor serial number: %s\n", 2111 snip(monitor->data.string)); 2112 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 2113 printf("Monitor ID: %s\n", 2114 snip(monitor->data.string)); 2115 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 2116 printf("Monitor name: %s\n", 2117 snip(monitor->data.string)); 2118 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 2119 printf("Monitor range limits, horizontal sync: " 2120 "%d-%d kHz, vertical refresh: " 2121 "%d-%d Hz, max pixel clock: " 2122 "%d MHz\n", 2123 monitor->data.range_data.horizontal_min, 2124 monitor->data.range_data.horizontal_max, 2125 monitor->data.range_data.vertical_min, 2126 monitor->data.range_data.vertical_max, 2127 monitor->data.range_data.pixel_clock_max * 10); 2128 } else { 2129 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 2130 u32 h_total, v_total, vfreq; 2131 2132 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 2133 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 2134 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 2135 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 2136 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 2137 2138 h_total = h_active + h_blanking; 2139 v_total = v_active + v_blanking; 2140 if (v_total > 0 && h_total > 0) 2141 vfreq = pixclock / (v_total * h_total); 2142 else 2143 vfreq = 1; /* Error case */ 2144 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 2145 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 2146 *have_timing = 1; 2147 } 2148 } 2149 2150 /** 2151 * Get the manufacturer name from an EDID info. 2152 * 2153 * @param edid_info The EDID info to be printed 2154 * @param name Returns the string of the manufacturer name 2155 */ 2156 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 2157 { 2158 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 2159 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 2160 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 2161 name[3] = '\0'; 2162 } 2163 2164 void edid_print_info(struct edid1_info *edid_info) 2165 { 2166 int i; 2167 char manufacturer[4]; 2168 unsigned int have_timing = 0; 2169 u32 serial_number; 2170 2171 if (edid_check_info(edid_info)) { 2172 printf("Not a valid EDID\n"); 2173 return; 2174 } 2175 2176 printf("EDID version: %d.%d\n", 2177 edid_info->version, edid_info->revision); 2178 2179 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 2180 2181 edid_get_manufacturer_name(edid_info, manufacturer); 2182 printf("Manufacturer: %s\n", manufacturer); 2183 2184 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 2185 if (serial_number != 0xffffffff) { 2186 if (strcmp(manufacturer, "MAG") == 0) 2187 serial_number -= 0x7000000; 2188 if (strcmp(manufacturer, "OQI") == 0) 2189 serial_number -= 456150000; 2190 if (strcmp(manufacturer, "VSC") == 0) 2191 serial_number -= 640000000; 2192 } 2193 printf("Serial number: %08x\n", serial_number); 2194 printf("Manufactured in week: %d year: %d\n", 2195 edid_info->week, edid_info->year + 1990); 2196 2197 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 2198 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 2199 "digital signal, " : "analog signal, ", 2200 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 2201 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 2202 ", blank to black" : "", 2203 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 2204 ", separate sync" : "", 2205 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 2206 ", composite sync" : "", 2207 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 2208 ", sync on green" : "", 2209 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 2210 ", serration v" : ""); 2211 2212 printf("Monitor is %s\n", 2213 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 2214 2215 printf("Maximum visible display size: %d cm x %d cm\n", 2216 edid_info->max_size_horizontal, 2217 edid_info->max_size_vertical); 2218 2219 printf("Power management features: %s%s, %s%s, %s%s\n", 2220 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 2221 "" : "no ", "active off", 2222 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 2223 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 2224 2225 printf("Estabilished timings:\n"); 2226 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 2227 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 2228 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 2229 printf("\t720x400\t\t88 Hz (XGA2)\n"); 2230 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 2231 printf("\t640x480\t\t60 Hz (VGA)\n"); 2232 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 2233 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 2234 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 2235 printf("\t640x480\t\t72 Hz (VESA)\n"); 2236 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 2237 printf("\t640x480\t\t75 Hz (VESA)\n"); 2238 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 2239 printf("\t800x600\t\t56 Hz (VESA)\n"); 2240 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 2241 printf("\t800x600\t\t60 Hz (VESA)\n"); 2242 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 2243 printf("\t800x600\t\t72 Hz (VESA)\n"); 2244 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 2245 printf("\t800x600\t\t75 Hz (VESA)\n"); 2246 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 2247 printf("\t832x624\t\t75 Hz (Mac II)\n"); 2248 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 2249 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 2250 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 2251 printf("\t1024x768\t60 Hz (VESA)\n"); 2252 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 2253 printf("\t1024x768\t70 Hz (VESA)\n"); 2254 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 2255 printf("\t1024x768\t75 Hz (VESA)\n"); 2256 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 2257 printf("\t1280x1024\t75 (VESA)\n"); 2258 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 2259 printf("\t1152x870\t75 (Mac II)\n"); 2260 2261 /* Standard timings. */ 2262 printf("Standard timings:\n"); 2263 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 2264 unsigned int aspect = 10000; 2265 unsigned int x, y; 2266 unsigned char xres, vfreq; 2267 2268 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 2269 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 2270 if ((xres != vfreq) || 2271 ((xres != 0) && (xres != 1)) || 2272 ((vfreq != 0) && (vfreq != 1))) { 2273 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 2274 i)) { 2275 case ASPECT_625: 2276 aspect = 6250; 2277 break; 2278 case ASPECT_75: 2279 aspect = 7500; 2280 break; 2281 case ASPECT_8: 2282 aspect = 8000; 2283 break; 2284 case ASPECT_5625: 2285 aspect = 5625; 2286 break; 2287 } 2288 x = (xres + 31) * 8; 2289 y = x * aspect / 10000; 2290 printf("\t%dx%d%c\t%d Hz\n", x, y, 2291 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 2292 have_timing = 1; 2293 } 2294 } 2295 2296 /* Detailed timing information. */ 2297 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 2298 i++) { 2299 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 2300 &have_timing); 2301 } 2302 2303 if (!have_timing) 2304 printf("\tNone\n"); 2305 } 2306 2307 /** 2308 * drm_cvt_mode -create a modeline based on the CVT algorithm 2309 * @hdisplay: hdisplay size 2310 * @vdisplay: vdisplay size 2311 * @vrefresh: vrefresh rate 2312 * @reduced: whether to use reduced blanking 2313 * @interlaced: whether to compute an interlaced mode 2314 * @margins: whether to add margins (borders) 2315 * 2316 * This function is called to generate the modeline based on CVT algorithm 2317 * according to the hdisplay, vdisplay, vrefresh. 2318 * It is based from the VESA(TM) Coordinated Video Timing Generator by 2319 * Graham Loveridge April 9, 2003 available at 2320 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 2321 * 2322 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 2323 * What I have done is to translate it by using integer calculation. 2324 * 2325 * Returns: 2326 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 2327 * The display mode object is allocated with drm_mode_create(). Returns NULL 2328 * when no mode could be allocated. 2329 */ 2330 static 2331 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 2332 bool reduced, bool interlaced, 2333 bool margins) 2334 { 2335 #define HV_FACTOR 1000 2336 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 2337 #define CVT_MARGIN_PERCENTAGE 18 2338 /* 2) character cell horizontal granularity (pixels) - default 8 */ 2339 #define CVT_H_GRANULARITY 8 2340 /* 3) Minimum vertical porch (lines) - default 3 */ 2341 #define CVT_MIN_V_PORCH 3 2342 /* 4) Minimum number of vertical back porch lines - default 6 */ 2343 #define CVT_MIN_V_BPORCH 6 2344 /* Pixel Clock step (kHz) */ 2345 #define CVT_CLOCK_STEP 250 2346 struct drm_display_mode *drm_mode; 2347 unsigned int vfieldrate, hperiod; 2348 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 2349 int interlace; 2350 2351 /* allocate the drm_display_mode structure. If failure, we will 2352 * return directly 2353 */ 2354 drm_mode = drm_mode_create(); 2355 if (!drm_mode) 2356 return NULL; 2357 2358 /* the CVT default refresh rate is 60Hz */ 2359 if (!vrefresh) 2360 vrefresh = 60; 2361 2362 /* the required field fresh rate */ 2363 if (interlaced) 2364 vfieldrate = vrefresh * 2; 2365 else 2366 vfieldrate = vrefresh; 2367 2368 /* horizontal pixels */ 2369 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 2370 2371 /* determine the left&right borders */ 2372 hmargin = 0; 2373 if (margins) { 2374 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2375 hmargin -= hmargin % CVT_H_GRANULARITY; 2376 } 2377 /* find the total active pixels */ 2378 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 2379 2380 /* find the number of lines per field */ 2381 if (interlaced) 2382 vdisplay_rnd = vdisplay / 2; 2383 else 2384 vdisplay_rnd = vdisplay; 2385 2386 /* find the top & bottom borders */ 2387 vmargin = 0; 2388 if (margins) 2389 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2390 2391 drm_mode->vdisplay = vdisplay + 2 * vmargin; 2392 2393 /* Interlaced */ 2394 if (interlaced) 2395 interlace = 1; 2396 else 2397 interlace = 0; 2398 2399 /* Determine VSync Width from aspect ratio */ 2400 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 2401 vsync = 4; 2402 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 2403 vsync = 5; 2404 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 2405 vsync = 6; 2406 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 2407 vsync = 7; 2408 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 2409 vsync = 7; 2410 else /* custom */ 2411 vsync = 10; 2412 2413 if (!reduced) { 2414 /* simplify the GTF calculation */ 2415 /* 4) Minimum time of vertical sync + back porch interval 2416 * default 550.0 2417 */ 2418 int tmp1, tmp2; 2419 #define CVT_MIN_VSYNC_BP 550 2420 /* 3) Nominal HSync width (% of line period) - default 8 */ 2421 #define CVT_HSYNC_PERCENTAGE 8 2422 unsigned int hblank_percentage; 2423 int vsyncandback_porch, hblank; 2424 2425 /* estimated the horizontal period */ 2426 tmp1 = HV_FACTOR * 1000000 - 2427 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2428 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2429 interlace; 2430 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2431 2432 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2433 /* 9. Find number of lines in sync + backporch */ 2434 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2435 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2436 else 2437 vsyncandback_porch = tmp1; 2438 /* 10. Find number of lines in back porch 2439 * vback_porch = vsyncandback_porch - vsync; 2440 */ 2441 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2442 vsyncandback_porch + CVT_MIN_V_PORCH; 2443 /* 5) Definition of Horizontal blanking time limitation */ 2444 /* Gradient (%/kHz) - default 600 */ 2445 #define CVT_M_FACTOR 600 2446 /* Offset (%) - default 40 */ 2447 #define CVT_C_FACTOR 40 2448 /* Blanking time scaling factor - default 128 */ 2449 #define CVT_K_FACTOR 128 2450 /* Scaling factor weighting - default 20 */ 2451 #define CVT_J_FACTOR 20 2452 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2453 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2454 CVT_J_FACTOR) 2455 /* 12. Find ideal blanking duty cycle from formula */ 2456 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2457 hperiod / 1000; 2458 /* 13. Blanking time */ 2459 if (hblank_percentage < 20 * HV_FACTOR) 2460 hblank_percentage = 20 * HV_FACTOR; 2461 hblank = drm_mode->hdisplay * hblank_percentage / 2462 (100 * HV_FACTOR - hblank_percentage); 2463 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2464 /* 14. find the total pixels per line */ 2465 drm_mode->htotal = drm_mode->hdisplay + hblank; 2466 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2467 drm_mode->hsync_start = drm_mode->hsync_end - 2468 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2469 drm_mode->hsync_start += CVT_H_GRANULARITY - 2470 drm_mode->hsync_start % CVT_H_GRANULARITY; 2471 /* fill the Vsync values */ 2472 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2473 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2474 } else { 2475 /* Reduced blanking */ 2476 /* Minimum vertical blanking interval time - default 460 */ 2477 #define CVT_RB_MIN_VBLANK 460 2478 /* Fixed number of clocks for horizontal sync */ 2479 #define CVT_RB_H_SYNC 32 2480 /* Fixed number of clocks for horizontal blanking */ 2481 #define CVT_RB_H_BLANK 160 2482 /* Fixed number of lines for vertical front porch - default 3*/ 2483 #define CVT_RB_VFPORCH 3 2484 int vbilines; 2485 int tmp1, tmp2; 2486 /* 8. Estimate Horizontal period. */ 2487 tmp1 = HV_FACTOR * 1000000 - 2488 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2489 tmp2 = vdisplay_rnd + 2 * vmargin; 2490 hperiod = tmp1 / (tmp2 * vfieldrate); 2491 /* 9. Find number of lines in vertical blanking */ 2492 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2493 /* 10. Check if vertical blanking is sufficient */ 2494 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2495 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2496 /* 11. Find total number of lines in vertical field */ 2497 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2498 /* 12. Find total number of pixels in a line */ 2499 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2500 /* Fill in HSync values */ 2501 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2502 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2503 /* Fill in VSync values */ 2504 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2505 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2506 } 2507 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2508 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2509 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2510 /* 18/16. Find actual vertical frame frequency */ 2511 /* ignore - just set the mode flag for interlaced */ 2512 if (interlaced) { 2513 drm_mode->vtotal *= 2; 2514 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2515 } 2516 2517 if (reduced) 2518 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2519 DRM_MODE_FLAG_NVSYNC); 2520 else 2521 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2522 DRM_MODE_FLAG_NHSYNC); 2523 2524 return drm_mode; 2525 } 2526 2527 static int 2528 cea_db_payload_len(const u8 *db) 2529 { 2530 return db[0] & 0x1f; 2531 } 2532 2533 static int 2534 cea_db_extended_tag(const u8 *db) 2535 { 2536 return db[1]; 2537 } 2538 2539 static int 2540 cea_db_tag(const u8 *db) 2541 { 2542 return db[0] >> 5; 2543 } 2544 2545 #define for_each_cea_db(cea, i, start, end) \ 2546 for ((i) = (start); (i) < (end) && (i) + \ 2547 cea_db_payload_len(&(cea)[(i)]) < \ 2548 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2549 2550 static int 2551 cea_revision(const u8 *cea) 2552 { 2553 return cea[1]; 2554 } 2555 2556 static int 2557 cea_db_offsets(const u8 *cea, int *start, int *end) 2558 { 2559 /* Data block offset in CEA extension block */ 2560 *start = 4; 2561 *end = cea[2]; 2562 if (*end == 0) 2563 *end = 127; 2564 if (*end < 4 || *end > 127) 2565 return -ERANGE; 2566 2567 /* 2568 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2569 */ 2570 if (*end != 4) { 2571 int i; 2572 2573 i = *start; 2574 while (i < (*end) && 2575 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2576 i += cea_db_payload_len(&(cea)[i]) + 1; 2577 2578 if (cea_db_payload_len(&(cea)[i]) && 2579 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2580 (*end)++; 2581 } 2582 2583 return 0; 2584 } 2585 2586 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2587 { 2588 int hdmi_id; 2589 2590 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2591 return false; 2592 2593 if (cea_db_payload_len(db) < 5) 2594 return false; 2595 2596 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2597 2598 return hdmi_id == HDMI_IEEE_OUI; 2599 } 2600 2601 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2602 { 2603 unsigned int oui; 2604 2605 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2606 return false; 2607 2608 if (cea_db_payload_len(db) < 7) 2609 return false; 2610 2611 oui = db[3] << 16 | db[2] << 8 | db[1]; 2612 2613 return oui == HDMI_FORUM_IEEE_OUI; 2614 } 2615 2616 static bool cea_db_is_y420cmdb(const u8 *db) 2617 { 2618 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2619 return false; 2620 2621 if (!cea_db_payload_len(db)) 2622 return false; 2623 2624 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2625 return false; 2626 2627 return true; 2628 } 2629 2630 static bool cea_db_is_y420vdb(const u8 *db) 2631 { 2632 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2633 return false; 2634 2635 if (!cea_db_payload_len(db)) 2636 return false; 2637 2638 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2639 return false; 2640 2641 return true; 2642 } 2643 2644 static bool drm_valid_hdmi_vic(u8 vic) 2645 { 2646 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2647 } 2648 2649 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2650 const struct drm_display_mode *mode) 2651 { 2652 struct drm_display_mode *mode_buf = data->mode_buf; 2653 2654 if (data->modes >= MODE_LEN) 2655 return; 2656 mode_buf[(data->modes)++] = *mode; 2657 } 2658 2659 static bool drm_valid_cea_vic(u8 vic) 2660 { 2661 return cea_mode_for_vic(vic) ? true : false; 2662 } 2663 2664 static u8 svd_to_vic(u8 svd) 2665 { 2666 /* 0-6 bit vic, 7th bit native mode indicator */ 2667 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2668 return svd & 127; 2669 2670 return svd; 2671 } 2672 2673 static struct drm_display_mode * 2674 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2675 u8 video_index) 2676 { 2677 struct drm_display_mode *newmode; 2678 u8 vic; 2679 2680 if (!video_db || video_index >= video_len) 2681 return NULL; 2682 2683 /* CEA modes are numbered 1..127 */ 2684 vic = svd_to_vic(video_db[video_index]); 2685 if (!drm_valid_cea_vic(vic)) 2686 return NULL; 2687 2688 newmode = drm_mode_create(); 2689 if (!newmode) 2690 return NULL; 2691 2692 *newmode = *cea_mode_for_vic(vic); 2693 newmode->vrefresh = 0; 2694 2695 return newmode; 2696 } 2697 2698 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2699 { 2700 unsigned long *p = map + BIT_WORD(start); 2701 const unsigned int size = start + len; 2702 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2703 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2704 2705 while (len - bits_to_set >= 0) { 2706 *p |= mask_to_set; 2707 len -= bits_to_set; 2708 bits_to_set = BITS_PER_LONG; 2709 mask_to_set = ~0UL; 2710 p++; 2711 } 2712 if (len) { 2713 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2714 *p |= mask_to_set; 2715 } 2716 } 2717 2718 static void 2719 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2720 { 2721 u8 vic = svd_to_vic(svd); 2722 2723 if (!drm_valid_cea_vic(vic)) 2724 return; 2725 2726 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2727 } 2728 2729 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2730 { 2731 int i, modes = 0; 2732 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2733 2734 for (i = 0; i < len; i++) { 2735 struct drm_display_mode *mode; 2736 2737 mode = drm_display_mode_from_vic_index(db, len, i); 2738 if (mode) { 2739 /* 2740 * YCBCR420 capability block contains a bitmap which 2741 * gives the index of CEA modes from CEA VDB, which 2742 * can support YCBCR 420 sampling output also (apart 2743 * from RGB/YCBCR444 etc). 2744 * For example, if the bit 0 in bitmap is set, 2745 * first mode in VDB can support YCBCR420 output too. 2746 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2747 */ 2748 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2749 drm_add_cmdb_modes(db[i], hdmi); 2750 drm_add_hdmi_modes(data, mode); 2751 drm_mode_destroy(mode); 2752 modes++; 2753 } 2754 } 2755 2756 return modes; 2757 } 2758 2759 /* 2760 * do_y420vdb_modes - Parse YCBCR 420 only modes 2761 * @data: the structure that save parsed hdmi edid data 2762 * @svds: start of the data block of CEA YCBCR 420 VDB 2763 * @svds_len: length of the CEA YCBCR 420 VDB 2764 * @hdmi: runtime information about the connected HDMI sink 2765 * 2766 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2767 * which contains modes which can be supported in YCBCR 420 2768 * output format only. 2769 */ 2770 static int 2771 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2772 { 2773 int modes = 0, i; 2774 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2775 2776 for (i = 0; i < svds_len; i++) { 2777 u8 vic = svd_to_vic(svds[i]); 2778 2779 if (!drm_valid_cea_vic(vic)) 2780 continue; 2781 2782 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2783 drm_add_hdmi_modes(data, cea_mode_for_vic(vic)); 2784 modes++; 2785 } 2786 2787 return modes; 2788 } 2789 2790 struct stereo_mandatory_mode { 2791 int width, height, vrefresh; 2792 unsigned int flags; 2793 }; 2794 2795 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2796 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2797 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2798 { 1920, 1080, 50, 2799 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2800 { 1920, 1080, 60, 2801 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2802 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2803 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2804 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2805 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2806 }; 2807 2808 static bool 2809 stereo_match_mandatory(const struct drm_display_mode *mode, 2810 const struct stereo_mandatory_mode *stereo_mode) 2811 { 2812 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2813 2814 return mode->hdisplay == stereo_mode->width && 2815 mode->vdisplay == stereo_mode->height && 2816 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2817 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2818 } 2819 2820 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2821 { 2822 const struct drm_display_mode *mode; 2823 int num = data->modes, modes = 0, i, k; 2824 2825 for (k = 0; k < num; k++) { 2826 mode = &data->mode_buf[k]; 2827 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2828 const struct stereo_mandatory_mode *mandatory; 2829 struct drm_display_mode *new_mode; 2830 2831 if (!stereo_match_mandatory(mode, 2832 &stereo_mandatory_modes[i])) 2833 continue; 2834 2835 mandatory = &stereo_mandatory_modes[i]; 2836 new_mode = drm_mode_create(); 2837 if (!new_mode) 2838 continue; 2839 2840 *new_mode = *mode; 2841 new_mode->flags |= mandatory->flags; 2842 drm_add_hdmi_modes(data, new_mode); 2843 drm_mode_destroy(new_mode); 2844 modes++; 2845 } 2846 } 2847 2848 return modes; 2849 } 2850 2851 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2852 const u8 *video_db, u8 video_len, u8 video_index) 2853 { 2854 struct drm_display_mode *newmode; 2855 int modes = 0; 2856 2857 if (structure & (1 << 0)) { 2858 newmode = drm_display_mode_from_vic_index(video_db, 2859 video_len, 2860 video_index); 2861 if (newmode) { 2862 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2863 drm_add_hdmi_modes(data, newmode); 2864 modes++; 2865 drm_mode_destroy(newmode); 2866 } 2867 } 2868 if (structure & (1 << 6)) { 2869 newmode = drm_display_mode_from_vic_index(video_db, 2870 video_len, 2871 video_index); 2872 if (newmode) { 2873 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2874 drm_add_hdmi_modes(data, newmode); 2875 modes++; 2876 drm_mode_destroy(newmode); 2877 } 2878 } 2879 if (structure & (1 << 8)) { 2880 newmode = drm_display_mode_from_vic_index(video_db, 2881 video_len, 2882 video_index); 2883 if (newmode) { 2884 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2885 drm_add_hdmi_modes(data, newmode); 2886 modes++; 2887 drm_mode_destroy(newmode); 2888 } 2889 } 2890 2891 return modes; 2892 } 2893 2894 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2895 { 2896 if (!drm_valid_hdmi_vic(vic)) { 2897 debug("Unknown HDMI VIC: %d\n", vic); 2898 return 0; 2899 } 2900 2901 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2902 2903 return 1; 2904 } 2905 2906 /* 2907 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2908 * @db: start of the CEA vendor specific block 2909 * @len: length of the CEA block payload, ie. one can access up to db[len] 2910 * 2911 * Parses the HDMI VSDB looking for modes to add to @data. This function 2912 * also adds the stereo 3d modes when applicable. 2913 */ 2914 static int 2915 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2916 struct hdmi_edid_data *data) 2917 { 2918 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2919 u8 vic_len, hdmi_3d_len = 0; 2920 u16 mask; 2921 u16 structure_all; 2922 2923 if (len < 8) 2924 goto out; 2925 2926 /* no HDMI_Video_Present */ 2927 if (!(db[8] & (1 << 5))) 2928 goto out; 2929 2930 /* Latency_Fields_Present */ 2931 if (db[8] & (1 << 7)) 2932 offset += 2; 2933 2934 /* I_Latency_Fields_Present */ 2935 if (db[8] & (1 << 6)) 2936 offset += 2; 2937 2938 /* the declared length is not long enough for the 2 first bytes 2939 * of additional video format capabilities 2940 */ 2941 if (len < (8 + offset + 2)) 2942 goto out; 2943 2944 /* 3D_Present */ 2945 offset++; 2946 if (db[8 + offset] & (1 << 7)) { 2947 modes += add_hdmi_mandatory_stereo_modes(data); 2948 2949 /* 3D_Multi_present */ 2950 multi_present = (db[8 + offset] & 0x60) >> 5; 2951 } 2952 2953 offset++; 2954 vic_len = db[8 + offset] >> 5; 2955 hdmi_3d_len = db[8 + offset] & 0x1f; 2956 2957 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2958 u8 vic; 2959 2960 vic = db[9 + offset + i]; 2961 modes += add_hdmi_mode(data, vic); 2962 } 2963 2964 offset += 1 + vic_len; 2965 2966 if (multi_present == 1) 2967 multi_len = 2; 2968 else if (multi_present == 2) 2969 multi_len = 4; 2970 else 2971 multi_len = 0; 2972 2973 if (len < (8 + offset + hdmi_3d_len - 1)) 2974 goto out; 2975 2976 if (hdmi_3d_len < multi_len) 2977 goto out; 2978 2979 if (multi_present == 1 || multi_present == 2) { 2980 /* 3D_Structure_ALL */ 2981 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2982 2983 /* check if 3D_MASK is present */ 2984 if (multi_present == 2) 2985 mask = (db[10 + offset] << 8) | db[11 + offset]; 2986 else 2987 mask = 0xffff; 2988 2989 for (i = 0; i < 16; i++) { 2990 if (mask & (1 << i)) 2991 modes += add_3d_struct_modes(data, 2992 structure_all, 2993 video_db, 2994 video_len, i); 2995 } 2996 } 2997 2998 offset += multi_len; 2999 3000 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3001 int vic_index; 3002 struct drm_display_mode *newmode = NULL; 3003 unsigned int newflag = 0; 3004 bool detail_present; 3005 3006 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3007 3008 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3009 break; 3010 3011 /* 2D_VIC_order_X */ 3012 vic_index = db[8 + offset + i] >> 4; 3013 3014 /* 3D_Structure_X */ 3015 switch (db[8 + offset + i] & 0x0f) { 3016 case 0: 3017 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3018 break; 3019 case 6: 3020 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3021 break; 3022 case 8: 3023 /* 3D_Detail_X */ 3024 if ((db[9 + offset + i] >> 4) == 1) 3025 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3026 break; 3027 } 3028 3029 if (newflag != 0) { 3030 newmode = drm_display_mode_from_vic_index( 3031 video_db, 3032 video_len, 3033 vic_index); 3034 3035 if (newmode) { 3036 newmode->flags |= newflag; 3037 drm_add_hdmi_modes(data, newmode); 3038 modes++; 3039 drm_mode_destroy(newmode); 3040 } 3041 } 3042 3043 if (detail_present) 3044 i++; 3045 } 3046 3047 out: 3048 return modes; 3049 } 3050 3051 /** 3052 * edid_get_quirks - return quirk flags for a given EDID 3053 * @edid: EDID to process 3054 * 3055 * This tells subsequent routines what fixes they need to apply. 3056 */ 3057 static u32 edid_get_quirks(struct edid *edid) 3058 { 3059 struct edid_quirk *quirk; 3060 int i; 3061 3062 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 3063 quirk = &edid_quirk_list[i]; 3064 3065 if (edid_vendor(edid, quirk->vendor) && 3066 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 3067 return quirk->quirks; 3068 } 3069 3070 return 0; 3071 } 3072 3073 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 3074 const u8 *db) 3075 { 3076 struct drm_display_info *info = &data->display_info; 3077 struct drm_hdmi_info *hdmi = &info->hdmi; 3078 u8 map_len = cea_db_payload_len(db) - 1; 3079 u8 count; 3080 u64 map = 0; 3081 3082 if (map_len == 0) { 3083 /* All CEA modes support ycbcr420 sampling also.*/ 3084 hdmi->y420_cmdb_map = U64_MAX; 3085 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3086 return; 3087 } 3088 3089 /* 3090 * This map indicates which of the existing CEA block modes 3091 * from VDB can support YCBCR420 output too. So if bit=0 is 3092 * set, first mode from VDB can support YCBCR420 output too. 3093 * We will parse and keep this map, before parsing VDB itself 3094 * to avoid going through the same block again and again. 3095 * 3096 * Spec is not clear about max possible size of this block. 3097 * Clamping max bitmap block size at 8 bytes. Every byte can 3098 * address 8 CEA modes, in this way this map can address 3099 * 8*8 = first 64 SVDs. 3100 */ 3101 if (map_len > 8) 3102 map_len = 8; 3103 3104 for (count = 0; count < map_len; count++) 3105 map |= (u64)db[2 + count] << (8 * count); 3106 3107 if (map) 3108 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3109 3110 hdmi->y420_cmdb_map = map; 3111 } 3112 3113 static 3114 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 3115 { 3116 switch (max_frl_rate) { 3117 case 1: 3118 *max_lanes = 3; 3119 *max_rate_per_lane = 3; 3120 break; 3121 case 2: 3122 *max_lanes = 3; 3123 *max_rate_per_lane = 6; 3124 break; 3125 case 3: 3126 *max_lanes = 4; 3127 *max_rate_per_lane = 6; 3128 break; 3129 case 4: 3130 *max_lanes = 4; 3131 *max_rate_per_lane = 8; 3132 break; 3133 case 5: 3134 *max_lanes = 4; 3135 *max_rate_per_lane = 10; 3136 break; 3137 case 6: 3138 *max_lanes = 4; 3139 *max_rate_per_lane = 12; 3140 break; 3141 case 0: 3142 default: 3143 *max_lanes = 0; 3144 *max_rate_per_lane = 0; 3145 } 3146 } 3147 3148 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 3149 const u8 *db) 3150 { 3151 u8 dc_mask; 3152 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 3153 3154 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 3155 hdmi->y420_dc_modes |= dc_mask; 3156 } 3157 3158 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 3159 const u8 *hf_vsdb) 3160 { 3161 struct drm_display_info *display = &data->display_info; 3162 struct drm_hdmi_info *hdmi = &display->hdmi; 3163 3164 if (hf_vsdb[6] & 0x80) { 3165 hdmi->scdc.supported = true; 3166 if (hf_vsdb[6] & 0x40) 3167 hdmi->scdc.read_request = true; 3168 } 3169 3170 /* 3171 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 3172 * And as per the spec, three factors confirm this: 3173 * * Availability of a HF-VSDB block in EDID (check) 3174 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 3175 * * SCDC support available (let's check) 3176 * Lets check it out. 3177 */ 3178 3179 if (hf_vsdb[5]) { 3180 /* max clock is 5000 KHz times block value */ 3181 u32 max_tmds_clock = hf_vsdb[5] * 5000; 3182 struct drm_scdc *scdc = &hdmi->scdc; 3183 3184 if (max_tmds_clock > 340000) { 3185 display->max_tmds_clock = max_tmds_clock; 3186 debug("HF-VSDB: max TMDS clock %d kHz\n", 3187 display->max_tmds_clock); 3188 } 3189 3190 if (scdc->supported) { 3191 scdc->scrambling.supported = true; 3192 3193 /* Few sinks support scrambling for cloks < 340M */ 3194 if ((hf_vsdb[6] & 0x8)) 3195 scdc->scrambling.low_rates = true; 3196 } 3197 } 3198 3199 if (hf_vsdb[7]) { 3200 u8 max_frl_rate; 3201 u8 dsc_max_frl_rate; 3202 u8 dsc_max_slices; 3203 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 3204 3205 debug("hdmi_21 sink detected. parsing edid\n"); 3206 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 3207 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 3208 &hdmi->max_frl_rate_per_lane); 3209 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 3210 3211 if (hdmi_dsc->v_1p2) { 3212 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 3213 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 3214 3215 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 3216 hdmi_dsc->bpc_supported = 16; 3217 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 3218 hdmi_dsc->bpc_supported = 12; 3219 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 3220 hdmi_dsc->bpc_supported = 10; 3221 else 3222 hdmi_dsc->bpc_supported = 0; 3223 3224 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 3225 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 3226 &hdmi_dsc->max_frl_rate_per_lane); 3227 hdmi_dsc->total_chunk_kbytes = 3228 hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 3229 3230 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 3231 switch (dsc_max_slices) { 3232 case 1: 3233 hdmi_dsc->max_slices = 1; 3234 hdmi_dsc->clk_per_slice = 340; 3235 break; 3236 case 2: 3237 hdmi_dsc->max_slices = 2; 3238 hdmi_dsc->clk_per_slice = 340; 3239 break; 3240 case 3: 3241 hdmi_dsc->max_slices = 4; 3242 hdmi_dsc->clk_per_slice = 340; 3243 break; 3244 case 4: 3245 hdmi_dsc->max_slices = 8; 3246 hdmi_dsc->clk_per_slice = 340; 3247 break; 3248 case 5: 3249 hdmi_dsc->max_slices = 8; 3250 hdmi_dsc->clk_per_slice = 400; 3251 break; 3252 case 6: 3253 hdmi_dsc->max_slices = 12; 3254 hdmi_dsc->clk_per_slice = 400; 3255 break; 3256 case 7: 3257 hdmi_dsc->max_slices = 16; 3258 hdmi_dsc->clk_per_slice = 400; 3259 break; 3260 case 0: 3261 default: 3262 hdmi_dsc->max_slices = 0; 3263 hdmi_dsc->clk_per_slice = 0; 3264 } 3265 } 3266 } 3267 3268 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 3269 } 3270 3271 /** 3272 * drm_default_rgb_quant_range - default RGB quantization range 3273 * @mode: display mode 3274 * 3275 * Determine the default RGB quantization range for the mode, 3276 * as specified in CEA-861. 3277 * 3278 * Return: The default RGB quantization range for the mode 3279 */ 3280 enum hdmi_quantization_range 3281 drm_default_rgb_quant_range(struct drm_display_mode *mode) 3282 { 3283 /* All CEA modes other than VIC 1 use limited quantization range. */ 3284 return drm_match_cea_mode(mode) > 1 ? 3285 HDMI_QUANTIZATION_RANGE_LIMITED : 3286 HDMI_QUANTIZATION_RANGE_FULL; 3287 } 3288 3289 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 3290 const u8 *hdmi) 3291 { 3292 struct drm_display_info *info = &data->display_info; 3293 unsigned int dc_bpc = 0; 3294 3295 /* HDMI supports at least 8 bpc */ 3296 info->bpc = 8; 3297 3298 if (cea_db_payload_len(hdmi) < 6) 3299 return; 3300 3301 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3302 dc_bpc = 10; 3303 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3304 debug("HDMI sink does deep color 30.\n"); 3305 } 3306 3307 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3308 dc_bpc = 12; 3309 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3310 debug("HDMI sink does deep color 36.\n"); 3311 } 3312 3313 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3314 dc_bpc = 16; 3315 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3316 debug("HDMI sink does deep color 48.\n"); 3317 } 3318 3319 if (dc_bpc == 0) { 3320 debug("No deep color support on this HDMI sink.\n"); 3321 return; 3322 } 3323 3324 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 3325 info->bpc = dc_bpc; 3326 3327 /* YCRCB444 is optional according to spec. */ 3328 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3329 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 3330 debug("HDMI sink does YCRCB444 in deep color.\n"); 3331 } 3332 3333 /* 3334 * Spec says that if any deep color mode is supported at all, 3335 * then deep color 36 bit must be supported. 3336 */ 3337 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 3338 debug("HDMI sink should do DC_36, but does not!\n"); 3339 } 3340 3341 /* 3342 * Search EDID for CEA extension block. 3343 */ 3344 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 3345 { 3346 u8 *edid_ext = NULL; 3347 int i; 3348 3349 /* No EDID or EDID extensions */ 3350 if (!edid || !edid->extensions) 3351 return NULL; 3352 3353 /* Find CEA extension */ 3354 for (i = 0; i < edid->extensions; i++) { 3355 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 3356 if (edid_ext[0] == ext_id) 3357 break; 3358 } 3359 3360 if (i == edid->extensions) 3361 return NULL; 3362 3363 return edid_ext; 3364 } 3365 3366 static u8 *drm_find_cea_extension(struct edid *edid) 3367 { 3368 return drm_find_edid_extension(edid, 0x02); 3369 } 3370 3371 #define AUDIO_BLOCK 0x01 3372 #define VIDEO_BLOCK 0x02 3373 #define VENDOR_BLOCK 0x03 3374 #define SPEAKER_BLOCK 0x04 3375 #define EDID_BASIC_AUDIO BIT(6) 3376 3377 /** 3378 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3379 * @edid: monitor EDID information 3380 * 3381 * Parse the CEA extension according to CEA-861-B. 3382 * 3383 * Return: True if the monitor is HDMI, false if not or unknown. 3384 */ 3385 bool drm_detect_hdmi_monitor(struct edid *edid) 3386 { 3387 u8 *edid_ext; 3388 int i; 3389 int start_offset, end_offset; 3390 3391 edid_ext = drm_find_cea_extension(edid); 3392 if (!edid_ext) 3393 return false; 3394 3395 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3396 return false; 3397 3398 /* 3399 * Because HDMI identifier is in Vendor Specific Block, 3400 * search it from all data blocks of CEA extension. 3401 */ 3402 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3403 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3404 return true; 3405 } 3406 3407 return false; 3408 } 3409 3410 /** 3411 * drm_detect_monitor_audio - check monitor audio capability 3412 * @edid: EDID block to scan 3413 * 3414 * Monitor should have CEA extension block. 3415 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3416 * audio' only. If there is any audio extension block and supported 3417 * audio format, assume at least 'basic audio' support, even if 'basic 3418 * audio' is not defined in EDID. 3419 * 3420 * Return: True if the monitor supports audio, false otherwise. 3421 */ 3422 bool drm_detect_monitor_audio(struct edid *edid) 3423 { 3424 u8 *edid_ext; 3425 int i, j; 3426 bool has_audio = false; 3427 int start_offset, end_offset; 3428 3429 edid_ext = drm_find_cea_extension(edid); 3430 if (!edid_ext) 3431 goto end; 3432 3433 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3434 3435 if (has_audio) { 3436 printf("Monitor has basic audio support\n"); 3437 goto end; 3438 } 3439 3440 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3441 goto end; 3442 3443 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3444 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3445 has_audio = true; 3446 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 3447 j += 3) 3448 debug("CEA audio format %d\n", 3449 (edid_ext[i + j] >> 3) & 0xf); 3450 goto end; 3451 } 3452 } 3453 end: 3454 return has_audio; 3455 } 3456 3457 static void 3458 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 3459 { 3460 struct drm_display_info *info = &data->display_info; 3461 u8 len = cea_db_payload_len(db); 3462 3463 if (len >= 6) 3464 info->dvi_dual = db[6] & 1; 3465 if (len >= 7) 3466 info->max_tmds_clock = db[7] * 5000; 3467 3468 drm_parse_hdmi_deep_color_info(data, db); 3469 } 3470 3471 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 3472 struct edid *edid) 3473 { 3474 struct drm_display_info *info = &data->display_info; 3475 const u8 *edid_ext; 3476 int i, start, end; 3477 3478 edid_ext = drm_find_cea_extension(edid); 3479 if (!edid_ext) 3480 return; 3481 3482 info->cea_rev = edid_ext[1]; 3483 3484 /* The existence of a CEA block should imply RGB support */ 3485 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3486 if (edid_ext[3] & EDID_CEA_YCRCB444) 3487 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3488 if (edid_ext[3] & EDID_CEA_YCRCB422) 3489 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3490 3491 if (cea_db_offsets(edid_ext, &start, &end)) 3492 return; 3493 3494 for_each_cea_db(edid_ext, i, start, end) { 3495 const u8 *db = &edid_ext[i]; 3496 3497 if (cea_db_is_hdmi_vsdb(db)) 3498 drm_parse_hdmi_vsdb_video(data, db); 3499 if (cea_db_is_hdmi_forum_vsdb(db)) 3500 drm_parse_hdmi_forum_vsdb(data, db); 3501 if (cea_db_is_y420cmdb(db)) 3502 drm_parse_y420cmdb_bitmap(data, db); 3503 } 3504 } 3505 3506 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 3507 { 3508 struct drm_display_info *info = &data->display_info; 3509 3510 info->width_mm = edid->width_cm * 10; 3511 info->height_mm = edid->height_cm * 10; 3512 3513 /* driver figures it out in this case */ 3514 info->bpc = 0; 3515 info->color_formats = 0; 3516 info->cea_rev = 0; 3517 info->max_tmds_clock = 0; 3518 info->dvi_dual = false; 3519 info->edid_hdmi_dc_modes = 0; 3520 3521 memset(&info->hdmi, 0, sizeof(info->hdmi)); 3522 3523 if (edid->revision < 3) 3524 return; 3525 3526 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3527 return; 3528 3529 drm_parse_cea_ext(data, edid); 3530 3531 /* 3532 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3533 * 3534 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3535 * tells us to assume 8 bpc color depth if the EDID doesn't have 3536 * extensions which tell otherwise. 3537 */ 3538 if ((info->bpc == 0) && (edid->revision < 4) && 3539 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3540 info->bpc = 8; 3541 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3542 } 3543 3544 /* Only defined for 1.4 with digital displays */ 3545 if (edid->revision < 4) 3546 return; 3547 3548 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3549 case DRM_EDID_DIGITAL_DEPTH_6: 3550 info->bpc = 6; 3551 break; 3552 case DRM_EDID_DIGITAL_DEPTH_8: 3553 info->bpc = 8; 3554 break; 3555 case DRM_EDID_DIGITAL_DEPTH_10: 3556 info->bpc = 10; 3557 break; 3558 case DRM_EDID_DIGITAL_DEPTH_12: 3559 info->bpc = 12; 3560 break; 3561 case DRM_EDID_DIGITAL_DEPTH_14: 3562 info->bpc = 14; 3563 break; 3564 case DRM_EDID_DIGITAL_DEPTH_16: 3565 info->bpc = 16; 3566 break; 3567 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3568 default: 3569 info->bpc = 0; 3570 break; 3571 } 3572 3573 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3574 info->bpc); 3575 3576 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3577 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3578 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3579 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3580 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3581 } 3582 3583 static 3584 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3585 { 3586 const u8 *cea = drm_find_cea_extension(edid); 3587 const u8 *db, *hdmi = NULL, *video = NULL; 3588 u8 dbl, hdmi_len, video_len = 0; 3589 int modes = 0; 3590 3591 if (cea && cea_revision(cea) >= 3) { 3592 int i, start, end; 3593 3594 if (cea_db_offsets(cea, &start, &end)) 3595 return 0; 3596 3597 for_each_cea_db(cea, i, start, end) { 3598 db = &cea[i]; 3599 dbl = cea_db_payload_len(db); 3600 3601 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3602 video = db + 1; 3603 video_len = dbl; 3604 modes += do_cea_modes(data, video, dbl); 3605 } else if (cea_db_is_hdmi_vsdb(db)) { 3606 hdmi = db; 3607 hdmi_len = dbl; 3608 } else if (cea_db_is_y420vdb(db)) { 3609 const u8 *vdb420 = &db[2]; 3610 3611 /* Add 4:2:0(only) modes present in EDID */ 3612 modes += do_y420vdb_modes(data, vdb420, 3613 dbl - 1); 3614 } 3615 } 3616 } 3617 3618 /* 3619 * We parse the HDMI VSDB after having added the cea modes as we will 3620 * be patching their flags when the sink supports stereo 3D. 3621 */ 3622 if (hdmi) 3623 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3624 video_len, data); 3625 3626 return modes; 3627 } 3628 3629 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3630 3631 static void 3632 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3633 { 3634 int i, n = 0; 3635 u8 d = ext[0x02]; 3636 u8 *det_base = ext + d; 3637 3638 if (d < 4 || d > 127) 3639 return; 3640 3641 n = (127 - d) / 18; 3642 for (i = 0; i < n; i++) 3643 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3644 } 3645 3646 static void 3647 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3648 { 3649 unsigned int i, n = min((int)ext[0x02], 6); 3650 u8 *det_base = ext + 5; 3651 3652 if (ext[0x01] != 1) 3653 return; /* unknown version */ 3654 3655 for (i = 0; i < n; i++) 3656 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3657 } 3658 3659 static void 3660 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3661 { 3662 int i; 3663 struct edid *edid = (struct edid *)raw_edid; 3664 3665 if (!edid) 3666 return; 3667 3668 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3669 cb(&edid->detailed_timings[i], closure); 3670 3671 for (i = 1; i <= raw_edid[0x7e]; i++) { 3672 u8 *ext = raw_edid + (i * EDID_SIZE); 3673 3674 switch (*ext) { 3675 case CEA_EXT: 3676 cea_for_each_detailed_block(ext, cb, closure); 3677 break; 3678 case VTB_EXT: 3679 vtb_for_each_detailed_block(ext, cb, closure); 3680 break; 3681 default: 3682 break; 3683 } 3684 } 3685 } 3686 3687 /* 3688 * EDID is delightfully ambiguous about how interlaced modes are to be 3689 * encoded. Our internal representation is of frame height, but some 3690 * HDTV detailed timings are encoded as field height. 3691 * 3692 * The format list here is from CEA, in frame size. Technically we 3693 * should be checking refresh rate too. Whatever. 3694 */ 3695 static void 3696 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3697 struct detailed_pixel_timing *pt) 3698 { 3699 int i; 3700 3701 static const struct { 3702 int w, h; 3703 } cea_interlaced[] = { 3704 { 1920, 1080 }, 3705 { 720, 480 }, 3706 { 1440, 480 }, 3707 { 2880, 480 }, 3708 { 720, 576 }, 3709 { 1440, 576 }, 3710 { 2880, 576 }, 3711 }; 3712 3713 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3714 return; 3715 3716 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3717 if ((mode->hdisplay == cea_interlaced[i].w) && 3718 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3719 mode->vdisplay *= 2; 3720 mode->vsync_start *= 2; 3721 mode->vsync_end *= 2; 3722 mode->vtotal *= 2; 3723 mode->vtotal |= 1; 3724 } 3725 } 3726 3727 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3728 } 3729 3730 /** 3731 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3732 * @edid: EDID block 3733 * @timing: EDID detailed timing info 3734 * @quirks: quirks to apply 3735 * 3736 * An EDID detailed timing block contains enough info for us to create and 3737 * return a new struct drm_display_mode. 3738 */ 3739 static 3740 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3741 struct detailed_timing *timing, 3742 u32 quirks) 3743 { 3744 struct drm_display_mode *mode; 3745 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3746 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3747 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3748 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3749 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3750 unsigned hsync_offset = 3751 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3752 pt->hsync_offset_lo; 3753 unsigned hsync_pulse_width = 3754 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3755 pt->hsync_pulse_width_lo; 3756 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3757 2 | pt->vsync_offset_pulse_width_lo >> 4; 3758 unsigned vsync_pulse_width = 3759 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3760 (pt->vsync_offset_pulse_width_lo & 0xf); 3761 3762 /* ignore tiny modes */ 3763 if (hactive < 64 || vactive < 64) 3764 return NULL; 3765 3766 if (pt->misc & DRM_EDID_PT_STEREO) { 3767 debug("stereo mode not supported\n"); 3768 return NULL; 3769 } 3770 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3771 debug("composite sync not supported\n"); 3772 3773 /* it is incorrect if hsync/vsync width is zero */ 3774 if (!hsync_pulse_width || !vsync_pulse_width) { 3775 debug("Incorrect Detailed timing. "); 3776 debug("Wrong Hsync/Vsync pulse width\n"); 3777 return NULL; 3778 } 3779 3780 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3781 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3782 if (!mode) 3783 return NULL; 3784 3785 goto set_refresh; 3786 } 3787 3788 mode = drm_mode_create(); 3789 if (!mode) 3790 return NULL; 3791 3792 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3793 timing->pixel_clock = cpu_to_le16(1088); 3794 3795 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3796 3797 mode->hdisplay = hactive; 3798 mode->hsync_start = mode->hdisplay + hsync_offset; 3799 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3800 mode->htotal = mode->hdisplay + hblank; 3801 3802 mode->vdisplay = vactive; 3803 mode->vsync_start = mode->vdisplay + vsync_offset; 3804 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3805 mode->vtotal = mode->vdisplay + vblank; 3806 3807 /* Some EDIDs have bogus h/vtotal values */ 3808 if (mode->hsync_end > mode->htotal) 3809 mode->htotal = mode->hsync_end + 1; 3810 if (mode->vsync_end > mode->vtotal) 3811 mode->vtotal = mode->vsync_end + 1; 3812 3813 drm_mode_do_interlace_quirk(mode, pt); 3814 3815 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3816 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3817 DRM_EDID_PT_VSYNC_POSITIVE; 3818 3819 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3820 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3821 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3822 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3823 3824 set_refresh: 3825 3826 mode->type = DRM_MODE_TYPE_DRIVER; 3827 mode->vrefresh = drm_get_vrefresh(mode); 3828 3829 return mode; 3830 } 3831 3832 /* 3833 * Calculate the alternate clock for the CEA mode 3834 * (60Hz vs. 59.94Hz etc.) 3835 */ 3836 static unsigned int 3837 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3838 { 3839 unsigned int clock = cea_mode->clock; 3840 3841 if (cea_mode->vrefresh % 6 != 0) 3842 return clock; 3843 3844 /* 3845 * edid_cea_modes contains the 59.94Hz 3846 * variant for 240 and 480 line modes, 3847 * and the 60Hz variant otherwise. 3848 */ 3849 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3850 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3851 else 3852 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3853 3854 return clock; 3855 } 3856 3857 /** 3858 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3859 * @mode1: first mode 3860 * @mode2: second mode 3861 * 3862 * Check to see if @mode1 and @mode2 are equivalent, but 3863 * don't check the pixel clocks nor the stereo layout. 3864 * 3865 * Returns: 3866 * True if the modes are equal, false otherwise. 3867 */ 3868 3869 static 3870 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3871 const struct drm_display_mode *mode2) 3872 { 3873 unsigned int flags_mask = 3874 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3875 3876 if (mode1->hdisplay == mode2->hdisplay && 3877 mode1->hsync_start == mode2->hsync_start && 3878 mode1->hsync_end == mode2->hsync_end && 3879 mode1->htotal == mode2->htotal && 3880 mode1->vdisplay == mode2->vdisplay && 3881 mode1->vsync_start == mode2->vsync_start && 3882 mode1->vsync_end == mode2->vsync_end && 3883 mode1->vtotal == mode2->vtotal && 3884 mode1->vscan == mode2->vscan && 3885 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3886 return true; 3887 3888 return false; 3889 } 3890 3891 /** 3892 * drm_mode_equal_no_clocks - test modes for equality 3893 * @mode1: first mode 3894 * @mode2: second mode 3895 * 3896 * Check to see if @mode1 and @mode2 are equivalent, but 3897 * don't check the pixel clocks. 3898 * 3899 * Returns: 3900 * True if the modes are equal, false otherwise. 3901 */ 3902 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3903 const struct drm_display_mode *mode2) 3904 { 3905 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3906 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3907 return false; 3908 3909 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3910 } 3911 3912 static 3913 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3914 unsigned int clock_tolerance) 3915 { 3916 u8 vic; 3917 3918 if (!to_match->clock) 3919 return 0; 3920 3921 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3922 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 3923 unsigned int clock1, clock2; 3924 3925 /* Check both 60Hz and 59.94Hz */ 3926 clock1 = cea_mode->clock; 3927 clock2 = cea_mode_alternate_clock(cea_mode); 3928 3929 if (abs(to_match->clock - clock1) > clock_tolerance && 3930 abs(to_match->clock - clock2) > clock_tolerance) 3931 continue; 3932 3933 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3934 return vic; 3935 } 3936 3937 return 0; 3938 } 3939 3940 static unsigned int 3941 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3942 { 3943 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3944 return hdmi_mode->clock; 3945 3946 return cea_mode_alternate_clock(hdmi_mode); 3947 } 3948 3949 static 3950 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3951 unsigned int clock_tolerance) 3952 { 3953 u8 vic; 3954 3955 if (!to_match->clock) 3956 return 0; 3957 3958 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3959 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3960 unsigned int clock1, clock2; 3961 3962 /* Make sure to also match alternate clocks */ 3963 clock1 = hdmi_mode->clock; 3964 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3965 3966 if (abs(to_match->clock - clock1) > clock_tolerance && 3967 abs(to_match->clock - clock2) > clock_tolerance) 3968 continue; 3969 3970 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3971 return vic; 3972 } 3973 3974 return 0; 3975 } 3976 3977 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3978 { 3979 const struct drm_display_mode *cea_mode; 3980 int clock1, clock2, clock; 3981 u8 vic; 3982 const char *type; 3983 3984 /* 3985 * allow 5kHz clock difference either way to account for 3986 * the 10kHz clock resolution limit of detailed timings. 3987 */ 3988 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3989 if (drm_valid_cea_vic(vic)) { 3990 type = "CEA"; 3991 cea_mode = cea_mode_for_vic(vic); 3992 clock1 = cea_mode->clock; 3993 clock2 = cea_mode_alternate_clock(cea_mode); 3994 } else { 3995 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3996 if (drm_valid_hdmi_vic(vic)) { 3997 type = "HDMI"; 3998 cea_mode = &edid_4k_modes[vic]; 3999 clock1 = cea_mode->clock; 4000 clock2 = hdmi_mode_alternate_clock(cea_mode); 4001 } else { 4002 return; 4003 } 4004 } 4005 4006 /* pick whichever is closest */ 4007 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4008 clock = clock1; 4009 else 4010 clock = clock2; 4011 4012 if (mode->clock == clock) 4013 return; 4014 4015 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4016 type, vic, mode->clock, clock); 4017 mode->clock = clock; 4018 } 4019 4020 static void 4021 do_detailed_mode(struct detailed_timing *timing, void *c) 4022 { 4023 struct detailed_mode_closure *closure = c; 4024 struct drm_display_mode *newmode; 4025 4026 if (timing->pixel_clock) { 4027 newmode = drm_mode_detailed( 4028 closure->edid, timing, 4029 closure->quirks); 4030 if (!newmode) 4031 return; 4032 4033 if (closure->preferred) 4034 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4035 4036 /* 4037 * Detailed modes are limited to 10kHz pixel clock resolution, 4038 * so fix up anything that looks like CEA/HDMI mode, 4039 * but the clock is just slightly off. 4040 */ 4041 fixup_detailed_cea_mode_clock(newmode); 4042 drm_add_hdmi_modes(closure->data, newmode); 4043 drm_mode_destroy(newmode); 4044 closure->modes++; 4045 closure->preferred = 0; 4046 } 4047 } 4048 4049 /* 4050 * add_detailed_modes - Add modes from detailed timings 4051 * @data: attached data 4052 * @edid: EDID block to scan 4053 * @quirks: quirks to apply 4054 */ 4055 static int 4056 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 4057 u32 quirks) 4058 { 4059 struct detailed_mode_closure closure = { 4060 .data = data, 4061 .edid = edid, 4062 .preferred = 1, 4063 .quirks = quirks, 4064 }; 4065 4066 if (closure.preferred && !version_greater(edid, 1, 3)) 4067 closure.preferred = 4068 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 4069 4070 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 4071 4072 return closure.modes; 4073 } 4074 4075 static int drm_cvt_modes(struct hdmi_edid_data *data, 4076 struct detailed_timing *timing) 4077 { 4078 int i, j, modes = 0; 4079 struct drm_display_mode *newmode; 4080 struct cvt_timing *cvt; 4081 const int rates[] = { 60, 85, 75, 60, 50 }; 4082 const u8 empty[3] = { 0, 0, 0 }; 4083 4084 for (i = 0; i < 4; i++) { 4085 int uninitialized_var(width), height; 4086 4087 cvt = &timing->data.other_data.data.cvt[i]; 4088 4089 if (!memcmp(cvt->code, empty, 3)) 4090 continue; 4091 4092 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4093 switch (cvt->code[1] & 0x0c) { 4094 case 0x00: 4095 width = height * 4 / 3; 4096 break; 4097 case 0x04: 4098 width = height * 16 / 9; 4099 break; 4100 case 0x08: 4101 width = height * 16 / 10; 4102 break; 4103 case 0x0c: 4104 width = height * 15 / 9; 4105 break; 4106 } 4107 4108 for (j = 1; j < 5; j++) { 4109 if (cvt->code[2] & (1 << j)) { 4110 newmode = drm_cvt_mode(width, height, 4111 rates[j], j == 0, 4112 false, false); 4113 if (newmode) { 4114 drm_add_hdmi_modes(data, newmode); 4115 modes++; 4116 drm_mode_destroy(newmode); 4117 } 4118 } 4119 } 4120 } 4121 4122 return modes; 4123 } 4124 4125 static void 4126 do_cvt_mode(struct detailed_timing *timing, void *c) 4127 { 4128 struct detailed_mode_closure *closure = c; 4129 struct detailed_non_pixel *data = &timing->data.other_data; 4130 4131 if (data->type == EDID_DETAIL_CVT_3BYTE) 4132 closure->modes += drm_cvt_modes(closure->data, timing); 4133 } 4134 4135 static int 4136 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 4137 { 4138 struct detailed_mode_closure closure = { 4139 .data = data, 4140 .edid = edid, 4141 }; 4142 4143 if (version_greater(edid, 1, 2)) 4144 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 4145 4146 /* XXX should also look for CVT codes in VTB blocks */ 4147 4148 return closure.modes; 4149 } 4150 4151 static void 4152 find_gtf2(struct detailed_timing *t, void *data) 4153 { 4154 u8 *r = (u8 *)t; 4155 4156 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 4157 *(u8 **)data = r; 4158 } 4159 4160 /* Secondary GTF curve kicks in above some break frequency */ 4161 static int 4162 drm_gtf2_hbreak(struct edid *edid) 4163 { 4164 u8 *r = NULL; 4165 4166 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4167 return r ? (r[12] * 2) : 0; 4168 } 4169 4170 static int 4171 drm_gtf2_2c(struct edid *edid) 4172 { 4173 u8 *r = NULL; 4174 4175 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4176 return r ? r[13] : 0; 4177 } 4178 4179 static int 4180 drm_gtf2_m(struct edid *edid) 4181 { 4182 u8 *r = NULL; 4183 4184 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4185 return r ? (r[15] << 8) + r[14] : 0; 4186 } 4187 4188 static int 4189 drm_gtf2_k(struct edid *edid) 4190 { 4191 u8 *r = NULL; 4192 4193 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4194 return r ? r[16] : 0; 4195 } 4196 4197 static int 4198 drm_gtf2_2j(struct edid *edid) 4199 { 4200 u8 *r = NULL; 4201 4202 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4203 return r ? r[17] : 0; 4204 } 4205 4206 /** 4207 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 4208 * @edid: EDID block to scan 4209 */ 4210 static int standard_timing_level(struct edid *edid) 4211 { 4212 if (edid->revision >= 2) { 4213 if (edid->revision >= 4 && 4214 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 4215 return LEVEL_CVT; 4216 if (drm_gtf2_hbreak(edid)) 4217 return LEVEL_GTF2; 4218 return LEVEL_GTF; 4219 } 4220 return LEVEL_DMT; 4221 } 4222 4223 /* 4224 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 4225 * monitors fill with ascii space (0x20) instead. 4226 */ 4227 static int 4228 bad_std_timing(u8 a, u8 b) 4229 { 4230 return (a == 0x00 && b == 0x00) || 4231 (a == 0x01 && b == 0x01) || 4232 (a == 0x20 && b == 0x20); 4233 } 4234 4235 static void 4236 is_rb(struct detailed_timing *t, void *data) 4237 { 4238 u8 *r = (u8 *)t; 4239 4240 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 4241 if (r[15] & 0x10) 4242 *(bool *)data = true; 4243 } 4244 4245 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 4246 static bool 4247 drm_monitor_supports_rb(struct edid *edid) 4248 { 4249 if (edid->revision >= 4) { 4250 bool ret = false; 4251 4252 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 4253 return ret; 4254 } 4255 4256 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 4257 } 4258 4259 static bool 4260 mode_is_rb(const struct drm_display_mode *mode) 4261 { 4262 return (mode->htotal - mode->hdisplay == 160) && 4263 (mode->hsync_end - mode->hdisplay == 80) && 4264 (mode->hsync_end - mode->hsync_start == 32) && 4265 (mode->vsync_start - mode->vdisplay == 3); 4266 } 4267 4268 /* 4269 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 4270 * @hsize: Mode width 4271 * @vsize: Mode height 4272 * @fresh: Mode refresh rate 4273 * @rb: Mode reduced-blanking-ness 4274 * 4275 * Walk the DMT mode list looking for a match for the given parameters. 4276 * 4277 * Return: A newly allocated copy of the mode, or NULL if not found. 4278 */ 4279 static struct drm_display_mode *drm_mode_find_dmt( 4280 int hsize, int vsize, int fresh, 4281 bool rb) 4282 { 4283 int i; 4284 struct drm_display_mode *newmode; 4285 4286 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4287 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4288 4289 if (hsize != ptr->hdisplay) 4290 continue; 4291 if (vsize != ptr->vdisplay) 4292 continue; 4293 if (fresh != drm_get_vrefresh(ptr)) 4294 continue; 4295 if (rb != mode_is_rb(ptr)) 4296 continue; 4297 4298 newmode = drm_mode_create(); 4299 *newmode = *ptr; 4300 return newmode; 4301 } 4302 4303 return NULL; 4304 } 4305 4306 static struct drm_display_mode * 4307 drm_gtf_mode_complex(int hdisplay, int vdisplay, 4308 int vrefresh, bool interlaced, int margins, 4309 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 4310 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 4311 #define GTF_MARGIN_PERCENTAGE 18 4312 /* 2) character cell horizontal granularity (pixels) - default 8 */ 4313 #define GTF_CELL_GRAN 8 4314 /* 3) Minimum vertical porch (lines) - default 3 */ 4315 #define GTF_MIN_V_PORCH 1 4316 /* width of vsync in lines */ 4317 #define V_SYNC_RQD 3 4318 /* width of hsync as % of total line */ 4319 #define H_SYNC_PERCENT 8 4320 /* min time of vsync + back porch (microsec) */ 4321 #define MIN_VSYNC_PLUS_BP 550 4322 /* C' and M' are part of the Blanking Duty Cycle computation */ 4323 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 4324 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 4325 struct drm_display_mode *drm_mode; 4326 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 4327 int top_margin, bottom_margin; 4328 int interlace; 4329 unsigned int hfreq_est; 4330 int vsync_plus_bp; 4331 unsigned int vtotal_lines; 4332 int left_margin, right_margin; 4333 unsigned int total_active_pixels, ideal_duty_cycle; 4334 unsigned int hblank, total_pixels, pixel_freq; 4335 int hsync, hfront_porch, vodd_front_porch_lines; 4336 unsigned int tmp1, tmp2; 4337 4338 drm_mode = drm_mode_create(); 4339 if (!drm_mode) 4340 return NULL; 4341 4342 /* 1. In order to give correct results, the number of horizontal 4343 * pixels requested is first processed to ensure that it is divisible 4344 * by the character size, by rounding it to the nearest character 4345 * cell boundary: 4346 */ 4347 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4348 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 4349 4350 /* 2. If interlace is requested, the number of vertical lines assumed 4351 * by the calculation must be halved, as the computation calculates 4352 * the number of vertical lines per field. 4353 */ 4354 if (interlaced) 4355 vdisplay_rnd = vdisplay / 2; 4356 else 4357 vdisplay_rnd = vdisplay; 4358 4359 /* 3. Find the frame rate required: */ 4360 if (interlaced) 4361 vfieldrate_rqd = vrefresh * 2; 4362 else 4363 vfieldrate_rqd = vrefresh; 4364 4365 /* 4. Find number of lines in Top margin: */ 4366 top_margin = 0; 4367 if (margins) 4368 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4369 1000; 4370 /* 5. Find number of lines in bottom margin: */ 4371 bottom_margin = top_margin; 4372 4373 /* 6. If interlace is required, then set variable interlace: */ 4374 if (interlaced) 4375 interlace = 1; 4376 else 4377 interlace = 0; 4378 4379 /* 7. Estimate the Horizontal frequency */ 4380 { 4381 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 4382 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 4383 2 + interlace; 4384 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 4385 } 4386 4387 /* 8. Find the number of lines in V sync + back porch */ 4388 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 4389 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 4390 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 4391 /* 9. Find the number of lines in V back porch alone: 4392 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 4393 */ 4394 /* 10. Find the total number of lines in Vertical field period: */ 4395 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 4396 vsync_plus_bp + GTF_MIN_V_PORCH; 4397 /* 11. Estimate the Vertical field frequency: 4398 * vfieldrate_est = hfreq_est / vtotal_lines; 4399 */ 4400 4401 /* 12. Find the actual horizontal period: 4402 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 4403 */ 4404 /* 13. Find the actual Vertical field frequency: 4405 * vfield_rate = hfreq_est / vtotal_lines; 4406 */ 4407 /* 14. Find the Vertical frame frequency: 4408 * if (interlaced) 4409 * vframe_rate = vfield_rate / 2; 4410 * else 4411 * vframe_rate = vfield_rate; 4412 */ 4413 /* 15. Find number of pixels in left margin: */ 4414 if (margins) 4415 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4416 1000; 4417 else 4418 left_margin = 0; 4419 4420 /* 16.Find number of pixels in right margin: */ 4421 right_margin = left_margin; 4422 /* 17.Find total number of active pixels in image and left and right */ 4423 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 4424 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 4425 ideal_duty_cycle = GTF_C_PRIME * 1000 - 4426 (GTF_M_PRIME * 1000000 / hfreq_est); 4427 /* 19.Find the number of pixels in the blanking time to the nearest 4428 * double character cell: 4429 */ 4430 hblank = total_active_pixels * ideal_duty_cycle / 4431 (100000 - ideal_duty_cycle); 4432 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 4433 hblank = hblank * 2 * GTF_CELL_GRAN; 4434 /* 20.Find total number of pixels: */ 4435 total_pixels = total_active_pixels + hblank; 4436 /* 21.Find pixel clock frequency: */ 4437 pixel_freq = total_pixels * hfreq_est / 1000; 4438 /* Stage 1 computations are now complete; I should really pass 4439 * the results to another function and do the Stage 2 computations, 4440 * but I only need a few more values so I'll just append the 4441 * computations here for now 4442 */ 4443 4444 /* 17. Find the number of pixels in the horizontal sync period: */ 4445 hsync = H_SYNC_PERCENT * total_pixels / 100; 4446 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4447 hsync = hsync * GTF_CELL_GRAN; 4448 /* 18. Find the number of pixels in horizontal front porch period */ 4449 hfront_porch = hblank / 2 - hsync; 4450 /* 36. Find the number of lines in the odd front porch period: */ 4451 vodd_front_porch_lines = GTF_MIN_V_PORCH; 4452 4453 /* finally, pack the results in the mode struct */ 4454 drm_mode->hdisplay = hdisplay_rnd; 4455 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 4456 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 4457 drm_mode->htotal = total_pixels; 4458 drm_mode->vdisplay = vdisplay_rnd; 4459 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 4460 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 4461 drm_mode->vtotal = vtotal_lines; 4462 4463 drm_mode->clock = pixel_freq; 4464 4465 if (interlaced) { 4466 drm_mode->vtotal *= 2; 4467 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 4468 } 4469 4470 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 4471 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 4472 else 4473 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 4474 4475 return drm_mode; 4476 } 4477 4478 /** 4479 * drm_gtf_mode - create the mode based on the GTF algorithm 4480 * @hdisplay: hdisplay size 4481 * @vdisplay: vdisplay size 4482 * @vrefresh: vrefresh rate. 4483 * @interlaced: whether to compute an interlaced mode 4484 * @margins: desired margin (borders) size 4485 * 4486 * return the mode based on GTF algorithm 4487 * 4488 * This function is to create the mode based on the GTF algorithm. 4489 * Generalized Timing Formula is derived from: 4490 * GTF Spreadsheet by Andy Morrish (1/5/97) 4491 * available at http://www.vesa.org 4492 * 4493 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 4494 * What I have done is to translate it by using integer calculation. 4495 * I also refer to the function of fb_get_mode in the file of 4496 * drivers/video/fbmon.c 4497 * 4498 * Standard GTF parameters: 4499 * M = 600 4500 * C = 40 4501 * K = 128 4502 * J = 20 4503 * 4504 * Returns: 4505 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 4506 * The display mode object is allocated with drm_mode_create(). Returns NULL 4507 * when no mode could be allocated. 4508 */ 4509 static struct drm_display_mode * 4510 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 4511 bool interlaced, int margins) 4512 { 4513 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 4514 interlaced, margins, 4515 600, 40 * 2, 128, 20 * 2); 4516 } 4517 4518 /** drm_mode_hsync - get the hsync of a mode 4519 * @mode: mode 4520 * 4521 * Returns: 4522 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 4523 * value first if it is not yet set. 4524 */ 4525 static int drm_mode_hsync(const struct drm_display_mode *mode) 4526 { 4527 unsigned int calc_val; 4528 4529 if (mode->htotal < 0) 4530 return 0; 4531 4532 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 4533 calc_val += 500; /* round to 1000Hz */ 4534 calc_val /= 1000; /* truncate to kHz */ 4535 4536 return calc_val; 4537 } 4538 4539 /** 4540 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 4541 * @data: the structure that save parsed hdmi edid data 4542 * @edid: EDID block to scan 4543 * @t: standard timing params 4544 * 4545 * Take the standard timing params (in this case width, aspect, and refresh) 4546 * and convert them into a real mode using CVT/GTF/DMT. 4547 */ 4548 static struct drm_display_mode * 4549 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4550 struct std_timing *t) 4551 { 4552 struct drm_display_mode *mode = NULL; 4553 int i, hsize, vsize; 4554 int vrefresh_rate; 4555 int num = data->modes; 4556 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4557 >> EDID_TIMING_ASPECT_SHIFT; 4558 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4559 >> EDID_TIMING_VFREQ_SHIFT; 4560 int timing_level = standard_timing_level(edid); 4561 4562 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4563 return NULL; 4564 4565 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4566 hsize = t->hsize * 8 + 248; 4567 /* vrefresh_rate = vfreq + 60 */ 4568 vrefresh_rate = vfreq + 60; 4569 /* the vdisplay is calculated based on the aspect ratio */ 4570 if (aspect_ratio == 0) { 4571 if (edid->revision < 3) 4572 vsize = hsize; 4573 else 4574 vsize = (hsize * 10) / 16; 4575 } else if (aspect_ratio == 1) { 4576 vsize = (hsize * 3) / 4; 4577 } else if (aspect_ratio == 2) { 4578 vsize = (hsize * 4) / 5; 4579 } else { 4580 vsize = (hsize * 9) / 16; 4581 } 4582 4583 /* HDTV hack, part 1 */ 4584 if (vrefresh_rate == 60 && 4585 ((hsize == 1360 && vsize == 765) || 4586 (hsize == 1368 && vsize == 769))) { 4587 hsize = 1366; 4588 vsize = 768; 4589 } 4590 4591 /* 4592 * If we already has a mode for this size and refresh 4593 * rate (because it came from detailed or CVT info), use that 4594 * instead. This way we don't have to guess at interlace or 4595 * reduced blanking. 4596 */ 4597 for (i = 0; i < num; i++) 4598 if (data->mode_buf[i].hdisplay == hsize && 4599 data->mode_buf[i].vdisplay == vsize && 4600 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4601 return NULL; 4602 4603 /* HDTV hack, part 2 */ 4604 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4605 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4606 false); 4607 mode->hdisplay = 1366; 4608 mode->hsync_start = mode->hsync_start - 1; 4609 mode->hsync_end = mode->hsync_end - 1; 4610 return mode; 4611 } 4612 4613 /* check whether it can be found in default mode table */ 4614 if (drm_monitor_supports_rb(edid)) { 4615 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4616 true); 4617 if (mode) 4618 return mode; 4619 } 4620 4621 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4622 if (mode) 4623 return mode; 4624 4625 /* okay, generate it */ 4626 switch (timing_level) { 4627 case LEVEL_DMT: 4628 break; 4629 case LEVEL_GTF: 4630 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4631 break; 4632 case LEVEL_GTF2: 4633 /* 4634 * This is potentially wrong if there's ever a monitor with 4635 * more than one ranges section, each claiming a different 4636 * secondary GTF curve. Please don't do that. 4637 */ 4638 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4639 if (!mode) 4640 return NULL; 4641 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4642 drm_mode_destroy(mode); 4643 mode = drm_gtf_mode_complex(hsize, vsize, 4644 vrefresh_rate, 0, 0, 4645 drm_gtf2_m(edid), 4646 drm_gtf2_2c(edid), 4647 drm_gtf2_k(edid), 4648 drm_gtf2_2j(edid)); 4649 } 4650 break; 4651 case LEVEL_CVT: 4652 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4653 false); 4654 break; 4655 } 4656 4657 return mode; 4658 } 4659 4660 static void 4661 do_standard_modes(struct detailed_timing *timing, void *c) 4662 { 4663 struct detailed_mode_closure *closure = c; 4664 struct detailed_non_pixel *data = &timing->data.other_data; 4665 struct edid *edid = closure->edid; 4666 4667 if (data->type == EDID_DETAIL_STD_MODES) { 4668 int i; 4669 4670 for (i = 0; i < 6; i++) { 4671 struct std_timing *std; 4672 struct drm_display_mode *newmode; 4673 4674 std = &data->data.timings[i]; 4675 newmode = drm_mode_std(closure->data, edid, std); 4676 if (newmode) { 4677 drm_add_hdmi_modes(closure->data, newmode); 4678 closure->modes++; 4679 drm_mode_destroy(newmode); 4680 } 4681 } 4682 } 4683 } 4684 4685 /** 4686 * add_standard_modes - get std. modes from EDID and add them 4687 * @data: data to add mode(s) to 4688 * @edid: EDID block to scan 4689 * 4690 * Standard modes can be calculated using the appropriate standard (DMT, 4691 * GTF or CVT. Grab them from @edid and add them to the list. 4692 */ 4693 static int 4694 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4695 { 4696 int i, modes = 0; 4697 struct detailed_mode_closure closure = { 4698 .data = data, 4699 .edid = edid, 4700 }; 4701 4702 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4703 struct drm_display_mode *newmode; 4704 4705 newmode = drm_mode_std(data, edid, 4706 &edid->standard_timings[i]); 4707 if (newmode) { 4708 drm_add_hdmi_modes(data, newmode); 4709 modes++; 4710 drm_mode_destroy(newmode); 4711 } 4712 } 4713 4714 if (version_greater(edid, 1, 0)) 4715 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4716 &closure); 4717 4718 /* XXX should also look for standard codes in VTB blocks */ 4719 4720 return modes + closure.modes; 4721 } 4722 4723 static int 4724 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4725 { 4726 int i, j, m, modes = 0; 4727 struct drm_display_mode *mode; 4728 u8 *est = ((u8 *)timing) + 6; 4729 4730 for (i = 0; i < 6; i++) { 4731 for (j = 7; j >= 0; j--) { 4732 m = (i * 8) + (7 - j); 4733 if (m >= ARRAY_SIZE(est3_modes)) 4734 break; 4735 if (est[i] & (1 << j)) { 4736 mode = drm_mode_find_dmt( 4737 est3_modes[m].w, 4738 est3_modes[m].h, 4739 est3_modes[m].r, 4740 est3_modes[m].rb); 4741 if (mode) { 4742 drm_add_hdmi_modes(data, mode); 4743 modes++; 4744 drm_mode_destroy(mode); 4745 } 4746 } 4747 } 4748 } 4749 4750 return modes; 4751 } 4752 4753 static void 4754 do_established_modes(struct detailed_timing *timing, void *c) 4755 { 4756 struct detailed_mode_closure *closure = c; 4757 struct detailed_non_pixel *data = &timing->data.other_data; 4758 4759 if (data->type == EDID_DETAIL_EST_TIMINGS) 4760 closure->modes += drm_est3_modes(closure->data, timing); 4761 } 4762 4763 /** 4764 * add_established_modes - get est. modes from EDID and add them 4765 * @data: data to add mode(s) to 4766 * @edid: EDID block to scan 4767 * 4768 * Each EDID block contains a bitmap of the supported "established modes" list 4769 * (defined above). Tease them out and add them to the modes list. 4770 */ 4771 static int 4772 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4773 { 4774 unsigned long est_bits = edid->established_timings.t1 | 4775 (edid->established_timings.t2 << 8) | 4776 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4777 int i, modes = 0; 4778 struct detailed_mode_closure closure = { 4779 .data = data, 4780 .edid = edid, 4781 }; 4782 4783 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4784 if (est_bits & (1 << i)) { 4785 struct drm_display_mode *newmode = drm_mode_create(); 4786 *newmode = edid_est_modes[i]; 4787 if (newmode) { 4788 drm_add_hdmi_modes(data, newmode); 4789 modes++; 4790 drm_mode_destroy(newmode); 4791 } 4792 } 4793 } 4794 4795 if (version_greater(edid, 1, 0)) 4796 drm_for_each_detailed_block((u8 *)edid, 4797 do_established_modes, &closure); 4798 4799 return modes + closure.modes; 4800 } 4801 4802 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4803 { 4804 u8 vic; 4805 4806 if (!to_match->clock) 4807 return 0; 4808 4809 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4810 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4811 unsigned int clock1, clock2; 4812 4813 /* Make sure to also match alternate clocks */ 4814 clock1 = hdmi_mode->clock; 4815 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4816 4817 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4818 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4819 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4820 return vic; 4821 } 4822 return 0; 4823 } 4824 4825 static int 4826 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4827 { 4828 struct drm_display_mode *mode; 4829 int i, num, modes = 0; 4830 4831 /* Don't add CEA modes if the CEA extension block is missing */ 4832 if (!drm_find_cea_extension(edid)) 4833 return 0; 4834 4835 /* 4836 * Go through all probed modes and create a new mode 4837 * with the alternate clock for certain CEA modes. 4838 */ 4839 num = data->modes; 4840 4841 for (i = 0; i < num; i++) { 4842 const struct drm_display_mode *cea_mode = NULL; 4843 struct drm_display_mode *newmode; 4844 u8 vic; 4845 unsigned int clock1, clock2; 4846 4847 mode = &data->mode_buf[i]; 4848 vic = drm_match_cea_mode(mode); 4849 4850 if (drm_valid_cea_vic(vic)) { 4851 cea_mode = cea_mode_for_vic(vic); 4852 clock2 = cea_mode_alternate_clock(cea_mode); 4853 } else { 4854 vic = drm_match_hdmi_mode(mode); 4855 if (drm_valid_hdmi_vic(vic)) { 4856 cea_mode = &edid_4k_modes[vic]; 4857 clock2 = hdmi_mode_alternate_clock(cea_mode); 4858 } 4859 } 4860 4861 if (!cea_mode) 4862 continue; 4863 4864 clock1 = cea_mode->clock; 4865 4866 if (clock1 == clock2) 4867 continue; 4868 4869 if (mode->clock != clock1 && mode->clock != clock2) 4870 continue; 4871 4872 newmode = drm_mode_create(); 4873 *newmode = *cea_mode; 4874 if (!newmode) 4875 continue; 4876 4877 /* Carry over the stereo flags */ 4878 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4879 4880 /* 4881 * The current mode could be either variant. Make 4882 * sure to pick the "other" clock for the new mode. 4883 */ 4884 if (mode->clock != clock1) 4885 newmode->clock = clock1; 4886 else 4887 newmode->clock = clock2; 4888 4889 drm_add_hdmi_modes(data, newmode); 4890 modes++; 4891 drm_mode_destroy(newmode); 4892 } 4893 4894 return modes; 4895 } 4896 4897 static u8 *drm_find_displayid_extension(struct edid *edid) 4898 { 4899 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4900 } 4901 4902 static int validate_displayid(u8 *displayid, int length, int idx) 4903 { 4904 int i; 4905 u8 csum = 0; 4906 struct displayid_hdr *base; 4907 4908 base = (struct displayid_hdr *)&displayid[idx]; 4909 4910 debug("base revision 0x%x, length %d, %d %d\n", 4911 base->rev, base->bytes, base->prod_id, base->ext_count); 4912 4913 if (base->bytes + 5 > length - idx) 4914 return -EINVAL; 4915 for (i = idx; i <= base->bytes + 5; i++) 4916 csum += displayid[i]; 4917 if (csum) { 4918 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4919 return -EINVAL; 4920 } 4921 return 0; 4922 } 4923 4924 static struct 4925 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4926 *timings) 4927 { 4928 struct drm_display_mode *mode; 4929 unsigned pixel_clock = (timings->pixel_clock[0] | 4930 (timings->pixel_clock[1] << 8) | 4931 (timings->pixel_clock[2] << 16)); 4932 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4933 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4934 unsigned hsync = (timings->hsync[0] | 4935 (timings->hsync[1] & 0x7f) << 8) + 1; 4936 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4937 unsigned vactive = (timings->vactive[0] | 4938 timings->vactive[1] << 8) + 1; 4939 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4940 unsigned vsync = (timings->vsync[0] | 4941 (timings->vsync[1] & 0x7f) << 8) + 1; 4942 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4943 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4944 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4945 4946 mode = drm_mode_create(); 4947 if (!mode) 4948 return NULL; 4949 4950 mode->clock = pixel_clock * 10; 4951 mode->hdisplay = hactive; 4952 mode->hsync_start = mode->hdisplay + hsync; 4953 mode->hsync_end = mode->hsync_start + hsync_width; 4954 mode->htotal = mode->hdisplay + hblank; 4955 4956 mode->vdisplay = vactive; 4957 mode->vsync_start = mode->vdisplay + vsync; 4958 mode->vsync_end = mode->vsync_start + vsync_width; 4959 mode->vtotal = mode->vdisplay + vblank; 4960 4961 mode->flags = 0; 4962 mode->flags |= 4963 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4964 mode->flags |= 4965 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4966 mode->type = DRM_MODE_TYPE_DRIVER; 4967 4968 if (timings->flags & 0x80) 4969 mode->type |= DRM_MODE_TYPE_PREFERRED; 4970 mode->vrefresh = drm_get_vrefresh(mode); 4971 4972 return mode; 4973 } 4974 4975 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 4976 struct displayid_block *block) 4977 { 4978 struct displayid_detailed_timing_block *det; 4979 int i; 4980 int num_timings; 4981 struct drm_display_mode *newmode; 4982 int num_modes = 0; 4983 4984 det = (struct displayid_detailed_timing_block *)block; 4985 /* blocks must be multiple of 20 bytes length */ 4986 if (block->num_bytes % 20) 4987 return 0; 4988 4989 num_timings = block->num_bytes / 20; 4990 for (i = 0; i < num_timings; i++) { 4991 struct displayid_detailed_timings_1 *timings = 4992 &det->timings[i]; 4993 4994 newmode = drm_displayid_detailed(timings); 4995 if (!newmode) 4996 continue; 4997 4998 drm_add_hdmi_modes(data, newmode); 4999 num_modes++; 5000 drm_mode_destroy(newmode); 5001 } 5002 return num_modes; 5003 } 5004 5005 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 5006 struct edid *edid) 5007 { 5008 u8 *displayid; 5009 int ret; 5010 int idx = 1; 5011 int length = EDID_SIZE; 5012 struct displayid_block *block; 5013 int num_modes = 0; 5014 5015 displayid = drm_find_displayid_extension(edid); 5016 if (!displayid) 5017 return 0; 5018 5019 ret = validate_displayid(displayid, length, idx); 5020 if (ret) 5021 return 0; 5022 5023 idx += sizeof(struct displayid_hdr); 5024 while (block = (struct displayid_block *)&displayid[idx], 5025 idx + sizeof(struct displayid_block) <= length && 5026 idx + sizeof(struct displayid_block) + block->num_bytes <= 5027 length && block->num_bytes > 0) { 5028 idx += block->num_bytes + sizeof(struct displayid_block); 5029 switch (block->tag) { 5030 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5031 num_modes += 5032 add_displayid_detailed_1_modes(data, block); 5033 break; 5034 } 5035 } 5036 return num_modes; 5037 } 5038 5039 static bool 5040 mode_in_hsync_range(const struct drm_display_mode *mode, 5041 struct edid *edid, u8 *t) 5042 { 5043 int hsync, hmin, hmax; 5044 5045 hmin = t[7]; 5046 if (edid->revision >= 4) 5047 hmin += ((t[4] & 0x04) ? 255 : 0); 5048 hmax = t[8]; 5049 if (edid->revision >= 4) 5050 hmax += ((t[4] & 0x08) ? 255 : 0); 5051 hsync = drm_mode_hsync(mode); 5052 5053 return (hsync <= hmax && hsync >= hmin); 5054 } 5055 5056 static bool 5057 mode_in_vsync_range(const struct drm_display_mode *mode, 5058 struct edid *edid, u8 *t) 5059 { 5060 int vsync, vmin, vmax; 5061 5062 vmin = t[5]; 5063 if (edid->revision >= 4) 5064 vmin += ((t[4] & 0x01) ? 255 : 0); 5065 vmax = t[6]; 5066 if (edid->revision >= 4) 5067 vmax += ((t[4] & 0x02) ? 255 : 0); 5068 vsync = drm_get_vrefresh(mode); 5069 5070 return (vsync <= vmax && vsync >= vmin); 5071 } 5072 5073 static u32 5074 range_pixel_clock(struct edid *edid, u8 *t) 5075 { 5076 /* unspecified */ 5077 if (t[9] == 0 || t[9] == 255) 5078 return 0; 5079 5080 /* 1.4 with CVT support gives us real precision, yay */ 5081 if (edid->revision >= 4 && t[10] == 0x04) 5082 return (t[9] * 10000) - ((t[12] >> 2) * 250); 5083 5084 /* 1.3 is pathetic, so fuzz up a bit */ 5085 return t[9] * 10000 + 5001; 5086 } 5087 5088 static bool 5089 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 5090 struct detailed_timing *timing) 5091 { 5092 u32 max_clock; 5093 u8 *t = (u8 *)timing; 5094 5095 if (!mode_in_hsync_range(mode, edid, t)) 5096 return false; 5097 5098 if (!mode_in_vsync_range(mode, edid, t)) 5099 return false; 5100 5101 max_clock = range_pixel_clock(edid, t); 5102 if (max_clock) 5103 if (mode->clock > max_clock) 5104 return false; 5105 5106 /* 1.4 max horizontal check */ 5107 if (edid->revision >= 4 && t[10] == 0x04) 5108 if (t[13] && mode->hdisplay > 8 * 5109 (t[13] + (256 * (t[12] & 0x3)))) 5110 return false; 5111 5112 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 5113 return false; 5114 5115 return true; 5116 } 5117 5118 static bool valid_inferred_mode(struct hdmi_edid_data *data, 5119 const struct drm_display_mode *mode) 5120 { 5121 const struct drm_display_mode *m; 5122 bool ok = false; 5123 int i; 5124 5125 for (i = 0; i < data->modes; i++) { 5126 m = &data->mode_buf[i]; 5127 if (mode->hdisplay == m->hdisplay && 5128 mode->vdisplay == m->vdisplay && 5129 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 5130 return false; /* duplicated */ 5131 if (mode->hdisplay <= m->hdisplay && 5132 mode->vdisplay <= m->vdisplay) 5133 ok = true; 5134 } 5135 return ok; 5136 } 5137 5138 static int 5139 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5140 struct detailed_timing *timing) 5141 { 5142 int i, modes = 0; 5143 5144 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 5145 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 5146 valid_inferred_mode(data, drm_dmt_modes + i)) { 5147 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 5148 modes++; 5149 } 5150 } 5151 5152 return modes; 5153 } 5154 5155 /* fix up 1366x768 mode from 1368x768; 5156 * GFT/CVT can't express 1366 width which isn't dividable by 8 5157 */ 5158 static void fixup_mode_1366x768(struct drm_display_mode *mode) 5159 { 5160 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 5161 mode->hdisplay = 1366; 5162 mode->hsync_start--; 5163 mode->hsync_end--; 5164 } 5165 } 5166 5167 static int 5168 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5169 struct detailed_timing *timing) 5170 { 5171 int i, modes = 0; 5172 struct drm_display_mode *newmode; 5173 5174 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5175 const struct minimode *m = &extra_modes[i]; 5176 5177 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 5178 if (!newmode) 5179 return modes; 5180 5181 fixup_mode_1366x768(newmode); 5182 if (!mode_in_range(newmode, edid, timing) || 5183 !valid_inferred_mode(data, newmode)) { 5184 drm_mode_destroy(newmode); 5185 continue; 5186 } 5187 5188 drm_add_hdmi_modes(data, newmode); 5189 modes++; 5190 drm_mode_destroy(newmode); 5191 } 5192 5193 return modes; 5194 } 5195 5196 static int 5197 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5198 struct detailed_timing *timing) 5199 { 5200 int i, modes = 0; 5201 struct drm_display_mode *newmode; 5202 bool rb = drm_monitor_supports_rb(edid); 5203 5204 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5205 const struct minimode *m = &extra_modes[i]; 5206 5207 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 5208 if (!newmode) 5209 return modes; 5210 5211 fixup_mode_1366x768(newmode); 5212 if (!mode_in_range(newmode, edid, timing) || 5213 !valid_inferred_mode(data, newmode)) { 5214 drm_mode_destroy(newmode); 5215 continue; 5216 } 5217 5218 drm_add_hdmi_modes(data, newmode); 5219 modes++; 5220 drm_mode_destroy(newmode); 5221 } 5222 5223 return modes; 5224 } 5225 5226 static void 5227 do_inferred_modes(struct detailed_timing *timing, void *c) 5228 { 5229 struct detailed_mode_closure *closure = c; 5230 struct detailed_non_pixel *data = &timing->data.other_data; 5231 struct detailed_data_monitor_range *range = &data->data.range; 5232 5233 if (data->type != EDID_DETAIL_MONITOR_RANGE) 5234 return; 5235 5236 closure->modes += drm_dmt_modes_for_range(closure->data, 5237 closure->edid, 5238 timing); 5239 5240 if (!version_greater(closure->edid, 1, 1)) 5241 return; /* GTF not defined yet */ 5242 5243 switch (range->flags) { 5244 case 0x02: /* secondary gtf, XXX could do more */ 5245 case 0x00: /* default gtf */ 5246 closure->modes += drm_gtf_modes_for_range(closure->data, 5247 closure->edid, 5248 timing); 5249 break; 5250 case 0x04: /* cvt, only in 1.4+ */ 5251 if (!version_greater(closure->edid, 1, 3)) 5252 break; 5253 5254 closure->modes += drm_cvt_modes_for_range(closure->data, 5255 closure->edid, 5256 timing); 5257 break; 5258 case 0x01: /* just the ranges, no formula */ 5259 default: 5260 break; 5261 } 5262 } 5263 5264 static int 5265 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 5266 { 5267 struct detailed_mode_closure closure = { 5268 .data = data, 5269 .edid = edid, 5270 }; 5271 5272 if (version_greater(edid, 1, 0)) 5273 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 5274 &closure); 5275 5276 return closure.modes; 5277 } 5278 5279 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 5280 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 5281 5282 /** 5283 * edid_fixup_preferred - set preferred modes based on quirk list 5284 * @data: the structure that save parsed hdmi edid data 5285 * @quirks: quirks list 5286 * 5287 * Walk the mode list, clearing the preferred status 5288 * on existing modes and setting it anew for the right mode ala @quirks. 5289 */ 5290 static void edid_fixup_preferred(struct hdmi_edid_data *data, 5291 u32 quirks) 5292 { 5293 struct drm_display_mode *cur_mode, *preferred_mode; 5294 int i, target_refresh = 0; 5295 int num = data->modes; 5296 int cur_vrefresh, preferred_vrefresh; 5297 5298 if (!num) 5299 return; 5300 5301 preferred_mode = data->preferred_mode; 5302 5303 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 5304 target_refresh = 60; 5305 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 5306 target_refresh = 75; 5307 5308 for (i = 0; i < num; i++) { 5309 cur_mode = &data->mode_buf[i]; 5310 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 5311 5312 if (cur_mode == preferred_mode) 5313 continue; 5314 5315 /* Largest mode is preferred */ 5316 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 5317 preferred_mode = cur_mode; 5318 5319 cur_vrefresh = cur_mode->vrefresh ? 5320 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 5321 preferred_vrefresh = preferred_mode->vrefresh ? 5322 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 5323 /* At a given size, try to get closest to target refresh */ 5324 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 5325 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 5326 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 5327 preferred_mode = cur_mode; 5328 } 5329 } 5330 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 5331 data->preferred_mode = preferred_mode; 5332 } 5333 5334 static const u8 edid_header[] = { 5335 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 5336 }; 5337 5338 /** 5339 * drm_edid_header_is_valid - sanity check the header of the base EDID block 5340 * @raw_edid: pointer to raw base EDID block 5341 * 5342 * Sanity check the header of the base EDID block. 5343 * 5344 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 5345 */ 5346 static int drm_edid_header_is_valid(const u8 *raw_edid) 5347 { 5348 int i, score = 0; 5349 5350 for (i = 0; i < sizeof(edid_header); i++) 5351 if (raw_edid[i] == edid_header[i]) 5352 score++; 5353 5354 return score; 5355 } 5356 5357 static int drm_edid_block_checksum(const u8 *raw_edid) 5358 { 5359 int i; 5360 u8 csum = 0; 5361 5362 for (i = 0; i < EDID_SIZE; i++) 5363 csum += raw_edid[i]; 5364 5365 return csum; 5366 } 5367 5368 static bool drm_edid_is_zero(const u8 *in_edid, int length) 5369 { 5370 if (memchr_inv(in_edid, 0, length)) 5371 return false; 5372 5373 return true; 5374 } 5375 5376 /** 5377 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 5378 * @raw_edid: pointer to raw EDID block 5379 * @block: type of block to validate (0 for base, extension otherwise) 5380 * @print_bad_edid: if true, dump bad EDID blocks to the console 5381 * @edid_corrupt: if true, the header or checksum is invalid 5382 * 5383 * Validate a base or extension EDID block and optionally dump bad blocks to 5384 * the console. 5385 * 5386 * Return: True if the block is valid, false otherwise. 5387 */ 5388 static 5389 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 5390 bool *edid_corrupt) 5391 { 5392 u8 csum; 5393 int edid_fixup = 6; 5394 struct edid *edid = (struct edid *)raw_edid; 5395 5396 if ((!raw_edid)) 5397 return false; 5398 5399 if (block == 0) { 5400 int score = drm_edid_header_is_valid(raw_edid); 5401 5402 if (score == 8) { 5403 if (edid_corrupt) 5404 *edid_corrupt = false; 5405 } else if (score >= edid_fixup) { 5406 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 5407 * The corrupt flag needs to be set here otherwise, the 5408 * fix-up code here will correct the problem, the 5409 * checksum is correct and the test fails 5410 */ 5411 if (edid_corrupt) 5412 *edid_corrupt = true; 5413 debug("Fixing header, your hardware may be failing\n"); 5414 memcpy(raw_edid, edid_header, sizeof(edid_header)); 5415 } else { 5416 if (edid_corrupt) 5417 *edid_corrupt = true; 5418 goto bad; 5419 } 5420 } 5421 5422 csum = drm_edid_block_checksum(raw_edid); 5423 if (csum) { 5424 if (print_bad_edid) { 5425 debug("EDID checksum is invalid, remainder is %d\n", 5426 csum); 5427 } 5428 5429 if (edid_corrupt) 5430 *edid_corrupt = true; 5431 5432 /* allow CEA to slide through, switches mangle this */ 5433 if (raw_edid[0] != 0x02) 5434 goto bad; 5435 } 5436 5437 /* per-block-type checks */ 5438 switch (raw_edid[0]) { 5439 case 0: /* base */ 5440 if (edid->version != 1) { 5441 debug("EDID has major version %d, instead of 1\n", 5442 edid->version); 5443 goto bad; 5444 } 5445 5446 if (edid->revision > 4) 5447 debug("minor > 4, assuming backward compatibility\n"); 5448 break; 5449 5450 default: 5451 break; 5452 } 5453 5454 return true; 5455 5456 bad: 5457 if (print_bad_edid) { 5458 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 5459 debug("EDID block is all zeroes\n"); 5460 } else { 5461 debug("Raw EDID:\n"); 5462 print_hex_dump("", DUMP_PREFIX_NONE, 16, 1, 5463 raw_edid, EDID_SIZE, false); 5464 } 5465 } 5466 return false; 5467 } 5468 5469 /** 5470 * drm_edid_is_valid - sanity check EDID data 5471 * @edid: EDID data 5472 * 5473 * Sanity-check an entire EDID record (including extensions) 5474 * 5475 * Return: True if the EDID data is valid, false otherwise. 5476 */ 5477 static bool drm_edid_is_valid(struct edid *edid) 5478 { 5479 int i; 5480 u8 *raw = (u8 *)edid; 5481 5482 if (!edid) 5483 return false; 5484 5485 for (i = 0; i <= edid->extensions; i++) 5486 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 5487 return false; 5488 5489 return true; 5490 } 5491 5492 /** 5493 * drm_add_edid_modes - add modes from EDID data, if available 5494 * @data: data we're probing 5495 * @edid: EDID data 5496 * 5497 * Add the specified modes to the data's mode list. 5498 * 5499 * Return: The number of modes added or 0 if we couldn't find any. 5500 */ 5501 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 5502 { 5503 int num_modes = 0; 5504 u32 quirks; 5505 struct edid *edid = (struct edid *)raw_edid; 5506 5507 if (!edid) { 5508 debug("no edid\n"); 5509 return 0; 5510 } 5511 5512 if (!drm_edid_is_valid(edid)) { 5513 debug("EDID invalid\n"); 5514 return 0; 5515 } 5516 5517 if (!data->mode_buf) { 5518 debug("mode buff is null\n"); 5519 return 0; 5520 } 5521 5522 quirks = edid_get_quirks(edid); 5523 /* 5524 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5525 * To avoid multiple parsing of same block, lets parse that map 5526 * from sink info, before parsing CEA modes. 5527 */ 5528 drm_add_display_info(data, edid); 5529 5530 /* 5531 * EDID spec says modes should be preferred in this order: 5532 * - preferred detailed mode 5533 * - other detailed modes from base block 5534 * - detailed modes from extension blocks 5535 * - CVT 3-byte code modes 5536 * - standard timing codes 5537 * - established timing codes 5538 * - modes inferred from GTF or CVT range information 5539 * 5540 * We get this pretty much right. 5541 * 5542 * XXX order for additional mode types in extension blocks? 5543 */ 5544 num_modes += add_detailed_modes(data, edid, quirks); 5545 num_modes += add_cvt_modes(data, edid); 5546 num_modes += add_standard_modes(data, edid); 5547 num_modes += add_established_modes(data, edid); 5548 num_modes += add_cea_modes(data, edid); 5549 num_modes += add_alternate_cea_modes(data, edid); 5550 num_modes += add_displayid_detailed_modes(data, edid); 5551 5552 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5553 num_modes += add_inferred_modes(data, edid); 5554 5555 if (num_modes > 0) 5556 data->preferred_mode = &data->mode_buf[0]; 5557 5558 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5559 edid_fixup_preferred(data, quirks); 5560 5561 if (quirks & EDID_QUIRK_FORCE_6BPC) 5562 data->display_info.bpc = 6; 5563 5564 if (quirks & EDID_QUIRK_FORCE_8BPC) 5565 data->display_info.bpc = 8; 5566 5567 if (quirks & EDID_QUIRK_FORCE_10BPC) 5568 data->display_info.bpc = 10; 5569 5570 if (quirks & EDID_QUIRK_FORCE_12BPC) 5571 data->display_info.bpc = 12; 5572 5573 return num_modes; 5574 } 5575 5576 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5577 { 5578 u8 vic; 5579 5580 if (!to_match->clock) { 5581 printf("can't find to match\n"); 5582 return 0; 5583 } 5584 5585 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 5586 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 5587 unsigned int clock1, clock2; 5588 5589 /* Check both 60Hz and 59.94Hz */ 5590 clock1 = cea_mode->clock; 5591 clock2 = cea_mode_alternate_clock(cea_mode); 5592 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5593 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5594 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5595 return vic; 5596 } 5597 5598 return 0; 5599 } 5600 5601 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5602 { 5603 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 5604 5605 if (mode) 5606 return mode->picture_aspect_ratio; 5607 5608 return HDMI_PICTURE_ASPECT_NONE; 5609 } 5610 5611 int 5612 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5613 struct drm_display_mode *mode, 5614 bool is_hdmi2_sink) 5615 { 5616 int err; 5617 5618 if (!frame || !mode) 5619 return -EINVAL; 5620 5621 err = hdmi_avi_infoframe_init(frame); 5622 if (err < 0) 5623 return err; 5624 5625 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5626 frame->pixel_repeat = 1; 5627 5628 frame->video_code = drm_match_cea_mode(mode); 5629 5630 /* 5631 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5632 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5633 * have to make sure we dont break HDMI 1.4 sinks. 5634 */ 5635 if (!is_hdmi2_sink && frame->video_code > 64) 5636 frame->video_code = 0; 5637 5638 /* 5639 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5640 * we should send its VIC in vendor infoframes, else send the 5641 * VIC in AVI infoframes. Lets check if this mode is present in 5642 * HDMI 1.4b 4K modes 5643 */ 5644 if (frame->video_code) { 5645 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5646 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5647 5648 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5649 frame->video_code = 0; 5650 } 5651 5652 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5653 5654 /* 5655 * Populate picture aspect ratio from either 5656 * user input (if specified) or from the CEA mode list. 5657 */ 5658 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5659 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5660 frame->picture_aspect = mode->picture_aspect_ratio; 5661 else if (frame->video_code > 0) 5662 frame->picture_aspect = drm_get_cea_aspect_ratio( 5663 frame->video_code); 5664 5665 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5666 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5667 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5668 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5669 5670 return 0; 5671 } 5672 5673 /** 5674 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5675 * @frame: HDMI vendor infoframe 5676 * 5677 * Returns 0 on success or a negative error code on failure. 5678 */ 5679 int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5680 { 5681 memset(frame, 0, sizeof(*frame)); 5682 5683 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5684 frame->version = 1; 5685 5686 frame->oui = HDMI_IEEE_OUI; 5687 5688 /* 5689 * 0 is a valid value for s3d_struct, so we use a special "not set" 5690 * value 5691 */ 5692 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5693 5694 return 0; 5695 } 5696 5697 /** 5698 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5699 * quantization range information 5700 * @frame: HDMI AVI infoframe 5701 * @rgb_quant_range: RGB quantization range (Q) 5702 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 5703 */ 5704 void 5705 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5706 struct drm_display_mode *mode, 5707 enum hdmi_quantization_range rgb_quant_range, 5708 bool rgb_quant_range_selectable) 5709 { 5710 /* 5711 * CEA-861: 5712 * "A Source shall not send a non-zero Q value that does not correspond 5713 * to the default RGB Quantization Range for the transmitted Picture 5714 * unless the Sink indicates support for the Q bit in a Video 5715 * Capabilities Data Block." 5716 * 5717 * HDMI 2.0 recommends sending non-zero Q when it does match the 5718 * default RGB quantization range for the mode, even when QS=0. 5719 */ 5720 if (rgb_quant_range_selectable || 5721 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5722 frame->quantization_range = rgb_quant_range; 5723 else 5724 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5725 5726 /* 5727 * CEA-861-F: 5728 * "When transmitting any RGB colorimetry, the Source should set the 5729 * YQ-field to match the RGB Quantization Range being transmitted 5730 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5731 * set YQ=1) and the Sink shall ignore the YQ-field." 5732 */ 5733 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5734 frame->ycc_quantization_range = 5735 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5736 else 5737 frame->ycc_quantization_range = 5738 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5739 } 5740 5741 static enum hdmi_3d_structure 5742 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5743 { 5744 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5745 5746 switch (layout) { 5747 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5748 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5749 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5750 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5751 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5752 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5753 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5754 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5755 case DRM_MODE_FLAG_3D_L_DEPTH: 5756 return HDMI_3D_STRUCTURE_L_DEPTH; 5757 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5758 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5759 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5760 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5761 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5762 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5763 default: 5764 return HDMI_3D_STRUCTURE_INVALID; 5765 } 5766 } 5767 5768 int 5769 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5770 struct drm_display_mode *mode) 5771 { 5772 int err; 5773 u32 s3d_flags; 5774 u8 vic; 5775 5776 if (!frame || !mode) 5777 return -EINVAL; 5778 5779 vic = drm_match_hdmi_mode(mode); 5780 5781 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5782 5783 if (!vic && !s3d_flags) 5784 return -EINVAL; 5785 5786 if (vic && s3d_flags) 5787 return -EINVAL; 5788 5789 err = hdmi_vendor_infoframe_init(frame); 5790 if (err < 0) 5791 return err; 5792 5793 if (vic) 5794 frame->vic = vic; 5795 else 5796 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5797 5798 return 0; 5799 } 5800 5801 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5802 { 5803 u8 csum = 0; 5804 size_t i; 5805 5806 /* compute checksum */ 5807 for (i = 0; i < size; i++) 5808 csum += ptr[i]; 5809 5810 return 256 - csum; 5811 } 5812 5813 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5814 { 5815 u8 *ptr = buffer; 5816 5817 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5818 } 5819 5820 /** 5821 * hdmi_avi_infoframe_init() - initialize an HDMI AVI infoframe 5822 * @frame: HDMI AVI infoframe 5823 * 5824 * Returns 0 on success or a negative error code on failure. 5825 */ 5826 int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5827 { 5828 memset(frame, 0, sizeof(*frame)); 5829 5830 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5831 frame->version = 2; 5832 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5833 5834 return 0; 5835 } 5836 EXPORT_SYMBOL(hdmi_avi_infoframe_init); 5837 5838 /** 5839 * hdmi_avi_infoframe_pack() - write HDMI AVI infoframe to binary buffer 5840 * @frame: HDMI AVI infoframe 5841 * @buffer: destination buffer 5842 * @size: size of buffer 5843 * 5844 * Packs the information contained in the @frame structure into a binary 5845 * representation that can be written into the corresponding controller 5846 * registers. Also computes the checksum as required by section 5.3.5 of 5847 * the HDMI 1.4 specification. 5848 * 5849 * Returns the number of bytes packed into the binary buffer or a negative 5850 * error code on failure. 5851 */ 5852 ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, 5853 size_t size) 5854 { 5855 u8 *ptr = buffer; 5856 size_t length; 5857 5858 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5859 5860 if (size < length) 5861 return -ENOSPC; 5862 5863 memset(buffer, 0, size); 5864 5865 ptr[0] = frame->type; 5866 ptr[1] = frame->version; 5867 ptr[2] = frame->length; 5868 ptr[3] = 0; /* checksum */ 5869 5870 /* start infoframe payload */ 5871 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5872 5873 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 5874 5875 /* 5876 * Data byte 1, bit 4 has to be set if we provide the active format 5877 * aspect ratio 5878 */ 5879 if (frame->active_aspect & 0xf) 5880 ptr[0] |= BIT(4); 5881 5882 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 5883 if (frame->top_bar || frame->bottom_bar) 5884 ptr[0] |= BIT(3); 5885 5886 if (frame->left_bar || frame->right_bar) 5887 ptr[0] |= BIT(2); 5888 5889 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 5890 ((frame->picture_aspect & 0x3) << 4) | 5891 (frame->active_aspect & 0xf); 5892 5893 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 5894 ((frame->quantization_range & 0x3) << 2) | 5895 (frame->nups & 0x3); 5896 5897 if (frame->itc) 5898 ptr[2] |= BIT(7); 5899 5900 ptr[3] = frame->video_code & 0x7f; 5901 5902 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 5903 ((frame->content_type & 0x3) << 4) | 5904 (frame->pixel_repeat & 0xf); 5905 5906 ptr[5] = frame->top_bar & 0xff; 5907 ptr[6] = (frame->top_bar >> 8) & 0xff; 5908 ptr[7] = frame->bottom_bar & 0xff; 5909 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 5910 ptr[9] = frame->left_bar & 0xff; 5911 ptr[10] = (frame->left_bar >> 8) & 0xff; 5912 ptr[11] = frame->right_bar & 0xff; 5913 ptr[12] = (frame->right_bar >> 8) & 0xff; 5914 5915 hdmi_infoframe_set_checksum(buffer, length); 5916 5917 return length; 5918 } 5919 EXPORT_SYMBOL(hdmi_avi_infoframe_pack); 5920 5921 static int hdmi_avi_infoframe_check_only(const struct hdmi_avi_infoframe *frame) 5922 { 5923 if (frame->type != HDMI_INFOFRAME_TYPE_AVI || 5924 frame->version != 2 || 5925 frame->length != HDMI_AVI_INFOFRAME_SIZE) 5926 return -EINVAL; 5927 5928 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5929 return -EINVAL; 5930 5931 return 0; 5932 } 5933 5934 /** 5935 * hdmi_avi_infoframe_check() - check a HDMI AVI infoframe 5936 * @frame: HDMI AVI infoframe 5937 * 5938 * Validates that the infoframe is consistent and updates derived fields 5939 * (eg. length) based on other fields. 5940 * 5941 * Returns 0 on success or a negative error code on failure. 5942 */ 5943 int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame) 5944 { 5945 return hdmi_avi_infoframe_check_only(frame); 5946 } 5947 EXPORT_SYMBOL(hdmi_avi_infoframe_check); 5948 5949 /** 5950 * hdmi_avi_infoframe_pack_only() - write HDMI AVI infoframe to binary buffer 5951 * @frame: HDMI AVI infoframe 5952 * @buffer: destination buffer 5953 * @size: size of buffer 5954 * 5955 * Packs the information contained in the @frame structure into a binary 5956 * representation that can be written into the corresponding controller 5957 * registers. Also computes the checksum as required by section 5.3.5 of 5958 * the HDMI 1.4 specification. 5959 * 5960 * Returns the number of bytes packed into the binary buffer or a negative 5961 * error code on failure. 5962 */ 5963 ssize_t hdmi_avi_infoframe_pack_only(const struct hdmi_avi_infoframe *frame, 5964 void *buffer, size_t size) 5965 { 5966 u8 *ptr = buffer; 5967 size_t length; 5968 int ret; 5969 5970 ret = hdmi_avi_infoframe_check_only(frame); 5971 if (ret) 5972 return ret; 5973 5974 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5975 5976 if (size < length) 5977 return -ENOSPC; 5978 5979 memset(buffer, 0, size); 5980 5981 ptr[0] = frame->type; 5982 ptr[1] = frame->version; 5983 ptr[2] = frame->length; 5984 ptr[3] = 0; /* checksum */ 5985 5986 /* start infoframe payload */ 5987 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5988 5989 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 5990 5991 /* 5992 * Data byte 1, bit 4 has to be set if we provide the active format 5993 * aspect ratio 5994 */ 5995 if (frame->active_aspect & 0xf) 5996 ptr[0] |= BIT(4); 5997 5998 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 5999 if (frame->top_bar || frame->bottom_bar) 6000 ptr[0] |= BIT(3); 6001 6002 if (frame->left_bar || frame->right_bar) 6003 ptr[0] |= BIT(2); 6004 6005 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 6006 ((frame->picture_aspect & 0x3) << 4) | 6007 (frame->active_aspect & 0xf); 6008 6009 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 6010 ((frame->quantization_range & 0x3) << 2) | 6011 (frame->nups & 0x3); 6012 6013 if (frame->itc) 6014 ptr[2] |= BIT(7); 6015 6016 ptr[3] = frame->video_code & 0xff; 6017 6018 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 6019 ((frame->content_type & 0x3) << 4) | 6020 (frame->pixel_repeat & 0xf); 6021 6022 ptr[5] = frame->top_bar & 0xff; 6023 ptr[6] = (frame->top_bar >> 8) & 0xff; 6024 ptr[7] = frame->bottom_bar & 0xff; 6025 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 6026 ptr[9] = frame->left_bar & 0xff; 6027 ptr[10] = (frame->left_bar >> 8) & 0xff; 6028 ptr[11] = frame->right_bar & 0xff; 6029 ptr[12] = (frame->right_bar >> 8) & 0xff; 6030 6031 hdmi_infoframe_set_checksum(buffer, length); 6032 6033 return length; 6034 } 6035 EXPORT_SYMBOL(hdmi_avi_infoframe_pack_only); 6036 6037 /** 6038 * hdmi_spd_infoframe_init() - initialize an HDMI SPD infoframe 6039 * @frame: HDMI SPD infoframe 6040 * @vendor: vendor string 6041 * @product: product string 6042 * 6043 * Returns 0 on success or a negative error code on failure. 6044 */ 6045 int hdmi_spd_infoframe_init(struct hdmi_spd_infoframe *frame, 6046 const char *vendor, const char *product) 6047 { 6048 memset(frame, 0, sizeof(*frame)); 6049 6050 frame->type = HDMI_INFOFRAME_TYPE_SPD; 6051 frame->version = 1; 6052 frame->length = HDMI_SPD_INFOFRAME_SIZE; 6053 6054 strncpy(frame->vendor, vendor, sizeof(frame->vendor)); 6055 strncpy(frame->product, product, sizeof(frame->product)); 6056 6057 return 0; 6058 } 6059 EXPORT_SYMBOL(hdmi_spd_infoframe_init); 6060 6061 /** 6062 * hdmi_spd_infoframe_pack() - write HDMI SPD infoframe to binary buffer 6063 * @frame: HDMI SPD infoframe 6064 * @buffer: destination buffer 6065 * @size: size of buffer 6066 * 6067 * Packs the information contained in the @frame structure into a binary 6068 * representation that can be written into the corresponding controller 6069 * registers. Also computes the checksum as required by section 5.3.5 of 6070 * the HDMI 1.4 specification. 6071 * 6072 * Returns the number of bytes packed into the binary buffer or a negative 6073 * error code on failure. 6074 */ 6075 ssize_t hdmi_spd_infoframe_pack(struct hdmi_spd_infoframe *frame, void *buffer, 6076 size_t size) 6077 { 6078 u8 *ptr = buffer; 6079 size_t length; 6080 6081 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6082 6083 if (size < length) 6084 return -ENOSPC; 6085 6086 memset(buffer, 0, size); 6087 6088 ptr[0] = frame->type; 6089 ptr[1] = frame->version; 6090 ptr[2] = frame->length; 6091 ptr[3] = 0; /* checksum */ 6092 6093 /* start infoframe payload */ 6094 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6095 6096 memcpy(ptr, frame->vendor, sizeof(frame->vendor)); 6097 memcpy(ptr + 8, frame->product, sizeof(frame->product)); 6098 6099 ptr[24] = frame->sdi; 6100 6101 hdmi_infoframe_set_checksum(buffer, length); 6102 6103 return length; 6104 } 6105 EXPORT_SYMBOL(hdmi_spd_infoframe_pack); 6106 6107 /** 6108 * hdmi_audio_infoframe_init() - initialize an HDMI audio infoframe 6109 * @frame: HDMI audio infoframe 6110 * 6111 * Returns 0 on success or a negative error code on failure. 6112 */ 6113 int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame) 6114 { 6115 memset(frame, 0, sizeof(*frame)); 6116 6117 frame->type = HDMI_INFOFRAME_TYPE_AUDIO; 6118 frame->version = 1; 6119 frame->length = HDMI_AUDIO_INFOFRAME_SIZE; 6120 6121 return 0; 6122 } 6123 6124 /** 6125 * hdmi_audio_infoframe_pack() - write HDMI audio infoframe to binary buffer 6126 * @frame: HDMI audio infoframe 6127 * @buffer: destination buffer 6128 * @size: size of buffer 6129 * 6130 * Packs the information contained in the @frame structure into a binary 6131 * representation that can be written into the corresponding controller 6132 * registers. Also computes the checksum as required by section 5.3.5 of 6133 * the HDMI 1.4 specification. 6134 * 6135 * Returns the number of bytes packed into the binary buffer or a negative 6136 * error code on failure. 6137 */ 6138 ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame, 6139 void *buffer, size_t size) 6140 { 6141 unsigned char channels; 6142 char *ptr = buffer; 6143 size_t length; 6144 6145 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6146 6147 if (size < length) 6148 return -ENOSPC; 6149 6150 memset(buffer, 0, size); 6151 6152 if (frame->channels >= 2) 6153 channels = frame->channels - 1; 6154 else 6155 channels = 0; 6156 6157 ptr[0] = frame->type; 6158 ptr[1] = frame->version; 6159 ptr[2] = frame->length; 6160 ptr[3] = 0; /* checksum */ 6161 6162 /* start infoframe payload */ 6163 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6164 6165 ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7); 6166 ptr[1] = ((frame->sample_frequency & 0x7) << 2) | 6167 (frame->sample_size & 0x3); 6168 ptr[2] = frame->coding_type_ext & 0x1f; 6169 ptr[3] = frame->channel_allocation; 6170 ptr[4] = (frame->level_shift_value & 0xf) << 3; 6171 6172 if (frame->downmix_inhibit) 6173 ptr[4] |= BIT(7); 6174 6175 hdmi_infoframe_set_checksum(buffer, length); 6176 6177 return length; 6178 } 6179 6180 /** 6181 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 6182 * @frame: HDMI infoframe 6183 * @buffer: destination buffer 6184 * @size: size of buffer 6185 * 6186 * Packs the information contained in the @frame structure into a binary 6187 * representation that can be written into the corresponding controller 6188 * registers. Also computes the checksum as required by section 5.3.5 of 6189 * the HDMI 1.4 specification. 6190 * 6191 * Returns the number of bytes packed into the binary buffer or a negative 6192 * error code on failure. 6193 */ 6194 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 6195 void *buffer, size_t size) 6196 { 6197 char *ptr = buffer; 6198 size_t length; 6199 6200 /* empty info frame */ 6201 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 6202 return -EINVAL; 6203 6204 /* only one of those can be supplied */ 6205 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 6206 return -EINVAL; 6207 6208 /* for side by side (half) we also need to provide 3D_Ext_Data */ 6209 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6210 frame->length = 6; 6211 else 6212 frame->length = 5; 6213 6214 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6215 6216 if (size < length) 6217 return -ENOSPC; 6218 6219 memset(buffer, 0, size); 6220 6221 ptr[0] = frame->type; 6222 ptr[1] = frame->version; 6223 ptr[2] = frame->length; 6224 ptr[3] = 0; /* checksum */ 6225 6226 /* HDMI OUI */ 6227 ptr[4] = 0x03; 6228 ptr[5] = 0x0c; 6229 ptr[6] = 0x00; 6230 6231 if (frame->vic) { 6232 ptr[7] = 0x1 << 5; /* video format */ 6233 ptr[8] = frame->vic; 6234 } else { 6235 ptr[7] = 0x2 << 5; /* video format */ 6236 ptr[8] = (frame->s3d_struct & 0xf) << 4; 6237 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6238 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 6239 } 6240 6241 hdmi_infoframe_set_checksum(buffer, length); 6242 6243 return length; 6244 } 6245 6246 /** 6247 * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and 6248 * mastering infoframe 6249 * @frame: HDMI DRM infoframe 6250 * 6251 * Returns 0 on success or a negative error code on failure. 6252 */ 6253 int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame) 6254 { 6255 memset(frame, 0, sizeof(*frame)); 6256 6257 frame->type = HDMI_INFOFRAME_TYPE_DRM; 6258 frame->version = 1; 6259 6260 return 0; 6261 } 6262 6263 /** 6264 * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer 6265 * @frame: HDMI DRM infoframe 6266 * @buffer: destination buffer 6267 * @size: size of buffer 6268 * 6269 * Packs the information contained in the @frame structure into a binary 6270 * representation that can be written into the corresponding controller 6271 * registers. Also computes the checksum as required by section 5.3.5 of 6272 * the HDMI 1.4 specification. 6273 * 6274 * Returns the number of bytes packed into the binary buffer or a negative 6275 * error code on failure. 6276 */ 6277 ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer, 6278 size_t size) 6279 { 6280 u8 *ptr = buffer; 6281 size_t length; 6282 6283 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6284 6285 if (size < length) 6286 return -ENOSPC; 6287 6288 memset(buffer, 0, size); 6289 6290 ptr[0] = frame->type; 6291 ptr[1] = frame->version; 6292 ptr[2] = frame->length; 6293 ptr[3] = 0; /* checksum */ 6294 6295 /* start infoframe payload */ 6296 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6297 6298 ptr[0] = frame->eotf; 6299 ptr[1] = frame->metadata_type; 6300 6301 ptr[2] = frame->display_primaries_x[0] & 0xff; 6302 ptr[3] = frame->display_primaries_x[0] >> 8; 6303 6304 ptr[4] = frame->display_primaries_x[1] & 0xff; 6305 ptr[5] = frame->display_primaries_x[1] >> 8; 6306 6307 ptr[6] = frame->display_primaries_x[2] & 0xff; 6308 ptr[7] = frame->display_primaries_x[2] >> 8; 6309 6310 ptr[9] = frame->display_primaries_y[0] & 0xff; 6311 ptr[10] = frame->display_primaries_y[0] >> 8; 6312 6313 ptr[11] = frame->display_primaries_y[1] & 0xff; 6314 ptr[12] = frame->display_primaries_y[1] >> 8; 6315 6316 ptr[13] = frame->display_primaries_y[2] & 0xff; 6317 ptr[14] = frame->display_primaries_y[2] >> 8; 6318 6319 ptr[15] = frame->white_point_x & 0xff; 6320 ptr[16] = frame->white_point_x >> 8; 6321 6322 ptr[17] = frame->white_point_y & 0xff; 6323 ptr[18] = frame->white_point_y >> 8; 6324 6325 ptr[19] = frame->max_mastering_display_luminance & 0xff; 6326 ptr[20] = frame->max_mastering_display_luminance >> 8; 6327 6328 ptr[21] = frame->min_mastering_display_luminance & 0xff; 6329 ptr[22] = frame->min_mastering_display_luminance >> 8; 6330 6331 ptr[23] = frame->max_cll & 0xff; 6332 ptr[24] = frame->max_cll >> 8; 6333 6334 ptr[25] = frame->max_fall & 0xff; 6335 ptr[26] = frame->max_fall >> 8; 6336 6337 hdmi_infoframe_set_checksum(buffer, length); 6338 6339 return length; 6340 } 6341 6342 /* 6343 * hdmi_vendor_any_infoframe_pack() - write a vendor infoframe to binary buffer 6344 */ 6345 static ssize_t 6346 hdmi_vendor_any_infoframe_pack(union hdmi_vendor_any_infoframe *frame, 6347 void *buffer, size_t size) 6348 { 6349 /* we only know about HDMI vendor infoframes */ 6350 if (frame->any.oui != HDMI_IEEE_OUI) 6351 return -EINVAL; 6352 6353 return hdmi_vendor_infoframe_pack(&frame->hdmi, buffer, size); 6354 } 6355 6356 /** 6357 * hdmi_infoframe_pack() - write a HDMI infoframe to binary buffer 6358 * @frame: HDMI infoframe 6359 * @buffer: destination buffer 6360 * @size: size of buffer 6361 * 6362 * Packs the information contained in the @frame structure into a binary 6363 * representation that can be written into the corresponding controller 6364 * registers. Also computes the checksum as required by section 5.3.5 of 6365 * the HDMI 1.4 specification. 6366 * 6367 * Returns the number of bytes packed into the binary buffer or a negative 6368 * error code on failure. 6369 */ 6370 ssize_t 6371 hdmi_infoframe_pack(union hdmi_infoframe *frame, void *buffer, size_t size) 6372 { 6373 ssize_t length; 6374 6375 switch (frame->any.type) { 6376 case HDMI_INFOFRAME_TYPE_AVI: 6377 length = hdmi_avi_infoframe_pack(&frame->avi, buffer, size); 6378 break; 6379 case HDMI_INFOFRAME_TYPE_DRM: 6380 length = hdmi_drm_infoframe_pack(&frame->drm, buffer, size); 6381 break; 6382 case HDMI_INFOFRAME_TYPE_SPD: 6383 length = hdmi_spd_infoframe_pack(&frame->spd, buffer, size); 6384 break; 6385 case HDMI_INFOFRAME_TYPE_AUDIO: 6386 length = hdmi_audio_infoframe_pack(&frame->audio, buffer, size); 6387 break; 6388 case HDMI_INFOFRAME_TYPE_VENDOR: 6389 length = hdmi_vendor_any_infoframe_pack(&frame->vendor, 6390 buffer, size); 6391 break; 6392 default: 6393 printf("Bad infoframe type %d\n", frame->any.type); 6394 length = -EINVAL; 6395 } 6396 6397 return length; 6398 } 6399 6400 /** 6401 * hdmi_avi_infoframe_unpack() - unpack binary buffer to a HDMI AVI infoframe 6402 * @buffer: source buffer 6403 * @frame: HDMI AVI infoframe 6404 * 6405 * Unpacks the information contained in binary @buffer into a structured 6406 * @frame of the HDMI Auxiliary Video (AVI) information frame. 6407 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6408 * specification. 6409 * 6410 * Returns 0 on success or a negative error code on failure. 6411 */ 6412 static int hdmi_avi_infoframe_unpack(struct hdmi_avi_infoframe *frame, 6413 void *buffer) 6414 { 6415 u8 *ptr = buffer; 6416 int ret; 6417 6418 if (ptr[0] != HDMI_INFOFRAME_TYPE_AVI || 6419 ptr[1] != 2 || 6420 ptr[2] != HDMI_AVI_INFOFRAME_SIZE) 6421 return -EINVAL; 6422 6423 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AVI)) != 0) 6424 return -EINVAL; 6425 6426 ret = hdmi_avi_infoframe_init(frame); 6427 if (ret) 6428 return ret; 6429 6430 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6431 6432 frame->colorspace = (ptr[0] >> 5) & 0x3; 6433 if (ptr[0] & 0x10) 6434 frame->active_aspect = ptr[1] & 0xf; 6435 if (ptr[0] & 0x8) { 6436 frame->top_bar = (ptr[5] << 8) + ptr[6]; 6437 frame->bottom_bar = (ptr[7] << 8) + ptr[8]; 6438 } 6439 if (ptr[0] & 0x4) { 6440 frame->left_bar = (ptr[9] << 8) + ptr[10]; 6441 frame->right_bar = (ptr[11] << 8) + ptr[12]; 6442 } 6443 frame->scan_mode = ptr[0] & 0x3; 6444 6445 frame->colorimetry = (ptr[1] >> 6) & 0x3; 6446 frame->picture_aspect = (ptr[1] >> 4) & 0x3; 6447 frame->active_aspect = ptr[1] & 0xf; 6448 6449 frame->itc = ptr[2] & 0x80 ? true : false; 6450 frame->extended_colorimetry = (ptr[2] >> 4) & 0x7; 6451 frame->quantization_range = (ptr[2] >> 2) & 0x3; 6452 frame->nups = ptr[2] & 0x3; 6453 6454 frame->video_code = ptr[3] & 0x7f; 6455 frame->ycc_quantization_range = (ptr[4] >> 6) & 0x3; 6456 frame->content_type = (ptr[4] >> 4) & 0x3; 6457 6458 frame->pixel_repeat = ptr[4] & 0xf; 6459 6460 return 0; 6461 } 6462 6463 /** 6464 * hdmi_spd_infoframe_unpack() - unpack binary buffer to a HDMI SPD infoframe 6465 * @buffer: source buffer 6466 * @frame: HDMI SPD infoframe 6467 * 6468 * Unpacks the information contained in binary @buffer into a structured 6469 * @frame of the HDMI Source Product Description (SPD) information frame. 6470 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6471 * specification. 6472 * 6473 * Returns 0 on success or a negative error code on failure. 6474 */ 6475 static int hdmi_spd_infoframe_unpack(struct hdmi_spd_infoframe *frame, 6476 void *buffer) 6477 { 6478 char *ptr = buffer; 6479 int ret; 6480 6481 if (ptr[0] != HDMI_INFOFRAME_TYPE_SPD || 6482 ptr[1] != 1 || 6483 ptr[2] != HDMI_SPD_INFOFRAME_SIZE) { 6484 return -EINVAL; 6485 } 6486 6487 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(SPD)) != 0) 6488 return -EINVAL; 6489 6490 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6491 6492 ret = hdmi_spd_infoframe_init(frame, ptr, ptr + 8); 6493 if (ret) 6494 return ret; 6495 6496 frame->sdi = ptr[24]; 6497 6498 return 0; 6499 } 6500 6501 /** 6502 * hdmi_audio_infoframe_unpack() - unpack binary buffer to a HDMI AUDIO infoframe 6503 * @buffer: source buffer 6504 * @frame: HDMI Audio infoframe 6505 * 6506 * Unpacks the information contained in binary @buffer into a structured 6507 * @frame of the HDMI Audio information frame. 6508 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6509 * specification. 6510 * 6511 * Returns 0 on success or a negative error code on failure. 6512 */ 6513 static int hdmi_audio_infoframe_unpack(struct hdmi_audio_infoframe *frame, 6514 void *buffer) 6515 { 6516 u8 *ptr = buffer; 6517 int ret; 6518 6519 if (ptr[0] != HDMI_INFOFRAME_TYPE_AUDIO || 6520 ptr[1] != 1 || 6521 ptr[2] != HDMI_AUDIO_INFOFRAME_SIZE) { 6522 return -EINVAL; 6523 } 6524 6525 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AUDIO)) != 0) 6526 return -EINVAL; 6527 6528 ret = hdmi_audio_infoframe_init(frame); 6529 if (ret) 6530 return ret; 6531 6532 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6533 6534 frame->channels = ptr[0] & 0x7; 6535 frame->coding_type = (ptr[0] >> 4) & 0xf; 6536 frame->sample_size = ptr[1] & 0x3; 6537 frame->sample_frequency = (ptr[1] >> 2) & 0x7; 6538 frame->coding_type_ext = ptr[2] & 0x1f; 6539 frame->channel_allocation = ptr[3]; 6540 frame->level_shift_value = (ptr[4] >> 3) & 0xf; 6541 frame->downmix_inhibit = ptr[4] & 0x80 ? true : false; 6542 6543 return 0; 6544 } 6545 6546 /** 6547 * hdmi_vendor_infoframe_unpack() - unpack binary buffer to a HDMI vendor infoframe 6548 * @buffer: source buffer 6549 * @frame: HDMI Vendor infoframe 6550 * 6551 * Unpacks the information contained in binary @buffer into a structured 6552 * @frame of the HDMI Vendor information frame. 6553 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6554 * specification. 6555 * 6556 * Returns 0 on success or a negative error code on failure. 6557 */ 6558 static int 6559 hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame, 6560 void *buffer) 6561 { 6562 u8 *ptr = buffer; 6563 size_t length; 6564 int ret; 6565 u8 hdmi_video_format; 6566 struct hdmi_vendor_infoframe *hvf = &frame->hdmi; 6567 6568 if (ptr[0] != HDMI_INFOFRAME_TYPE_VENDOR || 6569 ptr[1] != 1 || 6570 (ptr[2] != 4 && ptr[2] != 5 && ptr[2] != 6)) 6571 return -EINVAL; 6572 6573 length = ptr[2]; 6574 6575 if (hdmi_infoframe_checksum(buffer, 6576 HDMI_INFOFRAME_HEADER_SIZE + length) != 0) 6577 return -EINVAL; 6578 6579 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6580 6581 /* HDMI OUI */ 6582 if (ptr[0] != 0x03 || 6583 ptr[1] != 0x0c || 6584 ptr[2] != 0x00) 6585 return -EINVAL; 6586 6587 hdmi_video_format = ptr[3] >> 5; 6588 6589 if (hdmi_video_format > 0x2) 6590 return -EINVAL; 6591 6592 ret = hdmi_vendor_infoframe_init(hvf); 6593 if (ret) 6594 return ret; 6595 6596 hvf->length = length; 6597 6598 if (hdmi_video_format == 0x2) { 6599 if (length != 5 && length != 6) 6600 return -EINVAL; 6601 hvf->s3d_struct = ptr[4] >> 4; 6602 if (hvf->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) { 6603 if (length != 6) 6604 return -EINVAL; 6605 hvf->s3d_ext_data = ptr[5] >> 4; 6606 } 6607 } else if (hdmi_video_format == 0x1) { 6608 if (length != 5) 6609 return -EINVAL; 6610 hvf->vic = ptr[4]; 6611 } else { 6612 if (length != 4) 6613 return -EINVAL; 6614 } 6615 6616 return 0; 6617 } 6618 6619 /** 6620 * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe 6621 * @buffer: source buffer 6622 * @frame: HDMI infoframe 6623 * 6624 * Unpacks the information contained in binary buffer @buffer into a structured 6625 * @frame of a HDMI infoframe. 6626 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6627 * specification. 6628 * 6629 * Returns 0 on success or a negative error code on failure. 6630 */ 6631 int hdmi_infoframe_unpack(union hdmi_infoframe *frame, void *buffer) 6632 { 6633 int ret; 6634 u8 *ptr = buffer; 6635 6636 switch (ptr[0]) { 6637 case HDMI_INFOFRAME_TYPE_AVI: 6638 ret = hdmi_avi_infoframe_unpack(&frame->avi, buffer); 6639 break; 6640 case HDMI_INFOFRAME_TYPE_SPD: 6641 ret = hdmi_spd_infoframe_unpack(&frame->spd, buffer); 6642 break; 6643 case HDMI_INFOFRAME_TYPE_AUDIO: 6644 ret = hdmi_audio_infoframe_unpack(&frame->audio, buffer); 6645 break; 6646 case HDMI_INFOFRAME_TYPE_VENDOR: 6647 ret = hdmi_vendor_any_infoframe_unpack(&frame->vendor, buffer); 6648 break; 6649 default: 6650 ret = -EINVAL; 6651 break; 6652 } 6653 6654 return ret; 6655 } 6656 6657 /** 6658 * drm_mode_sort - sort mode list 6659 * @edid_data: modes structures to sort 6660 * 6661 * Sort @edid_data by favorability, moving good modes to the head of the list. 6662 */ 6663 void drm_mode_sort(struct hdmi_edid_data *edid_data) 6664 { 6665 struct drm_display_mode *a, *b; 6666 struct drm_display_mode c; 6667 int diff, i, j; 6668 6669 for (i = 0; i < (edid_data->modes - 1); i++) { 6670 a = &edid_data->mode_buf[i]; 6671 for (j = i + 1; j < edid_data->modes; j++) { 6672 b = &edid_data->mode_buf[j]; 6673 diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) - 6674 ((a->type & DRM_MODE_TYPE_PREFERRED) != 0); 6675 if (diff) { 6676 if (diff > 0) { 6677 c = *a; 6678 *a = *b; 6679 *b = c; 6680 } 6681 continue; 6682 } 6683 6684 diff = b->hdisplay * b->vdisplay 6685 - a->hdisplay * a->vdisplay; 6686 if (diff) { 6687 if (diff > 0) { 6688 c = *a; 6689 *a = *b; 6690 *b = c; 6691 } 6692 continue; 6693 } 6694 6695 diff = b->vrefresh - a->vrefresh; 6696 if (diff) { 6697 if (diff > 0) { 6698 c = *a; 6699 *a = *b; 6700 *b = c; 6701 } 6702 continue; 6703 } 6704 6705 diff = b->clock - a->clock; 6706 if (diff > 0) { 6707 c = *a; 6708 *a = *b; 6709 *b = c; 6710 } 6711 } 6712 } 6713 edid_data->preferred_mode = &edid_data->mode_buf[0]; 6714 } 6715 6716 /** 6717 * drm_mode_prune_invalid - remove invalid modes from mode list 6718 * @edid_data: structure store mode list 6719 * Returns: 6720 * Number of valid modes. 6721 */ 6722 int drm_mode_prune_invalid(struct hdmi_edid_data *edid_data) 6723 { 6724 int i, j; 6725 int num = edid_data->modes; 6726 int len = sizeof(struct drm_display_mode); 6727 struct drm_display_mode *mode_buf = edid_data->mode_buf; 6728 6729 for (i = 0; i < num; i++) { 6730 if (mode_buf[i].invalid) { 6731 /* If mode is invalid, delete it. */ 6732 for (j = i; j < num - 1; j++) 6733 memcpy(&mode_buf[j], &mode_buf[j + 1], len); 6734 6735 num--; 6736 i--; 6737 } 6738 } 6739 /* Clear redundant modes of mode_buf. */ 6740 memset(&mode_buf[num], 0, len * (edid_data->modes - num)); 6741 6742 edid_data->modes = num; 6743 return num; 6744 } 6745 6746 /** 6747 * drm_rk_filter_whitelist - mark modes out of white list from mode list 6748 * @edid_data: structure store mode list 6749 */ 6750 void drm_rk_filter_whitelist(struct hdmi_edid_data *edid_data) 6751 { 6752 int i, j, white_len; 6753 6754 if (sizeof(resolution_white)) { 6755 white_len = sizeof(resolution_white) / 6756 sizeof(resolution_white[0]); 6757 for (i = 0; i < edid_data->modes; i++) { 6758 for (j = 0; j < white_len; j++) { 6759 if (drm_mode_match((const struct drm_display_mode *)&resolution_white[j], 6760 &edid_data->mode_buf[i], 6761 DRM_MODE_MATCH_TIMINGS | 6762 DRM_MODE_MATCH_CLOCK | 6763 DRM_MODE_MATCH_FLAGS)) 6764 break; 6765 } 6766 6767 if (j == white_len) 6768 edid_data->mode_buf[i].invalid = true; 6769 } 6770 } 6771 } 6772 6773 void drm_rk_select_mode(struct hdmi_edid_data *edid_data, 6774 struct base_screen_info *screen_info) 6775 { 6776 int i; 6777 const struct base_drm_display_mode *base_mode; 6778 6779 if (!screen_info) { 6780 /* define init resolution here */ 6781 } else { 6782 base_mode = &screen_info->mode; 6783 for (i = 0; i < edid_data->modes; i++) { 6784 if (drm_mode_match((const struct drm_display_mode *)base_mode, 6785 &edid_data->mode_buf[i], 6786 DRM_MODE_MATCH_TIMINGS | 6787 DRM_MODE_MATCH_CLOCK | 6788 DRM_MODE_MATCH_FLAGS)) { 6789 edid_data->preferred_mode = 6790 &edid_data->mode_buf[i]; 6791 6792 if (edid_data->mode_buf[i].picture_aspect_ratio) 6793 break; 6794 } 6795 } 6796 } 6797 } 6798 6799 /** 6800 * drm_do_probe_ddc_edid() - get EDID information via I2C 6801 * @adap: ddc adapter 6802 * @buf: EDID data buffer to be filled 6803 * @block: 128 byte EDID block to start fetching from 6804 * @len: EDID data buffer length to fetch 6805 * 6806 * Try to fetch EDID information by calling I2C driver functions. 6807 * 6808 * Return: 0 on success or -1 on failure. 6809 */ 6810 static int 6811 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 6812 size_t len) 6813 { 6814 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 6815 unsigned char segment = block >> 1; 6816 unsigned char xfers = segment ? 3 : 2; 6817 int ret, retries = 5; 6818 6819 do { 6820 struct i2c_msg msgs[] = { 6821 { 6822 .addr = DDC_SEGMENT_ADDR, 6823 .flags = 0, 6824 .len = 1, 6825 .buf = &segment, 6826 }, { 6827 .addr = DDC_ADDR, 6828 .flags = 0, 6829 .len = 1, 6830 .buf = &start, 6831 }, { 6832 .addr = DDC_ADDR, 6833 .flags = I2C_M_RD, 6834 .len = len, 6835 .buf = buf, 6836 } 6837 }; 6838 6839 if (adap->ops) { 6840 ret = adap->ops->xfer(adap->i2c_bus, &msgs[3 - xfers], 6841 xfers); 6842 if (!ret) 6843 ret = xfers; 6844 } else { 6845 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 6846 } 6847 } while (ret != xfers && --retries); 6848 6849 /* All msg transfer successfully. */ 6850 return ret == xfers ? 0 : -1; 6851 } 6852 6853 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid) 6854 { 6855 int i, j, block_num, block = 0; 6856 bool edid_corrupt; 6857 #ifdef DEBUG 6858 u8 *buff; 6859 #endif 6860 6861 /* base block fetch */ 6862 for (i = 0; i < 4; i++) { 6863 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 6864 goto err; 6865 if (drm_edid_block_valid(edid, 0, true, 6866 &edid_corrupt)) 6867 break; 6868 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 6869 printf("edid base block is 0, get edid failed\n"); 6870 goto err; 6871 } 6872 } 6873 6874 if (i == 4) 6875 goto err; 6876 6877 block++; 6878 /* get the number of extensions */ 6879 block_num = edid[0x7e]; 6880 6881 for (j = 1; j <= block_num; j++) { 6882 for (i = 0; i < 4; i++) { 6883 if (drm_do_probe_ddc_edid(adap, &edid[0x80 * j], j, 6884 HDMI_EDID_BLOCK_SIZE)) 6885 goto err; 6886 if (drm_edid_block_valid(&edid[0x80 * j], j, 6887 true, NULL)) 6888 break; 6889 } 6890 6891 if (i == 4) 6892 goto err; 6893 block++; 6894 } 6895 6896 #ifdef DEBUG 6897 printf("RAW EDID:\n"); 6898 for (i = 0; i < block_num + 1; i++) { 6899 buff = &edid[0x80 * i]; 6900 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 6901 if (j % 16 == 0) 6902 printf("\n"); 6903 printf("0x%02x, ", buff[j]); 6904 } 6905 printf("\n"); 6906 } 6907 #endif 6908 6909 return 0; 6910 6911 err: 6912 printf("can't get edid block:%d\n", block); 6913 /* clear all read edid block, include invalid block */ 6914 memset(edid, 0, HDMI_EDID_BLOCK_SIZE * (block + 1)); 6915 return -EFAULT; 6916 } 6917 6918 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 6919 void *buffer, size_t size) 6920 { 6921 struct i2c_msg msgs[2] = { 6922 { 6923 .addr = addr, 6924 .flags = 0, 6925 .len = 1, 6926 .buf = &offset, 6927 }, { 6928 .addr = addr, 6929 .flags = I2C_M_RD, 6930 .len = size, 6931 .buf = buffer, 6932 } 6933 }; 6934 6935 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 6936 } 6937 6938 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 6939 const void *buffer, size_t size) 6940 { 6941 struct i2c_msg msg = { 6942 .addr = addr, 6943 .flags = 0, 6944 .len = 1 + size, 6945 .buf = NULL, 6946 }; 6947 void *data; 6948 int err; 6949 6950 data = malloc(1 + size); 6951 if (!data) 6952 return -ENOMEM; 6953 6954 msg.buf = data; 6955 6956 memcpy(data, &offset, sizeof(offset)); 6957 memcpy(data + 1, buffer, size); 6958 6959 err = adap->ddc_xfer(adap, &msg, 1); 6960 6961 free(data); 6962 6963 return err; 6964 } 6965 6966 /** 6967 * drm_scdc_readb - read a single byte from SCDC 6968 * @adap: ddc adapter 6969 * @offset: offset of register to read 6970 * @value: return location for the register value 6971 * 6972 * Reads a single byte from SCDC. This is a convenience wrapper around the 6973 * drm_scdc_read() function. 6974 * 6975 * Returns: 6976 * 0 on success or a negative error code on failure. 6977 */ 6978 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 6979 u8 *value) 6980 { 6981 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 6982 sizeof(*value)); 6983 } 6984 6985 /** 6986 * drm_scdc_writeb - write a single byte to SCDC 6987 * @adap: ddc adapter 6988 * @offset: offset of register to read 6989 * @value: return location for the register value 6990 * 6991 * Writes a single byte to SCDC. This is a convenience wrapper around the 6992 * drm_scdc_write() function. 6993 * 6994 * Returns: 6995 * 0 on success or a negative error code on failure. 6996 */ 6997 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 6998 u8 value) 6999 { 7000 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 7001 sizeof(value)); 7002 } 7003 7004