1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <malloc.h> 23 #include <mapmem.h> 24 #include <os.h> 25 #include <post.h> 26 #include <relocate.h> 27 #include <spi.h> 28 #include <status_led.h> 29 #include <timer.h> 30 #include <trace.h> 31 #include <video.h> 32 #include <watchdog.h> 33 #ifdef CONFIG_MACH_TYPE 34 #include <asm/mach-types.h> 35 #endif 36 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 37 #include <asm/mp.h> 38 #endif 39 #include <asm/io.h> 40 #include <asm/sections.h> 41 #include <dm/root.h> 42 #include <linux/errno.h> 43 #include <bidram.h> 44 #include <sysmem.h> 45 46 /* 47 * Pointer to initial global data area 48 * 49 * Here we initialize it if needed. 50 */ 51 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 52 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 53 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 54 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 55 #else 56 DECLARE_GLOBAL_DATA_PTR; 57 #endif 58 59 /* 60 * TODO(sjg@chromium.org): IMO this code should be 61 * refactored to a single function, something like: 62 * 63 * void led_set_state(enum led_colour_t colour, int on); 64 */ 65 /************************************************************************ 66 * Coloured LED functionality 67 ************************************************************************ 68 * May be supplied by boards if desired 69 */ 70 __weak void coloured_LED_init(void) {} 71 __weak void red_led_on(void) {} 72 __weak void red_led_off(void) {} 73 __weak void green_led_on(void) {} 74 __weak void green_led_off(void) {} 75 __weak void yellow_led_on(void) {} 76 __weak void yellow_led_off(void) {} 77 __weak void blue_led_on(void) {} 78 __weak void blue_led_off(void) {} 79 80 /* 81 * Why is gd allocated a register? Prior to reloc it might be better to 82 * just pass it around to each function in this file? 83 * 84 * After reloc one could argue that it is hardly used and doesn't need 85 * to be in a register. Or if it is it should perhaps hold pointers to all 86 * global data for all modules, so that post-reloc we can avoid the massive 87 * literal pool we get on ARM. Or perhaps just encourage each module to use 88 * a structure... 89 */ 90 91 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 92 static int init_func_watchdog_init(void) 93 { 94 # if defined(CONFIG_HW_WATCHDOG) && \ 95 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 96 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 97 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 98 defined(CONFIG_IMX_WATCHDOG)) 99 hw_watchdog_init(); 100 puts(" Watchdog enabled\n"); 101 # endif 102 WATCHDOG_RESET(); 103 104 return 0; 105 } 106 107 int init_func_watchdog_reset(void) 108 { 109 WATCHDOG_RESET(); 110 111 return 0; 112 } 113 #endif /* CONFIG_WATCHDOG */ 114 115 __weak void board_add_ram_info(int use_default) 116 { 117 /* please define platform specific board_add_ram_info() */ 118 } 119 120 static int init_baud_rate(void) 121 { 122 if (gd && gd->serial.using_pre_serial) 123 gd->baudrate = env_get_ulong("baudrate", 10, gd->serial.baudrate); 124 else 125 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 126 127 return 0; 128 } 129 130 static int display_text_info(void) 131 { 132 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 133 ulong bss_start, bss_end, text_base; 134 135 bss_start = (ulong)&__bss_start; 136 bss_end = (ulong)&__bss_end; 137 138 #ifdef CONFIG_SYS_TEXT_BASE 139 text_base = CONFIG_SYS_TEXT_BASE; 140 #else 141 text_base = CONFIG_SYS_MONITOR_BASE; 142 #endif 143 144 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 145 text_base, bss_start, bss_end); 146 #endif 147 148 return 0; 149 } 150 151 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) 152 static int announce_pre_serial(void) 153 { 154 if (gd && gd->serial.using_pre_serial) 155 printf("PreSerial: %d\n", gd->serial.id); 156 157 return 0; 158 } 159 #endif 160 161 static int announce_dram_init(void) 162 { 163 puts("DRAM: "); 164 return 0; 165 } 166 167 static int show_dram_config(void) 168 { 169 unsigned long long size; 170 171 #ifdef CONFIG_NR_DRAM_BANKS 172 int i; 173 174 debug("\nRAM Configuration:\n"); 175 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 176 size += gd->bd->bi_dram[i].size; 177 debug("Bank #%d: %llx ", i, 178 (unsigned long long)(gd->bd->bi_dram[i].start)); 179 #ifdef DEBUG 180 print_size(gd->bd->bi_dram[i].size, "\n"); 181 #endif 182 } 183 debug("\nDRAM: "); 184 #else 185 size = gd->ram_size; 186 #endif 187 188 #ifdef CONFIG_BIDRAM 189 size += bidram_append_size(); 190 #endif 191 print_size(size, ""); 192 board_add_ram_info(0); 193 putc('\n'); 194 195 return 0; 196 } 197 198 __weak int dram_init_banksize(void) 199 { 200 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 201 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 202 gd->bd->bi_dram[0].size = get_effective_memsize(); 203 #endif 204 205 return 0; 206 } 207 208 #if defined(CONFIG_SYS_I2C) 209 static int init_func_i2c(void) 210 { 211 puts("I2C: "); 212 #ifdef CONFIG_SYS_I2C 213 i2c_init_all(); 214 #else 215 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 216 #endif 217 puts("ready\n"); 218 return 0; 219 } 220 #endif 221 222 #if defined(CONFIG_HARD_SPI) 223 static int init_func_spi(void) 224 { 225 puts("SPI: "); 226 spi_init(); 227 puts("ready\n"); 228 return 0; 229 } 230 #endif 231 232 static int setup_mon_len(void) 233 { 234 #if defined(__ARM__) || defined(__MICROBLAZE__) 235 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 236 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 237 gd->mon_len = (ulong)&_end - (ulong)_init; 238 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 239 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 240 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 241 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 242 #elif defined(CONFIG_SYS_MONITOR_BASE) 243 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 244 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 245 #endif 246 return 0; 247 } 248 249 __weak int arch_cpu_init(void) 250 { 251 return 0; 252 } 253 254 __weak int mach_cpu_init(void) 255 { 256 return 0; 257 } 258 259 /* Get the top of usable RAM */ 260 __weak ulong board_get_usable_ram_top(ulong total_size) 261 { 262 #ifdef CONFIG_SYS_SDRAM_BASE 263 /* 264 * Detect whether we have so much RAM that it goes past the end of our 265 * 32-bit address space. If so, clip the usable RAM so it doesn't. 266 */ 267 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 268 /* 269 * Will wrap back to top of 32-bit space when reservations 270 * are made. 271 */ 272 return 0; 273 #endif 274 return gd->ram_top; 275 } 276 277 static int setup_dest_addr(void) 278 { 279 debug("Monitor len: %08lX\n", gd->mon_len); 280 /* 281 * Ram is setup, size stored in gd !! 282 */ 283 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 284 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 285 /* 286 * Subtract specified amount of memory to hide so that it won't 287 * get "touched" at all by U-Boot. By fixing up gd->ram_size 288 * the Linux kernel should now get passed the now "corrected" 289 * memory size and won't touch it either. This should work 290 * for arch/ppc and arch/powerpc. Only Linux board ports in 291 * arch/powerpc with bootwrapper support, that recalculate the 292 * memory size from the SDRAM controller setup will have to 293 * get fixed. 294 */ 295 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 296 #endif 297 #ifdef CONFIG_SYS_SDRAM_BASE 298 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 299 #endif 300 gd->ram_top += get_effective_memsize(); 301 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 302 gd->relocaddr = gd->ram_top; 303 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 304 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 305 /* 306 * We need to make sure the location we intend to put secondary core 307 * boot code is reserved and not used by any part of u-boot 308 */ 309 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 310 gd->relocaddr = determine_mp_bootpg(NULL); 311 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 312 } 313 #endif 314 return 0; 315 } 316 317 #ifdef CONFIG_PRAM 318 /* reserve protected RAM */ 319 static int reserve_pram(void) 320 { 321 ulong reg; 322 323 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 324 gd->relocaddr -= (reg << 10); /* size is in kB */ 325 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 326 gd->relocaddr); 327 return 0; 328 } 329 #endif /* CONFIG_PRAM */ 330 331 /* Round memory pointer down to next 4 kB limit */ 332 static int reserve_round_4k(void) 333 { 334 gd->relocaddr &= ~(4096 - 1); 335 return 0; 336 } 337 338 #ifdef CONFIG_ARM 339 __weak int reserve_mmu(void) 340 { 341 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 342 /* reserve TLB table */ 343 gd->arch.tlb_size = PGTABLE_SIZE; 344 gd->relocaddr -= gd->arch.tlb_size; 345 346 /* round down to next 64 kB limit */ 347 gd->relocaddr &= ~(0x10000 - 1); 348 349 gd->arch.tlb_addr = gd->relocaddr; 350 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 351 gd->arch.tlb_addr + gd->arch.tlb_size); 352 353 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 354 /* 355 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 356 * with location within secure ram. 357 */ 358 gd->arch.tlb_allocated = gd->arch.tlb_addr; 359 #endif 360 #endif 361 362 return 0; 363 } 364 #endif 365 366 static int reserve_video(void) 367 { 368 #ifdef CONFIG_DM_VIDEO 369 ulong addr; 370 int ret; 371 372 addr = gd->relocaddr; 373 ret = video_reserve(&addr); 374 if (ret) 375 return ret; 376 gd->relocaddr = addr; 377 #elif defined(CONFIG_LCD) 378 # ifdef CONFIG_FB_ADDR 379 gd->fb_base = CONFIG_FB_ADDR; 380 # else 381 /* reserve memory for LCD display (always full pages) */ 382 gd->relocaddr = lcd_setmem(gd->relocaddr); 383 gd->fb_base = gd->relocaddr; 384 # endif /* CONFIG_FB_ADDR */ 385 #elif defined(CONFIG_VIDEO) && \ 386 (!defined(CONFIG_PPC)) && \ 387 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 388 !defined(CONFIG_M68K) 389 /* reserve memory for video display (always full pages) */ 390 gd->relocaddr = video_setmem(gd->relocaddr); 391 gd->fb_base = gd->relocaddr; 392 #endif 393 394 return 0; 395 } 396 397 static int reserve_trace(void) 398 { 399 #ifdef CONFIG_TRACE 400 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 401 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 402 debug("Reserving %dk for trace data at: %08lx\n", 403 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 404 #endif 405 406 return 0; 407 } 408 409 static int reserve_uboot(void) 410 { 411 /* 412 * reserve memory for U-Boot code, data & bss 413 * round down to next 4 kB limit 414 */ 415 gd->relocaddr -= gd->mon_len; 416 gd->relocaddr &= ~(4096 - 1); 417 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 418 /* round down to next 64 kB limit so that IVPR stays aligned */ 419 gd->relocaddr &= ~(65536 - 1); 420 #endif 421 422 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 423 gd->relocaddr); 424 425 gd->start_addr_sp = gd->relocaddr; 426 427 return 0; 428 } 429 430 /* reserve memory for malloc() area */ 431 static int reserve_malloc(void) 432 { 433 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 434 debug("Reserving %dk for malloc() at: %08lx\n", 435 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 436 return 0; 437 } 438 439 #ifdef CONFIG_SYS_NONCACHED_MEMORY 440 static int reserve_noncached(void) 441 { 442 phys_addr_t start, end; 443 size_t size; 444 445 end = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; 446 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); 447 start = end - size; 448 gd->start_addr_sp = start; 449 debug("Reserving %zu for noncached_alloc() at: %08lx\n", 450 size, gd->start_addr_sp); 451 452 return 0; 453 } 454 #endif 455 456 /* (permanently) allocate a Board Info struct */ 457 static int reserve_board(void) 458 { 459 if (!gd->bd) { 460 gd->start_addr_sp -= sizeof(bd_t); 461 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 462 memset(gd->bd, '\0', sizeof(bd_t)); 463 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 464 sizeof(bd_t), gd->start_addr_sp); 465 } 466 return 0; 467 } 468 469 static int setup_machine(void) 470 { 471 #ifdef CONFIG_MACH_TYPE 472 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 473 #endif 474 return 0; 475 } 476 477 static int reserve_global_data(void) 478 { 479 gd->start_addr_sp -= sizeof(gd_t); 480 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 481 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 482 sizeof(gd_t), gd->start_addr_sp); 483 return 0; 484 } 485 486 static int reserve_fdt(void) 487 { 488 #ifndef CONFIG_OF_EMBED 489 /* 490 * If the device tree is sitting immediately above our image then we 491 * must relocate it. If it is embedded in the data section, then it 492 * will be relocated with other data. 493 */ 494 if (gd->fdt_blob) { 495 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 496 497 gd->start_addr_sp -= gd->fdt_size; 498 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 499 debug("Reserving %lu Bytes for FDT at: %08lx\n", 500 gd->fdt_size, gd->start_addr_sp); 501 } 502 #endif 503 504 return 0; 505 } 506 507 static int reserve_bootstage(void) 508 { 509 #ifdef CONFIG_BOOTSTAGE 510 int size = bootstage_get_size(); 511 512 gd->start_addr_sp -= size; 513 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 514 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 515 gd->start_addr_sp); 516 #endif 517 518 return 0; 519 } 520 521 int arch_reserve_stacks(void) 522 { 523 return 0; 524 } 525 526 static int reserve_stacks(void) 527 { 528 /* make stack pointer 16-byte aligned */ 529 gd->start_addr_sp -= 16; 530 gd->start_addr_sp &= ~0xf; 531 532 /* 533 * let the architecture-specific code tailor gd->start_addr_sp and 534 * gd->irq_sp 535 */ 536 return arch_reserve_stacks(); 537 } 538 539 static int display_new_sp(void) 540 { 541 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 542 543 return 0; 544 } 545 546 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 547 defined(CONFIG_SH) 548 static int setup_board_part1(void) 549 { 550 bd_t *bd = gd->bd; 551 552 /* 553 * Save local variables to board info struct 554 */ 555 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 556 bd->bi_memsize = gd->ram_size; /* size in bytes */ 557 558 #ifdef CONFIG_SYS_SRAM_BASE 559 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 560 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 561 #endif 562 563 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 564 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 565 #endif 566 #if defined(CONFIG_M68K) 567 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 568 #endif 569 #if defined(CONFIG_MPC83xx) 570 bd->bi_immrbar = CONFIG_SYS_IMMR; 571 #endif 572 573 return 0; 574 } 575 #endif 576 577 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 578 static int setup_board_part2(void) 579 { 580 bd_t *bd = gd->bd; 581 582 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 583 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 584 #if defined(CONFIG_CPM2) 585 bd->bi_cpmfreq = gd->arch.cpm_clk; 586 bd->bi_brgfreq = gd->arch.brg_clk; 587 bd->bi_sccfreq = gd->arch.scc_clk; 588 bd->bi_vco = gd->arch.vco_out; 589 #endif /* CONFIG_CPM2 */ 590 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 591 bd->bi_pcifreq = gd->pci_clk; 592 #endif 593 #if defined(CONFIG_EXTRA_CLOCK) 594 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 595 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 596 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 597 #endif 598 599 return 0; 600 } 601 #endif 602 603 #ifdef CONFIG_POST 604 static int init_post(void) 605 { 606 post_bootmode_init(); 607 post_run(NULL, POST_ROM | post_bootmode_get(0)); 608 609 return 0; 610 } 611 #endif 612 613 static int reloc_fdt(void) 614 { 615 #ifndef CONFIG_OF_EMBED 616 if (gd->flags & GD_FLG_SKIP_RELOC) 617 return 0; 618 if (gd->new_fdt) { 619 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 620 gd->fdt_blob = gd->new_fdt; 621 #ifdef CONFIG_USING_KERNEL_DTB 622 gd->ufdt_blob = gd->new_fdt; 623 #endif 624 } 625 #endif 626 627 return 0; 628 } 629 630 static int reloc_bootstage(void) 631 { 632 #ifdef CONFIG_BOOTSTAGE 633 if (gd->flags & GD_FLG_SKIP_RELOC) 634 return 0; 635 if (gd->new_bootstage) { 636 int size = bootstage_get_size(); 637 638 debug("Copying bootstage from %p to %p, size %x\n", 639 gd->bootstage, gd->new_bootstage, size); 640 memcpy(gd->new_bootstage, gd->bootstage, size); 641 gd->bootstage = gd->new_bootstage; 642 } 643 #endif 644 645 return 0; 646 } 647 648 static int setup_reloc(void) 649 { 650 if (gd->flags & GD_FLG_SKIP_RELOC) { 651 debug("Skipping relocation due to flag\n"); 652 return 0; 653 } 654 655 #ifndef CONFIG_SKIP_RELOCATE_UBOOT 656 #ifdef CONFIG_SYS_TEXT_BASE 657 #ifdef ARM 658 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 659 #elif defined(CONFIG_M68K) 660 /* 661 * On all ColdFire arch cpu, monitor code starts always 662 * just after the default vector table location, so at 0x400 663 */ 664 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 665 #else 666 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 667 #endif 668 #endif 669 670 #else 671 gd->reloc_off = 0; 672 #endif 673 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 674 675 printf("Relocation Offset: %08lx, fdt: %08lx\n", 676 gd->reloc_off, (ulong)gd->new_fdt); 677 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 678 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 679 gd->start_addr_sp); 680 681 return 0; 682 } 683 684 #ifdef CONFIG_OF_BOARD_FIXUP 685 static int fix_fdt(void) 686 { 687 return board_fix_fdt((void *)gd->fdt_blob); 688 } 689 #endif 690 691 /* ARM calls relocate_code from its crt0.S */ 692 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 693 !CONFIG_IS_ENABLED(X86_64) 694 695 static int jump_to_copy(void) 696 { 697 if (gd->flags & GD_FLG_SKIP_RELOC) 698 return 0; 699 /* 700 * x86 is special, but in a nice way. It uses a trampoline which 701 * enables the dcache if possible. 702 * 703 * For now, other archs use relocate_code(), which is implemented 704 * similarly for all archs. When we do generic relocation, hopefully 705 * we can make all archs enable the dcache prior to relocation. 706 */ 707 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 708 /* 709 * SDRAM and console are now initialised. The final stack can now 710 * be setup in SDRAM. Code execution will continue in Flash, but 711 * with the stack in SDRAM and Global Data in temporary memory 712 * (CPU cache) 713 */ 714 arch_setup_gd(gd->new_gd); 715 board_init_f_r_trampoline(gd->start_addr_sp); 716 #else 717 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 718 #endif 719 720 return 0; 721 } 722 #endif 723 724 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 725 static int initf_bootstage(void) 726 { 727 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 728 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 729 int ret; 730 731 ret = bootstage_init(!from_spl); 732 if (ret) 733 return ret; 734 if (from_spl) { 735 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 736 CONFIG_BOOTSTAGE_STASH_SIZE); 737 738 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 739 if (ret && ret != -ENOENT) { 740 debug("Failed to unstash bootstage: err=%d\n", ret); 741 return ret; 742 } 743 } 744 745 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 746 747 return 0; 748 } 749 750 static int initf_console_record(void) 751 { 752 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 753 return console_record_init(); 754 #else 755 return 0; 756 #endif 757 } 758 759 static int initf_dm(void) 760 { 761 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 762 int ret; 763 764 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 765 ret = dm_init_and_scan(true); 766 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 767 if (ret) 768 return ret; 769 #endif 770 #ifdef CONFIG_TIMER_EARLY 771 ret = dm_timer_init(); 772 if (ret) 773 return ret; 774 #endif 775 776 return 0; 777 } 778 779 /* Architecture-specific memory reservation */ 780 __weak int reserve_arch(void) 781 { 782 return 0; 783 } 784 785 __weak int arch_cpu_init_dm(void) 786 { 787 return 0; 788 } 789 790 static const init_fnc_t init_sequence_f[] = { 791 setup_mon_len, 792 #ifdef CONFIG_OF_CONTROL 793 fdtdec_setup, 794 #endif 795 #ifdef CONFIG_TRACE 796 trace_early_init, 797 #endif 798 initf_malloc, 799 log_init, 800 initf_bootstage, /* uses its own timer, so does not need DM */ 801 initf_console_record, 802 #if defined(CONFIG_HAVE_FSP) 803 arch_fsp_init, 804 #endif 805 arch_cpu_init, /* basic arch cpu dependent setup */ 806 mach_cpu_init, /* SoC/machine dependent CPU setup */ 807 initf_dm, 808 arch_cpu_init_dm, 809 #if defined(CONFIG_BOARD_EARLY_INIT_F) 810 board_early_init_f, 811 #endif 812 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 813 /* get CPU and bus clocks according to the environment variable */ 814 get_clocks, /* get CPU and bus clocks (etc.) */ 815 #endif 816 #if !defined(CONFIG_M68K) 817 timer_init, /* initialize timer */ 818 #endif 819 #if defined(CONFIG_BOARD_POSTCLK_INIT) 820 board_postclk_init, 821 #endif 822 env_init, /* initialize environment */ 823 init_baud_rate, /* initialze baudrate settings */ 824 serial_init, /* serial communications setup */ 825 console_init_f, /* stage 1 init of console */ 826 display_options, /* say that we are here */ 827 display_text_info, /* show debugging info if required */ 828 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 829 defined(CONFIG_X86) 830 checkcpu, 831 #endif 832 #if defined(CONFIG_DISPLAY_CPUINFO) 833 print_cpuinfo, /* display cpu info (and speed) */ 834 #endif 835 #if defined(CONFIG_DTB_RESELECT) 836 embedded_dtb_select, 837 #endif 838 #if defined(CONFIG_DISPLAY_BOARDINFO) 839 show_board_info, 840 #endif 841 INIT_FUNC_WATCHDOG_INIT 842 #if defined(CONFIG_MISC_INIT_F) 843 misc_init_f, 844 #endif 845 INIT_FUNC_WATCHDOG_RESET 846 #if defined(CONFIG_SYS_I2C) 847 init_func_i2c, 848 #endif 849 #if defined(CONFIG_HARD_SPI) 850 init_func_spi, 851 #endif 852 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) 853 announce_pre_serial, 854 #endif 855 announce_dram_init, 856 dram_init, /* configure available RAM banks */ 857 #ifdef CONFIG_POST 858 post_init_f, 859 #endif 860 INIT_FUNC_WATCHDOG_RESET 861 #if defined(CONFIG_SYS_DRAM_TEST) 862 testdram, 863 #endif /* CONFIG_SYS_DRAM_TEST */ 864 INIT_FUNC_WATCHDOG_RESET 865 866 #ifdef CONFIG_POST 867 init_post, 868 #endif 869 INIT_FUNC_WATCHDOG_RESET 870 /* 871 * Now that we have DRAM mapped and working, we can 872 * relocate the code and continue running from DRAM. 873 * 874 * Reserve memory at end of RAM for (top down in that order): 875 * - area that won't get touched by U-Boot and Linux (optional) 876 * - kernel log buffer 877 * - protected RAM 878 * - LCD framebuffer 879 * - monitor code 880 * - board info struct 881 */ 882 setup_dest_addr, 883 #ifdef CONFIG_PRAM 884 reserve_pram, 885 #endif 886 reserve_round_4k, 887 #ifdef CONFIG_ARM 888 reserve_mmu, 889 #endif 890 reserve_video, 891 reserve_trace, 892 reserve_uboot, 893 reserve_malloc, 894 #ifdef CONFIG_SYS_NONCACHED_MEMORY 895 reserve_noncached, 896 #endif 897 reserve_board, 898 setup_machine, 899 reserve_global_data, 900 reserve_fdt, 901 reserve_bootstage, 902 reserve_arch, 903 reserve_stacks, 904 dram_init_banksize, 905 show_dram_config, 906 #ifdef CONFIG_SYSMEM 907 sysmem_init, /* Validate above reserve memory */ 908 #endif 909 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 910 defined(CONFIG_SH) 911 setup_board_part1, 912 #endif 913 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 914 INIT_FUNC_WATCHDOG_RESET 915 setup_board_part2, 916 #endif 917 display_new_sp, 918 #ifdef CONFIG_OF_BOARD_FIXUP 919 fix_fdt, 920 #endif 921 INIT_FUNC_WATCHDOG_RESET 922 reloc_fdt, 923 reloc_bootstage, 924 setup_reloc, 925 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 926 copy_uboot_to_ram, 927 do_elf_reloc_fixups, 928 clear_bss, 929 #endif 930 #if defined(CONFIG_XTENSA) 931 clear_bss, 932 #endif 933 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 934 !CONFIG_IS_ENABLED(X86_64) 935 jump_to_copy, 936 #endif 937 NULL, 938 }; 939 940 void board_init_f(ulong boot_flags) 941 { 942 gd->flags = boot_flags; 943 gd->have_console = 0; 944 945 #if defined(CONFIG_DISABLE_CONSOLE) 946 gd->flags |= GD_FLG_DISABLE_CONSOLE; 947 #endif 948 949 if (initcall_run_list(init_sequence_f)) 950 hang(); 951 952 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 953 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 954 /* NOTREACHED - jump_to_copy() does not return */ 955 hang(); 956 #endif 957 } 958 959 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 960 /* 961 * For now this code is only used on x86. 962 * 963 * init_sequence_f_r is the list of init functions which are run when 964 * U-Boot is executing from Flash with a semi-limited 'C' environment. 965 * The following limitations must be considered when implementing an 966 * '_f_r' function: 967 * - 'static' variables are read-only 968 * - Global Data (gd->xxx) is read/write 969 * 970 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 971 * supported). It _should_, if possible, copy global data to RAM and 972 * initialise the CPU caches (to speed up the relocation process) 973 * 974 * NOTE: At present only x86 uses this route, but it is intended that 975 * all archs will move to this when generic relocation is implemented. 976 */ 977 static const init_fnc_t init_sequence_f_r[] = { 978 #if !CONFIG_IS_ENABLED(X86_64) 979 init_cache_f_r, 980 #endif 981 982 NULL, 983 }; 984 985 void board_init_f_r(void) 986 { 987 if (initcall_run_list(init_sequence_f_r)) 988 hang(); 989 990 /* 991 * The pre-relocation drivers may be using memory that has now gone 992 * away. Mark serial as unavailable - this will fall back to the debug 993 * UART if available. 994 * 995 * Do the same with log drivers since the memory may not be available. 996 */ 997 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 998 #ifdef CONFIG_TIMER 999 gd->timer = NULL; 1000 #endif 1001 1002 /* 1003 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 1004 * Transfer execution from Flash to RAM by calculating the address 1005 * of the in-RAM copy of board_init_r() and calling it 1006 */ 1007 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 1008 1009 /* NOTREACHED - board_init_r() does not return */ 1010 hang(); 1011 } 1012 #endif /* CONFIG_X86 */ 1013