1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <malloc.h> 23 #include <mapmem.h> 24 #include <os.h> 25 #include <post.h> 26 #include <relocate.h> 27 #include <spi.h> 28 #include <status_led.h> 29 #include <timer.h> 30 #include <trace.h> 31 #include <video.h> 32 #include <watchdog.h> 33 #ifdef CONFIG_MACH_TYPE 34 #include <asm/mach-types.h> 35 #endif 36 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 37 #include <asm/mp.h> 38 #endif 39 #include <asm/io.h> 40 #include <asm/sections.h> 41 #include <dm/root.h> 42 #include <linux/errno.h> 43 #include <bidram.h> 44 #include <sysmem.h> 45 46 /* 47 * Pointer to initial global data area 48 * 49 * Here we initialize it if needed. 50 */ 51 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 52 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 53 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 54 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 55 #else 56 DECLARE_GLOBAL_DATA_PTR; 57 #endif 58 59 /* 60 * TODO(sjg@chromium.org): IMO this code should be 61 * refactored to a single function, something like: 62 * 63 * void led_set_state(enum led_colour_t colour, int on); 64 */ 65 /************************************************************************ 66 * Coloured LED functionality 67 ************************************************************************ 68 * May be supplied by boards if desired 69 */ 70 __weak void coloured_LED_init(void) {} 71 __weak void red_led_on(void) {} 72 __weak void red_led_off(void) {} 73 __weak void green_led_on(void) {} 74 __weak void green_led_off(void) {} 75 __weak void yellow_led_on(void) {} 76 __weak void yellow_led_off(void) {} 77 __weak void blue_led_on(void) {} 78 __weak void blue_led_off(void) {} 79 80 /* 81 * Why is gd allocated a register? Prior to reloc it might be better to 82 * just pass it around to each function in this file? 83 * 84 * After reloc one could argue that it is hardly used and doesn't need 85 * to be in a register. Or if it is it should perhaps hold pointers to all 86 * global data for all modules, so that post-reloc we can avoid the massive 87 * literal pool we get on ARM. Or perhaps just encourage each module to use 88 * a structure... 89 */ 90 91 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 92 static int init_func_watchdog_init(void) 93 { 94 # if defined(CONFIG_HW_WATCHDOG) && \ 95 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 96 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 97 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 98 defined(CONFIG_IMX_WATCHDOG)) 99 hw_watchdog_init(); 100 puts(" Watchdog enabled\n"); 101 # endif 102 WATCHDOG_RESET(); 103 104 return 0; 105 } 106 107 int init_func_watchdog_reset(void) 108 { 109 WATCHDOG_RESET(); 110 111 return 0; 112 } 113 #endif /* CONFIG_WATCHDOG */ 114 115 __weak void board_add_ram_info(int use_default) 116 { 117 /* please define platform specific board_add_ram_info() */ 118 } 119 120 static int init_baud_rate(void) 121 { 122 if (gd && gd->serial.baudrate) 123 gd->baudrate = gd->serial.baudrate; 124 else 125 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 126 127 return 0; 128 } 129 130 static int display_text_info(void) 131 { 132 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 133 ulong bss_start, bss_end, text_base; 134 135 bss_start = (ulong)&__bss_start; 136 bss_end = (ulong)&__bss_end; 137 138 #ifdef CONFIG_SYS_TEXT_BASE 139 text_base = CONFIG_SYS_TEXT_BASE; 140 #else 141 text_base = CONFIG_SYS_MONITOR_BASE; 142 #endif 143 144 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 145 text_base, bss_start, bss_end); 146 #endif 147 148 return 0; 149 } 150 151 static int announce_serial(void) 152 { 153 if (gd && gd->serial.using_pre_serial) 154 printf("PreSerial: %d, ", gd->serial.id); 155 else 156 printf("Serial: "); 157 158 #ifdef CONFIG_DEBUG_UART_ALWAYS 159 printf("raw"); 160 #else 161 printf("console"); 162 #endif 163 printf(", 0x%lx\n", gd->serial.addr); 164 165 return 0; 166 } 167 168 static int announce_dram_init(void) 169 { 170 #ifndef CONFIG_SUPPORT_USBPLUG 171 puts("DRAM: "); 172 #endif 173 return 0; 174 } 175 176 static int show_dram_config(void) 177 { 178 unsigned long long size; 179 180 #ifdef CONFIG_NR_DRAM_BANKS 181 int i; 182 183 debug("\nRAM Configuration:\n"); 184 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 185 size += gd->bd->bi_dram[i].size; 186 debug("Bank #%d: %llx ", i, 187 (unsigned long long)(gd->bd->bi_dram[i].start)); 188 #ifdef DEBUG 189 print_size(gd->bd->bi_dram[i].size, "\n"); 190 #endif 191 } 192 debug("\nDRAM: "); 193 #else 194 size = gd->ram_size; 195 #endif 196 197 #ifdef CONFIG_BIDRAM 198 size += bidram_append_size(); 199 #endif 200 201 #ifndef CONFIG_SUPPORT_USBPLUG 202 print_size(size, ""); 203 board_add_ram_info(0); 204 putc('\n'); 205 #endif 206 return 0; 207 } 208 209 __weak int dram_init_banksize(void) 210 { 211 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 212 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 213 gd->bd->bi_dram[0].size = get_effective_memsize(); 214 #endif 215 216 return 0; 217 } 218 219 #if defined(CONFIG_SYS_I2C) 220 static int init_func_i2c(void) 221 { 222 puts("I2C: "); 223 #ifdef CONFIG_SYS_I2C 224 i2c_init_all(); 225 #else 226 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 227 #endif 228 puts("ready\n"); 229 return 0; 230 } 231 #endif 232 233 #if defined(CONFIG_HARD_SPI) 234 static int init_func_spi(void) 235 { 236 puts("SPI: "); 237 spi_init(); 238 puts("ready\n"); 239 return 0; 240 } 241 #endif 242 243 static int setup_mon_len(void) 244 { 245 #if defined(__ARM__) || defined(__MICROBLAZE__) 246 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 247 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 248 gd->mon_len = (ulong)&_end - (ulong)_init; 249 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 250 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 251 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 252 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 253 #elif defined(CONFIG_SYS_MONITOR_BASE) 254 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 255 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 256 #endif 257 return 0; 258 } 259 260 __weak int arch_fpga_init(void) 261 { 262 return 0; 263 } 264 265 __weak int arch_cpu_init(void) 266 { 267 return 0; 268 } 269 270 __weak int mach_cpu_init(void) 271 { 272 return 0; 273 } 274 275 /* Get the top of usable RAM */ 276 __weak ulong board_get_usable_ram_top(ulong total_size) 277 { 278 #ifdef CONFIG_SYS_SDRAM_BASE 279 /* 280 * Detect whether we have so much RAM that it goes past the end of our 281 * 32-bit address space. If so, clip the usable RAM so it doesn't. 282 */ 283 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 284 /* 285 * Will wrap back to top of 32-bit space when reservations 286 * are made. 287 */ 288 return 0; 289 #endif 290 return gd->ram_top; 291 } 292 293 static int setup_dest_addr(void) 294 { 295 debug("Monitor len: %08lX\n", gd->mon_len); 296 /* 297 * Ram is setup, size stored in gd !! 298 */ 299 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 300 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 301 /* 302 * Subtract specified amount of memory to hide so that it won't 303 * get "touched" at all by U-Boot. By fixing up gd->ram_size 304 * the Linux kernel should now get passed the now "corrected" 305 * memory size and won't touch it either. This should work 306 * for arch/ppc and arch/powerpc. Only Linux board ports in 307 * arch/powerpc with bootwrapper support, that recalculate the 308 * memory size from the SDRAM controller setup will have to 309 * get fixed. 310 */ 311 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 312 #endif 313 #ifdef CONFIG_SYS_SDRAM_BASE 314 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 315 #endif 316 gd->ram_top += get_effective_memsize(); 317 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 318 gd->relocaddr = gd->ram_top; 319 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 320 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 321 /* 322 * We need to make sure the location we intend to put secondary core 323 * boot code is reserved and not used by any part of u-boot 324 */ 325 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 326 gd->relocaddr = determine_mp_bootpg(NULL); 327 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 328 } 329 #endif 330 return 0; 331 } 332 333 #ifdef CONFIG_PRAM 334 /* reserve protected RAM */ 335 static int reserve_pram(void) 336 { 337 ulong reg; 338 339 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 340 gd->relocaddr -= (reg << 10); /* size is in kB */ 341 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 342 gd->relocaddr); 343 return 0; 344 } 345 #endif /* CONFIG_PRAM */ 346 347 /* Round memory pointer down to next 4 kB limit */ 348 static int reserve_round_4k(void) 349 { 350 gd->relocaddr &= ~(4096 - 1); 351 return 0; 352 } 353 354 #ifdef CONFIG_ARM 355 __weak int reserve_mmu(void) 356 { 357 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 358 /* reserve TLB table */ 359 gd->arch.tlb_size = PGTABLE_SIZE; 360 gd->relocaddr -= gd->arch.tlb_size; 361 362 /* round down to next 64 kB limit */ 363 gd->relocaddr &= ~(0x10000 - 1); 364 365 gd->arch.tlb_addr = gd->relocaddr; 366 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 367 gd->arch.tlb_addr + gd->arch.tlb_size); 368 369 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 370 /* 371 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 372 * with location within secure ram. 373 */ 374 gd->arch.tlb_allocated = gd->arch.tlb_addr; 375 #endif 376 #endif 377 378 return 0; 379 } 380 #endif 381 382 static int reserve_video(void) 383 { 384 #ifdef CONFIG_DM_VIDEO 385 ulong addr; 386 int ret; 387 388 addr = gd->relocaddr; 389 ret = video_reserve(&addr); 390 if (ret) 391 return ret; 392 gd->relocaddr = addr; 393 #elif defined(CONFIG_LCD) 394 # ifdef CONFIG_FB_ADDR 395 gd->fb_base = CONFIG_FB_ADDR; 396 # else 397 /* reserve memory for LCD display (always full pages) */ 398 gd->relocaddr = lcd_setmem(gd->relocaddr); 399 gd->fb_base = gd->relocaddr; 400 # endif /* CONFIG_FB_ADDR */ 401 #elif defined(CONFIG_VIDEO) && \ 402 (!defined(CONFIG_PPC)) && \ 403 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 404 !defined(CONFIG_M68K) 405 /* reserve memory for video display (always full pages) */ 406 gd->relocaddr = video_setmem(gd->relocaddr); 407 gd->fb_base = gd->relocaddr; 408 #endif 409 410 return 0; 411 } 412 413 static int reserve_trace(void) 414 { 415 #ifdef CONFIG_TRACE 416 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 417 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 418 debug("Reserving %dk for trace data at: %08lx\n", 419 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 420 #endif 421 422 return 0; 423 } 424 425 static int reserve_uboot(void) 426 { 427 /* 428 * reserve memory for U-Boot code, data & bss 429 * round down to next 4 kB limit 430 */ 431 gd->relocaddr -= gd->mon_len; 432 gd->relocaddr &= ~(4096 - 1); 433 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 434 /* round down to next 64 kB limit so that IVPR stays aligned */ 435 gd->relocaddr &= ~(65536 - 1); 436 #endif 437 438 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 439 gd->relocaddr); 440 441 gd->start_addr_sp = gd->relocaddr; 442 443 return 0; 444 } 445 446 /* reserve memory for malloc() area */ 447 static int reserve_malloc(void) 448 { 449 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 450 debug("Reserving %dk for malloc() at: %08lx\n", 451 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 452 return 0; 453 } 454 455 #ifdef CONFIG_SYS_NONCACHED_MEMORY 456 static int reserve_noncached(void) 457 { 458 phys_addr_t start, end; 459 size_t size; 460 461 end = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; 462 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); 463 start = end - size; 464 gd->start_addr_sp = start; 465 debug("Reserving %zu for noncached_alloc() at: %08lx\n", 466 size, gd->start_addr_sp); 467 468 return 0; 469 } 470 #endif 471 472 /* (permanently) allocate a Board Info struct */ 473 static int reserve_board(void) 474 { 475 if (!gd->bd) { 476 gd->start_addr_sp -= sizeof(bd_t); 477 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 478 memset(gd->bd, '\0', sizeof(bd_t)); 479 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 480 sizeof(bd_t), gd->start_addr_sp); 481 } 482 return 0; 483 } 484 485 static int setup_machine(void) 486 { 487 #ifdef CONFIG_MACH_TYPE 488 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 489 #endif 490 return 0; 491 } 492 493 static int reserve_global_data(void) 494 { 495 gd->start_addr_sp -= sizeof(gd_t); 496 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 497 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 498 sizeof(gd_t), gd->start_addr_sp); 499 return 0; 500 } 501 502 static int reserve_fdt(void) 503 { 504 #ifndef CONFIG_OF_EMBED 505 /* 506 * If the device tree is sitting immediately above our image then we 507 * must relocate it. If it is embedded in the data section, then it 508 * will be relocated with other data. 509 */ 510 if (gd->fdt_blob) { 511 u32 extrasize = 0; 512 513 if (gd->fdt_blob_kern) 514 extrasize = fdt_totalsize(gd->fdt_blob_kern); 515 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + extrasize + 0x1000, 32); 516 gd->start_addr_sp -= gd->fdt_size; 517 518 /* 8-byte align */ 519 gd->start_addr_sp -= 8; 520 gd->start_addr_sp &= ~0x7; 521 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 522 523 if (gd->fdt_blob_kern) 524 gd->fdt_blob_kern = (ulong *)ALIGN((ulong)gd->new_fdt + 525 fdt_totalsize(gd->fdt_blob), 8); 526 debug("Reserving %lu Bytes for FDT at: %08lx\n", 527 gd->fdt_size, gd->start_addr_sp); 528 } 529 #endif 530 531 return 0; 532 } 533 534 static int reserve_bootstage(void) 535 { 536 #ifdef CONFIG_BOOTSTAGE 537 int size = bootstage_get_size(); 538 539 gd->start_addr_sp -= size; 540 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 541 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 542 gd->start_addr_sp); 543 #endif 544 545 return 0; 546 } 547 548 int arch_reserve_stacks(void) 549 { 550 return 0; 551 } 552 553 static int reserve_stacks(void) 554 { 555 /* make stack pointer 16-byte aligned */ 556 gd->start_addr_sp -= 16; 557 gd->start_addr_sp &= ~0xf; 558 559 /* 560 * let the architecture-specific code tailor gd->start_addr_sp and 561 * gd->irq_sp 562 */ 563 return arch_reserve_stacks(); 564 } 565 566 static int display_new_sp(void) 567 { 568 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 569 570 return 0; 571 } 572 573 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 574 defined(CONFIG_SH) 575 static int setup_board_part1(void) 576 { 577 bd_t *bd = gd->bd; 578 579 /* 580 * Save local variables to board info struct 581 */ 582 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 583 bd->bi_memsize = gd->ram_size; /* size in bytes */ 584 585 #ifdef CONFIG_SYS_SRAM_BASE 586 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 587 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 588 #endif 589 590 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 591 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 592 #endif 593 #if defined(CONFIG_M68K) 594 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 595 #endif 596 #if defined(CONFIG_MPC83xx) 597 bd->bi_immrbar = CONFIG_SYS_IMMR; 598 #endif 599 600 return 0; 601 } 602 #endif 603 604 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 605 static int setup_board_part2(void) 606 { 607 bd_t *bd = gd->bd; 608 609 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 610 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 611 #if defined(CONFIG_CPM2) 612 bd->bi_cpmfreq = gd->arch.cpm_clk; 613 bd->bi_brgfreq = gd->arch.brg_clk; 614 bd->bi_sccfreq = gd->arch.scc_clk; 615 bd->bi_vco = gd->arch.vco_out; 616 #endif /* CONFIG_CPM2 */ 617 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 618 bd->bi_pcifreq = gd->pci_clk; 619 #endif 620 #if defined(CONFIG_EXTRA_CLOCK) 621 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 622 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 623 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 624 #endif 625 626 return 0; 627 } 628 #endif 629 630 #ifdef CONFIG_POST 631 static int init_post(void) 632 { 633 post_bootmode_init(); 634 post_run(NULL, POST_ROM | post_bootmode_get(0)); 635 636 return 0; 637 } 638 #endif 639 640 static int reloc_fdt(void) 641 { 642 #ifndef CONFIG_OF_EMBED 643 if (gd->flags & GD_FLG_SKIP_RELOC) 644 return 0; 645 if (gd->new_fdt) { 646 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 647 gd->fdt_blob = gd->new_fdt; 648 #ifdef CONFIG_USING_KERNEL_DTB 649 gd->ufdt_blob = gd->new_fdt; 650 #endif 651 } 652 #endif 653 654 return 0; 655 } 656 657 static int reloc_bootstage(void) 658 { 659 #ifdef CONFIG_BOOTSTAGE 660 if (gd->flags & GD_FLG_SKIP_RELOC) 661 return 0; 662 if (gd->new_bootstage) { 663 int size = bootstage_get_size(); 664 665 debug("Copying bootstage from %p to %p, size %x\n", 666 gd->bootstage, gd->new_bootstage, size); 667 memcpy(gd->new_bootstage, gd->bootstage, size); 668 gd->bootstage = gd->new_bootstage; 669 } 670 #endif 671 672 return 0; 673 } 674 675 static int setup_reloc(void) 676 { 677 if (gd->flags & GD_FLG_SKIP_RELOC) { 678 debug("Skipping relocation due to flag\n"); 679 return 0; 680 } 681 682 #ifndef CONFIG_SKIP_RELOCATE_UBOOT 683 #ifdef CONFIG_SYS_TEXT_BASE 684 #ifdef ARM 685 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 686 #elif defined(CONFIG_M68K) 687 /* 688 * On all ColdFire arch cpu, monitor code starts always 689 * just after the default vector table location, so at 0x400 690 */ 691 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 692 #else 693 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 694 #endif 695 #endif 696 697 #else 698 gd->reloc_off = 0; 699 #endif 700 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 701 702 #ifndef CONFIG_SUPPORT_USBPLUG 703 printf("Relocation Offset: %08lx\n", gd->reloc_off); 704 705 printf("Relocation fdt: %08lx - %08lx", (ulong)gd->new_fdt, 706 (ulong)gd->new_fdt + fdt_totalsize(gd->fdt_blob)); 707 if (gd->fdt_blob_kern) { 708 printf(", kfdt: %08lx - %08lx", (ulong)gd->fdt_blob_kern, 709 (ulong)gd->fdt_blob_kern + fdt_totalsize(gd->fdt_blob_kern)); 710 } 711 puts("\n"); 712 #endif 713 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 714 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 715 gd->start_addr_sp); 716 717 return 0; 718 } 719 720 #ifdef CONFIG_OF_BOARD_FIXUP 721 static int fix_fdt(void) 722 { 723 return board_fix_fdt((void *)gd->fdt_blob); 724 } 725 #endif 726 727 /* ARM calls relocate_code from its crt0.S */ 728 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 729 !CONFIG_IS_ENABLED(X86_64) 730 731 static int jump_to_copy(void) 732 { 733 if (gd->flags & GD_FLG_SKIP_RELOC) 734 return 0; 735 /* 736 * x86 is special, but in a nice way. It uses a trampoline which 737 * enables the dcache if possible. 738 * 739 * For now, other archs use relocate_code(), which is implemented 740 * similarly for all archs. When we do generic relocation, hopefully 741 * we can make all archs enable the dcache prior to relocation. 742 */ 743 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 744 /* 745 * SDRAM and console are now initialised. The final stack can now 746 * be setup in SDRAM. Code execution will continue in Flash, but 747 * with the stack in SDRAM and Global Data in temporary memory 748 * (CPU cache) 749 */ 750 arch_setup_gd(gd->new_gd); 751 board_init_f_r_trampoline(gd->start_addr_sp); 752 #else 753 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 754 #endif 755 756 return 0; 757 } 758 #endif 759 760 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 761 static int initf_bootstage(void) 762 { 763 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 764 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 765 int ret; 766 767 ret = bootstage_init(!from_spl); 768 if (ret) 769 return ret; 770 if (from_spl) { 771 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 772 CONFIG_BOOTSTAGE_STASH_SIZE); 773 774 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 775 if (ret && ret != -ENOENT) { 776 debug("Failed to unstash bootstage: err=%d\n", ret); 777 return ret; 778 } 779 } 780 781 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 782 783 return 0; 784 } 785 786 static int initf_console_record(void) 787 { 788 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 789 return console_record_init(); 790 #else 791 return 0; 792 #endif 793 } 794 795 static int initf_dm(void) 796 { 797 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 798 int ret; 799 800 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 801 ret = dm_init_and_scan(true); 802 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 803 if (ret) 804 return ret; 805 #endif 806 #ifdef CONFIG_TIMER_EARLY 807 ret = dm_timer_init(); 808 if (ret) 809 return ret; 810 #endif 811 812 return 0; 813 } 814 815 /* Architecture-specific memory reservation */ 816 __weak int reserve_arch(void) 817 { 818 return 0; 819 } 820 821 __weak int arch_cpu_init_dm(void) 822 { 823 return 0; 824 } 825 826 static const init_fnc_t init_sequence_f[] = { 827 setup_mon_len, 828 #ifdef CONFIG_OF_CONTROL 829 fdtdec_setup, 830 #endif 831 #ifdef CONFIG_TRACE 832 trace_early_init, 833 #endif 834 initf_malloc, 835 log_init, 836 initf_bootstage, /* uses its own timer, so does not need DM */ 837 initf_console_record, 838 #if defined(CONFIG_HAVE_FSP) 839 arch_fsp_init, 840 #endif 841 arch_fpga_init, 842 arch_cpu_init, /* basic arch cpu dependent setup */ 843 mach_cpu_init, /* SoC/machine dependent CPU setup */ 844 initf_dm, 845 arch_cpu_init_dm, 846 #if defined(CONFIG_BOARD_EARLY_INIT_F) 847 board_early_init_f, 848 #endif 849 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 850 /* get CPU and bus clocks according to the environment variable */ 851 get_clocks, /* get CPU and bus clocks (etc.) */ 852 #endif 853 #if !defined(CONFIG_M68K) 854 timer_init, /* initialize timer */ 855 #endif 856 #if defined(CONFIG_BOARD_POSTCLK_INIT) 857 board_postclk_init, 858 #endif 859 env_init, /* initialize environment */ 860 init_baud_rate, /* initialze baudrate settings */ 861 serial_init, /* serial communications setup */ 862 console_init_f, /* stage 1 init of console */ 863 display_options, /* say that we are here */ 864 display_text_info, /* show debugging info if required */ 865 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 866 defined(CONFIG_X86) 867 checkcpu, 868 #endif 869 #if defined(CONFIG_DISPLAY_CPUINFO) 870 print_cpuinfo, /* display cpu info (and speed) */ 871 #endif 872 #if defined(CONFIG_DTB_RESELECT) 873 embedded_dtb_select, 874 #endif 875 #if defined(CONFIG_DISPLAY_BOARDINFO) 876 show_board_info, 877 #endif 878 INIT_FUNC_WATCHDOG_INIT 879 #if defined(CONFIG_MISC_INIT_F) 880 misc_init_f, 881 #endif 882 INIT_FUNC_WATCHDOG_RESET 883 #if defined(CONFIG_SYS_I2C) 884 init_func_i2c, 885 #endif 886 #if defined(CONFIG_HARD_SPI) 887 init_func_spi, 888 #endif 889 announce_serial, 890 891 announce_dram_init, 892 dram_init, /* configure available RAM banks */ 893 #ifdef CONFIG_POST 894 post_init_f, 895 #endif 896 INIT_FUNC_WATCHDOG_RESET 897 #if defined(CONFIG_SYS_DRAM_TEST) 898 testdram, 899 #endif /* CONFIG_SYS_DRAM_TEST */ 900 INIT_FUNC_WATCHDOG_RESET 901 902 #ifdef CONFIG_POST 903 init_post, 904 #endif 905 INIT_FUNC_WATCHDOG_RESET 906 /* 907 * Now that we have DRAM mapped and working, we can 908 * relocate the code and continue running from DRAM. 909 * 910 * Reserve memory at end of RAM for (top down in that order): 911 * - area that won't get touched by U-Boot and Linux (optional) 912 * - kernel log buffer 913 * - protected RAM 914 * - LCD framebuffer 915 * - monitor code 916 * - board info struct 917 */ 918 setup_dest_addr, 919 #ifdef CONFIG_PRAM 920 reserve_pram, 921 #endif 922 reserve_round_4k, 923 #ifdef CONFIG_ARM 924 reserve_mmu, 925 #endif 926 reserve_video, 927 reserve_trace, 928 reserve_uboot, 929 reserve_malloc, 930 #ifdef CONFIG_SYS_NONCACHED_MEMORY 931 reserve_noncached, 932 #endif 933 reserve_board, 934 setup_machine, 935 reserve_global_data, 936 reserve_fdt, 937 reserve_bootstage, 938 reserve_arch, 939 reserve_stacks, 940 dram_init_banksize, 941 show_dram_config, 942 #ifdef CONFIG_SYSMEM 943 sysmem_init, /* Validate above reserve memory */ 944 #endif 945 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 946 defined(CONFIG_SH) 947 setup_board_part1, 948 #endif 949 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 950 INIT_FUNC_WATCHDOG_RESET 951 setup_board_part2, 952 #endif 953 display_new_sp, 954 #ifdef CONFIG_OF_BOARD_FIXUP 955 fix_fdt, 956 #endif 957 INIT_FUNC_WATCHDOG_RESET 958 reloc_fdt, 959 reloc_bootstage, 960 setup_reloc, 961 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 962 copy_uboot_to_ram, 963 do_elf_reloc_fixups, 964 clear_bss, 965 #endif 966 #if defined(CONFIG_XTENSA) 967 clear_bss, 968 #endif 969 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 970 !CONFIG_IS_ENABLED(X86_64) 971 jump_to_copy, 972 #endif 973 NULL, 974 }; 975 976 void board_init_f(ulong boot_flags) 977 { 978 gd->flags = boot_flags; 979 gd->have_console = 0; 980 981 if (initcall_run_list(init_sequence_f)) 982 hang(); 983 984 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 985 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 986 /* NOTREACHED - jump_to_copy() does not return */ 987 hang(); 988 #endif 989 } 990 991 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 992 /* 993 * For now this code is only used on x86. 994 * 995 * init_sequence_f_r is the list of init functions which are run when 996 * U-Boot is executing from Flash with a semi-limited 'C' environment. 997 * The following limitations must be considered when implementing an 998 * '_f_r' function: 999 * - 'static' variables are read-only 1000 * - Global Data (gd->xxx) is read/write 1001 * 1002 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 1003 * supported). It _should_, if possible, copy global data to RAM and 1004 * initialise the CPU caches (to speed up the relocation process) 1005 * 1006 * NOTE: At present only x86 uses this route, but it is intended that 1007 * all archs will move to this when generic relocation is implemented. 1008 */ 1009 static const init_fnc_t init_sequence_f_r[] = { 1010 #if !CONFIG_IS_ENABLED(X86_64) 1011 init_cache_f_r, 1012 #endif 1013 1014 NULL, 1015 }; 1016 1017 void board_init_f_r(void) 1018 { 1019 if (initcall_run_list(init_sequence_f_r)) 1020 hang(); 1021 1022 /* 1023 * The pre-relocation drivers may be using memory that has now gone 1024 * away. Mark serial as unavailable - this will fall back to the debug 1025 * UART if available. 1026 * 1027 * Do the same with log drivers since the memory may not be available. 1028 */ 1029 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 1030 #ifdef CONFIG_TIMER 1031 gd->timer = NULL; 1032 #endif 1033 1034 /* 1035 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 1036 * Transfer execution from Flash to RAM by calculating the address 1037 * of the in-RAM copy of board_init_r() and calling it 1038 */ 1039 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 1040 1041 /* NOTREACHED - board_init_r() does not return */ 1042 hang(); 1043 } 1044 #endif /* CONFIG_X86 */ 1045