1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <logbuff.h> 23 #include <malloc.h> 24 #include <mapmem.h> 25 #include <os.h> 26 #include <post.h> 27 #include <relocate.h> 28 #include <spi.h> 29 #include <status_led.h> 30 #include <timer.h> 31 #include <trace.h> 32 #include <video.h> 33 #include <watchdog.h> 34 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 35 #include <asm/mp.h> 36 #endif 37 #include <asm/io.h> 38 #include <asm/sections.h> 39 #include <dm/root.h> 40 #include <linux/errno.h> 41 42 /* 43 * Pointer to initial global data area 44 * 45 * Here we initialize it if needed. 46 */ 47 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 48 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 49 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 50 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 51 #else 52 DECLARE_GLOBAL_DATA_PTR; 53 #endif 54 55 /* 56 * TODO(sjg@chromium.org): IMO this code should be 57 * refactored to a single function, something like: 58 * 59 * void led_set_state(enum led_colour_t colour, int on); 60 */ 61 /************************************************************************ 62 * Coloured LED functionality 63 ************************************************************************ 64 * May be supplied by boards if desired 65 */ 66 __weak void coloured_LED_init(void) {} 67 __weak void red_led_on(void) {} 68 __weak void red_led_off(void) {} 69 __weak void green_led_on(void) {} 70 __weak void green_led_off(void) {} 71 __weak void yellow_led_on(void) {} 72 __weak void yellow_led_off(void) {} 73 __weak void blue_led_on(void) {} 74 __weak void blue_led_off(void) {} 75 76 /* 77 * Why is gd allocated a register? Prior to reloc it might be better to 78 * just pass it around to each function in this file? 79 * 80 * After reloc one could argue that it is hardly used and doesn't need 81 * to be in a register. Or if it is it should perhaps hold pointers to all 82 * global data for all modules, so that post-reloc we can avoid the massive 83 * literal pool we get on ARM. Or perhaps just encourage each module to use 84 * a structure... 85 */ 86 87 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 88 static int init_func_watchdog_init(void) 89 { 90 # if defined(CONFIG_HW_WATCHDOG) && \ 91 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 92 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 93 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 94 defined(CONFIG_IMX_WATCHDOG)) 95 hw_watchdog_init(); 96 puts(" Watchdog enabled\n"); 97 # endif 98 WATCHDOG_RESET(); 99 100 return 0; 101 } 102 103 int init_func_watchdog_reset(void) 104 { 105 WATCHDOG_RESET(); 106 107 return 0; 108 } 109 #endif /* CONFIG_WATCHDOG */ 110 111 __weak void board_add_ram_info(int use_default) 112 { 113 /* please define platform specific board_add_ram_info() */ 114 } 115 116 static int init_baud_rate(void) 117 { 118 gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); 119 return 0; 120 } 121 122 static int display_text_info(void) 123 { 124 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 125 ulong bss_start, bss_end, text_base; 126 127 bss_start = (ulong)&__bss_start; 128 bss_end = (ulong)&__bss_end; 129 130 #ifdef CONFIG_SYS_TEXT_BASE 131 text_base = CONFIG_SYS_TEXT_BASE; 132 #else 133 text_base = CONFIG_SYS_MONITOR_BASE; 134 #endif 135 136 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 137 text_base, bss_start, bss_end); 138 #endif 139 140 return 0; 141 } 142 143 static int announce_dram_init(void) 144 { 145 puts("DRAM: "); 146 return 0; 147 } 148 149 #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) 150 static int init_func_ram(void) 151 { 152 return initdram(); 153 } 154 #endif 155 156 static int show_dram_config(void) 157 { 158 unsigned long long size; 159 160 #ifdef CONFIG_NR_DRAM_BANKS 161 int i; 162 163 debug("\nRAM Configuration:\n"); 164 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 165 size += gd->bd->bi_dram[i].size; 166 debug("Bank #%d: %llx ", i, 167 (unsigned long long)(gd->bd->bi_dram[i].start)); 168 #ifdef DEBUG 169 print_size(gd->bd->bi_dram[i].size, "\n"); 170 #endif 171 } 172 debug("\nDRAM: "); 173 #else 174 size = gd->ram_size; 175 #endif 176 177 print_size(size, ""); 178 board_add_ram_info(0); 179 putc('\n'); 180 181 return 0; 182 } 183 184 __weak int dram_init_banksize(void) 185 { 186 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 187 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 188 gd->bd->bi_dram[0].size = get_effective_memsize(); 189 #endif 190 191 return 0; 192 } 193 194 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) 195 static int init_func_i2c(void) 196 { 197 puts("I2C: "); 198 #ifdef CONFIG_SYS_I2C 199 i2c_init_all(); 200 #else 201 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 202 #endif 203 puts("ready\n"); 204 return 0; 205 } 206 #endif 207 208 #if defined(CONFIG_HARD_SPI) 209 static int init_func_spi(void) 210 { 211 puts("SPI: "); 212 spi_init(); 213 puts("ready\n"); 214 return 0; 215 } 216 #endif 217 218 __maybe_unused 219 static int zero_global_data(void) 220 { 221 memset((void *)gd, '\0', sizeof(gd_t)); 222 223 return 0; 224 } 225 226 static int setup_mon_len(void) 227 { 228 #if defined(__ARM__) || defined(__MICROBLAZE__) 229 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 230 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 231 gd->mon_len = (ulong)&_end - (ulong)_init; 232 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 233 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 234 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) 235 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 236 #elif defined(CONFIG_SYS_MONITOR_BASE) 237 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 238 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 239 #endif 240 return 0; 241 } 242 243 __weak int arch_cpu_init(void) 244 { 245 return 0; 246 } 247 248 __weak int mach_cpu_init(void) 249 { 250 return 0; 251 } 252 253 /* Get the top of usable RAM */ 254 __weak ulong board_get_usable_ram_top(ulong total_size) 255 { 256 #ifdef CONFIG_SYS_SDRAM_BASE 257 /* 258 * Detect whether we have so much RAM that it goes past the end of our 259 * 32-bit address space. If so, clip the usable RAM so it doesn't. 260 */ 261 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 262 /* 263 * Will wrap back to top of 32-bit space when reservations 264 * are made. 265 */ 266 return 0; 267 #endif 268 return gd->ram_top; 269 } 270 271 static int setup_dest_addr(void) 272 { 273 debug("Monitor len: %08lX\n", gd->mon_len); 274 /* 275 * Ram is setup, size stored in gd !! 276 */ 277 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 278 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 279 /* 280 * Subtract specified amount of memory to hide so that it won't 281 * get "touched" at all by U-Boot. By fixing up gd->ram_size 282 * the Linux kernel should now get passed the now "corrected" 283 * memory size and won't touch it either. This should work 284 * for arch/ppc and arch/powerpc. Only Linux board ports in 285 * arch/powerpc with bootwrapper support, that recalculate the 286 * memory size from the SDRAM controller setup will have to 287 * get fixed. 288 */ 289 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 290 #endif 291 #ifdef CONFIG_SYS_SDRAM_BASE 292 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 293 #endif 294 gd->ram_top += get_effective_memsize(); 295 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 296 gd->relocaddr = gd->ram_top; 297 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 298 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 299 /* 300 * We need to make sure the location we intend to put secondary core 301 * boot code is reserved and not used by any part of u-boot 302 */ 303 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 304 gd->relocaddr = determine_mp_bootpg(NULL); 305 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 306 } 307 #endif 308 return 0; 309 } 310 311 #if defined(CONFIG_LOGBUFFER) 312 static int reserve_logbuffer(void) 313 { 314 #ifndef CONFIG_ALT_LB_ADDR 315 /* reserve kernel log buffer */ 316 gd->relocaddr -= LOGBUFF_RESERVE; 317 debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, 318 gd->relocaddr); 319 #endif 320 321 return 0; 322 } 323 #endif 324 325 #ifdef CONFIG_PRAM 326 /* reserve protected RAM */ 327 static int reserve_pram(void) 328 { 329 ulong reg; 330 331 reg = getenv_ulong("pram", 10, CONFIG_PRAM); 332 gd->relocaddr -= (reg << 10); /* size is in kB */ 333 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 334 gd->relocaddr); 335 return 0; 336 } 337 #endif /* CONFIG_PRAM */ 338 339 /* Round memory pointer down to next 4 kB limit */ 340 static int reserve_round_4k(void) 341 { 342 gd->relocaddr &= ~(4096 - 1); 343 return 0; 344 } 345 346 #ifdef CONFIG_ARM 347 static int reserve_mmu(void) 348 { 349 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 350 /* reserve TLB table */ 351 gd->arch.tlb_size = PGTABLE_SIZE; 352 gd->relocaddr -= gd->arch.tlb_size; 353 354 /* round down to next 64 kB limit */ 355 gd->relocaddr &= ~(0x10000 - 1); 356 357 gd->arch.tlb_addr = gd->relocaddr; 358 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 359 gd->arch.tlb_addr + gd->arch.tlb_size); 360 361 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 362 /* 363 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 364 * with location within secure ram. 365 */ 366 gd->arch.tlb_allocated = gd->arch.tlb_addr; 367 #endif 368 #endif 369 370 return 0; 371 } 372 #endif 373 374 static int reserve_video(void) 375 { 376 #ifdef CONFIG_DM_VIDEO 377 ulong addr; 378 int ret; 379 380 addr = gd->relocaddr; 381 ret = video_reserve(&addr); 382 if (ret) 383 return ret; 384 gd->relocaddr = addr; 385 #elif defined(CONFIG_LCD) 386 # ifdef CONFIG_FB_ADDR 387 gd->fb_base = CONFIG_FB_ADDR; 388 # else 389 /* reserve memory for LCD display (always full pages) */ 390 gd->relocaddr = lcd_setmem(gd->relocaddr); 391 gd->fb_base = gd->relocaddr; 392 # endif /* CONFIG_FB_ADDR */ 393 #elif defined(CONFIG_VIDEO) && \ 394 (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ 395 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 396 !defined(CONFIG_M68K) 397 /* reserve memory for video display (always full pages) */ 398 gd->relocaddr = video_setmem(gd->relocaddr); 399 gd->fb_base = gd->relocaddr; 400 #endif 401 402 return 0; 403 } 404 405 static int reserve_trace(void) 406 { 407 #ifdef CONFIG_TRACE 408 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 409 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 410 debug("Reserving %dk for trace data at: %08lx\n", 411 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 412 #endif 413 414 return 0; 415 } 416 417 static int reserve_uboot(void) 418 { 419 /* 420 * reserve memory for U-Boot code, data & bss 421 * round down to next 4 kB limit 422 */ 423 gd->relocaddr -= gd->mon_len; 424 gd->relocaddr &= ~(4096 - 1); 425 #ifdef CONFIG_E500 426 /* round down to next 64 kB limit so that IVPR stays aligned */ 427 gd->relocaddr &= ~(65536 - 1); 428 #endif 429 430 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 431 gd->relocaddr); 432 433 gd->start_addr_sp = gd->relocaddr; 434 435 return 0; 436 } 437 438 /* reserve memory for malloc() area */ 439 static int reserve_malloc(void) 440 { 441 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 442 debug("Reserving %dk for malloc() at: %08lx\n", 443 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 444 return 0; 445 } 446 447 /* (permanently) allocate a Board Info struct */ 448 static int reserve_board(void) 449 { 450 if (!gd->bd) { 451 gd->start_addr_sp -= sizeof(bd_t); 452 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 453 memset(gd->bd, '\0', sizeof(bd_t)); 454 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 455 sizeof(bd_t), gd->start_addr_sp); 456 } 457 return 0; 458 } 459 460 static int setup_machine(void) 461 { 462 #ifdef CONFIG_MACH_TYPE 463 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 464 #endif 465 return 0; 466 } 467 468 static int reserve_global_data(void) 469 { 470 gd->start_addr_sp -= sizeof(gd_t); 471 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 472 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 473 sizeof(gd_t), gd->start_addr_sp); 474 return 0; 475 } 476 477 static int reserve_fdt(void) 478 { 479 #ifndef CONFIG_OF_EMBED 480 /* 481 * If the device tree is sitting immediately above our image then we 482 * must relocate it. If it is embedded in the data section, then it 483 * will be relocated with other data. 484 */ 485 if (gd->fdt_blob) { 486 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 487 488 gd->start_addr_sp -= gd->fdt_size; 489 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 490 debug("Reserving %lu Bytes for FDT at: %08lx\n", 491 gd->fdt_size, gd->start_addr_sp); 492 } 493 #endif 494 495 return 0; 496 } 497 498 int arch_reserve_stacks(void) 499 { 500 return 0; 501 } 502 503 static int reserve_stacks(void) 504 { 505 /* make stack pointer 16-byte aligned */ 506 gd->start_addr_sp -= 16; 507 gd->start_addr_sp &= ~0xf; 508 509 /* 510 * let the architecture-specific code tailor gd->start_addr_sp and 511 * gd->irq_sp 512 */ 513 return arch_reserve_stacks(); 514 } 515 516 static int display_new_sp(void) 517 { 518 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 519 520 return 0; 521 } 522 523 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 524 defined(CONFIG_SH) 525 static int setup_board_part1(void) 526 { 527 bd_t *bd = gd->bd; 528 529 /* 530 * Save local variables to board info struct 531 */ 532 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 533 bd->bi_memsize = gd->ram_size; /* size in bytes */ 534 535 #ifdef CONFIG_SYS_SRAM_BASE 536 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 537 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 538 #endif 539 540 #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ 541 defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 542 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 543 #endif 544 #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) 545 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 546 #endif 547 #if defined(CONFIG_MPC83xx) 548 bd->bi_immrbar = CONFIG_SYS_IMMR; 549 #endif 550 551 return 0; 552 } 553 #endif 554 555 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 556 static int setup_board_part2(void) 557 { 558 bd_t *bd = gd->bd; 559 560 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 561 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 562 #if defined(CONFIG_CPM2) 563 bd->bi_cpmfreq = gd->arch.cpm_clk; 564 bd->bi_brgfreq = gd->arch.brg_clk; 565 bd->bi_sccfreq = gd->arch.scc_clk; 566 bd->bi_vco = gd->arch.vco_out; 567 #endif /* CONFIG_CPM2 */ 568 #if defined(CONFIG_MPC512X) 569 bd->bi_ipsfreq = gd->arch.ips_clk; 570 #endif /* CONFIG_MPC512X */ 571 #if defined(CONFIG_MPC5xxx) 572 bd->bi_ipbfreq = gd->arch.ipb_clk; 573 bd->bi_pcifreq = gd->pci_clk; 574 #endif /* CONFIG_MPC5xxx */ 575 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 576 bd->bi_pcifreq = gd->pci_clk; 577 #endif 578 #if defined(CONFIG_EXTRA_CLOCK) 579 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 580 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 581 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 582 #endif 583 584 return 0; 585 } 586 #endif 587 588 #ifdef CONFIG_POST 589 static int init_post(void) 590 { 591 post_bootmode_init(); 592 post_run(NULL, POST_ROM | post_bootmode_get(0)); 593 594 return 0; 595 } 596 #endif 597 598 static int reloc_fdt(void) 599 { 600 #ifndef CONFIG_OF_EMBED 601 if (gd->flags & GD_FLG_SKIP_RELOC) 602 return 0; 603 if (gd->new_fdt) { 604 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 605 gd->fdt_blob = gd->new_fdt; 606 } 607 #endif 608 609 return 0; 610 } 611 612 static int setup_reloc(void) 613 { 614 if (gd->flags & GD_FLG_SKIP_RELOC) { 615 debug("Skipping relocation due to flag\n"); 616 return 0; 617 } 618 619 #ifdef CONFIG_SYS_TEXT_BASE 620 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 621 #ifdef CONFIG_M68K 622 /* 623 * On all ColdFire arch cpu, monitor code starts always 624 * just after the default vector table location, so at 0x400 625 */ 626 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 627 #endif 628 #endif 629 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 630 631 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 632 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 633 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 634 gd->start_addr_sp); 635 636 return 0; 637 } 638 639 #ifdef CONFIG_OF_BOARD_FIXUP 640 static int fix_fdt(void) 641 { 642 return board_fix_fdt((void *)gd->fdt_blob); 643 } 644 #endif 645 646 /* ARM calls relocate_code from its crt0.S */ 647 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 648 !CONFIG_IS_ENABLED(X86_64) 649 650 static int jump_to_copy(void) 651 { 652 if (gd->flags & GD_FLG_SKIP_RELOC) 653 return 0; 654 /* 655 * x86 is special, but in a nice way. It uses a trampoline which 656 * enables the dcache if possible. 657 * 658 * For now, other archs use relocate_code(), which is implemented 659 * similarly for all archs. When we do generic relocation, hopefully 660 * we can make all archs enable the dcache prior to relocation. 661 */ 662 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 663 /* 664 * SDRAM and console are now initialised. The final stack can now 665 * be setup in SDRAM. Code execution will continue in Flash, but 666 * with the stack in SDRAM and Global Data in temporary memory 667 * (CPU cache) 668 */ 669 arch_setup_gd(gd->new_gd); 670 board_init_f_r_trampoline(gd->start_addr_sp); 671 #else 672 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 673 #endif 674 675 return 0; 676 } 677 #endif 678 679 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 680 static int mark_bootstage(void) 681 { 682 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 683 684 return 0; 685 } 686 687 static int initf_console_record(void) 688 { 689 #if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN) 690 return console_record_init(); 691 #else 692 return 0; 693 #endif 694 } 695 696 static int initf_dm(void) 697 { 698 #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) 699 int ret; 700 701 ret = dm_init_and_scan(true); 702 if (ret) 703 return ret; 704 #endif 705 #ifdef CONFIG_TIMER_EARLY 706 ret = dm_timer_init(); 707 if (ret) 708 return ret; 709 #endif 710 711 return 0; 712 } 713 714 /* Architecture-specific memory reservation */ 715 __weak int reserve_arch(void) 716 { 717 return 0; 718 } 719 720 __weak int arch_cpu_init_dm(void) 721 { 722 return 0; 723 } 724 725 static const init_fnc_t init_sequence_f[] = { 726 setup_mon_len, 727 #ifdef CONFIG_OF_CONTROL 728 fdtdec_setup, 729 #endif 730 #ifdef CONFIG_TRACE 731 trace_early_init, 732 #endif 733 initf_malloc, 734 initf_console_record, 735 #if defined(CONFIG_HAVE_FSP) 736 arch_fsp_init, 737 #endif 738 arch_cpu_init, /* basic arch cpu dependent setup */ 739 mach_cpu_init, /* SoC/machine dependent CPU setup */ 740 initf_dm, 741 arch_cpu_init_dm, 742 mark_bootstage, /* need timer, go after init dm */ 743 #if defined(CONFIG_BOARD_EARLY_INIT_F) 744 board_early_init_f, 745 #endif 746 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 747 /* get CPU and bus clocks according to the environment variable */ 748 get_clocks, /* get CPU and bus clocks (etc.) */ 749 #endif 750 timer_init, /* initialize timer */ 751 #if defined(CONFIG_BOARD_POSTCLK_INIT) 752 board_postclk_init, 753 #endif 754 env_init, /* initialize environment */ 755 init_baud_rate, /* initialze baudrate settings */ 756 serial_init, /* serial communications setup */ 757 console_init_f, /* stage 1 init of console */ 758 display_options, /* say that we are here */ 759 display_text_info, /* show debugging info if required */ 760 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 761 defined(CONFIG_X86) 762 checkcpu, 763 #endif 764 #if defined(CONFIG_DISPLAY_CPUINFO) 765 print_cpuinfo, /* display cpu info (and speed) */ 766 #endif 767 #if defined(CONFIG_DISPLAY_BOARDINFO) 768 show_board_info, 769 #endif 770 INIT_FUNC_WATCHDOG_INIT 771 #if defined(CONFIG_MISC_INIT_F) 772 misc_init_f, 773 #endif 774 INIT_FUNC_WATCHDOG_RESET 775 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) 776 init_func_i2c, 777 #endif 778 #if defined(CONFIG_HARD_SPI) 779 init_func_spi, 780 #endif 781 announce_dram_init, 782 /* TODO: unify all these dram functions? */ 783 #if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \ 784 defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || \ 785 defined(CONFIG_SH) 786 dram_init, /* configure available RAM banks */ 787 #endif 788 #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) 789 init_func_ram, 790 #endif 791 #ifdef CONFIG_POST 792 post_init_f, 793 #endif 794 INIT_FUNC_WATCHDOG_RESET 795 #if defined(CONFIG_SYS_DRAM_TEST) 796 testdram, 797 #endif /* CONFIG_SYS_DRAM_TEST */ 798 INIT_FUNC_WATCHDOG_RESET 799 800 #ifdef CONFIG_POST 801 init_post, 802 #endif 803 INIT_FUNC_WATCHDOG_RESET 804 /* 805 * Now that we have DRAM mapped and working, we can 806 * relocate the code and continue running from DRAM. 807 * 808 * Reserve memory at end of RAM for (top down in that order): 809 * - area that won't get touched by U-Boot and Linux (optional) 810 * - kernel log buffer 811 * - protected RAM 812 * - LCD framebuffer 813 * - monitor code 814 * - board info struct 815 */ 816 setup_dest_addr, 817 #if defined(CONFIG_LOGBUFFER) 818 reserve_logbuffer, 819 #endif 820 #ifdef CONFIG_PRAM 821 reserve_pram, 822 #endif 823 reserve_round_4k, 824 #ifdef CONFIG_ARM 825 reserve_mmu, 826 #endif 827 reserve_video, 828 reserve_trace, 829 reserve_uboot, 830 reserve_malloc, 831 reserve_board, 832 setup_machine, 833 reserve_global_data, 834 reserve_fdt, 835 reserve_arch, 836 reserve_stacks, 837 dram_init_banksize, 838 show_dram_config, 839 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 840 defined(CONFIG_SH) 841 setup_board_part1, 842 #endif 843 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 844 INIT_FUNC_WATCHDOG_RESET 845 setup_board_part2, 846 #endif 847 display_new_sp, 848 #ifdef CONFIG_SYS_EXTBDINFO 849 setup_board_extra, 850 #endif 851 #ifdef CONFIG_OF_BOARD_FIXUP 852 fix_fdt, 853 #endif 854 INIT_FUNC_WATCHDOG_RESET 855 reloc_fdt, 856 setup_reloc, 857 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 858 copy_uboot_to_ram, 859 do_elf_reloc_fixups, 860 clear_bss, 861 #endif 862 #if defined(CONFIG_XTENSA) 863 clear_bss, 864 #endif 865 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 866 !CONFIG_IS_ENABLED(X86_64) 867 jump_to_copy, 868 #endif 869 NULL, 870 }; 871 872 void board_init_f(ulong boot_flags) 873 { 874 #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA 875 /* 876 * For some architectures, global data is initialized and used before 877 * calling this function. The data should be preserved. For others, 878 * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack 879 * here to host global data until relocation. 880 */ 881 gd_t data; 882 883 gd = &data; 884 885 /* 886 * Clear global data before it is accessed at debug print 887 * in initcall_run_list. Otherwise the debug print probably 888 * get the wrong value of gd->have_console. 889 */ 890 zero_global_data(); 891 #endif 892 893 gd->flags = boot_flags; 894 gd->have_console = 0; 895 896 if (initcall_run_list(init_sequence_f)) 897 hang(); 898 899 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 900 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 901 /* NOTREACHED - jump_to_copy() does not return */ 902 hang(); 903 #endif 904 } 905 906 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 907 /* 908 * For now this code is only used on x86. 909 * 910 * init_sequence_f_r is the list of init functions which are run when 911 * U-Boot is executing from Flash with a semi-limited 'C' environment. 912 * The following limitations must be considered when implementing an 913 * '_f_r' function: 914 * - 'static' variables are read-only 915 * - Global Data (gd->xxx) is read/write 916 * 917 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 918 * supported). It _should_, if possible, copy global data to RAM and 919 * initialise the CPU caches (to speed up the relocation process) 920 * 921 * NOTE: At present only x86 uses this route, but it is intended that 922 * all archs will move to this when generic relocation is implemented. 923 */ 924 static const init_fnc_t init_sequence_f_r[] = { 925 #if !CONFIG_IS_ENABLED(X86_64) 926 init_cache_f_r, 927 #endif 928 929 NULL, 930 }; 931 932 void board_init_f_r(void) 933 { 934 if (initcall_run_list(init_sequence_f_r)) 935 hang(); 936 937 /* 938 * The pre-relocation drivers may be using memory that has now gone 939 * away. Mark serial as unavailable - this will fall back to the debug 940 * UART if available. 941 */ 942 gd->flags &= ~GD_FLG_SERIAL_READY; 943 944 /* 945 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 946 * Transfer execution from Flash to RAM by calculating the address 947 * of the in-RAM copy of board_init_r() and calling it 948 */ 949 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 950 951 /* NOTREACHED - board_init_r() does not return */ 952 hang(); 953 } 954 #endif /* CONFIG_X86 */ 955