1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <malloc.h> 23 #include <mapmem.h> 24 #include <os.h> 25 #include <post.h> 26 #include <relocate.h> 27 #include <spi.h> 28 #include <status_led.h> 29 #include <timer.h> 30 #include <trace.h> 31 #include <video.h> 32 #include <watchdog.h> 33 #ifdef CONFIG_MACH_TYPE 34 #include <asm/mach-types.h> 35 #endif 36 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 37 #include <asm/mp.h> 38 #endif 39 #include <asm/io.h> 40 #include <asm/sections.h> 41 #include <dm/root.h> 42 #include <linux/errno.h> 43 #include <sysmem.h> 44 45 /* 46 * Pointer to initial global data area 47 * 48 * Here we initialize it if needed. 49 */ 50 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 51 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 52 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 53 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 54 #else 55 DECLARE_GLOBAL_DATA_PTR; 56 #endif 57 58 /* 59 * TODO(sjg@chromium.org): IMO this code should be 60 * refactored to a single function, something like: 61 * 62 * void led_set_state(enum led_colour_t colour, int on); 63 */ 64 /************************************************************************ 65 * Coloured LED functionality 66 ************************************************************************ 67 * May be supplied by boards if desired 68 */ 69 __weak void coloured_LED_init(void) {} 70 __weak void red_led_on(void) {} 71 __weak void red_led_off(void) {} 72 __weak void green_led_on(void) {} 73 __weak void green_led_off(void) {} 74 __weak void yellow_led_on(void) {} 75 __weak void yellow_led_off(void) {} 76 __weak void blue_led_on(void) {} 77 __weak void blue_led_off(void) {} 78 79 /* 80 * Why is gd allocated a register? Prior to reloc it might be better to 81 * just pass it around to each function in this file? 82 * 83 * After reloc one could argue that it is hardly used and doesn't need 84 * to be in a register. Or if it is it should perhaps hold pointers to all 85 * global data for all modules, so that post-reloc we can avoid the massive 86 * literal pool we get on ARM. Or perhaps just encourage each module to use 87 * a structure... 88 */ 89 90 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 91 static int init_func_watchdog_init(void) 92 { 93 # if defined(CONFIG_HW_WATCHDOG) && \ 94 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 95 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 96 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 97 defined(CONFIG_IMX_WATCHDOG)) 98 hw_watchdog_init(); 99 puts(" Watchdog enabled\n"); 100 # endif 101 WATCHDOG_RESET(); 102 103 return 0; 104 } 105 106 int init_func_watchdog_reset(void) 107 { 108 WATCHDOG_RESET(); 109 110 return 0; 111 } 112 #endif /* CONFIG_WATCHDOG */ 113 114 __weak void board_add_ram_info(int use_default) 115 { 116 /* please define platform specific board_add_ram_info() */ 117 } 118 119 static int init_baud_rate(void) 120 { 121 if (gd && gd->serial.using_pre_serial) 122 gd->baudrate = env_get_ulong("baudrate", 10, gd->serial.baudrate); 123 else 124 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 125 126 return 0; 127 } 128 129 static int display_text_info(void) 130 { 131 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 132 ulong bss_start, bss_end, text_base; 133 134 bss_start = (ulong)&__bss_start; 135 bss_end = (ulong)&__bss_end; 136 137 #ifdef CONFIG_SYS_TEXT_BASE 138 text_base = CONFIG_SYS_TEXT_BASE; 139 #else 140 text_base = CONFIG_SYS_MONITOR_BASE; 141 #endif 142 143 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 144 text_base, bss_start, bss_end); 145 #endif 146 147 return 0; 148 } 149 150 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) 151 static int announce_pre_serial(void) 152 { 153 if (gd && gd->serial.using_pre_serial) 154 printf("PreSerial: %d\n", gd->serial.id); 155 156 return 0; 157 } 158 #endif 159 160 static int announce_dram_init(void) 161 { 162 puts("DRAM: "); 163 return 0; 164 } 165 166 static int show_dram_config(void) 167 { 168 unsigned long long size; 169 170 #ifdef CONFIG_NR_DRAM_BANKS 171 int i; 172 173 debug("\nRAM Configuration:\n"); 174 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 175 size += gd->bd->bi_dram[i].size; 176 debug("Bank #%d: %llx ", i, 177 (unsigned long long)(gd->bd->bi_dram[i].start)); 178 #ifdef DEBUG 179 print_size(gd->bd->bi_dram[i].size, "\n"); 180 #endif 181 } 182 debug("\nDRAM: "); 183 #else 184 size = gd->ram_size; 185 #endif 186 187 print_size(size, ""); 188 board_add_ram_info(0); 189 putc('\n'); 190 191 return 0; 192 } 193 194 __weak int dram_init_banksize(void) 195 { 196 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 197 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 198 gd->bd->bi_dram[0].size = get_effective_memsize(); 199 #endif 200 201 return 0; 202 } 203 204 #if defined(CONFIG_SYS_I2C) 205 static int init_func_i2c(void) 206 { 207 puts("I2C: "); 208 #ifdef CONFIG_SYS_I2C 209 i2c_init_all(); 210 #else 211 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 212 #endif 213 puts("ready\n"); 214 return 0; 215 } 216 #endif 217 218 #if defined(CONFIG_HARD_SPI) 219 static int init_func_spi(void) 220 { 221 puts("SPI: "); 222 spi_init(); 223 puts("ready\n"); 224 return 0; 225 } 226 #endif 227 228 static int setup_mon_len(void) 229 { 230 #if defined(__ARM__) || defined(__MICROBLAZE__) 231 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 232 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 233 gd->mon_len = (ulong)&_end - (ulong)_init; 234 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 235 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 236 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) 237 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 238 #elif defined(CONFIG_SYS_MONITOR_BASE) 239 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 240 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 241 #endif 242 return 0; 243 } 244 245 __weak int arch_cpu_init(void) 246 { 247 return 0; 248 } 249 250 __weak int mach_cpu_init(void) 251 { 252 return 0; 253 } 254 255 /* Get the top of usable RAM */ 256 __weak ulong board_get_usable_ram_top(ulong total_size) 257 { 258 #ifdef CONFIG_SYS_SDRAM_BASE 259 /* 260 * Detect whether we have so much RAM that it goes past the end of our 261 * 32-bit address space. If so, clip the usable RAM so it doesn't. 262 */ 263 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 264 /* 265 * Will wrap back to top of 32-bit space when reservations 266 * are made. 267 */ 268 return 0; 269 #endif 270 return gd->ram_top; 271 } 272 273 static int setup_dest_addr(void) 274 { 275 debug("Monitor len: %08lX\n", gd->mon_len); 276 /* 277 * Ram is setup, size stored in gd !! 278 */ 279 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 280 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 281 /* 282 * Subtract specified amount of memory to hide so that it won't 283 * get "touched" at all by U-Boot. By fixing up gd->ram_size 284 * the Linux kernel should now get passed the now "corrected" 285 * memory size and won't touch it either. This should work 286 * for arch/ppc and arch/powerpc. Only Linux board ports in 287 * arch/powerpc with bootwrapper support, that recalculate the 288 * memory size from the SDRAM controller setup will have to 289 * get fixed. 290 */ 291 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 292 #endif 293 #ifdef CONFIG_SYS_SDRAM_BASE 294 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 295 #endif 296 gd->ram_top += get_effective_memsize(); 297 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 298 gd->relocaddr = gd->ram_top; 299 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 300 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 301 /* 302 * We need to make sure the location we intend to put secondary core 303 * boot code is reserved and not used by any part of u-boot 304 */ 305 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 306 gd->relocaddr = determine_mp_bootpg(NULL); 307 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 308 } 309 #endif 310 return 0; 311 } 312 313 #ifdef CONFIG_PRAM 314 /* reserve protected RAM */ 315 static int reserve_pram(void) 316 { 317 ulong reg; 318 319 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 320 gd->relocaddr -= (reg << 10); /* size is in kB */ 321 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 322 gd->relocaddr); 323 return 0; 324 } 325 #endif /* CONFIG_PRAM */ 326 327 /* Round memory pointer down to next 4 kB limit */ 328 static int reserve_round_4k(void) 329 { 330 gd->relocaddr &= ~(4096 - 1); 331 return 0; 332 } 333 334 #ifdef CONFIG_ARM 335 __weak int reserve_mmu(void) 336 { 337 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 338 /* reserve TLB table */ 339 gd->arch.tlb_size = PGTABLE_SIZE; 340 gd->relocaddr -= gd->arch.tlb_size; 341 342 /* round down to next 64 kB limit */ 343 gd->relocaddr &= ~(0x10000 - 1); 344 345 gd->arch.tlb_addr = gd->relocaddr; 346 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 347 gd->arch.tlb_addr + gd->arch.tlb_size); 348 349 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 350 /* 351 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 352 * with location within secure ram. 353 */ 354 gd->arch.tlb_allocated = gd->arch.tlb_addr; 355 #endif 356 #endif 357 358 return 0; 359 } 360 #endif 361 362 static int reserve_video(void) 363 { 364 #ifdef CONFIG_DM_VIDEO 365 ulong addr; 366 int ret; 367 368 addr = gd->relocaddr; 369 ret = video_reserve(&addr); 370 if (ret) 371 return ret; 372 gd->relocaddr = addr; 373 #elif defined(CONFIG_LCD) 374 # ifdef CONFIG_FB_ADDR 375 gd->fb_base = CONFIG_FB_ADDR; 376 # else 377 /* reserve memory for LCD display (always full pages) */ 378 gd->relocaddr = lcd_setmem(gd->relocaddr); 379 gd->fb_base = gd->relocaddr; 380 # endif /* CONFIG_FB_ADDR */ 381 #elif defined(CONFIG_VIDEO) && \ 382 (!defined(CONFIG_PPC)) && \ 383 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 384 !defined(CONFIG_M68K) 385 /* reserve memory for video display (always full pages) */ 386 gd->relocaddr = video_setmem(gd->relocaddr); 387 gd->fb_base = gd->relocaddr; 388 #endif 389 390 return 0; 391 } 392 393 static int reserve_trace(void) 394 { 395 #ifdef CONFIG_TRACE 396 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 397 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 398 debug("Reserving %dk for trace data at: %08lx\n", 399 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 400 #endif 401 402 return 0; 403 } 404 405 static int reserve_uboot(void) 406 { 407 /* 408 * reserve memory for U-Boot code, data & bss 409 * round down to next 4 kB limit 410 */ 411 gd->relocaddr -= gd->mon_len; 412 gd->relocaddr &= ~(4096 - 1); 413 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 414 /* round down to next 64 kB limit so that IVPR stays aligned */ 415 gd->relocaddr &= ~(65536 - 1); 416 #endif 417 418 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 419 gd->relocaddr); 420 421 gd->start_addr_sp = gd->relocaddr; 422 423 return 0; 424 } 425 426 /* reserve memory for malloc() area */ 427 static int reserve_malloc(void) 428 { 429 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 430 debug("Reserving %dk for malloc() at: %08lx\n", 431 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 432 return 0; 433 } 434 435 /* (permanently) allocate a Board Info struct */ 436 static int reserve_board(void) 437 { 438 if (!gd->bd) { 439 gd->start_addr_sp -= sizeof(bd_t); 440 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 441 memset(gd->bd, '\0', sizeof(bd_t)); 442 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 443 sizeof(bd_t), gd->start_addr_sp); 444 } 445 return 0; 446 } 447 448 static int setup_machine(void) 449 { 450 #ifdef CONFIG_MACH_TYPE 451 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 452 #endif 453 return 0; 454 } 455 456 static int reserve_global_data(void) 457 { 458 gd->start_addr_sp -= sizeof(gd_t); 459 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 460 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 461 sizeof(gd_t), gd->start_addr_sp); 462 return 0; 463 } 464 465 static int reserve_fdt(void) 466 { 467 #ifndef CONFIG_OF_EMBED 468 /* 469 * If the device tree is sitting immediately above our image then we 470 * must relocate it. If it is embedded in the data section, then it 471 * will be relocated with other data. 472 */ 473 if (gd->fdt_blob) { 474 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 475 476 gd->start_addr_sp -= gd->fdt_size; 477 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 478 debug("Reserving %lu Bytes for FDT at: %08lx\n", 479 gd->fdt_size, gd->start_addr_sp); 480 } 481 #endif 482 483 return 0; 484 } 485 486 static int reserve_bootstage(void) 487 { 488 #ifdef CONFIG_BOOTSTAGE 489 int size = bootstage_get_size(); 490 491 gd->start_addr_sp -= size; 492 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 493 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 494 gd->start_addr_sp); 495 #endif 496 497 return 0; 498 } 499 500 int arch_reserve_stacks(void) 501 { 502 return 0; 503 } 504 505 static int reserve_stacks(void) 506 { 507 /* make stack pointer 16-byte aligned */ 508 gd->start_addr_sp -= 16; 509 gd->start_addr_sp &= ~0xf; 510 511 /* 512 * let the architecture-specific code tailor gd->start_addr_sp and 513 * gd->irq_sp 514 */ 515 return arch_reserve_stacks(); 516 } 517 518 static int display_new_sp(void) 519 { 520 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 521 522 return 0; 523 } 524 525 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 526 defined(CONFIG_SH) 527 static int setup_board_part1(void) 528 { 529 bd_t *bd = gd->bd; 530 531 /* 532 * Save local variables to board info struct 533 */ 534 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 535 bd->bi_memsize = gd->ram_size; /* size in bytes */ 536 537 #ifdef CONFIG_SYS_SRAM_BASE 538 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 539 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 540 #endif 541 542 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 543 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 544 #endif 545 #if defined(CONFIG_M68K) 546 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 547 #endif 548 #if defined(CONFIG_MPC83xx) 549 bd->bi_immrbar = CONFIG_SYS_IMMR; 550 #endif 551 552 return 0; 553 } 554 #endif 555 556 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 557 static int setup_board_part2(void) 558 { 559 bd_t *bd = gd->bd; 560 561 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 562 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 563 #if defined(CONFIG_CPM2) 564 bd->bi_cpmfreq = gd->arch.cpm_clk; 565 bd->bi_brgfreq = gd->arch.brg_clk; 566 bd->bi_sccfreq = gd->arch.scc_clk; 567 bd->bi_vco = gd->arch.vco_out; 568 #endif /* CONFIG_CPM2 */ 569 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 570 bd->bi_pcifreq = gd->pci_clk; 571 #endif 572 #if defined(CONFIG_EXTRA_CLOCK) 573 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 574 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 575 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 576 #endif 577 578 return 0; 579 } 580 #endif 581 582 #ifdef CONFIG_POST 583 static int init_post(void) 584 { 585 post_bootmode_init(); 586 post_run(NULL, POST_ROM | post_bootmode_get(0)); 587 588 return 0; 589 } 590 #endif 591 592 static int reloc_fdt(void) 593 { 594 #ifndef CONFIG_OF_EMBED 595 if (gd->flags & GD_FLG_SKIP_RELOC) 596 return 0; 597 if (gd->new_fdt) { 598 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 599 gd->fdt_blob = gd->new_fdt; 600 } 601 #endif 602 603 return 0; 604 } 605 606 static int reloc_bootstage(void) 607 { 608 #ifdef CONFIG_BOOTSTAGE 609 if (gd->flags & GD_FLG_SKIP_RELOC) 610 return 0; 611 if (gd->new_bootstage) { 612 int size = bootstage_get_size(); 613 614 debug("Copying bootstage from %p to %p, size %x\n", 615 gd->bootstage, gd->new_bootstage, size); 616 memcpy(gd->new_bootstage, gd->bootstage, size); 617 gd->bootstage = gd->new_bootstage; 618 } 619 #endif 620 621 return 0; 622 } 623 624 static int setup_reloc(void) 625 { 626 if (gd->flags & GD_FLG_SKIP_RELOC) { 627 debug("Skipping relocation due to flag\n"); 628 return 0; 629 } 630 631 #ifndef CONFIG_SKIP_RELOCATE_UBOOT 632 #ifdef CONFIG_SYS_TEXT_BASE 633 #ifdef ARM 634 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 635 #elif defined(CONFIG_M68K) 636 /* 637 * On all ColdFire arch cpu, monitor code starts always 638 * just after the default vector table location, so at 0x400 639 */ 640 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 641 #else 642 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 643 #endif 644 #endif 645 646 #else 647 gd->reloc_off = 0; 648 #endif 649 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 650 651 printf("Relocation Offset is: %08lx\n", gd->reloc_off); 652 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 653 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 654 gd->start_addr_sp); 655 656 return 0; 657 } 658 659 #ifdef CONFIG_OF_BOARD_FIXUP 660 static int fix_fdt(void) 661 { 662 return board_fix_fdt((void *)gd->fdt_blob); 663 } 664 #endif 665 666 /* ARM calls relocate_code from its crt0.S */ 667 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 668 !CONFIG_IS_ENABLED(X86_64) 669 670 static int jump_to_copy(void) 671 { 672 if (gd->flags & GD_FLG_SKIP_RELOC) 673 return 0; 674 /* 675 * x86 is special, but in a nice way. It uses a trampoline which 676 * enables the dcache if possible. 677 * 678 * For now, other archs use relocate_code(), which is implemented 679 * similarly for all archs. When we do generic relocation, hopefully 680 * we can make all archs enable the dcache prior to relocation. 681 */ 682 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 683 /* 684 * SDRAM and console are now initialised. The final stack can now 685 * be setup in SDRAM. Code execution will continue in Flash, but 686 * with the stack in SDRAM and Global Data in temporary memory 687 * (CPU cache) 688 */ 689 arch_setup_gd(gd->new_gd); 690 board_init_f_r_trampoline(gd->start_addr_sp); 691 #else 692 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 693 #endif 694 695 return 0; 696 } 697 #endif 698 699 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 700 static int initf_bootstage(void) 701 { 702 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 703 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 704 int ret; 705 706 ret = bootstage_init(!from_spl); 707 if (ret) 708 return ret; 709 if (from_spl) { 710 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 711 CONFIG_BOOTSTAGE_STASH_SIZE); 712 713 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 714 if (ret && ret != -ENOENT) { 715 debug("Failed to unstash bootstage: err=%d\n", ret); 716 return ret; 717 } 718 } 719 720 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 721 722 return 0; 723 } 724 725 static int initf_console_record(void) 726 { 727 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 728 return console_record_init(); 729 #else 730 return 0; 731 #endif 732 } 733 734 static int initf_dm(void) 735 { 736 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 737 int ret; 738 739 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 740 ret = dm_init_and_scan(true); 741 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 742 if (ret) 743 return ret; 744 #endif 745 #ifdef CONFIG_TIMER_EARLY 746 ret = dm_timer_init(); 747 if (ret) 748 return ret; 749 #endif 750 751 return 0; 752 } 753 754 /* Architecture-specific memory reservation */ 755 __weak int reserve_arch(void) 756 { 757 return 0; 758 } 759 760 __weak int arch_cpu_init_dm(void) 761 { 762 return 0; 763 } 764 765 static const init_fnc_t init_sequence_f[] = { 766 setup_mon_len, 767 #ifdef CONFIG_OF_CONTROL 768 fdtdec_setup, 769 #endif 770 #ifdef CONFIG_TRACE 771 trace_early_init, 772 #endif 773 initf_malloc, 774 log_init, 775 initf_bootstage, /* uses its own timer, so does not need DM */ 776 initf_console_record, 777 #if defined(CONFIG_HAVE_FSP) 778 arch_fsp_init, 779 #endif 780 arch_cpu_init, /* basic arch cpu dependent setup */ 781 mach_cpu_init, /* SoC/machine dependent CPU setup */ 782 initf_dm, 783 arch_cpu_init_dm, 784 #if defined(CONFIG_BOARD_EARLY_INIT_F) 785 board_early_init_f, 786 #endif 787 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 788 /* get CPU and bus clocks according to the environment variable */ 789 get_clocks, /* get CPU and bus clocks (etc.) */ 790 #endif 791 #if !defined(CONFIG_M68K) 792 timer_init, /* initialize timer */ 793 #endif 794 #if defined(CONFIG_BOARD_POSTCLK_INIT) 795 board_postclk_init, 796 #endif 797 env_init, /* initialize environment */ 798 init_baud_rate, /* initialze baudrate settings */ 799 serial_init, /* serial communications setup */ 800 console_init_f, /* stage 1 init of console */ 801 display_options, /* say that we are here */ 802 display_text_info, /* show debugging info if required */ 803 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 804 defined(CONFIG_X86) 805 checkcpu, 806 #endif 807 #if defined(CONFIG_DISPLAY_CPUINFO) 808 print_cpuinfo, /* display cpu info (and speed) */ 809 #endif 810 #if defined(CONFIG_DTB_RESELECT) 811 embedded_dtb_select, 812 #endif 813 #if defined(CONFIG_DISPLAY_BOARDINFO) 814 show_board_info, 815 #endif 816 INIT_FUNC_WATCHDOG_INIT 817 #if defined(CONFIG_MISC_INIT_F) 818 misc_init_f, 819 #endif 820 INIT_FUNC_WATCHDOG_RESET 821 #if defined(CONFIG_SYS_I2C) 822 init_func_i2c, 823 #endif 824 #if defined(CONFIG_HARD_SPI) 825 init_func_spi, 826 #endif 827 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) 828 announce_pre_serial, 829 #endif 830 announce_dram_init, 831 dram_init, /* configure available RAM banks */ 832 #ifdef CONFIG_POST 833 post_init_f, 834 #endif 835 INIT_FUNC_WATCHDOG_RESET 836 #if defined(CONFIG_SYS_DRAM_TEST) 837 testdram, 838 #endif /* CONFIG_SYS_DRAM_TEST */ 839 INIT_FUNC_WATCHDOG_RESET 840 841 #ifdef CONFIG_POST 842 init_post, 843 #endif 844 INIT_FUNC_WATCHDOG_RESET 845 /* 846 * Now that we have DRAM mapped and working, we can 847 * relocate the code and continue running from DRAM. 848 * 849 * Reserve memory at end of RAM for (top down in that order): 850 * - area that won't get touched by U-Boot and Linux (optional) 851 * - kernel log buffer 852 * - protected RAM 853 * - LCD framebuffer 854 * - monitor code 855 * - board info struct 856 */ 857 setup_dest_addr, 858 #ifdef CONFIG_PRAM 859 reserve_pram, 860 #endif 861 reserve_round_4k, 862 #ifdef CONFIG_ARM 863 reserve_mmu, 864 #endif 865 reserve_video, 866 reserve_trace, 867 reserve_uboot, 868 reserve_malloc, 869 reserve_board, 870 setup_machine, 871 reserve_global_data, 872 reserve_fdt, 873 reserve_bootstage, 874 reserve_arch, 875 reserve_stacks, 876 dram_init_banksize, 877 show_dram_config, 878 #ifdef CONFIG_SYSMEM 879 sysmem_init, /* Validate above reserve memory */ 880 #endif 881 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 882 defined(CONFIG_SH) 883 setup_board_part1, 884 #endif 885 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 886 INIT_FUNC_WATCHDOG_RESET 887 setup_board_part2, 888 #endif 889 display_new_sp, 890 #ifdef CONFIG_OF_BOARD_FIXUP 891 fix_fdt, 892 #endif 893 INIT_FUNC_WATCHDOG_RESET 894 reloc_fdt, 895 reloc_bootstage, 896 setup_reloc, 897 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 898 copy_uboot_to_ram, 899 do_elf_reloc_fixups, 900 clear_bss, 901 #endif 902 #if defined(CONFIG_XTENSA) 903 clear_bss, 904 #endif 905 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 906 !CONFIG_IS_ENABLED(X86_64) 907 jump_to_copy, 908 #endif 909 NULL, 910 }; 911 912 void board_init_f(ulong boot_flags) 913 { 914 gd->flags = boot_flags; 915 gd->have_console = 0; 916 917 if (initcall_run_list(init_sequence_f)) 918 hang(); 919 920 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 921 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 922 /* NOTREACHED - jump_to_copy() does not return */ 923 hang(); 924 #endif 925 } 926 927 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 928 /* 929 * For now this code is only used on x86. 930 * 931 * init_sequence_f_r is the list of init functions which are run when 932 * U-Boot is executing from Flash with a semi-limited 'C' environment. 933 * The following limitations must be considered when implementing an 934 * '_f_r' function: 935 * - 'static' variables are read-only 936 * - Global Data (gd->xxx) is read/write 937 * 938 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 939 * supported). It _should_, if possible, copy global data to RAM and 940 * initialise the CPU caches (to speed up the relocation process) 941 * 942 * NOTE: At present only x86 uses this route, but it is intended that 943 * all archs will move to this when generic relocation is implemented. 944 */ 945 static const init_fnc_t init_sequence_f_r[] = { 946 #if !CONFIG_IS_ENABLED(X86_64) 947 init_cache_f_r, 948 #endif 949 950 NULL, 951 }; 952 953 void board_init_f_r(void) 954 { 955 if (initcall_run_list(init_sequence_f_r)) 956 hang(); 957 958 /* 959 * The pre-relocation drivers may be using memory that has now gone 960 * away. Mark serial as unavailable - this will fall back to the debug 961 * UART if available. 962 * 963 * Do the same with log drivers since the memory may not be available. 964 */ 965 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 966 #ifdef CONFIG_TIMER 967 gd->timer = NULL; 968 #endif 969 970 /* 971 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 972 * Transfer execution from Flash to RAM by calculating the address 973 * of the in-RAM copy of board_init_r() and calling it 974 */ 975 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 976 977 /* NOTREACHED - board_init_r() does not return */ 978 hang(); 979 } 980 #endif /* CONFIG_X86 */ 981