1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <malloc.h> 23 #include <mapmem.h> 24 #include <os.h> 25 #include <post.h> 26 #include <relocate.h> 27 #include <spi.h> 28 #include <status_led.h> 29 #include <timer.h> 30 #include <trace.h> 31 #include <video.h> 32 #include <watchdog.h> 33 #ifdef CONFIG_MACH_TYPE 34 #include <asm/mach-types.h> 35 #endif 36 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 37 #include <asm/mp.h> 38 #endif 39 #include <asm/io.h> 40 #include <asm/sections.h> 41 #include <dm/root.h> 42 #include <linux/errno.h> 43 44 /* 45 * Pointer to initial global data area 46 * 47 * Here we initialize it if needed. 48 */ 49 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 50 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 51 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 52 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 53 #else 54 DECLARE_GLOBAL_DATA_PTR; 55 #endif 56 57 /* 58 * TODO(sjg@chromium.org): IMO this code should be 59 * refactored to a single function, something like: 60 * 61 * void led_set_state(enum led_colour_t colour, int on); 62 */ 63 /************************************************************************ 64 * Coloured LED functionality 65 ************************************************************************ 66 * May be supplied by boards if desired 67 */ 68 __weak void coloured_LED_init(void) {} 69 __weak void red_led_on(void) {} 70 __weak void red_led_off(void) {} 71 __weak void green_led_on(void) {} 72 __weak void green_led_off(void) {} 73 __weak void yellow_led_on(void) {} 74 __weak void yellow_led_off(void) {} 75 __weak void blue_led_on(void) {} 76 __weak void blue_led_off(void) {} 77 78 /* 79 * Why is gd allocated a register? Prior to reloc it might be better to 80 * just pass it around to each function in this file? 81 * 82 * After reloc one could argue that it is hardly used and doesn't need 83 * to be in a register. Or if it is it should perhaps hold pointers to all 84 * global data for all modules, so that post-reloc we can avoid the massive 85 * literal pool we get on ARM. Or perhaps just encourage each module to use 86 * a structure... 87 */ 88 89 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 90 static int init_func_watchdog_init(void) 91 { 92 # if defined(CONFIG_HW_WATCHDOG) && \ 93 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 94 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 95 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 96 defined(CONFIG_IMX_WATCHDOG)) 97 hw_watchdog_init(); 98 puts(" Watchdog enabled\n"); 99 # endif 100 WATCHDOG_RESET(); 101 102 return 0; 103 } 104 105 int init_func_watchdog_reset(void) 106 { 107 WATCHDOG_RESET(); 108 109 return 0; 110 } 111 #endif /* CONFIG_WATCHDOG */ 112 113 __weak void board_add_ram_info(int use_default) 114 { 115 /* please define platform specific board_add_ram_info() */ 116 } 117 118 static int init_baud_rate(void) 119 { 120 if (gd && gd->serial.using_pre_serial) 121 gd->baudrate = env_get_ulong("baudrate", 10, gd->serial.baudrate); 122 else 123 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 124 125 return 0; 126 } 127 128 static int display_text_info(void) 129 { 130 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 131 ulong bss_start, bss_end, text_base; 132 133 bss_start = (ulong)&__bss_start; 134 bss_end = (ulong)&__bss_end; 135 136 #ifdef CONFIG_SYS_TEXT_BASE 137 text_base = CONFIG_SYS_TEXT_BASE; 138 #else 139 text_base = CONFIG_SYS_MONITOR_BASE; 140 #endif 141 142 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 143 text_base, bss_start, bss_end); 144 #endif 145 146 return 0; 147 } 148 149 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) 150 static int announce_pre_serial(void) 151 { 152 if (gd && gd->serial.using_pre_serial) 153 printf("PreSerial: %d\n", gd->serial.id); 154 155 return 0; 156 } 157 #endif 158 159 static int announce_dram_init(void) 160 { 161 puts("DRAM: "); 162 return 0; 163 } 164 165 static int show_dram_config(void) 166 { 167 unsigned long long size; 168 169 #ifdef CONFIG_NR_DRAM_BANKS 170 int i; 171 172 debug("\nRAM Configuration:\n"); 173 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 174 size += gd->bd->bi_dram[i].size; 175 debug("Bank #%d: %llx ", i, 176 (unsigned long long)(gd->bd->bi_dram[i].start)); 177 #ifdef DEBUG 178 print_size(gd->bd->bi_dram[i].size, "\n"); 179 #endif 180 } 181 debug("\nDRAM: "); 182 #else 183 size = gd->ram_size; 184 #endif 185 186 print_size(size, ""); 187 board_add_ram_info(0); 188 putc('\n'); 189 190 return 0; 191 } 192 193 __weak int dram_init_banksize(void) 194 { 195 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 196 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 197 gd->bd->bi_dram[0].size = get_effective_memsize(); 198 #endif 199 200 return 0; 201 } 202 203 #if defined(CONFIG_SYS_I2C) 204 static int init_func_i2c(void) 205 { 206 puts("I2C: "); 207 #ifdef CONFIG_SYS_I2C 208 i2c_init_all(); 209 #else 210 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 211 #endif 212 puts("ready\n"); 213 return 0; 214 } 215 #endif 216 217 #if defined(CONFIG_HARD_SPI) 218 static int init_func_spi(void) 219 { 220 puts("SPI: "); 221 spi_init(); 222 puts("ready\n"); 223 return 0; 224 } 225 #endif 226 227 static int setup_mon_len(void) 228 { 229 #if defined(__ARM__) || defined(__MICROBLAZE__) 230 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 231 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 232 gd->mon_len = (ulong)&_end - (ulong)_init; 233 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 234 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 235 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) 236 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 237 #elif defined(CONFIG_SYS_MONITOR_BASE) 238 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 239 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 240 #endif 241 return 0; 242 } 243 244 __weak int arch_cpu_init(void) 245 { 246 return 0; 247 } 248 249 __weak int mach_cpu_init(void) 250 { 251 return 0; 252 } 253 254 /* Get the top of usable RAM */ 255 __weak ulong board_get_usable_ram_top(ulong total_size) 256 { 257 #ifdef CONFIG_SYS_SDRAM_BASE 258 /* 259 * Detect whether we have so much RAM that it goes past the end of our 260 * 32-bit address space. If so, clip the usable RAM so it doesn't. 261 */ 262 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 263 /* 264 * Will wrap back to top of 32-bit space when reservations 265 * are made. 266 */ 267 return 0; 268 #endif 269 return gd->ram_top; 270 } 271 272 static int setup_dest_addr(void) 273 { 274 debug("Monitor len: %08lX\n", gd->mon_len); 275 /* 276 * Ram is setup, size stored in gd !! 277 */ 278 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 279 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 280 /* 281 * Subtract specified amount of memory to hide so that it won't 282 * get "touched" at all by U-Boot. By fixing up gd->ram_size 283 * the Linux kernel should now get passed the now "corrected" 284 * memory size and won't touch it either. This should work 285 * for arch/ppc and arch/powerpc. Only Linux board ports in 286 * arch/powerpc with bootwrapper support, that recalculate the 287 * memory size from the SDRAM controller setup will have to 288 * get fixed. 289 */ 290 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 291 #endif 292 #ifdef CONFIG_SYS_SDRAM_BASE 293 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 294 #endif 295 gd->ram_top += get_effective_memsize(); 296 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 297 gd->relocaddr = gd->ram_top; 298 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 299 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 300 /* 301 * We need to make sure the location we intend to put secondary core 302 * boot code is reserved and not used by any part of u-boot 303 */ 304 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 305 gd->relocaddr = determine_mp_bootpg(NULL); 306 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 307 } 308 #endif 309 return 0; 310 } 311 312 #ifdef CONFIG_PRAM 313 /* reserve protected RAM */ 314 static int reserve_pram(void) 315 { 316 ulong reg; 317 318 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 319 gd->relocaddr -= (reg << 10); /* size is in kB */ 320 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 321 gd->relocaddr); 322 return 0; 323 } 324 #endif /* CONFIG_PRAM */ 325 326 /* Round memory pointer down to next 4 kB limit */ 327 static int reserve_round_4k(void) 328 { 329 gd->relocaddr &= ~(4096 - 1); 330 return 0; 331 } 332 333 #ifdef CONFIG_ARM 334 __weak int reserve_mmu(void) 335 { 336 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 337 /* reserve TLB table */ 338 gd->arch.tlb_size = PGTABLE_SIZE; 339 gd->relocaddr -= gd->arch.tlb_size; 340 341 /* round down to next 64 kB limit */ 342 gd->relocaddr &= ~(0x10000 - 1); 343 344 gd->arch.tlb_addr = gd->relocaddr; 345 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 346 gd->arch.tlb_addr + gd->arch.tlb_size); 347 348 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 349 /* 350 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 351 * with location within secure ram. 352 */ 353 gd->arch.tlb_allocated = gd->arch.tlb_addr; 354 #endif 355 #endif 356 357 return 0; 358 } 359 #endif 360 361 static int reserve_video(void) 362 { 363 #ifdef CONFIG_DM_VIDEO 364 ulong addr; 365 int ret; 366 367 addr = gd->relocaddr; 368 ret = video_reserve(&addr); 369 if (ret) 370 return ret; 371 gd->relocaddr = addr; 372 #elif defined(CONFIG_LCD) 373 # ifdef CONFIG_FB_ADDR 374 gd->fb_base = CONFIG_FB_ADDR; 375 # else 376 /* reserve memory for LCD display (always full pages) */ 377 gd->relocaddr = lcd_setmem(gd->relocaddr); 378 gd->fb_base = gd->relocaddr; 379 # endif /* CONFIG_FB_ADDR */ 380 #elif defined(CONFIG_VIDEO) && \ 381 (!defined(CONFIG_PPC)) && \ 382 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 383 !defined(CONFIG_M68K) 384 /* reserve memory for video display (always full pages) */ 385 gd->relocaddr = video_setmem(gd->relocaddr); 386 gd->fb_base = gd->relocaddr; 387 #endif 388 389 return 0; 390 } 391 392 static int reserve_trace(void) 393 { 394 #ifdef CONFIG_TRACE 395 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 396 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 397 debug("Reserving %dk for trace data at: %08lx\n", 398 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 399 #endif 400 401 return 0; 402 } 403 404 static int reserve_uboot(void) 405 { 406 /* 407 * reserve memory for U-Boot code, data & bss 408 * round down to next 4 kB limit 409 */ 410 gd->relocaddr -= gd->mon_len; 411 gd->relocaddr &= ~(4096 - 1); 412 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 413 /* round down to next 64 kB limit so that IVPR stays aligned */ 414 gd->relocaddr &= ~(65536 - 1); 415 #endif 416 417 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 418 gd->relocaddr); 419 420 gd->start_addr_sp = gd->relocaddr; 421 422 return 0; 423 } 424 425 /* reserve memory for malloc() area */ 426 static int reserve_malloc(void) 427 { 428 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 429 debug("Reserving %dk for malloc() at: %08lx\n", 430 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 431 return 0; 432 } 433 434 /* (permanently) allocate a Board Info struct */ 435 static int reserve_board(void) 436 { 437 if (!gd->bd) { 438 gd->start_addr_sp -= sizeof(bd_t); 439 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 440 memset(gd->bd, '\0', sizeof(bd_t)); 441 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 442 sizeof(bd_t), gd->start_addr_sp); 443 } 444 return 0; 445 } 446 447 static int setup_machine(void) 448 { 449 #ifdef CONFIG_MACH_TYPE 450 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 451 #endif 452 return 0; 453 } 454 455 static int reserve_global_data(void) 456 { 457 gd->start_addr_sp -= sizeof(gd_t); 458 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 459 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 460 sizeof(gd_t), gd->start_addr_sp); 461 return 0; 462 } 463 464 static int reserve_fdt(void) 465 { 466 #ifndef CONFIG_OF_EMBED 467 /* 468 * If the device tree is sitting immediately above our image then we 469 * must relocate it. If it is embedded in the data section, then it 470 * will be relocated with other data. 471 */ 472 if (gd->fdt_blob) { 473 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 474 475 gd->start_addr_sp -= gd->fdt_size; 476 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 477 debug("Reserving %lu Bytes for FDT at: %08lx\n", 478 gd->fdt_size, gd->start_addr_sp); 479 } 480 #endif 481 482 return 0; 483 } 484 485 static int reserve_bootstage(void) 486 { 487 #ifdef CONFIG_BOOTSTAGE 488 int size = bootstage_get_size(); 489 490 gd->start_addr_sp -= size; 491 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 492 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 493 gd->start_addr_sp); 494 #endif 495 496 return 0; 497 } 498 499 int arch_reserve_stacks(void) 500 { 501 return 0; 502 } 503 504 static int reserve_stacks(void) 505 { 506 /* make stack pointer 16-byte aligned */ 507 gd->start_addr_sp -= 16; 508 gd->start_addr_sp &= ~0xf; 509 510 /* 511 * let the architecture-specific code tailor gd->start_addr_sp and 512 * gd->irq_sp 513 */ 514 return arch_reserve_stacks(); 515 } 516 517 static int display_new_sp(void) 518 { 519 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 520 521 return 0; 522 } 523 524 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 525 defined(CONFIG_SH) 526 static int setup_board_part1(void) 527 { 528 bd_t *bd = gd->bd; 529 530 /* 531 * Save local variables to board info struct 532 */ 533 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 534 bd->bi_memsize = gd->ram_size; /* size in bytes */ 535 536 #ifdef CONFIG_SYS_SRAM_BASE 537 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 538 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 539 #endif 540 541 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 542 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 543 #endif 544 #if defined(CONFIG_M68K) 545 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 546 #endif 547 #if defined(CONFIG_MPC83xx) 548 bd->bi_immrbar = CONFIG_SYS_IMMR; 549 #endif 550 551 return 0; 552 } 553 #endif 554 555 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 556 static int setup_board_part2(void) 557 { 558 bd_t *bd = gd->bd; 559 560 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 561 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 562 #if defined(CONFIG_CPM2) 563 bd->bi_cpmfreq = gd->arch.cpm_clk; 564 bd->bi_brgfreq = gd->arch.brg_clk; 565 bd->bi_sccfreq = gd->arch.scc_clk; 566 bd->bi_vco = gd->arch.vco_out; 567 #endif /* CONFIG_CPM2 */ 568 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 569 bd->bi_pcifreq = gd->pci_clk; 570 #endif 571 #if defined(CONFIG_EXTRA_CLOCK) 572 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 573 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 574 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 575 #endif 576 577 return 0; 578 } 579 #endif 580 581 #ifdef CONFIG_POST 582 static int init_post(void) 583 { 584 post_bootmode_init(); 585 post_run(NULL, POST_ROM | post_bootmode_get(0)); 586 587 return 0; 588 } 589 #endif 590 591 static int reloc_fdt(void) 592 { 593 #ifndef CONFIG_OF_EMBED 594 if (gd->flags & GD_FLG_SKIP_RELOC) 595 return 0; 596 if (gd->new_fdt) { 597 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 598 gd->fdt_blob = gd->new_fdt; 599 } 600 #endif 601 602 return 0; 603 } 604 605 static int reloc_bootstage(void) 606 { 607 #ifdef CONFIG_BOOTSTAGE 608 if (gd->flags & GD_FLG_SKIP_RELOC) 609 return 0; 610 if (gd->new_bootstage) { 611 int size = bootstage_get_size(); 612 613 debug("Copying bootstage from %p to %p, size %x\n", 614 gd->bootstage, gd->new_bootstage, size); 615 memcpy(gd->new_bootstage, gd->bootstage, size); 616 gd->bootstage = gd->new_bootstage; 617 } 618 #endif 619 620 return 0; 621 } 622 623 static int setup_reloc(void) 624 { 625 if (gd->flags & GD_FLG_SKIP_RELOC) { 626 debug("Skipping relocation due to flag\n"); 627 return 0; 628 } 629 630 #ifdef CONFIG_SYS_TEXT_BASE 631 #ifdef ARM 632 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 633 #elif defined(CONFIG_M68K) 634 /* 635 * On all ColdFire arch cpu, monitor code starts always 636 * just after the default vector table location, so at 0x400 637 */ 638 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 639 #else 640 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 641 #endif 642 #endif 643 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 644 645 printf("Relocation Offset is: %08lx\n", gd->reloc_off); 646 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 647 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 648 gd->start_addr_sp); 649 650 return 0; 651 } 652 653 #ifdef CONFIG_OF_BOARD_FIXUP 654 static int fix_fdt(void) 655 { 656 return board_fix_fdt((void *)gd->fdt_blob); 657 } 658 #endif 659 660 /* ARM calls relocate_code from its crt0.S */ 661 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 662 !CONFIG_IS_ENABLED(X86_64) 663 664 static int jump_to_copy(void) 665 { 666 if (gd->flags & GD_FLG_SKIP_RELOC) 667 return 0; 668 /* 669 * x86 is special, but in a nice way. It uses a trampoline which 670 * enables the dcache if possible. 671 * 672 * For now, other archs use relocate_code(), which is implemented 673 * similarly for all archs. When we do generic relocation, hopefully 674 * we can make all archs enable the dcache prior to relocation. 675 */ 676 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 677 /* 678 * SDRAM and console are now initialised. The final stack can now 679 * be setup in SDRAM. Code execution will continue in Flash, but 680 * with the stack in SDRAM and Global Data in temporary memory 681 * (CPU cache) 682 */ 683 arch_setup_gd(gd->new_gd); 684 board_init_f_r_trampoline(gd->start_addr_sp); 685 #else 686 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 687 #endif 688 689 return 0; 690 } 691 #endif 692 693 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 694 static int initf_bootstage(void) 695 { 696 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 697 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 698 int ret; 699 700 ret = bootstage_init(!from_spl); 701 if (ret) 702 return ret; 703 if (from_spl) { 704 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 705 CONFIG_BOOTSTAGE_STASH_SIZE); 706 707 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 708 if (ret && ret != -ENOENT) { 709 debug("Failed to unstash bootstage: err=%d\n", ret); 710 return ret; 711 } 712 } 713 714 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 715 716 return 0; 717 } 718 719 static int initf_console_record(void) 720 { 721 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 722 return console_record_init(); 723 #else 724 return 0; 725 #endif 726 } 727 728 static int initf_dm(void) 729 { 730 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 731 int ret; 732 733 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 734 ret = dm_init_and_scan(true); 735 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 736 if (ret) 737 return ret; 738 #endif 739 #ifdef CONFIG_TIMER_EARLY 740 ret = dm_timer_init(); 741 if (ret) 742 return ret; 743 #endif 744 745 return 0; 746 } 747 748 /* Architecture-specific memory reservation */ 749 __weak int reserve_arch(void) 750 { 751 return 0; 752 } 753 754 __weak int arch_cpu_init_dm(void) 755 { 756 return 0; 757 } 758 759 static const init_fnc_t init_sequence_f[] = { 760 setup_mon_len, 761 #ifdef CONFIG_OF_CONTROL 762 fdtdec_setup, 763 #endif 764 #ifdef CONFIG_TRACE 765 trace_early_init, 766 #endif 767 initf_malloc, 768 log_init, 769 initf_bootstage, /* uses its own timer, so does not need DM */ 770 initf_console_record, 771 #if defined(CONFIG_HAVE_FSP) 772 arch_fsp_init, 773 #endif 774 arch_cpu_init, /* basic arch cpu dependent setup */ 775 mach_cpu_init, /* SoC/machine dependent CPU setup */ 776 initf_dm, 777 arch_cpu_init_dm, 778 #if defined(CONFIG_BOARD_EARLY_INIT_F) 779 board_early_init_f, 780 #endif 781 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 782 /* get CPU and bus clocks according to the environment variable */ 783 get_clocks, /* get CPU and bus clocks (etc.) */ 784 #endif 785 #if !defined(CONFIG_M68K) 786 timer_init, /* initialize timer */ 787 #endif 788 #if defined(CONFIG_BOARD_POSTCLK_INIT) 789 board_postclk_init, 790 #endif 791 env_init, /* initialize environment */ 792 init_baud_rate, /* initialze baudrate settings */ 793 serial_init, /* serial communications setup */ 794 console_init_f, /* stage 1 init of console */ 795 display_options, /* say that we are here */ 796 display_text_info, /* show debugging info if required */ 797 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 798 defined(CONFIG_X86) 799 checkcpu, 800 #endif 801 #if defined(CONFIG_DISPLAY_CPUINFO) 802 print_cpuinfo, /* display cpu info (and speed) */ 803 #endif 804 #if defined(CONFIG_DTB_RESELECT) 805 embedded_dtb_select, 806 #endif 807 #if defined(CONFIG_DISPLAY_BOARDINFO) 808 show_board_info, 809 #endif 810 INIT_FUNC_WATCHDOG_INIT 811 #if defined(CONFIG_MISC_INIT_F) 812 misc_init_f, 813 #endif 814 INIT_FUNC_WATCHDOG_RESET 815 #if defined(CONFIG_SYS_I2C) 816 init_func_i2c, 817 #endif 818 #if defined(CONFIG_HARD_SPI) 819 init_func_spi, 820 #endif 821 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) 822 announce_pre_serial, 823 #endif 824 announce_dram_init, 825 dram_init, /* configure available RAM banks */ 826 #ifdef CONFIG_POST 827 post_init_f, 828 #endif 829 INIT_FUNC_WATCHDOG_RESET 830 #if defined(CONFIG_SYS_DRAM_TEST) 831 testdram, 832 #endif /* CONFIG_SYS_DRAM_TEST */ 833 INIT_FUNC_WATCHDOG_RESET 834 835 #ifdef CONFIG_POST 836 init_post, 837 #endif 838 INIT_FUNC_WATCHDOG_RESET 839 /* 840 * Now that we have DRAM mapped and working, we can 841 * relocate the code and continue running from DRAM. 842 * 843 * Reserve memory at end of RAM for (top down in that order): 844 * - area that won't get touched by U-Boot and Linux (optional) 845 * - kernel log buffer 846 * - protected RAM 847 * - LCD framebuffer 848 * - monitor code 849 * - board info struct 850 */ 851 setup_dest_addr, 852 #ifdef CONFIG_PRAM 853 reserve_pram, 854 #endif 855 reserve_round_4k, 856 #ifdef CONFIG_ARM 857 reserve_mmu, 858 #endif 859 reserve_video, 860 reserve_trace, 861 reserve_uboot, 862 reserve_malloc, 863 reserve_board, 864 setup_machine, 865 reserve_global_data, 866 reserve_fdt, 867 reserve_bootstage, 868 reserve_arch, 869 reserve_stacks, 870 dram_init_banksize, 871 show_dram_config, 872 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 873 defined(CONFIG_SH) 874 setup_board_part1, 875 #endif 876 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 877 INIT_FUNC_WATCHDOG_RESET 878 setup_board_part2, 879 #endif 880 display_new_sp, 881 #ifdef CONFIG_OF_BOARD_FIXUP 882 fix_fdt, 883 #endif 884 INIT_FUNC_WATCHDOG_RESET 885 reloc_fdt, 886 reloc_bootstage, 887 setup_reloc, 888 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 889 copy_uboot_to_ram, 890 do_elf_reloc_fixups, 891 clear_bss, 892 #endif 893 #if defined(CONFIG_XTENSA) 894 clear_bss, 895 #endif 896 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 897 !CONFIG_IS_ENABLED(X86_64) 898 jump_to_copy, 899 #endif 900 NULL, 901 }; 902 903 void board_init_f(ulong boot_flags) 904 { 905 gd->flags = boot_flags; 906 gd->have_console = 0; 907 908 if (initcall_run_list(init_sequence_f)) 909 hang(); 910 911 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 912 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 913 /* NOTREACHED - jump_to_copy() does not return */ 914 hang(); 915 #endif 916 } 917 918 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 919 /* 920 * For now this code is only used on x86. 921 * 922 * init_sequence_f_r is the list of init functions which are run when 923 * U-Boot is executing from Flash with a semi-limited 'C' environment. 924 * The following limitations must be considered when implementing an 925 * '_f_r' function: 926 * - 'static' variables are read-only 927 * - Global Data (gd->xxx) is read/write 928 * 929 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 930 * supported). It _should_, if possible, copy global data to RAM and 931 * initialise the CPU caches (to speed up the relocation process) 932 * 933 * NOTE: At present only x86 uses this route, but it is intended that 934 * all archs will move to this when generic relocation is implemented. 935 */ 936 static const init_fnc_t init_sequence_f_r[] = { 937 #if !CONFIG_IS_ENABLED(X86_64) 938 init_cache_f_r, 939 #endif 940 941 NULL, 942 }; 943 944 void board_init_f_r(void) 945 { 946 if (initcall_run_list(init_sequence_f_r)) 947 hang(); 948 949 /* 950 * The pre-relocation drivers may be using memory that has now gone 951 * away. Mark serial as unavailable - this will fall back to the debug 952 * UART if available. 953 * 954 * Do the same with log drivers since the memory may not be available. 955 */ 956 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 957 #ifdef CONFIG_TIMER 958 gd->timer = NULL; 959 #endif 960 961 /* 962 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 963 * Transfer execution from Flash to RAM by calculating the address 964 * of the in-RAM copy of board_init_r() and calling it 965 */ 966 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 967 968 /* NOTREACHED - board_init_r() does not return */ 969 hang(); 970 } 971 #endif /* CONFIG_X86 */ 972