1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <malloc.h> 23 #include <mapmem.h> 24 #include <os.h> 25 #include <post.h> 26 #include <relocate.h> 27 #include <spi.h> 28 #include <status_led.h> 29 #include <timer.h> 30 #include <trace.h> 31 #include <video.h> 32 #include <watchdog.h> 33 #ifdef CONFIG_MACH_TYPE 34 #include <asm/mach-types.h> 35 #endif 36 #if defined(CONFIG_MP) && defined(CONFIG_PPC) 37 #include <asm/mp.h> 38 #endif 39 #include <asm/io.h> 40 #include <asm/sections.h> 41 #include <dm/root.h> 42 #include <linux/errno.h> 43 #include <bidram.h> 44 #include <sysmem.h> 45 46 /* 47 * Pointer to initial global data area 48 * 49 * Here we initialize it if needed. 50 */ 51 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 52 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 53 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 54 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 55 #else 56 DECLARE_GLOBAL_DATA_PTR; 57 #endif 58 59 /* 60 * TODO(sjg@chromium.org): IMO this code should be 61 * refactored to a single function, something like: 62 * 63 * void led_set_state(enum led_colour_t colour, int on); 64 */ 65 /************************************************************************ 66 * Coloured LED functionality 67 ************************************************************************ 68 * May be supplied by boards if desired 69 */ 70 __weak void coloured_LED_init(void) {} 71 __weak void red_led_on(void) {} 72 __weak void red_led_off(void) {} 73 __weak void green_led_on(void) {} 74 __weak void green_led_off(void) {} 75 __weak void yellow_led_on(void) {} 76 __weak void yellow_led_off(void) {} 77 __weak void blue_led_on(void) {} 78 __weak void blue_led_off(void) {} 79 80 /* 81 * Why is gd allocated a register? Prior to reloc it might be better to 82 * just pass it around to each function in this file? 83 * 84 * After reloc one could argue that it is hardly used and doesn't need 85 * to be in a register. Or if it is it should perhaps hold pointers to all 86 * global data for all modules, so that post-reloc we can avoid the massive 87 * literal pool we get on ARM. Or perhaps just encourage each module to use 88 * a structure... 89 */ 90 91 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 92 static int init_func_watchdog_init(void) 93 { 94 # if defined(CONFIG_HW_WATCHDOG) && \ 95 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 96 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 97 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 98 defined(CONFIG_IMX_WATCHDOG)) 99 hw_watchdog_init(); 100 puts(" Watchdog enabled\n"); 101 # endif 102 WATCHDOG_RESET(); 103 104 return 0; 105 } 106 107 int init_func_watchdog_reset(void) 108 { 109 WATCHDOG_RESET(); 110 111 return 0; 112 } 113 #endif /* CONFIG_WATCHDOG */ 114 115 __weak void board_add_ram_info(int use_default) 116 { 117 /* please define platform specific board_add_ram_info() */ 118 } 119 120 static int init_baud_rate(void) 121 { 122 if (gd && gd->serial.using_pre_serial) 123 gd->baudrate = env_get_ulong("baudrate", 10, gd->serial.baudrate); 124 else 125 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE); 126 127 return 0; 128 } 129 130 static int display_text_info(void) 131 { 132 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 133 ulong bss_start, bss_end, text_base; 134 135 bss_start = (ulong)&__bss_start; 136 bss_end = (ulong)&__bss_end; 137 138 #ifdef CONFIG_SYS_TEXT_BASE 139 text_base = CONFIG_SYS_TEXT_BASE; 140 #else 141 text_base = CONFIG_SYS_MONITOR_BASE; 142 #endif 143 144 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 145 text_base, bss_start, bss_end); 146 #endif 147 148 return 0; 149 } 150 151 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) 152 static int announce_pre_serial(void) 153 { 154 if (gd && gd->serial.using_pre_serial) 155 printf("PreSerial: %d\n", gd->serial.id); 156 157 return 0; 158 } 159 #endif 160 161 static int announce_dram_init(void) 162 { 163 #ifndef CONFIG_SUPPORT_USBPLUG 164 puts("DRAM: "); 165 #endif 166 return 0; 167 } 168 169 static int show_dram_config(void) 170 { 171 unsigned long long size; 172 173 #ifdef CONFIG_NR_DRAM_BANKS 174 int i; 175 176 debug("\nRAM Configuration:\n"); 177 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 178 size += gd->bd->bi_dram[i].size; 179 debug("Bank #%d: %llx ", i, 180 (unsigned long long)(gd->bd->bi_dram[i].start)); 181 #ifdef DEBUG 182 print_size(gd->bd->bi_dram[i].size, "\n"); 183 #endif 184 } 185 debug("\nDRAM: "); 186 #else 187 size = gd->ram_size; 188 #endif 189 190 #ifdef CONFIG_BIDRAM 191 size += bidram_append_size(); 192 #endif 193 194 #ifndef CONFIG_SUPPORT_USBPLUG 195 print_size(size, ""); 196 board_add_ram_info(0); 197 putc('\n'); 198 #endif 199 return 0; 200 } 201 202 __weak int dram_init_banksize(void) 203 { 204 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 205 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 206 gd->bd->bi_dram[0].size = get_effective_memsize(); 207 #endif 208 209 return 0; 210 } 211 212 #if defined(CONFIG_SYS_I2C) 213 static int init_func_i2c(void) 214 { 215 puts("I2C: "); 216 #ifdef CONFIG_SYS_I2C 217 i2c_init_all(); 218 #else 219 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 220 #endif 221 puts("ready\n"); 222 return 0; 223 } 224 #endif 225 226 #if defined(CONFIG_HARD_SPI) 227 static int init_func_spi(void) 228 { 229 puts("SPI: "); 230 spi_init(); 231 puts("ready\n"); 232 return 0; 233 } 234 #endif 235 236 static int setup_mon_len(void) 237 { 238 #if defined(__ARM__) || defined(__MICROBLAZE__) 239 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 240 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 241 gd->mon_len = (ulong)&_end - (ulong)_init; 242 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 243 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 244 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV) 245 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 246 #elif defined(CONFIG_SYS_MONITOR_BASE) 247 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 248 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 249 #endif 250 return 0; 251 } 252 253 __weak int arch_fpga_init(void) 254 { 255 return 0; 256 } 257 258 __weak int arch_cpu_init(void) 259 { 260 return 0; 261 } 262 263 __weak int mach_cpu_init(void) 264 { 265 return 0; 266 } 267 268 /* Get the top of usable RAM */ 269 __weak ulong board_get_usable_ram_top(ulong total_size) 270 { 271 #ifdef CONFIG_SYS_SDRAM_BASE 272 /* 273 * Detect whether we have so much RAM that it goes past the end of our 274 * 32-bit address space. If so, clip the usable RAM so it doesn't. 275 */ 276 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 277 /* 278 * Will wrap back to top of 32-bit space when reservations 279 * are made. 280 */ 281 return 0; 282 #endif 283 return gd->ram_top; 284 } 285 286 static int setup_dest_addr(void) 287 { 288 debug("Monitor len: %08lX\n", gd->mon_len); 289 /* 290 * Ram is setup, size stored in gd !! 291 */ 292 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 293 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 294 /* 295 * Subtract specified amount of memory to hide so that it won't 296 * get "touched" at all by U-Boot. By fixing up gd->ram_size 297 * the Linux kernel should now get passed the now "corrected" 298 * memory size and won't touch it either. This should work 299 * for arch/ppc and arch/powerpc. Only Linux board ports in 300 * arch/powerpc with bootwrapper support, that recalculate the 301 * memory size from the SDRAM controller setup will have to 302 * get fixed. 303 */ 304 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 305 #endif 306 #ifdef CONFIG_SYS_SDRAM_BASE 307 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 308 #endif 309 gd->ram_top += get_effective_memsize(); 310 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 311 gd->relocaddr = gd->ram_top; 312 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 313 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 314 /* 315 * We need to make sure the location we intend to put secondary core 316 * boot code is reserved and not used by any part of u-boot 317 */ 318 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 319 gd->relocaddr = determine_mp_bootpg(NULL); 320 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 321 } 322 #endif 323 return 0; 324 } 325 326 #ifdef CONFIG_PRAM 327 /* reserve protected RAM */ 328 static int reserve_pram(void) 329 { 330 ulong reg; 331 332 reg = env_get_ulong("pram", 10, CONFIG_PRAM); 333 gd->relocaddr -= (reg << 10); /* size is in kB */ 334 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 335 gd->relocaddr); 336 return 0; 337 } 338 #endif /* CONFIG_PRAM */ 339 340 /* Round memory pointer down to next 4 kB limit */ 341 static int reserve_round_4k(void) 342 { 343 gd->relocaddr &= ~(4096 - 1); 344 return 0; 345 } 346 347 #ifdef CONFIG_ARM 348 __weak int reserve_mmu(void) 349 { 350 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 351 /* reserve TLB table */ 352 gd->arch.tlb_size = PGTABLE_SIZE; 353 gd->relocaddr -= gd->arch.tlb_size; 354 355 /* round down to next 64 kB limit */ 356 gd->relocaddr &= ~(0x10000 - 1); 357 358 gd->arch.tlb_addr = gd->relocaddr; 359 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 360 gd->arch.tlb_addr + gd->arch.tlb_size); 361 362 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 363 /* 364 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 365 * with location within secure ram. 366 */ 367 gd->arch.tlb_allocated = gd->arch.tlb_addr; 368 #endif 369 #endif 370 371 return 0; 372 } 373 #endif 374 375 static int reserve_video(void) 376 { 377 #ifdef CONFIG_DM_VIDEO 378 ulong addr; 379 int ret; 380 381 addr = gd->relocaddr; 382 ret = video_reserve(&addr); 383 if (ret) 384 return ret; 385 gd->relocaddr = addr; 386 #elif defined(CONFIG_LCD) 387 # ifdef CONFIG_FB_ADDR 388 gd->fb_base = CONFIG_FB_ADDR; 389 # else 390 /* reserve memory for LCD display (always full pages) */ 391 gd->relocaddr = lcd_setmem(gd->relocaddr); 392 gd->fb_base = gd->relocaddr; 393 # endif /* CONFIG_FB_ADDR */ 394 #elif defined(CONFIG_VIDEO) && \ 395 (!defined(CONFIG_PPC)) && \ 396 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 397 !defined(CONFIG_M68K) 398 /* reserve memory for video display (always full pages) */ 399 gd->relocaddr = video_setmem(gd->relocaddr); 400 gd->fb_base = gd->relocaddr; 401 #endif 402 403 return 0; 404 } 405 406 static int reserve_trace(void) 407 { 408 #ifdef CONFIG_TRACE 409 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 410 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 411 debug("Reserving %dk for trace data at: %08lx\n", 412 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 413 #endif 414 415 return 0; 416 } 417 418 static int reserve_uboot(void) 419 { 420 /* 421 * reserve memory for U-Boot code, data & bss 422 * round down to next 4 kB limit 423 */ 424 gd->relocaddr -= gd->mon_len; 425 gd->relocaddr &= ~(4096 - 1); 426 #if defined(CONFIG_E500) || defined(CONFIG_MIPS) 427 /* round down to next 64 kB limit so that IVPR stays aligned */ 428 gd->relocaddr &= ~(65536 - 1); 429 #endif 430 431 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 432 gd->relocaddr); 433 434 gd->start_addr_sp = gd->relocaddr; 435 436 return 0; 437 } 438 439 /* reserve memory for malloc() area */ 440 static int reserve_malloc(void) 441 { 442 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 443 debug("Reserving %dk for malloc() at: %08lx\n", 444 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 445 return 0; 446 } 447 448 #ifdef CONFIG_SYS_NONCACHED_MEMORY 449 static int reserve_noncached(void) 450 { 451 phys_addr_t start, end; 452 size_t size; 453 454 end = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) - MMU_SECTION_SIZE; 455 size = ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE); 456 start = end - size; 457 gd->start_addr_sp = start; 458 debug("Reserving %zu for noncached_alloc() at: %08lx\n", 459 size, gd->start_addr_sp); 460 461 return 0; 462 } 463 #endif 464 465 /* (permanently) allocate a Board Info struct */ 466 static int reserve_board(void) 467 { 468 if (!gd->bd) { 469 gd->start_addr_sp -= sizeof(bd_t); 470 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 471 memset(gd->bd, '\0', sizeof(bd_t)); 472 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 473 sizeof(bd_t), gd->start_addr_sp); 474 } 475 return 0; 476 } 477 478 static int setup_machine(void) 479 { 480 #ifdef CONFIG_MACH_TYPE 481 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 482 #endif 483 return 0; 484 } 485 486 static int reserve_global_data(void) 487 { 488 gd->start_addr_sp -= sizeof(gd_t); 489 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 490 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 491 sizeof(gd_t), gd->start_addr_sp); 492 return 0; 493 } 494 495 static int reserve_fdt(void) 496 { 497 #ifndef CONFIG_OF_EMBED 498 /* 499 * If the device tree is sitting immediately above our image then we 500 * must relocate it. If it is embedded in the data section, then it 501 * will be relocated with other data. 502 */ 503 if (gd->fdt_blob) { 504 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 505 506 gd->start_addr_sp -= gd->fdt_size; 507 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 508 debug("Reserving %lu Bytes for FDT at: %08lx\n", 509 gd->fdt_size, gd->start_addr_sp); 510 } 511 #endif 512 513 return 0; 514 } 515 516 static int reserve_bootstage(void) 517 { 518 #ifdef CONFIG_BOOTSTAGE 519 int size = bootstage_get_size(); 520 521 gd->start_addr_sp -= size; 522 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size); 523 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size, 524 gd->start_addr_sp); 525 #endif 526 527 return 0; 528 } 529 530 int arch_reserve_stacks(void) 531 { 532 return 0; 533 } 534 535 static int reserve_stacks(void) 536 { 537 /* make stack pointer 16-byte aligned */ 538 gd->start_addr_sp -= 16; 539 gd->start_addr_sp &= ~0xf; 540 541 /* 542 * let the architecture-specific code tailor gd->start_addr_sp and 543 * gd->irq_sp 544 */ 545 return arch_reserve_stacks(); 546 } 547 548 static int display_new_sp(void) 549 { 550 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 551 552 return 0; 553 } 554 555 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 556 defined(CONFIG_SH) 557 static int setup_board_part1(void) 558 { 559 bd_t *bd = gd->bd; 560 561 /* 562 * Save local variables to board info struct 563 */ 564 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 565 bd->bi_memsize = gd->ram_size; /* size in bytes */ 566 567 #ifdef CONFIG_SYS_SRAM_BASE 568 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 569 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 570 #endif 571 572 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 573 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 574 #endif 575 #if defined(CONFIG_M68K) 576 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 577 #endif 578 #if defined(CONFIG_MPC83xx) 579 bd->bi_immrbar = CONFIG_SYS_IMMR; 580 #endif 581 582 return 0; 583 } 584 #endif 585 586 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 587 static int setup_board_part2(void) 588 { 589 bd_t *bd = gd->bd; 590 591 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 592 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 593 #if defined(CONFIG_CPM2) 594 bd->bi_cpmfreq = gd->arch.cpm_clk; 595 bd->bi_brgfreq = gd->arch.brg_clk; 596 bd->bi_sccfreq = gd->arch.scc_clk; 597 bd->bi_vco = gd->arch.vco_out; 598 #endif /* CONFIG_CPM2 */ 599 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 600 bd->bi_pcifreq = gd->pci_clk; 601 #endif 602 #if defined(CONFIG_EXTRA_CLOCK) 603 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 604 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 605 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 606 #endif 607 608 return 0; 609 } 610 #endif 611 612 #ifdef CONFIG_POST 613 static int init_post(void) 614 { 615 post_bootmode_init(); 616 post_run(NULL, POST_ROM | post_bootmode_get(0)); 617 618 return 0; 619 } 620 #endif 621 622 static int reloc_fdt(void) 623 { 624 #ifndef CONFIG_OF_EMBED 625 if (gd->flags & GD_FLG_SKIP_RELOC) 626 return 0; 627 if (gd->new_fdt) { 628 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 629 gd->fdt_blob = gd->new_fdt; 630 #ifdef CONFIG_USING_KERNEL_DTB 631 gd->ufdt_blob = gd->new_fdt; 632 #endif 633 } 634 #endif 635 636 return 0; 637 } 638 639 static int reloc_bootstage(void) 640 { 641 #ifdef CONFIG_BOOTSTAGE 642 if (gd->flags & GD_FLG_SKIP_RELOC) 643 return 0; 644 if (gd->new_bootstage) { 645 int size = bootstage_get_size(); 646 647 debug("Copying bootstage from %p to %p, size %x\n", 648 gd->bootstage, gd->new_bootstage, size); 649 memcpy(gd->new_bootstage, gd->bootstage, size); 650 gd->bootstage = gd->new_bootstage; 651 } 652 #endif 653 654 return 0; 655 } 656 657 static int setup_reloc(void) 658 { 659 if (gd->flags & GD_FLG_SKIP_RELOC) { 660 debug("Skipping relocation due to flag\n"); 661 return 0; 662 } 663 664 #ifndef CONFIG_SKIP_RELOCATE_UBOOT 665 #ifdef CONFIG_SYS_TEXT_BASE 666 #ifdef ARM 667 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start; 668 #elif defined(CONFIG_M68K) 669 /* 670 * On all ColdFire arch cpu, monitor code starts always 671 * just after the default vector table location, so at 0x400 672 */ 673 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 674 #else 675 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 676 #endif 677 #endif 678 679 #else 680 gd->reloc_off = 0; 681 #endif 682 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 683 684 #ifndef CONFIG_SUPPORT_USBPLUG 685 printf("Relocation Offset: %08lx, fdt: %08lx\n", 686 gd->reloc_off, (ulong)gd->new_fdt); 687 #endif 688 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 689 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 690 gd->start_addr_sp); 691 692 return 0; 693 } 694 695 #ifdef CONFIG_OF_BOARD_FIXUP 696 static int fix_fdt(void) 697 { 698 return board_fix_fdt((void *)gd->fdt_blob); 699 } 700 #endif 701 702 /* ARM calls relocate_code from its crt0.S */ 703 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 704 !CONFIG_IS_ENABLED(X86_64) 705 706 static int jump_to_copy(void) 707 { 708 if (gd->flags & GD_FLG_SKIP_RELOC) 709 return 0; 710 /* 711 * x86 is special, but in a nice way. It uses a trampoline which 712 * enables the dcache if possible. 713 * 714 * For now, other archs use relocate_code(), which is implemented 715 * similarly for all archs. When we do generic relocation, hopefully 716 * we can make all archs enable the dcache prior to relocation. 717 */ 718 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 719 /* 720 * SDRAM and console are now initialised. The final stack can now 721 * be setup in SDRAM. Code execution will continue in Flash, but 722 * with the stack in SDRAM and Global Data in temporary memory 723 * (CPU cache) 724 */ 725 arch_setup_gd(gd->new_gd); 726 board_init_f_r_trampoline(gd->start_addr_sp); 727 #else 728 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 729 #endif 730 731 return 0; 732 } 733 #endif 734 735 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 736 static int initf_bootstage(void) 737 { 738 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) && 739 IS_ENABLED(CONFIG_BOOTSTAGE_STASH); 740 int ret; 741 742 ret = bootstage_init(!from_spl); 743 if (ret) 744 return ret; 745 if (from_spl) { 746 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR, 747 CONFIG_BOOTSTAGE_STASH_SIZE); 748 749 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE); 750 if (ret && ret != -ENOENT) { 751 debug("Failed to unstash bootstage: err=%d\n", ret); 752 return ret; 753 } 754 } 755 756 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 757 758 return 0; 759 } 760 761 static int initf_console_record(void) 762 { 763 #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN) 764 return console_record_init(); 765 #else 766 return 0; 767 #endif 768 } 769 770 static int initf_dm(void) 771 { 772 #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN) 773 int ret; 774 775 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f"); 776 ret = dm_init_and_scan(true); 777 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F); 778 if (ret) 779 return ret; 780 #endif 781 #ifdef CONFIG_TIMER_EARLY 782 ret = dm_timer_init(); 783 if (ret) 784 return ret; 785 #endif 786 787 return 0; 788 } 789 790 /* Architecture-specific memory reservation */ 791 __weak int reserve_arch(void) 792 { 793 return 0; 794 } 795 796 __weak int arch_cpu_init_dm(void) 797 { 798 return 0; 799 } 800 801 static const init_fnc_t init_sequence_f[] = { 802 setup_mon_len, 803 #ifdef CONFIG_OF_CONTROL 804 fdtdec_setup, 805 #endif 806 #ifdef CONFIG_TRACE 807 trace_early_init, 808 #endif 809 initf_malloc, 810 log_init, 811 initf_bootstage, /* uses its own timer, so does not need DM */ 812 initf_console_record, 813 #if defined(CONFIG_HAVE_FSP) 814 arch_fsp_init, 815 #endif 816 arch_fpga_init, 817 arch_cpu_init, /* basic arch cpu dependent setup */ 818 mach_cpu_init, /* SoC/machine dependent CPU setup */ 819 initf_dm, 820 arch_cpu_init_dm, 821 #if defined(CONFIG_BOARD_EARLY_INIT_F) 822 board_early_init_f, 823 #endif 824 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 825 /* get CPU and bus clocks according to the environment variable */ 826 get_clocks, /* get CPU and bus clocks (etc.) */ 827 #endif 828 #if !defined(CONFIG_M68K) 829 timer_init, /* initialize timer */ 830 #endif 831 #if defined(CONFIG_BOARD_POSTCLK_INIT) 832 board_postclk_init, 833 #endif 834 env_init, /* initialize environment */ 835 init_baud_rate, /* initialze baudrate settings */ 836 serial_init, /* serial communications setup */ 837 console_init_f, /* stage 1 init of console */ 838 display_options, /* say that we are here */ 839 display_text_info, /* show debugging info if required */ 840 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 841 defined(CONFIG_X86) 842 checkcpu, 843 #endif 844 #if defined(CONFIG_DISPLAY_CPUINFO) 845 print_cpuinfo, /* display cpu info (and speed) */ 846 #endif 847 #if defined(CONFIG_DTB_RESELECT) 848 embedded_dtb_select, 849 #endif 850 #if defined(CONFIG_DISPLAY_BOARDINFO) 851 show_board_info, 852 #endif 853 INIT_FUNC_WATCHDOG_INIT 854 #if defined(CONFIG_MISC_INIT_F) 855 misc_init_f, 856 #endif 857 INIT_FUNC_WATCHDOG_RESET 858 #if defined(CONFIG_SYS_I2C) 859 init_func_i2c, 860 #endif 861 #if defined(CONFIG_HARD_SPI) 862 init_func_spi, 863 #endif 864 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) 865 announce_pre_serial, 866 #endif 867 announce_dram_init, 868 dram_init, /* configure available RAM banks */ 869 #ifdef CONFIG_POST 870 post_init_f, 871 #endif 872 INIT_FUNC_WATCHDOG_RESET 873 #if defined(CONFIG_SYS_DRAM_TEST) 874 testdram, 875 #endif /* CONFIG_SYS_DRAM_TEST */ 876 INIT_FUNC_WATCHDOG_RESET 877 878 #ifdef CONFIG_POST 879 init_post, 880 #endif 881 INIT_FUNC_WATCHDOG_RESET 882 /* 883 * Now that we have DRAM mapped and working, we can 884 * relocate the code and continue running from DRAM. 885 * 886 * Reserve memory at end of RAM for (top down in that order): 887 * - area that won't get touched by U-Boot and Linux (optional) 888 * - kernel log buffer 889 * - protected RAM 890 * - LCD framebuffer 891 * - monitor code 892 * - board info struct 893 */ 894 setup_dest_addr, 895 #ifdef CONFIG_PRAM 896 reserve_pram, 897 #endif 898 reserve_round_4k, 899 #ifdef CONFIG_ARM 900 reserve_mmu, 901 #endif 902 reserve_video, 903 reserve_trace, 904 reserve_uboot, 905 reserve_malloc, 906 #ifdef CONFIG_SYS_NONCACHED_MEMORY 907 reserve_noncached, 908 #endif 909 reserve_board, 910 setup_machine, 911 reserve_global_data, 912 reserve_fdt, 913 reserve_bootstage, 914 reserve_arch, 915 reserve_stacks, 916 dram_init_banksize, 917 show_dram_config, 918 #ifdef CONFIG_SYSMEM 919 sysmem_init, /* Validate above reserve memory */ 920 #endif 921 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 922 defined(CONFIG_SH) 923 setup_board_part1, 924 #endif 925 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 926 INIT_FUNC_WATCHDOG_RESET 927 setup_board_part2, 928 #endif 929 display_new_sp, 930 #ifdef CONFIG_OF_BOARD_FIXUP 931 fix_fdt, 932 #endif 933 INIT_FUNC_WATCHDOG_RESET 934 reloc_fdt, 935 reloc_bootstage, 936 setup_reloc, 937 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 938 copy_uboot_to_ram, 939 do_elf_reloc_fixups, 940 clear_bss, 941 #endif 942 #if defined(CONFIG_XTENSA) 943 clear_bss, 944 #endif 945 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 946 !CONFIG_IS_ENABLED(X86_64) 947 jump_to_copy, 948 #endif 949 NULL, 950 }; 951 952 void board_init_f(ulong boot_flags) 953 { 954 gd->flags = boot_flags; 955 gd->have_console = 0; 956 957 #if defined(CONFIG_DISABLE_CONSOLE) 958 gd->flags |= GD_FLG_DISABLE_CONSOLE; 959 #endif 960 961 if (initcall_run_list(init_sequence_f)) 962 hang(); 963 964 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 965 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 966 /* NOTREACHED - jump_to_copy() does not return */ 967 hang(); 968 #endif 969 } 970 971 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 972 /* 973 * For now this code is only used on x86. 974 * 975 * init_sequence_f_r is the list of init functions which are run when 976 * U-Boot is executing from Flash with a semi-limited 'C' environment. 977 * The following limitations must be considered when implementing an 978 * '_f_r' function: 979 * - 'static' variables are read-only 980 * - Global Data (gd->xxx) is read/write 981 * 982 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 983 * supported). It _should_, if possible, copy global data to RAM and 984 * initialise the CPU caches (to speed up the relocation process) 985 * 986 * NOTE: At present only x86 uses this route, but it is intended that 987 * all archs will move to this when generic relocation is implemented. 988 */ 989 static const init_fnc_t init_sequence_f_r[] = { 990 #if !CONFIG_IS_ENABLED(X86_64) 991 init_cache_f_r, 992 #endif 993 994 NULL, 995 }; 996 997 void board_init_f_r(void) 998 { 999 if (initcall_run_list(init_sequence_f_r)) 1000 hang(); 1001 1002 /* 1003 * The pre-relocation drivers may be using memory that has now gone 1004 * away. Mark serial as unavailable - this will fall back to the debug 1005 * UART if available. 1006 * 1007 * Do the same with log drivers since the memory may not be available. 1008 */ 1009 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY); 1010 #ifdef CONFIG_TIMER 1011 gd->timer = NULL; 1012 #endif 1013 1014 /* 1015 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 1016 * Transfer execution from Flash to RAM by calculating the address 1017 * of the in-RAM copy of board_init_r() and calling it 1018 */ 1019 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 1020 1021 /* NOTREACHED - board_init_r() does not return */ 1022 hang(); 1023 } 1024 #endif /* CONFIG_X86 */ 1025