1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 /* 13 * PCI routines 14 */ 15 16 #include <common.h> 17 #include <bootretry.h> 18 #include <cli.h> 19 #include <command.h> 20 #include <console.h> 21 #include <dm.h> 22 #include <asm/processor.h> 23 #include <asm/io.h> 24 #include <pci.h> 25 26 struct pci_reg_info { 27 const char *name; 28 enum pci_size_t size; 29 u8 offset; 30 }; 31 32 static int pci_byte_size(enum pci_size_t size) 33 { 34 switch (size) { 35 case PCI_SIZE_8: 36 return 1; 37 case PCI_SIZE_16: 38 return 2; 39 case PCI_SIZE_32: 40 default: 41 return 4; 42 } 43 } 44 45 static int pci_field_width(enum pci_size_t size) 46 { 47 return pci_byte_size(size) * 2; 48 } 49 50 static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs) 51 { 52 for (; regs->name; regs++) { 53 unsigned long val; 54 55 dm_pci_read_config(dev, regs->offset, &val, regs->size); 56 printf(" %s =%*s%#.*lx\n", regs->name, 57 (int)(28 - strlen(regs->name)), "", 58 pci_field_width(regs->size), val); 59 } 60 } 61 62 static int pci_bar_show(struct udevice *dev) 63 { 64 u8 header_type; 65 int bar_cnt, bar_id, mem_type; 66 bool is_64, is_io; 67 u32 base_low, base_high; 68 u32 size_low, size_high; 69 u64 base, size; 70 u32 reg_addr; 71 int prefetchable; 72 73 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type); 74 75 if (header_type == PCI_HEADER_TYPE_CARDBUS) { 76 printf("CardBus doesn't support BARs\n"); 77 return -ENOSYS; 78 } 79 80 bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2; 81 82 printf("ID Base Size Width Type\n"); 83 printf("----------------------------------------------------------\n"); 84 85 bar_id = 0; 86 reg_addr = PCI_BASE_ADDRESS_0; 87 while (bar_cnt) { 88 dm_pci_read_config32(dev, reg_addr, &base_low); 89 dm_pci_write_config32(dev, reg_addr, 0xffffffff); 90 dm_pci_read_config32(dev, reg_addr, &size_low); 91 dm_pci_write_config32(dev, reg_addr, base_low); 92 reg_addr += 4; 93 94 base = base_low & ~0xf; 95 size = size_low & ~0xf; 96 base_high = 0x0; 97 size_high = 0xffffffff; 98 is_64 = 0; 99 prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH; 100 is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO; 101 mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 102 103 if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) { 104 dm_pci_read_config32(dev, reg_addr, &base_high); 105 dm_pci_write_config32(dev, reg_addr, 0xffffffff); 106 dm_pci_read_config32(dev, reg_addr, &size_high); 107 dm_pci_write_config32(dev, reg_addr, base_high); 108 bar_cnt--; 109 reg_addr += 4; 110 is_64 = 1; 111 } 112 113 base = base | ((u64)base_high << 32); 114 size = size | ((u64)size_high << 32); 115 116 if ((!is_64 && size_low) || (is_64 && size)) { 117 size = ~size + 1; 118 printf(" %d %#018llx %#018llx %d %s %s\n", 119 bar_id, (unsigned long long)base, 120 (unsigned long long)size, is_64 ? 64 : 32, 121 is_io ? "I/O" : "MEM", 122 prefetchable ? "Prefetchable" : ""); 123 } 124 125 bar_id++; 126 bar_cnt--; 127 } 128 129 return 0; 130 } 131 132 static struct pci_reg_info regs_start[] = { 133 { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID }, 134 { "device ID", PCI_SIZE_16, PCI_DEVICE_ID }, 135 { "command register ID", PCI_SIZE_16, PCI_COMMAND }, 136 { "status register", PCI_SIZE_16, PCI_STATUS }, 137 { "revision ID", PCI_SIZE_8, PCI_REVISION_ID }, 138 {}, 139 }; 140 141 static struct pci_reg_info regs_rest[] = { 142 { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE }, 143 { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG }, 144 { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE }, 145 { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER }, 146 { "header type", PCI_SIZE_8, PCI_HEADER_TYPE }, 147 { "BIST", PCI_SIZE_8, PCI_BIST }, 148 { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 }, 149 {}, 150 }; 151 152 static struct pci_reg_info regs_normal[] = { 153 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 }, 154 { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 }, 155 { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 }, 156 { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 }, 157 { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 }, 158 { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS }, 159 { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID }, 160 { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID }, 161 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS }, 162 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE }, 163 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN }, 164 { "min Grant", PCI_SIZE_8, PCI_MIN_GNT }, 165 { "max Latency", PCI_SIZE_8, PCI_MAX_LAT }, 166 {}, 167 }; 168 169 static struct pci_reg_info regs_bridge[] = { 170 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 }, 171 { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS }, 172 { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS }, 173 { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS }, 174 { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER }, 175 { "IO base", PCI_SIZE_8, PCI_IO_BASE }, 176 { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT }, 177 { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS }, 178 { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE }, 179 { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT }, 180 { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE }, 181 { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT }, 182 { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 }, 183 { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 }, 184 { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 }, 185 { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 }, 186 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 }, 187 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE }, 188 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN }, 189 { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL }, 190 {}, 191 }; 192 193 static struct pci_reg_info regs_cardbus[] = { 194 { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST }, 195 { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS }, 196 { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS }, 197 { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS }, 198 { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS }, 199 { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER }, 200 { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 }, 201 { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 }, 202 { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 }, 203 { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 }, 204 { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 }, 205 { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI }, 206 { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 }, 207 { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI }, 208 { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 }, 209 { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI }, 210 { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 }, 211 { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI }, 212 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE }, 213 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN }, 214 { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL }, 215 { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID }, 216 { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID }, 217 { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE }, 218 {}, 219 }; 220 221 /** 222 * pci_header_show() - Show the header of the specified PCI device. 223 * 224 * @dev: Bus+Device+Function number 225 */ 226 static void pci_header_show(struct udevice *dev) 227 { 228 unsigned long class, header_type; 229 230 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8); 231 dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8); 232 pci_show_regs(dev, regs_start); 233 printf(" class code = 0x%.2x (%s)\n", (int)class, 234 pci_class_str(class)); 235 pci_show_regs(dev, regs_rest); 236 237 switch (header_type & 0x03) { 238 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */ 239 pci_show_regs(dev, regs_normal); 240 break; 241 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */ 242 pci_show_regs(dev, regs_bridge); 243 break; 244 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */ 245 pci_show_regs(dev, regs_cardbus); 246 break; 247 248 default: 249 printf("unknown header\n"); 250 break; 251 } 252 } 253 254 static void pciinfo_header(int busnum, bool short_listing) 255 { 256 printf("Scanning PCI devices on bus %d\n", busnum); 257 258 if (short_listing) { 259 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n"); 260 printf("_____________________________________________________________\n"); 261 } 262 } 263 264 /** 265 * pci_header_show_brief() - Show the short-form PCI device header 266 * 267 * Reads and prints the header of the specified PCI device in short form. 268 * 269 * @dev: PCI device to show 270 */ 271 static void pci_header_show_brief(struct udevice *dev) 272 { 273 ulong vendor, device; 274 ulong class, subclass; 275 276 dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16); 277 dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16); 278 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8); 279 dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8); 280 281 printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n", 282 vendor, device, 283 pci_class_str(class), subclass); 284 } 285 286 static void pciinfo(struct udevice *bus, bool short_listing) 287 { 288 struct udevice *dev; 289 290 pciinfo_header(bus->seq, short_listing); 291 292 for (device_find_first_child(bus, &dev); 293 dev; 294 device_find_next_child(&dev)) { 295 struct pci_child_platdata *pplat; 296 297 pplat = dev_get_parent_platdata(dev); 298 if (short_listing) { 299 printf("%02x.%02x.%02x ", bus->seq, 300 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn)); 301 pci_header_show_brief(dev); 302 } else { 303 printf("\nFound PCI device %02x.%02x.%02x:\n", bus->seq, 304 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn)); 305 pci_header_show(dev); 306 } 307 } 308 } 309 310 /** 311 * get_pci_dev() - Convert the "bus.device.function" identifier into a number 312 * 313 * @name: Device string in the form "bus.device.function" where each is in hex 314 * @return encoded pci_dev_t or -1 if the string was invalid 315 */ 316 static pci_dev_t get_pci_dev(char *name) 317 { 318 char cnum[12]; 319 int len, i, iold, n; 320 int bdfs[3] = {0,0,0}; 321 322 len = strlen(name); 323 if (len > 8) 324 return -1; 325 for (i = 0, iold = 0, n = 0; i < len; i++) { 326 if (name[i] == '.') { 327 memcpy(cnum, &name[iold], i - iold); 328 cnum[i - iold] = '\0'; 329 bdfs[n++] = simple_strtoul(cnum, NULL, 16); 330 iold = i + 1; 331 } 332 } 333 strcpy(cnum, &name[iold]); 334 if (n == 0) 335 n = 1; 336 bdfs[n] = simple_strtoul(cnum, NULL, 16); 337 338 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); 339 } 340 341 static int pci_cfg_display(struct udevice *dev, ulong addr, 342 enum pci_size_t size, ulong length) 343 { 344 #define DISP_LINE_LEN 16 345 ulong i, nbytes, linebytes; 346 int byte_size; 347 int rc = 0; 348 349 byte_size = pci_byte_size(size); 350 if (length == 0) 351 length = 0x40 / byte_size; /* Standard PCI config space */ 352 353 /* Print the lines. 354 * once, and all accesses are with the specified bus width. 355 */ 356 nbytes = length * byte_size; 357 do { 358 printf("%08lx:", addr); 359 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; 360 for (i = 0; i < linebytes; i += byte_size) { 361 unsigned long val; 362 363 dm_pci_read_config(dev, addr, &val, size); 364 printf(" %0*lx", pci_field_width(size), val); 365 addr += byte_size; 366 } 367 printf("\n"); 368 nbytes -= linebytes; 369 if (ctrlc()) { 370 rc = 1; 371 break; 372 } 373 } while (nbytes > 0); 374 375 return (rc); 376 } 377 378 static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size, 379 ulong value, int incrflag) 380 { 381 ulong i; 382 int nbytes; 383 ulong val; 384 385 /* Print the address, followed by value. Then accept input for 386 * the next value. A non-converted value exits. 387 */ 388 do { 389 printf("%08lx:", addr); 390 dm_pci_read_config(dev, addr, &val, size); 391 printf(" %0*lx", pci_field_width(size), val); 392 393 nbytes = cli_readline(" ? "); 394 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { 395 /* <CR> pressed as only input, don't modify current 396 * location and move to next. "-" pressed will go back. 397 */ 398 if (incrflag) 399 addr += nbytes ? -size : size; 400 nbytes = 1; 401 /* good enough to not time out */ 402 bootretry_reset_cmd_timeout(); 403 } 404 #ifdef CONFIG_BOOT_RETRY_TIME 405 else if (nbytes == -2) { 406 break; /* timed out, exit the command */ 407 } 408 #endif 409 else { 410 char *endp; 411 i = simple_strtoul(console_buffer, &endp, 16); 412 nbytes = endp - console_buffer; 413 if (nbytes) { 414 /* good enough to not time out 415 */ 416 bootretry_reset_cmd_timeout(); 417 dm_pci_write_config(dev, addr, i, size); 418 if (incrflag) 419 addr += size; 420 } 421 } 422 } while (nbytes); 423 424 return 0; 425 } 426 427 static const struct pci_flag_info { 428 uint flag; 429 const char *name; 430 } pci_flag_info[] = { 431 { PCI_REGION_IO, "io" }, 432 { PCI_REGION_PREFETCH, "prefetch" }, 433 { PCI_REGION_SYS_MEMORY, "sysmem" }, 434 { PCI_REGION_RO, "readonly" }, 435 { PCI_REGION_IO, "io" }, 436 }; 437 438 static void pci_show_regions(struct udevice *bus) 439 { 440 struct pci_controller *hose = dev_get_uclass_priv(bus); 441 const struct pci_region *reg; 442 int i, j; 443 444 if (!hose) { 445 printf("Bus '%s' is not a PCI controller\n", bus->name); 446 return; 447 } 448 449 printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size", 450 "Flags"); 451 for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) { 452 printf("%d %#018llx %#018llx %#018llx ", i, 453 (unsigned long long)reg->bus_start, 454 (unsigned long long)reg->phys_start, 455 (unsigned long long)reg->size); 456 if (!(reg->flags & PCI_REGION_TYPE)) 457 printf("mem "); 458 for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) { 459 if (reg->flags & pci_flag_info[j].flag) 460 printf("%s ", pci_flag_info[j].name); 461 } 462 printf("\n"); 463 } 464 } 465 466 /* PCI Configuration Space access commands 467 * 468 * Syntax: 469 * pci display[.b, .w, .l] bus.device.function} [addr] [len] 470 * pci next[.b, .w, .l] bus.device.function [addr] 471 * pci modify[.b, .w, .l] bus.device.function [addr] 472 * pci write[.b, .w, .l] bus.device.function addr value 473 */ 474 static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 475 { 476 ulong addr = 0, value = 0, cmd_size = 0; 477 enum pci_size_t size = PCI_SIZE_32; 478 struct udevice *dev, *bus; 479 int busnum = 0; 480 pci_dev_t bdf = 0; 481 char cmd = 's'; 482 int ret = 0; 483 484 if (argc > 1) 485 cmd = argv[1][0]; 486 487 switch (cmd) { 488 case 'd': /* display */ 489 case 'n': /* next */ 490 case 'm': /* modify */ 491 case 'w': /* write */ 492 /* Check for a size specification. */ 493 cmd_size = cmd_get_data_size(argv[1], 4); 494 size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1; 495 if (argc > 3) 496 addr = simple_strtoul(argv[3], NULL, 16); 497 if (argc > 4) 498 value = simple_strtoul(argv[4], NULL, 16); 499 case 'h': /* header */ 500 case 'b': /* bars */ 501 if (argc < 3) 502 goto usage; 503 if ((bdf = get_pci_dev(argv[2])) == -1) 504 return 1; 505 break; 506 case 'e': 507 pci_init(); 508 return 0; 509 case 'r': /* no break */ 510 default: /* scan bus */ 511 value = 1; /* short listing */ 512 if (argc > 1) { 513 if (cmd != 'r' && argv[argc-1][0] == 'l') { 514 value = 0; 515 argc--; 516 } 517 if (argc > 1) 518 busnum = simple_strtoul(argv[1], NULL, 16); 519 } 520 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus); 521 if (ret) { 522 printf("No such bus\n"); 523 return CMD_RET_FAILURE; 524 } 525 if (cmd == 'r') 526 pci_show_regions(bus); 527 else 528 pciinfo(bus, value); 529 return 0; 530 } 531 532 ret = dm_pci_bus_find_bdf(bdf, &dev); 533 if (ret) { 534 printf("No such device\n"); 535 return CMD_RET_FAILURE; 536 } 537 538 switch (argv[1][0]) { 539 case 'h': /* header */ 540 pci_header_show(dev); 541 break; 542 case 'd': /* display */ 543 return pci_cfg_display(dev, addr, size, value); 544 case 'n': /* next */ 545 if (argc < 4) 546 goto usage; 547 ret = pci_cfg_modify(dev, addr, size, value, 0); 548 break; 549 case 'm': /* modify */ 550 if (argc < 4) 551 goto usage; 552 ret = pci_cfg_modify(dev, addr, size, value, 1); 553 break; 554 case 'w': /* write */ 555 if (argc < 5) 556 goto usage; 557 ret = dm_pci_write_config(dev, addr, value, size); 558 break; 559 case 'b': /* bars */ 560 return pci_bar_show(dev); 561 default: 562 ret = CMD_RET_USAGE; 563 break; 564 } 565 566 return ret; 567 usage: 568 return CMD_RET_USAGE; 569 } 570 571 /***************************************************/ 572 573 #ifdef CONFIG_SYS_LONGHELP 574 static char pci_help_text[] = 575 "[bus] [long]\n" 576 " - short or long list of PCI devices on bus 'bus'\n" 577 "pci enum\n" 578 " - Enumerate PCI buses\n" 579 "pci header b.d.f\n" 580 " - show header of PCI device 'bus.device.function'\n" 581 "pci bar b.d.f\n" 582 " - show BARs base and size for device b.d.f'\n" 583 "pci regions\n" 584 " - show PCI regions\n" 585 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n" 586 " - display PCI configuration space (CFG)\n" 587 "pci next[.b, .w, .l] b.d.f address\n" 588 " - modify, read and keep CFG address\n" 589 "pci modify[.b, .w, .l] b.d.f address\n" 590 " - modify, auto increment CFG address\n" 591 "pci write[.b, .w, .l] b.d.f address value\n" 592 " - write to CFG address"; 593 #endif 594 595 U_BOOT_CMD( 596 pci, 5, 1, do_pci, 597 "list and access PCI Configuration Space", pci_help_text 598 ); 599