1*f9a1c31dSWesley Yao /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2*f9a1c31dSWesley Yao /* 3*f9a1c31dSWesley Yao * Copyright (C) 2019 Rockchip Electronics Co., Ltd. 4*f9a1c31dSWesley Yao */ 5*f9a1c31dSWesley Yao 6*f9a1c31dSWesley Yao #ifndef __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H 7*f9a1c31dSWesley Yao #define __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H 8*f9a1c31dSWesley Yao 9*f9a1c31dSWesley Yao #define CPU_2_IO_ALIGN_LEN (16) /* 16 byte */ 10*f9a1c31dSWesley Yao 11*f9a1c31dSWesley Yao int data_cpu_2_io(void *p, u32 len); 12*f9a1c31dSWesley Yao void data_cpu_2_io_init(void); 13*f9a1c31dSWesley Yao 14*f9a1c31dSWesley Yao #endif /* __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H */ 15