1 /* 2 * Copyright (C) 2009 3 * Marek Vasut <marek.vasut@gmail.com> 4 * 5 * Heavily based on pxa255_idp platform 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <command.h> 12 #include <serial.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/pxa.h> 15 #include <asm/arch/regs-mmc.h> 16 #include <spi.h> 17 #include <asm/io.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #ifdef CONFIG_CMD_SPI 22 void lcd_start(void); 23 #else 24 inline void lcd_start(void) {}; 25 #endif 26 27 /* 28 * Miscelaneous platform dependent initialisations 29 */ 30 int board_init(void) 31 { 32 /* We have RAM, disable cache */ 33 dcache_disable(); 34 icache_disable(); 35 36 /* arch number of Z2 */ 37 gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; 38 39 /* adress of boot parameters */ 40 gd->bd->bi_boot_params = 0xa0000100; 41 42 /* Enable LCD */ 43 lcd_start(); 44 45 return 0; 46 } 47 48 int dram_init(void) 49 { 50 pxa2xx_dram_init(); 51 gd->ram_size = PHYS_SDRAM_1_SIZE; 52 return 0; 53 } 54 55 void dram_init_banksize(void) 56 { 57 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 58 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 59 } 60 61 #ifdef CONFIG_CMD_MMC 62 int board_mmc_init(bd_t *bis) 63 { 64 pxa_mmc_register(0); 65 return 0; 66 } 67 #endif 68 69 #ifdef CONFIG_CMD_SPI 70 71 struct { 72 unsigned char reg; 73 unsigned short data; 74 unsigned char mdelay; 75 } lcd_data[] = { 76 { 0x07, 0x0000, 0 }, 77 { 0x13, 0x0000, 10 }, 78 { 0x11, 0x3004, 0 }, 79 { 0x14, 0x200F, 0 }, 80 { 0x10, 0x1a20, 0 }, 81 { 0x13, 0x0040, 50 }, 82 { 0x13, 0x0060, 0 }, 83 { 0x13, 0x0070, 200 }, 84 { 0x01, 0x0127, 0 }, 85 { 0x02, 0x0700, 0 }, 86 { 0x03, 0x1030, 0 }, 87 { 0x08, 0x0208, 0 }, 88 { 0x0B, 0x0620, 0 }, 89 { 0x0C, 0x0110, 0 }, 90 { 0x30, 0x0120, 0 }, 91 { 0x31, 0x0127, 0 }, 92 { 0x32, 0x0000, 0 }, 93 { 0x33, 0x0503, 0 }, 94 { 0x34, 0x0727, 0 }, 95 { 0x35, 0x0124, 0 }, 96 { 0x36, 0x0706, 0 }, 97 { 0x37, 0x0701, 0 }, 98 { 0x38, 0x0F00, 0 }, 99 { 0x39, 0x0F00, 0 }, 100 { 0x40, 0x0000, 0 }, 101 { 0x41, 0x0000, 0 }, 102 { 0x42, 0x013f, 0 }, 103 { 0x43, 0x0000, 0 }, 104 { 0x44, 0x013f, 0 }, 105 { 0x45, 0x0000, 0 }, 106 { 0x46, 0xef00, 0 }, 107 { 0x47, 0x013f, 0 }, 108 { 0x48, 0x0000, 0 }, 109 { 0x07, 0x0015, 30 }, 110 { 0x07, 0x0017, 0 }, 111 { 0x20, 0x0000, 0 }, 112 { 0x21, 0x0000, 0 }, 113 { 0x22, 0x0000, 0 }, 114 }; 115 116 void zipitz2_spi_sda(int set) 117 { 118 /* GPIO 13 */ 119 if (set) 120 writel((1 << 13), GPSR0); 121 else 122 writel((1 << 13), GPCR0); 123 } 124 125 void zipitz2_spi_scl(int set) 126 { 127 /* GPIO 22 */ 128 if (set) 129 writel((1 << 22), GPCR0); 130 else 131 writel((1 << 22), GPSR0); 132 } 133 134 unsigned char zipitz2_spi_read(void) 135 { 136 /* GPIO 40 */ 137 return !!(readl(GPLR1) & (1 << 8)); 138 } 139 140 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 141 { 142 /* Always valid */ 143 return 1; 144 } 145 146 void spi_cs_activate(struct spi_slave *slave) 147 { 148 /* GPIO 88 low */ 149 writel((1 << 24), GPCR2); 150 } 151 152 void spi_cs_deactivate(struct spi_slave *slave) 153 { 154 /* GPIO 88 high */ 155 writel((1 << 24), GPSR2); 156 } 157 158 void lcd_start(void) 159 { 160 int i; 161 unsigned char reg[3] = { 0x74, 0x00, 0 }; 162 unsigned char data[3] = { 0x76, 0, 0 }; 163 unsigned char dummy[3] = { 0, 0, 0 }; 164 165 /* PWM2 AF */ 166 writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); 167 /* Enable clock to all PWM */ 168 writel(readl(CKEN) | 0x3, CKEN); 169 /* Configure PWM2 */ 170 writel(0x4f, PWM_CTRL2); 171 writel(0x2ff, PWM_PWDUTY2); 172 writel(792, PWM_PERVAL2); 173 174 /* Toggle the reset pin to reset the LCD */ 175 writel((1 << 19), GPSR0); 176 udelay(100000); 177 writel((1 << 19), GPCR0); 178 udelay(20000); 179 writel((1 << 19), GPSR0); 180 udelay(20000); 181 182 /* Program the LCD init sequence */ 183 for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { 184 reg[0] = 0x74; 185 reg[1] = 0x0; 186 reg[2] = lcd_data[i].reg; 187 spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); 188 189 data[0] = 0x76; 190 data[1] = lcd_data[i].data >> 8; 191 data[2] = lcd_data[i].data & 0xff; 192 spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); 193 194 if (lcd_data[i].mdelay) 195 udelay(lcd_data[i].mdelay * 1000); 196 } 197 198 writel((1 << 11), GPSR0); 199 } 200 #endif 201