1f19eb154SVasily Khoruzhick /* 2f19eb154SVasily Khoruzhick * Copyright (C) 2009 3f19eb154SVasily Khoruzhick * Marek Vasut <marek.vasut@gmail.com> 4f19eb154SVasily Khoruzhick * 5f19eb154SVasily Khoruzhick * Heavily based on pxa255_idp platform 6f19eb154SVasily Khoruzhick * 7f19eb154SVasily Khoruzhick * SPDX-License-Identifier: GPL-2.0+ 8f19eb154SVasily Khoruzhick */ 9f19eb154SVasily Khoruzhick 10f19eb154SVasily Khoruzhick #include <common.h> 11f19eb154SVasily Khoruzhick #include <command.h> 12f19eb154SVasily Khoruzhick #include <serial.h> 13f19eb154SVasily Khoruzhick #include <asm/arch/hardware.h> 14f19eb154SVasily Khoruzhick #include <asm/arch/pxa.h> 15f19eb154SVasily Khoruzhick #include <asm/arch/regs-mmc.h> 16f19eb154SVasily Khoruzhick #include <spi.h> 17f19eb154SVasily Khoruzhick #include <asm/io.h> 18afed7ebeSVasily Khoruzhick #include <usb.h> 19f19eb154SVasily Khoruzhick 20f19eb154SVasily Khoruzhick DECLARE_GLOBAL_DATA_PTR; 21f19eb154SVasily Khoruzhick 22f19eb154SVasily Khoruzhick #ifdef CONFIG_CMD_SPI 23f19eb154SVasily Khoruzhick void lcd_start(void); 24f19eb154SVasily Khoruzhick #else 25f19eb154SVasily Khoruzhick inline void lcd_start(void) {}; 26f19eb154SVasily Khoruzhick #endif 27f19eb154SVasily Khoruzhick 28f19eb154SVasily Khoruzhick /* 29f19eb154SVasily Khoruzhick * Miscelaneous platform dependent initialisations 30f19eb154SVasily Khoruzhick */ 31f19eb154SVasily Khoruzhick int board_init(void) 32f19eb154SVasily Khoruzhick { 33f19eb154SVasily Khoruzhick /* arch number of Z2 */ 34f19eb154SVasily Khoruzhick gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; 35f19eb154SVasily Khoruzhick 36f19eb154SVasily Khoruzhick /* adress of boot parameters */ 37f19eb154SVasily Khoruzhick gd->bd->bi_boot_params = 0xa0000100; 38f19eb154SVasily Khoruzhick 39f19eb154SVasily Khoruzhick /* Enable LCD */ 40f19eb154SVasily Khoruzhick lcd_start(); 41f19eb154SVasily Khoruzhick 42f19eb154SVasily Khoruzhick return 0; 43f19eb154SVasily Khoruzhick } 44f19eb154SVasily Khoruzhick 45f19eb154SVasily Khoruzhick int dram_init(void) 46f19eb154SVasily Khoruzhick { 47f19eb154SVasily Khoruzhick pxa2xx_dram_init(); 48f19eb154SVasily Khoruzhick gd->ram_size = PHYS_SDRAM_1_SIZE; 49f19eb154SVasily Khoruzhick return 0; 50f19eb154SVasily Khoruzhick } 51f19eb154SVasily Khoruzhick 52afed7ebeSVasily Khoruzhick #ifdef CONFIG_CMD_USB 53afed7ebeSVasily Khoruzhick int board_usb_init(int index, enum usb_init_type init) 54afed7ebeSVasily Khoruzhick { 55afed7ebeSVasily Khoruzhick /* enable port 2 */ 56afed7ebeSVasily Khoruzhick writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | 57afed7ebeSVasily Khoruzhick UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); 58afed7ebeSVasily Khoruzhick 59afed7ebeSVasily Khoruzhick return 0; 60afed7ebeSVasily Khoruzhick } 61afed7ebeSVasily Khoruzhick 62afed7ebeSVasily Khoruzhick int board_usb_cleanup(int index, enum usb_init_type init) 63afed7ebeSVasily Khoruzhick { 64afed7ebeSVasily Khoruzhick return 0; 65afed7ebeSVasily Khoruzhick } 66afed7ebeSVasily Khoruzhick 67afed7ebeSVasily Khoruzhick void usb_board_stop(void) 68afed7ebeSVasily Khoruzhick { 69afed7ebeSVasily Khoruzhick } 70afed7ebeSVasily Khoruzhick #endif 71afed7ebeSVasily Khoruzhick 72*76b00acaSSimon Glass int dram_init_banksize(void) 73f19eb154SVasily Khoruzhick { 74f19eb154SVasily Khoruzhick gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 75f19eb154SVasily Khoruzhick gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 76*76b00acaSSimon Glass 77*76b00acaSSimon Glass return 0; 78f19eb154SVasily Khoruzhick } 79f19eb154SVasily Khoruzhick 80f19eb154SVasily Khoruzhick #ifdef CONFIG_CMD_MMC 81f19eb154SVasily Khoruzhick int board_mmc_init(bd_t *bis) 82f19eb154SVasily Khoruzhick { 83f19eb154SVasily Khoruzhick pxa_mmc_register(0); 84f19eb154SVasily Khoruzhick return 0; 85f19eb154SVasily Khoruzhick } 86f19eb154SVasily Khoruzhick #endif 87f19eb154SVasily Khoruzhick 88f19eb154SVasily Khoruzhick #ifdef CONFIG_CMD_SPI 89f19eb154SVasily Khoruzhick 90f19eb154SVasily Khoruzhick struct { 91f19eb154SVasily Khoruzhick unsigned char reg; 92f19eb154SVasily Khoruzhick unsigned short data; 93f19eb154SVasily Khoruzhick unsigned char mdelay; 94f19eb154SVasily Khoruzhick } lcd_data[] = { 95f19eb154SVasily Khoruzhick { 0x07, 0x0000, 0 }, 96f19eb154SVasily Khoruzhick { 0x13, 0x0000, 10 }, 97f19eb154SVasily Khoruzhick { 0x11, 0x3004, 0 }, 98f19eb154SVasily Khoruzhick { 0x14, 0x200F, 0 }, 99f19eb154SVasily Khoruzhick { 0x10, 0x1a20, 0 }, 100f19eb154SVasily Khoruzhick { 0x13, 0x0040, 50 }, 101f19eb154SVasily Khoruzhick { 0x13, 0x0060, 0 }, 102f19eb154SVasily Khoruzhick { 0x13, 0x0070, 200 }, 103f19eb154SVasily Khoruzhick { 0x01, 0x0127, 0 }, 104f19eb154SVasily Khoruzhick { 0x02, 0x0700, 0 }, 105f19eb154SVasily Khoruzhick { 0x03, 0x1030, 0 }, 106f19eb154SVasily Khoruzhick { 0x08, 0x0208, 0 }, 107f19eb154SVasily Khoruzhick { 0x0B, 0x0620, 0 }, 108f19eb154SVasily Khoruzhick { 0x0C, 0x0110, 0 }, 109f19eb154SVasily Khoruzhick { 0x30, 0x0120, 0 }, 110f19eb154SVasily Khoruzhick { 0x31, 0x0127, 0 }, 111f19eb154SVasily Khoruzhick { 0x32, 0x0000, 0 }, 112f19eb154SVasily Khoruzhick { 0x33, 0x0503, 0 }, 113f19eb154SVasily Khoruzhick { 0x34, 0x0727, 0 }, 114f19eb154SVasily Khoruzhick { 0x35, 0x0124, 0 }, 115f19eb154SVasily Khoruzhick { 0x36, 0x0706, 0 }, 116f19eb154SVasily Khoruzhick { 0x37, 0x0701, 0 }, 117f19eb154SVasily Khoruzhick { 0x38, 0x0F00, 0 }, 118f19eb154SVasily Khoruzhick { 0x39, 0x0F00, 0 }, 119f19eb154SVasily Khoruzhick { 0x40, 0x0000, 0 }, 120f19eb154SVasily Khoruzhick { 0x41, 0x0000, 0 }, 121f19eb154SVasily Khoruzhick { 0x42, 0x013f, 0 }, 122f19eb154SVasily Khoruzhick { 0x43, 0x0000, 0 }, 123f19eb154SVasily Khoruzhick { 0x44, 0x013f, 0 }, 124f19eb154SVasily Khoruzhick { 0x45, 0x0000, 0 }, 125f19eb154SVasily Khoruzhick { 0x46, 0xef00, 0 }, 126f19eb154SVasily Khoruzhick { 0x47, 0x013f, 0 }, 127f19eb154SVasily Khoruzhick { 0x48, 0x0000, 0 }, 128f19eb154SVasily Khoruzhick { 0x07, 0x0015, 30 }, 129f19eb154SVasily Khoruzhick { 0x07, 0x0017, 0 }, 130f19eb154SVasily Khoruzhick { 0x20, 0x0000, 0 }, 131f19eb154SVasily Khoruzhick { 0x21, 0x0000, 0 }, 132f19eb154SVasily Khoruzhick { 0x22, 0x0000, 0 }, 133f19eb154SVasily Khoruzhick }; 134f19eb154SVasily Khoruzhick 135f19eb154SVasily Khoruzhick void zipitz2_spi_sda(int set) 136f19eb154SVasily Khoruzhick { 137f19eb154SVasily Khoruzhick /* GPIO 13 */ 138f19eb154SVasily Khoruzhick if (set) 139f19eb154SVasily Khoruzhick writel((1 << 13), GPSR0); 140f19eb154SVasily Khoruzhick else 141f19eb154SVasily Khoruzhick writel((1 << 13), GPCR0); 142f19eb154SVasily Khoruzhick } 143f19eb154SVasily Khoruzhick 144f19eb154SVasily Khoruzhick void zipitz2_spi_scl(int set) 145f19eb154SVasily Khoruzhick { 146f19eb154SVasily Khoruzhick /* GPIO 22 */ 147f19eb154SVasily Khoruzhick if (set) 148f19eb154SVasily Khoruzhick writel((1 << 22), GPCR0); 149f19eb154SVasily Khoruzhick else 150f19eb154SVasily Khoruzhick writel((1 << 22), GPSR0); 151f19eb154SVasily Khoruzhick } 152f19eb154SVasily Khoruzhick 153f19eb154SVasily Khoruzhick unsigned char zipitz2_spi_read(void) 154f19eb154SVasily Khoruzhick { 155f19eb154SVasily Khoruzhick /* GPIO 40 */ 156f19eb154SVasily Khoruzhick return !!(readl(GPLR1) & (1 << 8)); 157f19eb154SVasily Khoruzhick } 158f19eb154SVasily Khoruzhick 159f19eb154SVasily Khoruzhick int spi_cs_is_valid(unsigned int bus, unsigned int cs) 160f19eb154SVasily Khoruzhick { 161f19eb154SVasily Khoruzhick /* Always valid */ 162f19eb154SVasily Khoruzhick return 1; 163f19eb154SVasily Khoruzhick } 164f19eb154SVasily Khoruzhick 165f19eb154SVasily Khoruzhick void spi_cs_activate(struct spi_slave *slave) 166f19eb154SVasily Khoruzhick { 167f19eb154SVasily Khoruzhick /* GPIO 88 low */ 168f19eb154SVasily Khoruzhick writel((1 << 24), GPCR2); 169f19eb154SVasily Khoruzhick } 170f19eb154SVasily Khoruzhick 171f19eb154SVasily Khoruzhick void spi_cs_deactivate(struct spi_slave *slave) 172f19eb154SVasily Khoruzhick { 173f19eb154SVasily Khoruzhick /* GPIO 88 high */ 174f19eb154SVasily Khoruzhick writel((1 << 24), GPSR2); 175f19eb154SVasily Khoruzhick } 176f19eb154SVasily Khoruzhick 177f19eb154SVasily Khoruzhick void lcd_start(void) 178f19eb154SVasily Khoruzhick { 179f19eb154SVasily Khoruzhick int i; 180f19eb154SVasily Khoruzhick unsigned char reg[3] = { 0x74, 0x00, 0 }; 181f19eb154SVasily Khoruzhick unsigned char data[3] = { 0x76, 0, 0 }; 182f19eb154SVasily Khoruzhick unsigned char dummy[3] = { 0, 0, 0 }; 183f19eb154SVasily Khoruzhick 184f19eb154SVasily Khoruzhick /* PWM2 AF */ 185f19eb154SVasily Khoruzhick writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); 186f19eb154SVasily Khoruzhick /* Enable clock to all PWM */ 187f19eb154SVasily Khoruzhick writel(readl(CKEN) | 0x3, CKEN); 188f19eb154SVasily Khoruzhick /* Configure PWM2 */ 189f19eb154SVasily Khoruzhick writel(0x4f, PWM_CTRL2); 190f19eb154SVasily Khoruzhick writel(0x2ff, PWM_PWDUTY2); 191f19eb154SVasily Khoruzhick writel(792, PWM_PERVAL2); 192f19eb154SVasily Khoruzhick 193f19eb154SVasily Khoruzhick /* Toggle the reset pin to reset the LCD */ 194f19eb154SVasily Khoruzhick writel((1 << 19), GPSR0); 195f19eb154SVasily Khoruzhick udelay(100000); 196f19eb154SVasily Khoruzhick writel((1 << 19), GPCR0); 197f19eb154SVasily Khoruzhick udelay(20000); 198f19eb154SVasily Khoruzhick writel((1 << 19), GPSR0); 199f19eb154SVasily Khoruzhick udelay(20000); 200f19eb154SVasily Khoruzhick 201f19eb154SVasily Khoruzhick /* Program the LCD init sequence */ 202f19eb154SVasily Khoruzhick for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { 203f19eb154SVasily Khoruzhick reg[0] = 0x74; 204f19eb154SVasily Khoruzhick reg[1] = 0x0; 205f19eb154SVasily Khoruzhick reg[2] = lcd_data[i].reg; 206f19eb154SVasily Khoruzhick spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); 207f19eb154SVasily Khoruzhick 208f19eb154SVasily Khoruzhick data[0] = 0x76; 209f19eb154SVasily Khoruzhick data[1] = lcd_data[i].data >> 8; 210f19eb154SVasily Khoruzhick data[2] = lcd_data[i].data & 0xff; 211f19eb154SVasily Khoruzhick spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); 212f19eb154SVasily Khoruzhick 213f19eb154SVasily Khoruzhick if (lcd_data[i].mdelay) 214f19eb154SVasily Khoruzhick udelay(lcd_data[i].mdelay * 1000); 215f19eb154SVasily Khoruzhick } 216f19eb154SVasily Khoruzhick 217f19eb154SVasily Khoruzhick writel((1 << 11), GPSR0); 218f19eb154SVasily Khoruzhick } 219f19eb154SVasily Khoruzhick #endif 220