1*ad5b5801SMichal Simek 2*ad5b5801SMichal Simek /****************************************************************************** 3*ad5b5801SMichal Simek * 4*ad5b5801SMichal Simek * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. 5*ad5b5801SMichal Simek * 6*ad5b5801SMichal Simek * SPDX-License-Identifier: GPL-2.0+ 7*ad5b5801SMichal Simek * 8*ad5b5801SMichal Simek * 9*ad5b5801SMichal Simek *******************************************************************************/ 10*ad5b5801SMichal Simek /****************************************************************************/ 11*ad5b5801SMichal Simek /** 12*ad5b5801SMichal Simek * 13*ad5b5801SMichal Simek * @file ps7_init.h 14*ad5b5801SMichal Simek * 15*ad5b5801SMichal Simek * This file can be included in FSBL code 16*ad5b5801SMichal Simek * to get prototype of ps7_init() function 17*ad5b5801SMichal Simek * and error codes 18*ad5b5801SMichal Simek * 19*ad5b5801SMichal Simek *****************************************************************************/ 20*ad5b5801SMichal Simek 21*ad5b5801SMichal Simek #ifdef __cplusplus 22*ad5b5801SMichal Simek extern "C" { 23*ad5b5801SMichal Simek #endif 24*ad5b5801SMichal Simek 25*ad5b5801SMichal Simek 26*ad5b5801SMichal Simek //typedef unsigned int u32; 27*ad5b5801SMichal Simek 28*ad5b5801SMichal Simek 29*ad5b5801SMichal Simek /** do we need to make this name more unique ? **/ 30*ad5b5801SMichal Simek //extern u32 ps7_init_data[]; 31*ad5b5801SMichal Simek extern unsigned long * ps7_ddr_init_data; 32*ad5b5801SMichal Simek extern unsigned long * ps7_mio_init_data; 33*ad5b5801SMichal Simek extern unsigned long * ps7_pll_init_data; 34*ad5b5801SMichal Simek extern unsigned long * ps7_clock_init_data; 35*ad5b5801SMichal Simek extern unsigned long * ps7_peripherals_init_data; 36*ad5b5801SMichal Simek 37*ad5b5801SMichal Simek 38*ad5b5801SMichal Simek 39*ad5b5801SMichal Simek #define OPCODE_EXIT 0U 40*ad5b5801SMichal Simek #define OPCODE_CLEAR 1U 41*ad5b5801SMichal Simek #define OPCODE_WRITE 2U 42*ad5b5801SMichal Simek #define OPCODE_MASKWRITE 3U 43*ad5b5801SMichal Simek #define OPCODE_MASKPOLL 4U 44*ad5b5801SMichal Simek #define OPCODE_MASKDELAY 5U 45*ad5b5801SMichal Simek #define NEW_PS7_ERR_CODE 1 46*ad5b5801SMichal Simek 47*ad5b5801SMichal Simek /* Encode number of arguments in last nibble */ 48*ad5b5801SMichal Simek #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) 49*ad5b5801SMichal Simek #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr 50*ad5b5801SMichal Simek #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val 51*ad5b5801SMichal Simek #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val 52*ad5b5801SMichal Simek #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask 53*ad5b5801SMichal Simek #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask 54*ad5b5801SMichal Simek 55*ad5b5801SMichal Simek /* Returns codes of PS7_Init */ 56*ad5b5801SMichal Simek #define PS7_INIT_SUCCESS (0) // 0 is success in good old C 57*ad5b5801SMichal Simek #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now 58*ad5b5801SMichal Simek #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out 59*ad5b5801SMichal Simek #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init 60*ad5b5801SMichal Simek #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit 61*ad5b5801SMichal Simek #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init 62*ad5b5801SMichal Simek 63*ad5b5801SMichal Simek 64*ad5b5801SMichal Simek /* Silicon Versions */ 65*ad5b5801SMichal Simek #define PCW_SILICON_VERSION_1 0 66*ad5b5801SMichal Simek #define PCW_SILICON_VERSION_2 1 67*ad5b5801SMichal Simek #define PCW_SILICON_VERSION_3 2 68*ad5b5801SMichal Simek 69*ad5b5801SMichal Simek /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ 70*ad5b5801SMichal Simek #define PS7_POST_CONFIG 71*ad5b5801SMichal Simek 72*ad5b5801SMichal Simek /* Freq of all peripherals */ 73*ad5b5801SMichal Simek 74*ad5b5801SMichal Simek #define APU_FREQ 666666687 75*ad5b5801SMichal Simek #define DDR_FREQ 533333374 76*ad5b5801SMichal Simek #define DCI_FREQ 10158731 77*ad5b5801SMichal Simek #define QSPI_FREQ 200000000 78*ad5b5801SMichal Simek #define SMC_FREQ 10000000 79*ad5b5801SMichal Simek #define ENET0_FREQ 125000000 80*ad5b5801SMichal Simek #define ENET1_FREQ 10000000 81*ad5b5801SMichal Simek #define USB0_FREQ 60000000 82*ad5b5801SMichal Simek #define USB1_FREQ 60000000 83*ad5b5801SMichal Simek #define SDIO_FREQ 50000000 84*ad5b5801SMichal Simek #define UART_FREQ 50000000 85*ad5b5801SMichal Simek #define SPI_FREQ 10000000 86*ad5b5801SMichal Simek #define I2C_FREQ 111111115 87*ad5b5801SMichal Simek #define WDT_FREQ 111111115 88*ad5b5801SMichal Simek #define TTC_FREQ 50000000 89*ad5b5801SMichal Simek #define CAN_FREQ 10000000 90*ad5b5801SMichal Simek #define PCAP_FREQ 200000000 91*ad5b5801SMichal Simek #define TPIU_FREQ 200000000 92*ad5b5801SMichal Simek #define FPGA0_FREQ 100000000 93*ad5b5801SMichal Simek #define FPGA1_FREQ 100000000 94*ad5b5801SMichal Simek #define FPGA2_FREQ 33333336 95*ad5b5801SMichal Simek #define FPGA3_FREQ 50000000 96*ad5b5801SMichal Simek 97*ad5b5801SMichal Simek 98*ad5b5801SMichal Simek /* For delay calculation using global registers*/ 99*ad5b5801SMichal Simek #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 100*ad5b5801SMichal Simek #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 101*ad5b5801SMichal Simek #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 102*ad5b5801SMichal Simek #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 103*ad5b5801SMichal Simek 104*ad5b5801SMichal Simek int ps7_config( unsigned long*); 105*ad5b5801SMichal Simek int ps7_init(); 106*ad5b5801SMichal Simek int ps7_post_config(); 107*ad5b5801SMichal Simek int ps7_debug(); 108*ad5b5801SMichal Simek char* getPS7MessageInfo(unsigned key); 109*ad5b5801SMichal Simek 110*ad5b5801SMichal Simek void perf_start_clock(void); 111*ad5b5801SMichal Simek void perf_disable_clock(void); 112*ad5b5801SMichal Simek void perf_reset_clock(void); 113*ad5b5801SMichal Simek void perf_reset_and_start_timer(); 114*ad5b5801SMichal Simek int get_number_of_cycles_for_delay(unsigned int delay); 115*ad5b5801SMichal Simek #ifdef __cplusplus 116*ad5b5801SMichal Simek } 117*ad5b5801SMichal Simek #endif 118