1 /* 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <fpga.h> 10 #include <mmc.h> 11 #include <zynqpl.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/sys_proto.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 18 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 19 static xilinx_desc fpga; 20 21 /* It can be done differently */ 22 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 23 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); 24 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 25 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 26 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); 27 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 28 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 29 #endif 30 31 int board_init(void) 32 { 33 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 34 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 35 u32 idcode; 36 37 idcode = zynq_slcr_get_idcode(); 38 39 switch (idcode) { 40 case XILINX_ZYNQ_7010: 41 fpga = fpga010; 42 break; 43 case XILINX_ZYNQ_7015: 44 fpga = fpga015; 45 break; 46 case XILINX_ZYNQ_7020: 47 fpga = fpga020; 48 break; 49 case XILINX_ZYNQ_7030: 50 fpga = fpga030; 51 break; 52 case XILINX_ZYNQ_7035: 53 fpga = fpga035; 54 break; 55 case XILINX_ZYNQ_7045: 56 fpga = fpga045; 57 break; 58 case XILINX_ZYNQ_7100: 59 fpga = fpga100; 60 break; 61 } 62 #endif 63 64 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 65 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 66 fpga_init(); 67 fpga_add(fpga_xilinx, &fpga); 68 #endif 69 70 return 0; 71 } 72 73 int board_late_init(void) 74 { 75 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 76 case ZYNQ_BM_NOR: 77 setenv("modeboot", "norboot"); 78 break; 79 case ZYNQ_BM_SD: 80 setenv("modeboot", "sdboot"); 81 break; 82 case ZYNQ_BM_JTAG: 83 setenv("modeboot", "jtagboot"); 84 break; 85 default: 86 setenv("modeboot", ""); 87 break; 88 } 89 90 return 0; 91 } 92 93 #ifdef CONFIG_DISPLAY_BOARDINFO 94 int checkboard(void) 95 { 96 puts("Board: Xilinx Zynq\n"); 97 return 0; 98 } 99 #endif 100 101 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 102 { 103 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 104 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) 105 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 106 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 107 ethaddr, 6)) 108 printf("I2C EEPROM MAC address read failed\n"); 109 #endif 110 111 return 0; 112 } 113 114 int dram_init(void) 115 { 116 int node; 117 fdt_addr_t addr; 118 fdt_size_t size; 119 const void *blob = gd->fdt_blob; 120 121 node = fdt_node_offset_by_prop_value(blob, -1, "device_type", 122 "memory", 7); 123 if (node == -FDT_ERR_NOTFOUND) { 124 debug("ZYNQ DRAM: Can't get memory node\n"); 125 return -1; 126 } 127 addr = fdtdec_get_addr_size(blob, node, "reg", &size); 128 if (addr == FDT_ADDR_T_NONE || size == 0) { 129 debug("ZYNQ DRAM: Can't get base address or size\n"); 130 return -1; 131 } 132 gd->ram_size = size; 133 zynq_ddrc_init(); 134 135 return 0; 136 } 137