1 /* 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <fdtdec.h> 9 #include <fpga.h> 10 #include <mmc.h> 11 #include <zynqpl.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/sys_proto.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 18 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 19 static xilinx_desc fpga; 20 21 /* It can be done differently */ 22 static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); 23 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 24 static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); 25 static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); 26 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); 27 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 28 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 29 static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); 30 static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 31 static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 32 #endif 33 34 int board_init(void) 35 { 36 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 37 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 38 u32 idcode; 39 40 idcode = zynq_slcr_get_idcode(); 41 42 switch (idcode) { 43 case XILINX_ZYNQ_7007S: 44 fpga = fpga007s; 45 break; 46 case XILINX_ZYNQ_7010: 47 fpga = fpga010; 48 break; 49 case XILINX_ZYNQ_7012S: 50 fpga = fpga012s; 51 break; 52 case XILINX_ZYNQ_7014S: 53 fpga = fpga014s; 54 break; 55 case XILINX_ZYNQ_7015: 56 fpga = fpga015; 57 break; 58 case XILINX_ZYNQ_7020: 59 fpga = fpga020; 60 break; 61 case XILINX_ZYNQ_7030: 62 fpga = fpga030; 63 break; 64 case XILINX_ZYNQ_7035: 65 fpga = fpga035; 66 break; 67 case XILINX_ZYNQ_7045: 68 fpga = fpga045; 69 break; 70 case XILINX_ZYNQ_7100: 71 fpga = fpga100; 72 break; 73 } 74 #endif 75 76 #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ 77 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) 78 fpga_init(); 79 fpga_add(fpga_xilinx, &fpga); 80 #endif 81 82 return 0; 83 } 84 85 int board_late_init(void) 86 { 87 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 88 case ZYNQ_BM_NOR: 89 setenv("modeboot", "norboot"); 90 break; 91 case ZYNQ_BM_SD: 92 setenv("modeboot", "sdboot"); 93 break; 94 case ZYNQ_BM_JTAG: 95 setenv("modeboot", "jtagboot"); 96 break; 97 default: 98 setenv("modeboot", ""); 99 break; 100 } 101 102 return 0; 103 } 104 105 #ifdef CONFIG_DISPLAY_BOARDINFO 106 int checkboard(void) 107 { 108 puts("Board: Xilinx Zynq\n"); 109 return 0; 110 } 111 #endif 112 113 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) 114 { 115 #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ 116 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) 117 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, 118 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, 119 ethaddr, 6)) 120 printf("I2C EEPROM MAC address read failed\n"); 121 #endif 122 123 return 0; 124 } 125 126 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) 127 static const void *get_memory_reg_prop(const void *fdt, int *lenp) 128 { 129 int offset; 130 131 offset = fdt_path_offset(fdt, "/memory"); 132 if (offset < 0) 133 return NULL; 134 135 return fdt_getprop(fdt, offset, "reg", lenp); 136 } 137 138 void dram_init_banksize(void) 139 { 140 const void *fdt = gd->fdt_blob; 141 const fdt32_t *val; 142 int ac, sc, cells, len, i; 143 144 val = get_memory_reg_prop(fdt, &len); 145 if (len < 0) 146 return; 147 148 ac = fdt_address_cells(fdt, 0); 149 sc = fdt_size_cells(fdt, 0); 150 if (ac < 1 || sc > 2 || sc < 1 || sc > 2) { 151 printf("invalid address/size cells\n"); 152 return; 153 } 154 155 cells = ac + sc; 156 157 len /= sizeof(*val); 158 159 for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells; 160 i++, len -= cells) { 161 gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac); 162 val += ac; 163 gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc); 164 val += sc; 165 166 debug("DRAM bank %d: start = %08lx, size = %08lx\n", 167 i, (unsigned long)gd->bd->bi_dram[i].start, 168 (unsigned long)gd->bd->bi_dram[i].size); 169 } 170 } 171 172 int dram_init(void) 173 { 174 const void *fdt = gd->fdt_blob; 175 const fdt32_t *val; 176 int ac, sc, len; 177 178 ac = fdt_address_cells(fdt, 0); 179 sc = fdt_size_cells(fdt, 0); 180 if (ac < 0 || sc < 1 || sc > 2) { 181 printf("invalid address/size cells\n"); 182 return -EINVAL; 183 } 184 185 val = get_memory_reg_prop(fdt, &len); 186 if (len / sizeof(*val) < ac + sc) 187 return -EINVAL; 188 189 val += ac; 190 191 gd->ram_size = fdtdec_get_number(val, sc); 192 193 debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size); 194 195 zynq_ddrc_init(); 196 197 return 0; 198 } 199 #else 200 int dram_init(void) 201 { 202 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 203 204 zynq_ddrc_init(); 205 206 return 0; 207 } 208 #endif 209