152a822edSMichal Simek /* 252a822edSMichal Simek * (C) Copyright 2007 Michal Simek 352a822edSMichal Simek * 452a822edSMichal Simek * Michal SIMEK <monstr@monstr.eu> 552a822edSMichal Simek * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 752a822edSMichal Simek * 820637888SStephan Linz * CAUTION: This file is a faked configuration !!! 920637888SStephan Linz * There is no real target for the microblaze-generic 1020637888SStephan Linz * configuration. You have to replace this file with 1120637888SStephan Linz * the generated file from your Xilinx design flow. 1252a822edSMichal Simek */ 1352a822edSMichal Simek 14330e5545SMichal Simek #define XILINX_BOARD_NAME microblaze-generic 15330e5545SMichal Simek 1652a822edSMichal Simek /* System Clock Frequency */ 1752a822edSMichal Simek #define XILINX_CLOCK_FREQ 100000000 1852a822edSMichal Simek 1952a822edSMichal Simek /* Microblaze is microblaze_0 */ 2052a822edSMichal Simek #define XILINX_USE_MSR_INSTR 1 2152a822edSMichal Simek #define XILINX_FSL_NUMBER 3 2252a822edSMichal Simek 2352a822edSMichal Simek /* Interrupt controller is opb_intc_0 */ 2452a822edSMichal Simek #define XILINX_INTC_BASEADDR 0x41200000 2552a822edSMichal Simek #define XILINX_INTC_NUM_INTR_INPUTS 6 2652a822edSMichal Simek 2752a822edSMichal Simek /* Timer pheriphery is opb_timer_1 */ 2852a822edSMichal Simek #define XILINX_TIMER_BASEADDR 0x41c00000 2952a822edSMichal Simek #define XILINX_TIMER_IRQ 0 3052a822edSMichal Simek 3152a822edSMichal Simek /* Uart pheriphery is RS232_Uart */ 3252a822edSMichal Simek #define XILINX_UARTLITE_BASEADDR 0x40600000 3352a822edSMichal Simek #define XILINX_UARTLITE_BAUDRATE 115200 3452a822edSMichal Simek 3552a822edSMichal Simek /* IIC pheriphery is IIC_EEPROM */ 3652a822edSMichal Simek #define XILINX_IIC_0_BASEADDR 0x40800000 3752a822edSMichal Simek #define XILINX_IIC_0_FREQ 100000 3852a822edSMichal Simek #define XILINX_IIC_0_BIT 0 3952a822edSMichal Simek 4052a822edSMichal Simek /* GPIO is LEDs_4Bit*/ 4152a822edSMichal Simek #define XILINX_GPIO_BASEADDR 0x40000000 4252a822edSMichal Simek 4352a822edSMichal Simek /* Flash Memory is FLASH_2Mx32 */ 4452a822edSMichal Simek #define XILINX_FLASH_START 0x2c000000 4552a822edSMichal Simek #define XILINX_FLASH_SIZE 0x00800000 4652a822edSMichal Simek 4752a822edSMichal Simek /* Main Memory is DDR_SDRAM_64Mx32 */ 4852a822edSMichal Simek #define XILINX_RAM_START 0x28000000 4952a822edSMichal Simek #define XILINX_RAM_SIZE 0x04000000 5052a822edSMichal Simek 5152a822edSMichal Simek /* Sysace Controller is SysACE_CompactFlash */ 5252a822edSMichal Simek #define XILINX_SYSACE_BASEADDR 0x41800000 5352a822edSMichal Simek #define XILINX_SYSACE_HIGHADDR 0x4180ffff 5452a822edSMichal Simek #define XILINX_SYSACE_MEM_WIDTH 16 5552a822edSMichal Simek 5652a822edSMichal Simek /* Ethernet controller is Ethernet_MAC */ 5752a822edSMichal Simek #define XILINX_EMACLITE_BASEADDR 0x40C00000 5820637888SStephan Linz 5920637888SStephan Linz /* LL_TEMAC Ethernet controller */ 6020637888SStephan Linz #define XILINX_LLTEMAC_BASEADDR 0x44000000 6120637888SStephan Linz #define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180 6220637888SStephan Linz #define XILINX_LLTEMAC_BASEADDR1 0x44200000 6320637888SStephan Linz #define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000 640f21f98dSMichal Simek 650f21f98dSMichal Simek /* Watchdog IP is wxi_timebase_wdt_0 */ 660f21f98dSMichal Simek #define XILINX_WATCHDOG_BASEADDR 0x50000000 670f21f98dSMichal Simek #define XILINX_WATCHDOG_IRQ 1 68