xref: /rk3399_rockchip-uboot/board/xilinx/microblaze-generic/microblaze-generic.c (revision 8848668e136cccb30229b5e1484d41e0b5a6830a)
1 /*
2  * (C) Copyright 2007 Michal Simek
3  *
4  * Michal  SIMEK <monstr@monstr.eu>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 /* This is a board specific file.  It's OK to include board specific
26  * header files */
27 
28 #include <common.h>
29 #include <config.h>
30 #include <netdev.h>
31 #include <asm/processor.h>
32 #include <asm/microblaze_intc.h>
33 #include <asm/asm.h>
34 
35 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
36 {
37 #ifdef CONFIG_SYS_GPIO_0
38 	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
39 	    ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
40 #endif
41 
42 	puts ("Reseting board\n");
43 	__asm__ __volatile__ ("	mts rmsr, r0;" \
44 				"bra r0");
45 
46 	return 0;
47 }
48 
49 int gpio_init (void)
50 {
51 #ifdef CONFIG_SYS_GPIO_0
52 	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF;
53 #endif
54 	return 0;
55 }
56 
57 void board_init(void)
58 {
59 	gpio_init();
60 }
61 
62 int board_eth_init(bd_t *bis)
63 {
64 	int ret = 0;
65 
66 #ifdef CONFIG_XILINX_AXIEMAC
67 	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
68 						XILINX_AXIDMA_BASEADDR);
69 #endif
70 
71 #ifdef CONFIG_XILINX_EMACLITE
72 	u32 txpp = 0;
73 	u32 rxpp = 0;
74 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
75 	txpp = 1;
76 # endif
77 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
78 	rxpp = 1;
79 # endif
80 	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
81 			txpp, rxpp);
82 #endif
83 
84 #ifdef CONFIG_XILINX_LL_TEMAC
85 # ifdef XILINX_LLTEMAC_BASEADDR
86 #  ifdef XILINX_LLTEMAC_FIFO_BASEADDR
87 	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
88 			XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
89 #  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
90 #   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
91 	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
92 			XILINX_LL_TEMAC_M_SDMA_DCR,
93 			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
94 #   else
95 	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
96 			XILINX_LL_TEMAC_M_SDMA_PLB,
97 			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
98 #   endif
99 #  endif
100 # endif
101 # ifdef XILINX_LLTEMAC_BASEADDR1
102 #  ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
103 	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
104 			XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
105 #  elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
106 #   if XILINX_LLTEMAC_SDMA_USE_DCR == 1
107 	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
108 			XILINX_LL_TEMAC_M_SDMA_DCR,
109 			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
110 #   else
111 	ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
112 			XILINX_LL_TEMAC_M_SDMA_PLB,
113 			XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
114 #   endif
115 #  endif
116 # endif
117 #endif
118 
119 	return ret;
120 }
121