152a822edSMichal Simek /* 252a822edSMichal Simek * (C) Copyright 2007 Michal Simek 352a822edSMichal Simek * 452a822edSMichal Simek * Michal SIMEK <monstr@monstr.eu> 552a822edSMichal Simek * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 752a822edSMichal Simek */ 852a822edSMichal Simek 952a822edSMichal Simek /* This is a board specific file. It's OK to include board specific 1052a822edSMichal Simek * header files */ 1152a822edSMichal Simek 1252a822edSMichal Simek #include <common.h> 1352a822edSMichal Simek #include <config.h> 14e945f6dcSMichal Simek #include <fdtdec.h> 15d69f8f41SMichal Simek #include <netdev.h> 162380b8f5SMichal Simek #include <asm/processor.h> 1752a822edSMichal Simek #include <asm/microblaze_intc.h> 1852a822edSMichal Simek #include <asm/asm.h> 194e779ad2SMichal Simek #include <asm/gpio.h> 204e779ad2SMichal Simek 21e945f6dcSMichal Simek DECLARE_GLOBAL_DATA_PTR; 22e945f6dcSMichal Simek 234e779ad2SMichal Simek #ifdef CONFIG_XILINX_GPIO 244e779ad2SMichal Simek static int reset_pin = -1; 254e779ad2SMichal Simek #endif 2652a822edSMichal Simek 270f925822SMasahiro Yamada #if CONFIG_IS_ENABLED(OF_CONTROL) 28e945f6dcSMichal Simek ulong ram_base; 29e945f6dcSMichal Simek 30e945f6dcSMichal Simek void dram_init_banksize(void) 31e945f6dcSMichal Simek { 32e945f6dcSMichal Simek gd->bd->bi_dram[0].start = ram_base; 33e945f6dcSMichal Simek gd->bd->bi_dram[0].size = get_effective_memsize(); 34e945f6dcSMichal Simek } 35e945f6dcSMichal Simek 36e945f6dcSMichal Simek int dram_init(void) 37e945f6dcSMichal Simek { 38e945f6dcSMichal Simek int node; 39e945f6dcSMichal Simek fdt_addr_t addr; 40e945f6dcSMichal Simek fdt_size_t size; 41e945f6dcSMichal Simek const void *blob = gd->fdt_blob; 42e945f6dcSMichal Simek 43e945f6dcSMichal Simek node = fdt_node_offset_by_prop_value(blob, -1, "device_type", 44e945f6dcSMichal Simek "memory", 7); 45e945f6dcSMichal Simek if (node == -FDT_ERR_NOTFOUND) { 46e945f6dcSMichal Simek debug("DRAM: Can't get memory node\n"); 47e945f6dcSMichal Simek return 1; 48e945f6dcSMichal Simek } 49e945f6dcSMichal Simek addr = fdtdec_get_addr_size(blob, node, "reg", &size); 50e945f6dcSMichal Simek if (addr == FDT_ADDR_T_NONE || size == 0) { 51e945f6dcSMichal Simek debug("DRAM: Can't get base address or size\n"); 52e945f6dcSMichal Simek return 1; 53e945f6dcSMichal Simek } 54e945f6dcSMichal Simek ram_base = addr; 55e945f6dcSMichal Simek 56e945f6dcSMichal Simek gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */ 57e945f6dcSMichal Simek gd->ram_size = size; 58e945f6dcSMichal Simek 59e945f6dcSMichal Simek return 0; 60e945f6dcSMichal Simek }; 61e945f6dcSMichal Simek #else 62e945f6dcSMichal Simek int dram_init(void) 63e945f6dcSMichal Simek { 64e945f6dcSMichal Simek gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 65e945f6dcSMichal Simek 66e945f6dcSMichal Simek return 0; 67e945f6dcSMichal Simek } 68e945f6dcSMichal Simek #endif 69e945f6dcSMichal Simek 70882b7d72SMike Frysinger int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 7152a822edSMichal Simek { 72*b5e9b9a9SMichal Simek #ifndef CONFIG_SPL_BUILD 734e779ad2SMichal Simek #ifdef CONFIG_XILINX_GPIO 744e779ad2SMichal Simek if (reset_pin != -1) 754e779ad2SMichal Simek gpio_direction_output(reset_pin, 1); 7652a822edSMichal Simek #endif 77b364727aSMichal Simek 780f21f98dSMichal Simek #ifdef CONFIG_XILINX_TB_WATCHDOG 790f21f98dSMichal Simek hw_watchdog_disable(); 800f21f98dSMichal Simek #endif 81*b5e9b9a9SMichal Simek #endif 8252a822edSMichal Simek puts ("Reseting board\n"); 838848668eSMichal Simek __asm__ __volatile__ (" mts rmsr, r0;" \ 848848668eSMichal Simek "bra r0"); 85b364727aSMichal Simek 86882b7d72SMike Frysinger return 0; 8752a822edSMichal Simek } 8852a822edSMichal Simek 8952a822edSMichal Simek int gpio_init (void) 9052a822edSMichal Simek { 914e779ad2SMichal Simek #ifdef CONFIG_XILINX_GPIO 924e779ad2SMichal Simek reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); 934e779ad2SMichal Simek if (reset_pin != -1) 944e779ad2SMichal Simek gpio_request(reset_pin, "reset_pin"); 9552a822edSMichal Simek #endif 9652a822edSMichal Simek return 0; 9752a822edSMichal Simek } 9852a822edSMichal Simek 992380b8f5SMichal Simek void board_init(void) 1002380b8f5SMichal Simek { 1012380b8f5SMichal Simek gpio_init(); 1022380b8f5SMichal Simek } 1032380b8f5SMichal Simek 104d69f8f41SMichal Simek int board_eth_init(bd_t *bis) 105d69f8f41SMichal Simek { 106c1044a1eSMichal Simek int ret = 0; 107e634138eSMichal Simek 108e634138eSMichal Simek #ifdef CONFIG_XILINX_AXIEMAC 109e634138eSMichal Simek ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, 110e634138eSMichal Simek XILINX_AXIDMA_BASEADDR); 111e634138eSMichal Simek #endif 112e634138eSMichal Simek 113127e8a5eSNathan Rossi #if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR) 114c1044a1eSMichal Simek u32 txpp = 0; 115c1044a1eSMichal Simek u32 rxpp = 0; 116c1044a1eSMichal Simek # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 117c1044a1eSMichal Simek txpp = 1; 118d69f8f41SMichal Simek # endif 119c1044a1eSMichal Simek # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 120c1044a1eSMichal Simek rxpp = 1; 121c1044a1eSMichal Simek # endif 122c1044a1eSMichal Simek ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, 123c1044a1eSMichal Simek txpp, rxpp); 124c1044a1eSMichal Simek #endif 1253ceecef1SStephan Linz 126c1044a1eSMichal Simek return ret; 127d69f8f41SMichal Simek } 128