152a822edSMichal Simek /* 252a822edSMichal Simek * (C) Copyright 2007 Michal Simek 352a822edSMichal Simek * 452a822edSMichal Simek * Michal SIMEK <monstr@monstr.eu> 552a822edSMichal Simek * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 752a822edSMichal Simek */ 852a822edSMichal Simek 952a822edSMichal Simek /* This is a board specific file. It's OK to include board specific 1052a822edSMichal Simek * header files */ 1152a822edSMichal Simek 1252a822edSMichal Simek #include <common.h> 1352a822edSMichal Simek #include <config.h> 14e945f6dcSMichal Simek #include <fdtdec.h> 152380b8f5SMichal Simek #include <asm/processor.h> 1652a822edSMichal Simek #include <asm/microblaze_intc.h> 1752a822edSMichal Simek #include <asm/asm.h> 184e779ad2SMichal Simek #include <asm/gpio.h> 194e779ad2SMichal Simek 20e945f6dcSMichal Simek DECLARE_GLOBAL_DATA_PTR; 21e945f6dcSMichal Simek 224e779ad2SMichal Simek #ifdef CONFIG_XILINX_GPIO 234e779ad2SMichal Simek static int reset_pin = -1; 244e779ad2SMichal Simek #endif 2552a822edSMichal Simek 26e945f6dcSMichal Simek ulong ram_base; 27e945f6dcSMichal Simek 28e945f6dcSMichal Simek void dram_init_banksize(void) 29e945f6dcSMichal Simek { 30e945f6dcSMichal Simek gd->bd->bi_dram[0].start = ram_base; 31e945f6dcSMichal Simek gd->bd->bi_dram[0].size = get_effective_memsize(); 32e945f6dcSMichal Simek } 33e945f6dcSMichal Simek 34e945f6dcSMichal Simek int dram_init(void) 35e945f6dcSMichal Simek { 36e945f6dcSMichal Simek int node; 37e945f6dcSMichal Simek fdt_addr_t addr; 38e945f6dcSMichal Simek fdt_size_t size; 39e945f6dcSMichal Simek const void *blob = gd->fdt_blob; 40e945f6dcSMichal Simek 41e945f6dcSMichal Simek node = fdt_node_offset_by_prop_value(blob, -1, "device_type", 42e945f6dcSMichal Simek "memory", 7); 43e945f6dcSMichal Simek if (node == -FDT_ERR_NOTFOUND) { 44e945f6dcSMichal Simek debug("DRAM: Can't get memory node\n"); 45e945f6dcSMichal Simek return 1; 46e945f6dcSMichal Simek } 47e945f6dcSMichal Simek addr = fdtdec_get_addr_size(blob, node, "reg", &size); 48e945f6dcSMichal Simek if (addr == FDT_ADDR_T_NONE || size == 0) { 49e945f6dcSMichal Simek debug("DRAM: Can't get base address or size\n"); 50e945f6dcSMichal Simek return 1; 51e945f6dcSMichal Simek } 52e945f6dcSMichal Simek ram_base = addr; 53e945f6dcSMichal Simek 54e945f6dcSMichal Simek gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */ 55e945f6dcSMichal Simek gd->ram_size = size; 56e945f6dcSMichal Simek 57e945f6dcSMichal Simek return 0; 58e945f6dcSMichal Simek }; 59e945f6dcSMichal Simek 60882b7d72SMike Frysinger int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 6152a822edSMichal Simek { 62b5e9b9a9SMichal Simek #ifndef CONFIG_SPL_BUILD 634e779ad2SMichal Simek #ifdef CONFIG_XILINX_GPIO 644e779ad2SMichal Simek if (reset_pin != -1) 654e779ad2SMichal Simek gpio_direction_output(reset_pin, 1); 6652a822edSMichal Simek #endif 67b364727aSMichal Simek 680f21f98dSMichal Simek #ifdef CONFIG_XILINX_TB_WATCHDOG 690f21f98dSMichal Simek hw_watchdog_disable(); 700f21f98dSMichal Simek #endif 71b5e9b9a9SMichal Simek #endif 7252a822edSMichal Simek puts ("Reseting board\n"); 738848668eSMichal Simek __asm__ __volatile__ (" mts rmsr, r0;" \ 748848668eSMichal Simek "bra r0"); 75b364727aSMichal Simek 76882b7d72SMike Frysinger return 0; 7752a822edSMichal Simek } 7852a822edSMichal Simek 79*38c4761cSMichal Simek static int gpio_init(void) 8052a822edSMichal Simek { 814e779ad2SMichal Simek #ifdef CONFIG_XILINX_GPIO 824e779ad2SMichal Simek reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1); 834e779ad2SMichal Simek if (reset_pin != -1) 844e779ad2SMichal Simek gpio_request(reset_pin, "reset_pin"); 8552a822edSMichal Simek #endif 8652a822edSMichal Simek return 0; 8752a822edSMichal Simek } 8852a822edSMichal Simek 89*38c4761cSMichal Simek int board_late_init(void) 902380b8f5SMichal Simek { 912380b8f5SMichal Simek gpio_init(); 92*38c4761cSMichal Simek 93*38c4761cSMichal Simek return 0; 942380b8f5SMichal Simek } 95