1 /* 2 * Copyright 2008 Extreme Engineering Solutions, Inc. 3 * Copyright 2008 Freescale Semiconductor, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <i2c.h> 26 27 #include <asm/fsl_ddr_sdram.h> 28 #include <asm/fsl_ddr_dimm_params.h> 29 30 static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) 31 { 32 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, 33 sizeof(ddr2_spd_eeprom_t)); 34 } 35 36 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, 37 unsigned int ctrl_num) 38 { 39 unsigned int i; 40 unsigned int i2c_address = 0; 41 42 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 43 if (ctrl_num == 0) 44 i2c_address = SPD_EEPROM_ADDRESS1; 45 if (ctrl_num == 1) 46 i2c_address = SPD_EEPROM_ADDRESS2; 47 get_spd(&(ctrl_dimms_spd[i]), i2c_address); 48 } 49 } 50 51 /* 52 * There are four board-specific SDRAM timing parameters which must be 53 * calculated based on the particular PCB artwork. These are: 54 * 1.) CPO (Read Capture Delay) 55 * - TIMING_CFG_2 register 56 * Source: Calculation based on board trace lengths and 57 * chip-specific internal delays. 58 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) 59 * - TIMING_CFG_2 register 60 * Source: Calculation based on board trace lengths. 61 * Unless clock and DQ lanes are very different 62 * lengths (>2"), this should be set to the nominal value 63 * of 1/2 clock delay. 64 * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) 65 * - DDR_SDRAM_CLK_CNTL register 66 * Source: Signal Integrity Simulations 67 * 4.) 2T Timing on Addr/Ctl 68 * - TIMING_CFG_2 register 69 * Source: Signal Integrity Simulations 70 * Usually only needed with heavy load/very high speed (>DDR2-800) 71 * 72 * ====== XPedite5370 DDR2-600 read delay calculations ====== 73 * 74 * See Freescale's App Note AN2583 as refrence. This document also 75 * contains the chip-specific delays for 8548E, 8572, etc. 76 * 77 * For MPC8572E 78 * Minimum chip delay (Ch 0): 1.372ns 79 * Maximum chip delay (Ch 0): 2.914ns 80 * Minimum chip delay (Ch 1): 1.220ns 81 * Maximum chip delay (Ch 1): 2.595ns 82 * 83 * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps 84 * 85 * Minimum delay calc (Ch 0): 86 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly 87 * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps 88 * = 3808ps 89 * = 3.808ns 90 * 91 * Maximum delay calc (Ch 0): 92 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly 93 * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps 94 * = 6240ps 95 * = 6.240ns 96 * 97 * Minimum delay calc (Ch 1): 98 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly 99 * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps 100 * = 3288ps 101 * = 3.288ns 102 * 103 * Maximum delay calc (Ch 1): 104 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly 105 * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps 106 * = 5536ps 107 * = 5.536ns 108 * 109 * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target) 110 * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) 111 * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target) 112 * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7) 113 * 114 * 115 * ====== XPedite5370 DDR2-800 read delay calculations ====== 116 * 117 * See Freescale's App Note AN2583 as refrence. This document also 118 * contains the chip-specific delays for 8548E, 8572, etc. 119 * 120 * For MPC8572E 121 * Minimum chip delay (Ch 0): 1.372ns 122 * Maximum chip delay (Ch 0): 2.914ns 123 * Minimum chip delay (Ch 1): 1.220ns 124 * Maximum chip delay (Ch 1): 2.595ns 125 * 126 * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps 127 * 128 * Minimum delay calc (Ch 0): 129 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly 130 * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps 131 * = 3341ps 132 * = 3.341ns 133 * 134 * Maximum delay calc (Ch 0): 135 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly 136 * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps 137 * = 5673ps 138 * = 5.673ns 139 * 140 * Minimum delay calc (Ch 1): 141 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly 142 * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps 143 * = 2822ps 144 * = 2.822ns 145 * 146 * Maximum delay calc (Ch 1): 147 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly 148 * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps 149 * = 4968ps 150 * = 4.968ns 151 * 152 * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target) 153 * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9) 154 * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target) 155 * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) 156 * 157 * Write latency (WR_DATA_DELAY) is calculated by doing the following: 158 * 159 * The DDR SDRAM specification requires DQS be received no sooner than 160 * 75% of an SDRAM clock period—and no later than 125% of a clock 161 * period—from the capturing clock edge of the command/address at the 162 * SDRAM. 163 * 164 * Based on the above tracelengths, the following are calculated: 165 * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns 166 * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns 167 * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns 168 * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns 169 * 170 * Difference in arrival time CLK vs. DQS: 171 * Ch. 0 0.072ns 172 * Ch. 1 0.138ns 173 * 174 * Both of these values are much less than 25% of the clock 175 * period at DDR2-600 or DDR2-800, so no additional delay is needed over 176 * the 1/2 cycle which normally aligns the first DQS transition 177 * exactly WL (CAS latency minus one cycle) after the CAS strobe. 178 * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's 179 * terminology corresponds to exactly one clock period delay after 180 * the CAS strobe. (due to the fact that the "delay" is referenced 181 * from the *falling* edge of the CLK, just after the rising edge 182 * which the CAS strobe is latched on. 183 */ 184 185 typedef struct board_memctl_options { 186 uint16_t datarate_mhz_low; 187 uint16_t datarate_mhz_high; 188 uint8_t clk_adjust; 189 uint8_t cpo_override; 190 uint8_t write_data_delay; 191 } board_memctl_options_t; 192 193 static struct board_memctl_options bopts_ctrl[][2] = { 194 { 195 /* Controller 0 */ 196 { 197 /* DDR2 600/667 */ 198 .datarate_mhz_low = 500, 199 .datarate_mhz_high = 750, 200 .clk_adjust = 5, 201 .cpo_override = 8, 202 .write_data_delay = 2, 203 }, 204 { 205 /* DDR2 800 */ 206 .datarate_mhz_low = 750, 207 .datarate_mhz_high = 850, 208 .clk_adjust = 5, 209 .cpo_override = 9, 210 .write_data_delay = 2, 211 }, 212 }, 213 { 214 /* Controller 1 */ 215 { 216 /* DDR2 600/667 */ 217 .datarate_mhz_low = 500, 218 .datarate_mhz_high = 750, 219 .clk_adjust = 5, 220 .cpo_override = 7, 221 .write_data_delay = 2, 222 }, 223 { 224 /* DDR2 800 */ 225 .datarate_mhz_low = 750, 226 .datarate_mhz_high = 850, 227 .clk_adjust = 5, 228 .cpo_override = 8, 229 .write_data_delay = 2, 230 }, 231 }, 232 }; 233 234 void fsl_ddr_board_options(memctl_options_t *popts, 235 dimm_params_t *pdimm, 236 unsigned int ctrl_num) 237 { 238 struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; 239 sys_info_t sysinfo; 240 int i; 241 unsigned int datarate; 242 243 get_sys_info(&sysinfo); 244 datarate = sysinfo.freqDDRBus / 1000 / 1000; 245 246 for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { 247 if ((bopts[i].datarate_mhz_low <= datarate) && 248 (bopts[i].datarate_mhz_high >= datarate)) { 249 debug("controller %d:\n", ctrl_num); 250 debug(" clk_adjust = %d\n", bopts[i].clk_adjust); 251 debug(" cpo = %d\n", bopts[i].cpo_override); 252 debug(" write_data_delay = %d\n", 253 bopts[i].write_data_delay); 254 popts->clk_adjust = bopts[i].clk_adjust; 255 popts->cpo_override = bopts[i].cpo_override; 256 popts->write_data_delay = bopts[i].write_data_delay; 257 } 258 } 259 260 /* 261 * Factors to consider for half-strength driver enable: 262 * - number of DIMMs installed 263 */ 264 popts->half_strength_driver_enable = 0; 265 } 266