1c00ac259SPeter Tyser /* 2c00ac259SPeter Tyser * Copyright 2008 Extreme Engineering Solutions, Inc. 3c00ac259SPeter Tyser * Copyright 2008 Freescale Semiconductor, Inc. 4c00ac259SPeter Tyser * 5c00ac259SPeter Tyser * (C) Copyright 2000 6c00ac259SPeter Tyser * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7c00ac259SPeter Tyser * 8*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9c00ac259SPeter Tyser */ 10c00ac259SPeter Tyser 11c00ac259SPeter Tyser #include <common.h> 12c00ac259SPeter Tyser #include <asm/mmu.h> 13c00ac259SPeter Tyser 14c00ac259SPeter Tyser struct fsl_e_tlb_entry tlb_table[] = { 15c00ac259SPeter Tyser /* TLB 0 - for temp stack in cache */ 16c00ac259SPeter Tyser SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 17c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, 0, 18c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_4K, 0), 19c00ac259SPeter Tyser SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 20c00ac259SPeter Tyser CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 21c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, 0, 22c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_4K, 0), 23c00ac259SPeter Tyser SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 24c00ac259SPeter Tyser CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 25c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, 0, 26c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_4K, 0), 27c00ac259SPeter Tyser SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 28c00ac259SPeter Tyser CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 29c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, 0, 30c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_4K, 0), 31c00ac259SPeter Tyser 32c00ac259SPeter Tyser /* W**G* - NOR flashes */ 33c00ac259SPeter Tyser /* This will be changed to *I*G* after relocation to RAM. */ 34c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, 35c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 36c00ac259SPeter Tyser 0, 0, BOOKE_PAGESZ_256M, 1), 37c00ac259SPeter Tyser 38c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 39c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 40c00ac259SPeter Tyser 0, 1, BOOKE_PAGESZ_1M, 1), 41c00ac259SPeter Tyser 42c00ac259SPeter Tyser /* *I*G* - NAND flash */ 43c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, 44c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 45c00ac259SPeter Tyser 0, 2, BOOKE_PAGESZ_1M, 1), 46c00ac259SPeter Tyser 47c00ac259SPeter Tyser #if CONFIG_PCI1 48c00ac259SPeter Tyser /* *I*G* - PCI MEM */ 49c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, 50c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51c00ac259SPeter Tyser 0, 3, BOOKE_PAGESZ_1G, 1), 52c00ac259SPeter Tyser #endif 53c00ac259SPeter Tyser 54c00ac259SPeter Tyser #if CONFIG_PCI2 55c00ac259SPeter Tyser /* *I*G* - PCI MEM */ 56c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, 57c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 58c00ac259SPeter Tyser 0, 4, BOOKE_PAGESZ_256M, 1), 59c00ac259SPeter Tyser #endif 60c00ac259SPeter Tyser 61c00ac259SPeter Tyser #if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) 62c00ac259SPeter Tyser /* *I*G* - PCI IO */ 63c00ac259SPeter Tyser SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, 64c00ac259SPeter Tyser MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 65c00ac259SPeter Tyser 0, 5, BOOKE_PAGESZ_16M, 1), 66c00ac259SPeter Tyser #endif 67c00ac259SPeter Tyser }; 68c00ac259SPeter Tyser 69c00ac259SPeter Tyser int num_tlb_entries = ARRAY_SIZE(tlb_table); 70