1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12 #include <asm/arch/clock.h> 13 #include <asm/arch/iomux.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/imx-common/iomux-v3.h> 19 #include <asm/io.h> 20 #include <asm/sizes.h> 21 #include <common.h> 22 #include <fsl_esdhc.h> 23 #include <mmc.h> 24 #include <miiphy.h> 25 #include <netdev.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 30 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 31 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 32 33 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 34 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 35 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 36 37 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 38 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 39 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 40 41 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) 42 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) 43 44 int dram_init(void) 45 { 46 gd->ram_size = CONFIG_DDR_MB * SZ_1M; 47 48 return 0; 49 } 50 51 static iomux_v3_cfg_t const uart1_pads[] = { 52 MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), 53 MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), 54 }; 55 56 static iomux_v3_cfg_t const usdhc3_pads[] = { 57 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 58 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 59 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 60 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 61 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 62 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 63 /* SOM MicroSD Card Detect */ 64 MX6_PAD_EIM_DA9__GPIO_3_9 | MUX_PAD_CTRL(NO_PAD_CTRL), 65 }; 66 67 static iomux_v3_cfg_t const enet_pads[] = { 68 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 69 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 70 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 71 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 72 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 73 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 74 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 75 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 76 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 77 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 78 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 /* AR8031 PHY Reset */ 84 MX6_PAD_EIM_D29__GPIO_3_29 | MUX_PAD_CTRL(NO_PAD_CTRL), 85 }; 86 87 static void setup_iomux_uart(void) 88 { 89 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 90 } 91 92 static void setup_iomux_enet(void) 93 { 94 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 95 96 /* Reset AR8031 PHY */ 97 gpio_direction_output(ETH_PHY_RESET, 0); 98 udelay(500); 99 gpio_set_value(ETH_PHY_RESET, 1); 100 } 101 102 static struct fsl_esdhc_cfg usdhc_cfg[1] = { 103 {USDHC3_BASE_ADDR}, 104 }; 105 106 int board_mmc_getcd(struct mmc *mmc) 107 { 108 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 109 int ret = 0; 110 111 switch (cfg->esdhc_base) { 112 case USDHC3_BASE_ADDR: 113 ret = !gpio_get_value(USDHC3_CD_GPIO); 114 break; 115 } 116 117 return ret; 118 } 119 120 int board_mmc_init(bd_t *bis) 121 { 122 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 123 124 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 125 usdhc_cfg[0].max_bus_width = 4; 126 gpio_direction_input(USDHC3_CD_GPIO); 127 128 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 129 } 130 131 static int mx6_rgmii_rework(struct phy_device *phydev) 132 { 133 unsigned short val; 134 135 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 136 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 137 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 138 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 139 140 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 141 val &= 0xffe3; 142 val |= 0x18; 143 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 144 145 /* introduce tx clock delay */ 146 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 147 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 148 val |= 0x0100; 149 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 150 151 return 0; 152 } 153 154 int board_phy_config(struct phy_device *phydev) 155 { 156 mx6_rgmii_rework(phydev); 157 158 if (phydev->drv->config) 159 phydev->drv->config(phydev); 160 161 return 0; 162 } 163 164 int board_eth_init(bd_t *bis) 165 { 166 int ret; 167 168 setup_iomux_enet(); 169 170 ret = cpu_eth_init(bis); 171 if (ret) 172 printf("FEC MXC: %s:failed\n", __func__); 173 174 return 0; 175 } 176 177 int board_early_init_f(void) 178 { 179 setup_iomux_uart(); 180 return 0; 181 } 182 183 int board_init(void) 184 { 185 /* address of boot parameters */ 186 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 187 188 return 0; 189 } 190 191 int checkboard(void) 192 { 193 puts("Board: Wandboard\n"); 194 195 return 0; 196 } 197