1*80b9c3bbSStefan Agner /*
2*80b9c3bbSStefan Agner * Copyright 2017 Toradex AG
3*80b9c3bbSStefan Agner *
4*80b9c3bbSStefan Agner * FSL DCU platform driver
5*80b9c3bbSStefan Agner * SPDX-License-Identifier: GPL-2.0+
6*80b9c3bbSStefan Agner */
7*80b9c3bbSStefan Agner
8*80b9c3bbSStefan Agner #include <asm/arch/crm_regs.h>
9*80b9c3bbSStefan Agner #include <asm/io.h>
10*80b9c3bbSStefan Agner #include <common.h>
11*80b9c3bbSStefan Agner #include <fsl_dcu_fb.h>
12*80b9c3bbSStefan Agner #include "div64.h"
13*80b9c3bbSStefan Agner
14*80b9c3bbSStefan Agner DECLARE_GLOBAL_DATA_PTR;
15*80b9c3bbSStefan Agner
dcu_set_pixel_clock(unsigned int pixclock)16*80b9c3bbSStefan Agner unsigned int dcu_set_pixel_clock(unsigned int pixclock)
17*80b9c3bbSStefan Agner {
18*80b9c3bbSStefan Agner struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
19*80b9c3bbSStefan Agner unsigned long long div;
20*80b9c3bbSStefan Agner
21*80b9c3bbSStefan Agner clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
22*80b9c3bbSStefan Agner clrsetbits_le32(&ccm->cscdr3,
23*80b9c3bbSStefan Agner CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
24*80b9c3bbSStefan Agner CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
25*80b9c3bbSStefan Agner div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
26*80b9c3bbSStefan Agner do_div(div, pixclock);
27*80b9c3bbSStefan Agner
28*80b9c3bbSStefan Agner return div;
29*80b9c3bbSStefan Agner }
30*80b9c3bbSStefan Agner
platform_dcu_init(unsigned int xres,unsigned int yres,const char * port,struct fb_videomode * dcu_fb_videomode)31*80b9c3bbSStefan Agner int platform_dcu_init(unsigned int xres, unsigned int yres,
32*80b9c3bbSStefan Agner const char *port,
33*80b9c3bbSStefan Agner struct fb_videomode *dcu_fb_videomode)
34*80b9c3bbSStefan Agner {
35*80b9c3bbSStefan Agner fsl_dcu_init(xres, yres, 32);
36*80b9c3bbSStefan Agner
37*80b9c3bbSStefan Agner return 0;
38*80b9c3bbSStefan Agner }
39