1*f38f5f4bSMarcel Ziswiler /* 2*f38f5f4bSMarcel Ziswiler * Copyright (c) 2012-2016 Toradex, Inc. 3*f38f5f4bSMarcel Ziswiler * 4*f38f5f4bSMarcel Ziswiler * SPDX-License-Identifier: GPL-2.0+ 5*f38f5f4bSMarcel Ziswiler */ 6*f38f5f4bSMarcel Ziswiler 7*f38f5f4bSMarcel Ziswiler /* AS3722-PMIC-specific early init regs */ 8*f38f5f4bSMarcel Ziswiler 9*f38f5f4bSMarcel Ziswiler #define AS3722_I2C_ADDR 0x80 10*f38f5f4bSMarcel Ziswiler 11*f38f5f4bSMarcel Ziswiler #define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */ 12*f38f5f4bSMarcel Ziswiler #define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */ 13*f38f5f4bSMarcel Ziswiler #define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */ 14*f38f5f4bSMarcel Ziswiler #define AS3722_SDCONTROL_REG 0x4D 15*f38f5f4bSMarcel Ziswiler 16*f38f5f4bSMarcel Ziswiler #define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */ 17*f38f5f4bSMarcel Ziswiler #define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */ 18*f38f5f4bSMarcel Ziswiler #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */ 19*f38f5f4bSMarcel Ziswiler #define AS3722_LDCONTROL_REG 0x4E 20*f38f5f4bSMarcel Ziswiler 21*f38f5f4bSMarcel Ziswiler #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG) 22*f38f5f4bSMarcel Ziswiler #define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG) 23*f38f5f4bSMarcel Ziswiler 24*f38f5f4bSMarcel Ziswiler #define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG) 25*f38f5f4bSMarcel Ziswiler #define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG) 26*f38f5f4bSMarcel Ziswiler 27*f38f5f4bSMarcel Ziswiler #define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG) 28*f38f5f4bSMarcel Ziswiler #define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG) 29*f38f5f4bSMarcel Ziswiler 30*f38f5f4bSMarcel Ziswiler #define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG) 31*f38f5f4bSMarcel Ziswiler #define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG) 32*f38f5f4bSMarcel Ziswiler 33*f38f5f4bSMarcel Ziswiler #define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG) 34*f38f5f4bSMarcel Ziswiler #define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG) 35*f38f5f4bSMarcel Ziswiler 36*f38f5f4bSMarcel Ziswiler #define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG) 37*f38f5f4bSMarcel Ziswiler #define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG) 38*f38f5f4bSMarcel Ziswiler 39*f38f5f4bSMarcel Ziswiler #define I2C_SEND_2_BYTES 0x0A02 40*f38f5f4bSMarcel Ziswiler 41*f38f5f4bSMarcel Ziswiler void pmic_enable_cpu_vdd(void); 42