1f38f5f4bSMarcel Ziswiler /*
2f38f5f4bSMarcel Ziswiler * Copyright (c) 2016 Toradex, Inc.
3f38f5f4bSMarcel Ziswiler *
4f38f5f4bSMarcel Ziswiler * SPDX-License-Identifier: GPL-2.0+
5f38f5f4bSMarcel Ziswiler */
6f38f5f4bSMarcel Ziswiler
7f38f5f4bSMarcel Ziswiler #include <common.h>
8f38f5f4bSMarcel Ziswiler #include <asm/arch-tegra/ap.h>
9f38f5f4bSMarcel Ziswiler #include <asm/gpio.h>
10f38f5f4bSMarcel Ziswiler #include <asm/io.h>
11f38f5f4bSMarcel Ziswiler #include <asm/arch/gpio.h>
12f38f5f4bSMarcel Ziswiler #include <asm/arch/pinmux.h>
13f38f5f4bSMarcel Ziswiler #include <power/as3722.h>
14f38f5f4bSMarcel Ziswiler
15f38f5f4bSMarcel Ziswiler #include "../common/tdx-common.h"
16f38f5f4bSMarcel Ziswiler #include "pinmux-config-apalis-tk1.h"
17f38f5f4bSMarcel Ziswiler
18f38f5f4bSMarcel Ziswiler #define LAN_RESET_N TEGRA_GPIO(S, 2)
19f38f5f4bSMarcel Ziswiler
arch_misc_init(void)20f38f5f4bSMarcel Ziswiler int arch_misc_init(void)
21f38f5f4bSMarcel Ziswiler {
22f38f5f4bSMarcel Ziswiler if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
23f38f5f4bSMarcel Ziswiler NVBOOTTYPE_RECOVERY)
24f38f5f4bSMarcel Ziswiler printf("USB recovery mode\n");
25f38f5f4bSMarcel Ziswiler
26f38f5f4bSMarcel Ziswiler return 0;
27f38f5f4bSMarcel Ziswiler }
28f38f5f4bSMarcel Ziswiler
checkboard(void)29f38f5f4bSMarcel Ziswiler int checkboard(void)
30f38f5f4bSMarcel Ziswiler {
31f38f5f4bSMarcel Ziswiler puts("Model: Toradex Apalis TK1 2GB\n");
32f38f5f4bSMarcel Ziswiler
33f38f5f4bSMarcel Ziswiler return 0;
34f38f5f4bSMarcel Ziswiler }
35f38f5f4bSMarcel Ziswiler
36f38f5f4bSMarcel Ziswiler #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)37f38f5f4bSMarcel Ziswiler int ft_board_setup(void *blob, bd_t *bd)
38f38f5f4bSMarcel Ziswiler {
39f38f5f4bSMarcel Ziswiler return ft_common_board_setup(blob, bd);
40f38f5f4bSMarcel Ziswiler }
41f38f5f4bSMarcel Ziswiler #endif
42f38f5f4bSMarcel Ziswiler
43f38f5f4bSMarcel Ziswiler /*
44f38f5f4bSMarcel Ziswiler * Routine: pinmux_init
45f38f5f4bSMarcel Ziswiler * Description: Do individual peripheral pinmux configs
46f38f5f4bSMarcel Ziswiler */
pinmux_init(void)47f38f5f4bSMarcel Ziswiler void pinmux_init(void)
48f38f5f4bSMarcel Ziswiler {
49f38f5f4bSMarcel Ziswiler pinmux_clear_tristate_input_clamping();
50f38f5f4bSMarcel Ziswiler
51f38f5f4bSMarcel Ziswiler gpio_config_table(apalis_tk1_gpio_inits,
52f38f5f4bSMarcel Ziswiler ARRAY_SIZE(apalis_tk1_gpio_inits));
53f38f5f4bSMarcel Ziswiler
54f38f5f4bSMarcel Ziswiler pinmux_config_pingrp_table(apalis_tk1_pingrps,
55f38f5f4bSMarcel Ziswiler ARRAY_SIZE(apalis_tk1_pingrps));
56f38f5f4bSMarcel Ziswiler
57f38f5f4bSMarcel Ziswiler pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
58f38f5f4bSMarcel Ziswiler ARRAY_SIZE(apalis_tk1_drvgrps));
59f38f5f4bSMarcel Ziswiler }
60f38f5f4bSMarcel Ziswiler
61f38f5f4bSMarcel Ziswiler #ifdef CONFIG_PCI_TEGRA
tegra_pcie_board_init(void)62f38f5f4bSMarcel Ziswiler int tegra_pcie_board_init(void)
63f38f5f4bSMarcel Ziswiler {
64*e3f44f5cSSimon Glass /* TODO: Convert to driver model
65f38f5f4bSMarcel Ziswiler struct udevice *pmic;
66f38f5f4bSMarcel Ziswiler int err;
67f38f5f4bSMarcel Ziswiler
68f38f5f4bSMarcel Ziswiler err = as3722_init(&pmic);
69f38f5f4bSMarcel Ziswiler if (err) {
70f38f5f4bSMarcel Ziswiler error("failed to initialize AS3722 PMIC: %d\n", err);
71f38f5f4bSMarcel Ziswiler return err;
72f38f5f4bSMarcel Ziswiler }
73f38f5f4bSMarcel Ziswiler
74f38f5f4bSMarcel Ziswiler err = as3722_sd_enable(pmic, 4);
75f38f5f4bSMarcel Ziswiler if (err < 0) {
76f38f5f4bSMarcel Ziswiler error("failed to enable SD4: %d\n", err);
77f38f5f4bSMarcel Ziswiler return err;
78f38f5f4bSMarcel Ziswiler }
79f38f5f4bSMarcel Ziswiler
80f38f5f4bSMarcel Ziswiler err = as3722_sd_set_voltage(pmic, 4, 0x24);
81f38f5f4bSMarcel Ziswiler if (err < 0) {
82f38f5f4bSMarcel Ziswiler error("failed to set SD4 voltage: %d\n", err);
83f38f5f4bSMarcel Ziswiler return err;
84f38f5f4bSMarcel Ziswiler }
85f38f5f4bSMarcel Ziswiler
86f38f5f4bSMarcel Ziswiler err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH |
87f38f5f4bSMarcel Ziswiler AS3722_GPIO_INVERT);
88f38f5f4bSMarcel Ziswiler if (err < 0) {
89f38f5f4bSMarcel Ziswiler error("failed to configure GPIO#1 as output: %d\n", err);
90f38f5f4bSMarcel Ziswiler return err;
91f38f5f4bSMarcel Ziswiler }
92f38f5f4bSMarcel Ziswiler
93f38f5f4bSMarcel Ziswiler err = as3722_gpio_direction_output(pmic, 2, 1);
94f38f5f4bSMarcel Ziswiler if (err < 0) {
95f38f5f4bSMarcel Ziswiler error("failed to set GPIO#2 high: %d\n", err);
96f38f5f4bSMarcel Ziswiler return err;
97f38f5f4bSMarcel Ziswiler }
98*e3f44f5cSSimon Glass */
99f38f5f4bSMarcel Ziswiler
100f38f5f4bSMarcel Ziswiler /* Reset I210 Gigabit Ethernet Controller */
101f38f5f4bSMarcel Ziswiler gpio_request(LAN_RESET_N, "LAN_RESET_N");
102f38f5f4bSMarcel Ziswiler gpio_direction_output(LAN_RESET_N, 0);
103f38f5f4bSMarcel Ziswiler
104f38f5f4bSMarcel Ziswiler /*
105f38f5f4bSMarcel Ziswiler * Make sure we don't get any back feeding from LAN_WAKE_N resp.
106f38f5f4bSMarcel Ziswiler * DEV_OFF_N
107f38f5f4bSMarcel Ziswiler */
108f38f5f4bSMarcel Ziswiler gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N");
109f38f5f4bSMarcel Ziswiler gpio_direction_output(TEGRA_GPIO(O, 5), 0);
110f38f5f4bSMarcel Ziswiler
111f38f5f4bSMarcel Ziswiler gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N");
112f38f5f4bSMarcel Ziswiler gpio_direction_output(TEGRA_GPIO(O, 6), 0);
113f38f5f4bSMarcel Ziswiler
114f38f5f4bSMarcel Ziswiler /* Make sure LDO9 and LDO10 are initially enabled @ 0V */
115*e3f44f5cSSimon Glass /* TODO: Convert to driver model
116f38f5f4bSMarcel Ziswiler err = as3722_ldo_enable(pmic, 9);
117f38f5f4bSMarcel Ziswiler if (err < 0) {
118f38f5f4bSMarcel Ziswiler error("failed to enable LDO9: %d\n", err);
119f38f5f4bSMarcel Ziswiler return err;
120f38f5f4bSMarcel Ziswiler }
121f38f5f4bSMarcel Ziswiler err = as3722_ldo_enable(pmic, 10);
122f38f5f4bSMarcel Ziswiler if (err < 0) {
123f38f5f4bSMarcel Ziswiler error("failed to enable LDO10: %d\n", err);
124f38f5f4bSMarcel Ziswiler return err;
125f38f5f4bSMarcel Ziswiler }
126f38f5f4bSMarcel Ziswiler err = as3722_ldo_set_voltage(pmic, 9, 0x80);
127f38f5f4bSMarcel Ziswiler if (err < 0) {
128f38f5f4bSMarcel Ziswiler error("failed to set LDO9 voltage: %d\n", err);
129f38f5f4bSMarcel Ziswiler return err;
130f38f5f4bSMarcel Ziswiler }
131f38f5f4bSMarcel Ziswiler err = as3722_ldo_set_voltage(pmic, 10, 0x80);
132f38f5f4bSMarcel Ziswiler if (err < 0) {
133f38f5f4bSMarcel Ziswiler error("failed to set LDO10 voltage: %d\n", err);
134f38f5f4bSMarcel Ziswiler return err;
135f38f5f4bSMarcel Ziswiler }
136*e3f44f5cSSimon Glass */
137f38f5f4bSMarcel Ziswiler
138f38f5f4bSMarcel Ziswiler mdelay(100);
139f38f5f4bSMarcel Ziswiler
140f38f5f4bSMarcel Ziswiler /* Make sure controller gets enabled by disabling DEV_OFF_N */
141f38f5f4bSMarcel Ziswiler gpio_set_value(TEGRA_GPIO(O, 6), 1);
142f38f5f4bSMarcel Ziswiler
143f38f5f4bSMarcel Ziswiler /* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */
144*e3f44f5cSSimon Glass /* TODO: Convert to driver model
145f38f5f4bSMarcel Ziswiler err = as3722_ldo_set_voltage(pmic, 9, 0xff);
146f38f5f4bSMarcel Ziswiler if (err < 0) {
147f38f5f4bSMarcel Ziswiler error("failed to set LDO9 voltage: %d\n", err);
148f38f5f4bSMarcel Ziswiler return err;
149f38f5f4bSMarcel Ziswiler }
150f38f5f4bSMarcel Ziswiler err = as3722_ldo_set_voltage(pmic, 10, 0xff);
151f38f5f4bSMarcel Ziswiler if (err < 0) {
152f38f5f4bSMarcel Ziswiler error("failed to set LDO10 voltage: %d\n", err);
153f38f5f4bSMarcel Ziswiler return err;
154f38f5f4bSMarcel Ziswiler }
155*e3f44f5cSSimon Glass */
156f38f5f4bSMarcel Ziswiler
157f38f5f4bSMarcel Ziswiler mdelay(100);
158f38f5f4bSMarcel Ziswiler gpio_set_value(LAN_RESET_N, 1);
159f38f5f4bSMarcel Ziswiler
160f38f5f4bSMarcel Ziswiler #ifdef APALIS_TK1_PCIE_EVALBOARD_INIT
161f38f5f4bSMarcel Ziswiler #define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
162f38f5f4bSMarcel Ziswiler #define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
163f38f5f4bSMarcel Ziswiler
164f38f5f4bSMarcel Ziswiler /* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation
165f38f5f4bSMarcel Ziswiler Board */
166f38f5f4bSMarcel Ziswiler gpio_request(PEX_PERST_N, "PEX_PERST_N");
167f38f5f4bSMarcel Ziswiler gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
168f38f5f4bSMarcel Ziswiler gpio_direction_output(PEX_PERST_N, 0);
169f38f5f4bSMarcel Ziswiler gpio_direction_output(RESET_MOCI_CTRL, 0);
170f38f5f4bSMarcel Ziswiler /* Must be asserted for 100 ms after power and clocks are stable */
171f38f5f4bSMarcel Ziswiler mdelay(100);
172f38f5f4bSMarcel Ziswiler gpio_set_value(PEX_PERST_N, 1);
173f38f5f4bSMarcel Ziswiler /* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until
174f38f5f4bSMarcel Ziswiler 900 us After PEX_PERST# De-assertion */
175f38f5f4bSMarcel Ziswiler mdelay(1);
176f38f5f4bSMarcel Ziswiler gpio_set_value(RESET_MOCI_CTRL, 1);
177f38f5f4bSMarcel Ziswiler #endif /* APALIS_T30_PCIE_EVALBOARD_INIT */
178f38f5f4bSMarcel Ziswiler
179f38f5f4bSMarcel Ziswiler return 0;
180f38f5f4bSMarcel Ziswiler }
181f38f5f4bSMarcel Ziswiler #endif /* CONFIG_PCI_TEGRA */
182