1b1babef8SHao Zhang /* 2b1babef8SHao Zhang * Keystone2: DDR3 configuration 3b1babef8SHao Zhang * 4b1babef8SHao Zhang * (C) Copyright 2012-2014 5b1babef8SHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6b1babef8SHao Zhang * 7b1babef8SHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8b1babef8SHao Zhang */ 9b1babef8SHao Zhang 10b1babef8SHao Zhang #ifndef __DDR3_CFG_H 11b1babef8SHao Zhang #define __DDR3_CFG_H 12b1babef8SHao Zhang 13*d9a76e77SVitaly Andrianov #include <asm/arch/ddr3.h> 14a9068479SHao Zhang 15345af534SHao Zhang extern struct ddr3_phy_config ddr3phy_1600_2g; 16345af534SHao Zhang extern struct ddr3_emif_config ddr3_1600_2g; 17345af534SHao Zhang 18*d9a76e77SVitaly Andrianov int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb); 19b1babef8SHao Zhang 20b1babef8SHao Zhang #endif /* __DDR3_CFG_H */ 21